LC_CTRL Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: a9c19f09f3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.940s	88.708us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	34.812us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.030s	14.087us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.070s	94.063us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.660s	53.669us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.010s	91.050us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.030s	14.087us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	53.669us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.330s	133.204us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.900s	391.230us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	14.519us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.440s	136.670us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.690s	2.958ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_prog_failure	5.440s	136.670us	50	50	100.00
		lc_ctrl_errors	18.690s	2.958ms	50	50	100.00
		lc_ctrl_security_escalation	15.610s	615.691us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.183m	12.628ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.300s	6.314ms	20	20	100.00
		lc_ctrl_jtag_errors	1.762m	34.770ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.390s	1.828ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	20.530s	2.092ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.300s	6.314ms	20	20	100.00
		lc_ctrl_jtag_errors	1.762m	34.770ms	20	20	100.00
		lc_ctrl_jtag_access	19.130s	829.125us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	20.470s	1.542ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.040s	226.943us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.630s	551.988us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	40.170s	3.978ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.080s	851.735us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.430s	97.359us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.380s	247.472us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.420s	1.160ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.011m	2.844ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.160s	16.992us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.042m	93.795ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.490s	32.165us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.190s	100.887us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.190s	100.887us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	34.812us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	14.087us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	53.669us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	189.813us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	34.812us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	14.087us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	53.669us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	189.813us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
		lc_ctrl_tl_intg_err	3.320s	155.646us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.320s	155.646us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.900s	391.230us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.430s	680.287us	50	50	100.00
		lc_ctrl_sec_cm	37.660s	901.785us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.610s	615.691us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.330s	133.204us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	20.530s	2.092ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.870s	691.980us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.870s	691.980us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.930s	2.282ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.890s	2.136ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.890s	2.136ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	37.309m	45.285ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			986	1030	95.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.38	97.29	95.97	91.98	100.00	96.13	98.48	94.82

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.37702065160795278048907343405205629851833915452550687389481166194351495697400
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:c8b4f8ce-b23e-48a9-b1af-5bda10b59714
      

    • 6.lc_ctrl_stress_all_with_rand_reset.36369476607186228418834552052571109264180223395827521746706852563632458808576
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:2c214273-33b7-458a-8cf4-ac9105d4ce3c
      

    • ... and 24 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 7 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.7796313758614810430942313492050243084553465211656927256409514759388685471401
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:be03b261-737d-401e-98dc-e8543d43a245
      

    • 7.lc_ctrl_stress_all_with_rand_reset.72597514570632801356524219286151724104935223032769652325573663501013249764275
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:fec84b3e-30cb-4548-b334-c5cec0eedc88
      

    • ... and 5 more failures.

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.101938409846979890734625254939120406724169884336121317294501254636702819404356
      Line 19662, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 71501766865 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x1c5d0000
        UVM_INFO @ 71501766865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.lc_ctrl_stress_all_with_rand_reset.99324247937412915873297777562222686954567316810620700904795127818306035718229
      Line 22454, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 49397074596 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x7f68ea00
        UVM_INFO @ 49397074596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.63347824472847026878947126150692717359740606614802615616620066347976612986825
      Line 7908, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12481285697 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
        UVM_INFO @ 12481285697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.lc_ctrl_stress_all_with_rand_reset.85919458565227574378158804332173328461205428134086925269996610121947065185024
      Line 1678, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 300146837 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
        UVM_INFO @ 300146837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.26105370725202563883441119086856746843917856645967871637993168687468268031030
      Line 5353, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5687539508 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked3
        UVM_INFO @ 5687539508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_ctrl reset value: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.96829687990631644249625558716121715544329243474985407808917764454188711566260
      Line 329, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2402944423 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.transition_ctrl reset value: 0x0
        UVM_INFO @ 2402944423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStRaw has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.22425920739049490346655731633554877197778340900765636295007741289289469766349
      Line 10029, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7877621868 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStRaw
        UVM_INFO @ 7877621868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.otp_vendor_test_ctrl reset value: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.23521048525940773325685309839949633192764600594767140164354695759935015296472
      Line 3510, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15591461621 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 174841577 [0xa6bdee9]) Regname: lc_ctrl_reg_block.otp_vendor_test_ctrl reset value: 0x0
        UVM_INFO @ 15591461621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2023.12.28_03.23.05
• 2023.12.25_01.25.43
• 2023.12.21_00.15.46
• 2023.11.23_02.09.59
• 2023.11.02_03.38.10
• 2023.10.30_18.19.21