Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59388510

1

T64

119192

T97

1521

T98

3833

auto[1]

1184940

1

T1

198

T2

2156

T10

792

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59391158

1

T64

119192

T97

1521

T98

3833

auto[1]

1182292

1

T1

297

T2

2254

T10

990

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5398146	1			T64	93		T97	99		T98	83
auto[IdleSt]	14803225	1			T64	119099		T97	1422		T98	3750
auto[ClkMuxSt]	27736	1			T1	5		T3	81		T10	18
auto[CntIncrSt]	27526	1			T1	5		T3	81		T10	18
auto[CntProgSt]	1643253	1			T1	234		T3	162		T10	863
auto[TransCheckSt]	21561	1			T3	81		T4	34		T14	40
auto[TokenHashSt]	15617200	1			T3	1020		T4	147139		T14	1251
auto[FlashRmaSt]	22204	1			T3	117		T4	84		T14	30
auto[TokenCheck0St]	9627	1			T3	32		T4	34		T14	25
auto[TokenCheck1St]	6927	1			T3	5		T4	34		T14	21
auto[TransProgSt]	406262	1			T4	9679		T14	907		T16	2403
auto[PostTransSt]	8540804	1			T1	280		T3	13141		T10	1091
auto[ScrapSt]	88638	1			T99	3577		T111	1243		T120	1962
auto[EscalateSt]	5354715	1			T1	727		T2	17301		T10	2302
auto[InvalidSt]	8604303	1			T2	48574		T12	7391		T4	86657

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1323	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	8604303	1			T2	48574		T12	7391		T4	86657
EscalateSt	5354715	1			T1	727		T2	17301		T10	2302
ScrapSt	88638	1			T99	3577		T111	1243		T120	1962
PostTransSt	8540804	1			T1	280		T3	13141		T10	1091
TransProgSt	406262	1			T4	9679		T14	907		T16	2403
TokenCheck1St	6927	1			T3	5		T4	34		T14	21
TokenCheck0St	9627	1			T3	32		T4	34		T14	25
FlashRmaSt	22204	1			T3	117		T4	84		T14	30
TokenHashSt	15617200	1			T3	1020		T4	147139		T14	1251
TransCheckSt	21561	1			T3	81		T4	34		T14	40
CntProgSt	1643253	1			T1	234		T3	162		T10	863
CntIncrSt	27526	1			T1	5		T3	81		T10	18
ClkMuxSt	27736	1			T1	5		T3	81		T10	18
IdleSt	14803225	1			T64	119099		T97	1422		T98	3750
ResetSt	5398146	1			T64	93		T97	99		T98	83
arcs[ResetSt=>IdleSt]	40922	1			T64	1		T97	3		T98	1
arcs[IdleSt=>ScrapSt]	222	1			T99	1		T111	2		T120	1
arcs[IdleSt=>ClkMuxSt]	27592	1			T1	5		T3	81		T10	18
arcs[ClkMuxSt=>CntIncrSt]	27526	1			T1	5		T3	81		T10	18
arcs[CntIncrSt=>PostTransSt]	1230	1			T47	8		T48	6		T19	29
arcs[CntIncrSt=>CntProgSt]	26237	1			T1	5		T3	81		T10	18
arcs[CntProgSt=>PostTransSt]	3503	1			T1	5		T10	18		T13	7
arcs[CntProgSt=>TransCheckSt]	21561	1			T3	81		T4	34		T14	40
arcs[TransCheckSt=>PostTransSt]	3016	1			T3	31		T15	22		T63	35
arcs[TransCheckSt=>TokenHashSt]	18458	1			T3	50		T4	34		T14	40
arcs[TokenHashSt=>PostTransSt]	8171	1			T3	18		T15	10		T50	98
arcs[TokenHashSt=>FlashRmaSt]	9733	1			T3	32		T4	34		T14	28
arcs[FlashRmaSt=>TokenCheck0St]	9627	1			T3	32		T4	34		T14	25
arcs[TokenCheck0St=>PostTransSt]	2666	1			T3	27		T15	9		T63	27
arcs[TokenCheck0St=>TokenCheck1St]	6927	1			T3	5		T4	34		T14	21
arcs[TokenCheck1St=>PostTransSt]	599	1			T3	5		T15	11		T63	14
arcs[TransProgSt=>PostTransSt]	5388	1			T4	34		T14	3		T16	7
arcs[IdleSt=>EscalateSt]	204	1			T68	7		T90	9		T198	12
arcs[ClkMuxSt=>EscalateSt]	66	1			T14	4		T68	2		T90	3
arcs[CntIncrSt=>EscalateSt]	59	1			T90	2		T91	1		T199	1
arcs[CntProgSt=>EscalateSt]	1172	1			T14	28		T68	25		T90	8
arcs[TransCheckSt=>EscalateSt]	87	1			T90	12		T199	1		T133	8
arcs[TokenHashSt=>EscalateSt]	551	1			T14	12		T68	8		T90	24
arcs[FlashRmaSt=>EscalateSt]	106	1			T14	3		T68	3		T90	2
arcs[TokenCheck0St=>EscalateSt]	34	1			T14	4		T90	2		T133	1
arcs[TokenCheck1St=>EscalateSt]	171	1			T14	3		T68	6		T90	3
arcs[TransProgSt=>EscalateSt]	769	1			T14	15		T68	18		T90	3
arcs[PostTransSt=>EscalateSt]	3715	1			T1	5		T10	18		T13	7
arcs[InvalidSt=>EscalateSt]	11003	1			T2	45		T12	49		T4	146

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5397979	1			T64	93		T97	99		T98	83
auto[0]	auto[IdleSt]	14803089	1			T64	119099		T97	1422		T98	3750
auto[0]	auto[ClkMuxSt]	27696	1			T1	5		T3	81		T10	18
auto[0]	auto[CntIncrSt]	27487	1			T1	5		T3	81		T10	18
auto[0]	auto[CntProgSt]	1642477	1			T1	234		T3	162		T10	863
auto[0]	auto[TransCheckSt]	21505	1			T3	81		T4	34		T14	40
auto[0]	auto[TokenHashSt]	15616819	1			T3	1020		T4	147139		T14	1243
auto[0]	auto[FlashRmaSt]	22141	1			T3	117		T4	84		T14	28
auto[0]	auto[TokenCheck0St]	9605	1			T3	32		T4	34		T14	22
auto[0]	auto[TokenCheck1St]	6812	1			T3	5		T4	34		T14	19
auto[0]	auto[TransProgSt]	405764	1			T4	9679		T14	896		T16	2403
auto[0]	auto[PostTransSt]	8538939	1			T1	278		T3	13141		T10	1083
auto[0]	auto[ScrapSt]	88591	1			T99	3577		T111	1243		T120	1962
auto[0]	auto[EscalateSt]	4179531	1			T1	531		T2	15167		T10	1518
auto[0]	auto[InvalidSt]	8598752	1			T2	48552		T12	7365		T4	86582
auto[1]	auto[ResetSt]	167	1			T14	5		T68	4		T90	3
auto[1]	auto[IdleSt]	136	1			T68	5		T90	4		T198	5
auto[1]	auto[ClkMuxSt]	40	1			T14	1		T68	2		T90	3
auto[1]	auto[CntIncrSt]	39	1			T90	2		T91	1		T133	1
auto[1]	auto[CntProgSt]	776	1			T14	17		T68	16		T90	3
auto[1]	auto[TransCheckSt]	56	1			T90	10		T199	1		T133	4
auto[1]	auto[TokenHashSt]	381	1			T14	8		T68	7		T90	16
auto[1]	auto[FlashRmaSt]	63	1			T14	2		T68	2		T90	1
auto[1]	auto[TokenCheck0St]	22	1			T14	3		T90	1		T133	1
auto[1]	auto[TokenCheck1St]	115	1			T14	2		T68	5		T90	2
auto[1]	auto[TransProgSt]	498	1			T14	11		T68	9		T90	1
auto[1]	auto[PostTransSt]	1865	1			T1	2		T10	8		T13	6
auto[1]	auto[ScrapSt]	47	1			T14	1		T68	1		T90	2
auto[1]	auto[EscalateSt]	1175184	1			T1	196		T2	2134		T10	784
auto[1]	auto[InvalidSt]	5551	1			T2	22		T12	26		T4	75

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5397970	1			T64	93		T97	99		T98	83
auto[0]	auto[IdleSt]	14803094	1			T64	119099		T97	1422		T98	3750
auto[0]	auto[ClkMuxSt]	27691	1			T1	5		T3	81		T10	18
auto[0]	auto[CntIncrSt]	27488	1			T1	5		T3	81		T10	18
auto[0]	auto[CntProgSt]	1642466	1			T1	234		T3	162		T10	863
auto[0]	auto[TransCheckSt]	21505	1			T3	81		T4	34		T14	40
auto[0]	auto[TokenHashSt]	15616857	1			T3	1020		T4	147139		T14	1244
auto[0]	auto[FlashRmaSt]	22130	1			T3	117		T4	84		T14	27
auto[0]	auto[TokenCheck0St]	9604	1			T3	32		T4	34		T14	24
auto[0]	auto[TokenCheck1St]	6811	1			T3	5		T4	34		T14	19
auto[0]	auto[TransProgSt]	405735	1			T4	9679		T14	897		T16	2403
auto[0]	auto[PostTransSt]	8538900	1			T1	277		T3	13141		T10	1081
auto[0]	auto[ScrapSt]	88599	1			T99	3577		T111	1243		T120	1962
auto[0]	auto[EscalateSt]	4182134	1			T1	433		T2	15070		T10	1322
auto[0]	auto[InvalidSt]	8598851	1			T2	48551		T12	7368		T4	86586
auto[1]	auto[ResetSt]	176	1			T14	6		T68	5		T90	4
auto[1]	auto[IdleSt]	131	1			T68	5		T90	6		T198	8
auto[1]	auto[ClkMuxSt]	45	1			T14	4		T134	2		T200	1
auto[1]	auto[CntIncrSt]	38	1			T90	1		T199	1		T133	1
auto[1]	auto[CntProgSt]	787	1			T14	20		T68	21		T90	6
auto[1]	auto[TransCheckSt]	56	1			T90	8		T133	4		T198	2
auto[1]	auto[TokenHashSt]	343	1			T14	7		T68	4		T90	14
auto[1]	auto[FlashRmaSt]	74	1			T14	3		T68	2		T90	1
auto[1]	auto[TokenCheck0St]	23	1			T14	1		T90	2		T134	1
auto[1]	auto[TokenCheck1St]	116	1			T14	2		T68	5		T90	1
auto[1]	auto[TransProgSt]	527	1			T14	10		T68	15		T90	2
auto[1]	auto[PostTransSt]	1904	1			T1	3		T10	10		T13	1
auto[1]	auto[ScrapSt]	39	1			T14	1		T68	2		T90	1
auto[1]	auto[EscalateSt]	1172581	1			T1	294		T2	2231		T10	980
auto[1]	auto[InvalidSt]	5452	1			T2	23		T12	23		T4	71