Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	711818	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

892678

1

T97

351

T99

203

T100

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1328985	1			T97	104		T99	192		T100	10
values[0x0]	137269	1			T97	127		T99	91		T100	34
values[0x1]	138242	1			T97	148		T99	101		T100	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	562785	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1041711

1

T97

354

T99

234

T100

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4344	1			T110	3		T111	2		T114	15
valid_sources[0x01]	12973	1			T100	1		T101	1		T102	2
valid_sources[0x02]	5433	1			T102	3		T110	2		T111	2
valid_sources[0x03]	4629	1			T102	8		T110	1		T170	1
valid_sources[0x04]	4317	1			T101	1		T102	1		T110	2
valid_sources[0x05]	4402	1			T105	18		T158	1		T118	1
valid_sources[0x06]	4277	1			T111	3		T170	3		T139	2
valid_sources[0x07]	6236	1			T102	2		T105	19		T110	1
valid_sources[0x08]	6726	1			T110	3		T158	1		T118	5
valid_sources[0x09]	4284	1			T101	2		T102	6		T169	1
valid_sources[0x0a]	5078	1			T105	19		T118	4		T112	5
valid_sources[0x0b]	6867	1			T118	1		T136	2		T120	1
valid_sources[0x0c]	4475	1			T102	2		T114	1		T118	1
valid_sources[0x0d]	8559	1			T111	1		T170	1		T118	2
valid_sources[0x0e]	4439	1			T102	2		T169	1		T170	2
valid_sources[0x0f]	4486	1			T102	5		T114	6		T169	1
valid_sources[0x10]	4520	1			T158	1		T170	2		T173	3
valid_sources[0x11]	4670	1			T102	1		T114	1		T170	3
valid_sources[0x12]	4295	1			T101	1		T114	4		T169	1
valid_sources[0x13]	17508	1			T102	4		T169	1		T170	2
valid_sources[0x14]	5101	1			T102	1		T110	13		T114	12
valid_sources[0x15]	4325	1			T101	1		T102	1		T110	2
valid_sources[0x16]	4460	1			T110	3		T114	7		T169	1
valid_sources[0x17]	8928	1			T102	1		T112	1		T135	2
valid_sources[0x18]	4646	1			T102	2		T110	1		T170	2
valid_sources[0x19]	4817	1			T102	1		T158	1		T118	1
valid_sources[0x1a]	8301	1			T110	4		T169	1		T173	1
valid_sources[0x1b]	5174	1			T100	1		T102	3		T111	5
valid_sources[0x1c]	5983	1			T102	4		T158	4		T114	5
valid_sources[0x1d]	4249	1			T101	1		T105	22		T110	2
valid_sources[0x1e]	4515	1			T102	1		T114	1		T169	1
valid_sources[0x1f]	4483	1			T100	1		T101	2		T170	1
valid_sources[0x20]	21250	1			T114	1		T120	8		T143	2
valid_sources[0x21]	4387	1			T97	6		T102	2		T111	1
valid_sources[0x22]	4179	1			T114	3		T135	2		T136	3
valid_sources[0x23]	5821	1			T102	3		T111	5		T140	19
valid_sources[0x24]	4838	1			T102	1		T111	7		T158	1
valid_sources[0x25]	4461	1			T102	2		T170	1		T118	2
valid_sources[0x26]	4263	1			T110	4		T139	1		T135	3
valid_sources[0x27]	5801	1			T114	15		T170	1		T135	5
valid_sources[0x28]	4535	1			T101	1		T102	2		T110	3
valid_sources[0x29]	4651	1			T101	1		T102	2		T158	1
valid_sources[0x2a]	4355	1			T102	1		T110	3		T158	1
valid_sources[0x2b]	5484	1			T102	3		T110	7		T111	1
valid_sources[0x2c]	4491	1			T102	2		T111	2		T158	1
valid_sources[0x2d]	4714	1			T97	46		T102	3		T158	1
valid_sources[0x2e]	4732	1			T102	3		T110	6		T114	2
valid_sources[0x2f]	4408	1			T102	2		T114	2		T139	6
valid_sources[0x30]	4561	1			T102	1		T114	13		T173	1
valid_sources[0x31]	5464	1			T97	9		T100	4		T114	4
valid_sources[0x32]	4687	1			T101	1		T114	2		T169	1
valid_sources[0x33]	5688	1			T100	2		T170	2		T173	1
valid_sources[0x34]	4286	1			T105	36		T170	2		T118	5
valid_sources[0x35]	4463	1			T102	3		T111	1		T170	3
valid_sources[0x36]	4205	1			T100	1		T101	1		T102	1
valid_sources[0x37]	4302	1			T102	1		T111	2		T158	1
valid_sources[0x38]	5407	1			T100	2		T110	2		T170	2
valid_sources[0x39]	4365	1			T102	1		T110	3		T170	1
valid_sources[0x3a]	4418	1			T100	1		T110	5		T158	2
valid_sources[0x3b]	4473	1			T102	2		T169	1		T170	1
valid_sources[0x3c]	4605	1			T102	3		T111	1		T173	1
valid_sources[0x3d]	4358	1			T102	2		T111	6		T139	5
valid_sources[0x3e]	4368	1			T101	1		T170	1		T135	3
valid_sources[0x3f]	4686	1			T102	1		T114	3		T170	1
valid_sources[0x40]	4381	1			T100	6		T135	2		T136	2
valid_sources[0x41]	4644	1			T97	20		T99	128		T101	2
valid_sources[0x42]	5745	1			T102	1		T110	5		T170	1
valid_sources[0x43]	4555	1			T170	1		T135	2		T136	1
valid_sources[0x44]	4544	1			T101	1		T102	4		T110	1
valid_sources[0x45]	4360	1			T102	3		T110	3		T169	1
valid_sources[0x46]	4067	1			T102	3		T158	1		T114	5
valid_sources[0x47]	5844	1			T111	2		T114	2		T170	1
valid_sources[0x48]	4942	1			T118	3		T135	3		T136	1
valid_sources[0x49]	5670	1			T102	1		T170	2		T118	1
valid_sources[0x4a]	7341	1			T102	3		T110	3		T111	1
valid_sources[0x4b]	4615	1			T100	7		T102	3		T111	1
valid_sources[0x4c]	4648	1			T101	2		T102	7		T169	1
valid_sources[0x4d]	4386	1			T102	2		T111	6		T114	6
valid_sources[0x4e]	4517	1			T100	2		T102	2		T114	1
valid_sources[0x4f]	4542	1			T101	1		T102	1		T114	8
valid_sources[0x50]	4525	1			T102	4		T170	1		T173	2
valid_sources[0x51]	4395	1			T101	1		T110	8		T114	1
valid_sources[0x52]	4422	1			T102	1		T105	16		T110	3
valid_sources[0x53]	4785	1			T102	1		T169	1		T118	2
valid_sources[0x54]	5823	1			T101	1		T102	1		T114	1
valid_sources[0x55]	4494	1			T102	3		T111	4		T170	2
valid_sources[0x56]	5640	1			T97	49		T101	1		T102	2
valid_sources[0x57]	4900	1			T114	7		T112	4		T173	1
valid_sources[0x58]	4756	1			T110	1		T114	4		T170	1
valid_sources[0x59]	4302	1			T102	1		T111	2		T158	1
valid_sources[0x5a]	4288	1			T158	1		T114	4		T170	1
valid_sources[0x5b]	4859	1			T100	1		T102	5		T111	2
valid_sources[0x5c]	5772	1			T102	2		T169	1		T173	1
valid_sources[0x5d]	4329	1			T100	7		T102	1		T110	6
valid_sources[0x5e]	4693	1			T102	1		T110	11		T114	2
valid_sources[0x5f]	4655	1			T101	1		T110	4		T169	1
valid_sources[0x60]	15032	1			T170	2		T118	1		T173	1
valid_sources[0x61]	4537	1			T169	1		T170	1		T173	1
valid_sources[0x62]	4616	1			T102	4		T111	2		T118	2
valid_sources[0x63]	4192	1			T102	6		T118	3		T135	5
valid_sources[0x64]	5557	1			T110	1		T114	5		T135	3
valid_sources[0x65]	4503	1			T101	1		T102	1		T105	16
valid_sources[0x66]	4384	1			T101	1		T102	2		T170	1
valid_sources[0x67]	4266	1			T100	1		T101	1		T110	1
valid_sources[0x68]	4583	1			T102	1		T105	79		T114	4
valid_sources[0x69]	4602	1			T97	3		T102	2		T114	1
valid_sources[0x6a]	5811	1			T101	1		T102	5		T110	3
valid_sources[0x6b]	32605	1			T110	15		T158	1		T135	8
valid_sources[0x6c]	4535	1			T101	2		T102	2		T158	2
valid_sources[0x6d]	6994	1			T102	1		T111	3		T114	1
valid_sources[0x6e]	4607	1			T97	70		T102	2		T169	2
valid_sources[0x6f]	4197	1			T110	1		T158	1		T114	1
valid_sources[0x70]	6594	1			T102	2		T110	8		T170	2
valid_sources[0x71]	4441	1			T110	9		T158	1		T114	10
valid_sources[0x72]	4639	1			T101	1		T102	3		T158	1
valid_sources[0x73]	9322	1			T101	3		T102	4		T169	1
valid_sources[0x74]	4410	1			T110	8		T114	1		T170	1
valid_sources[0x75]	5220	1			T111	2		T118	2		T173	2
valid_sources[0x76]	4374	1			T100	1		T158	1		T169	2
valid_sources[0x77]	8255	1			T102	2		T114	3		T139	1
valid_sources[0x78]	7655	1			T97	28		T105	11		T114	3
valid_sources[0x79]	65782	1			T102	1		T110	1		T158	1
valid_sources[0x7a]	5748	1			T102	3		T110	3		T170	1
valid_sources[0x7b]	4385	1			T110	7		T173	1		T135	4
valid_sources[0x7c]	6330	1			T102	2		T158	1		T169	1
valid_sources[0x7d]	4459	1			T101	1		T102	1		T110	1
valid_sources[0x7e]	6677	1			T100	5		T105	4		T114	4
valid_sources[0x7f]	4539	1			T135	4		T136	2		T174	1
valid_sources[0x80]	5649	1			T101	1		T114	5		T170	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

655018

1

T97

86

T99

106

T100

1

values[0x0]

all_enables

biggest_size

119209

1

T97

123

T99

54

T100

28

values[0x1]

all_enables

biggest_size

118451

1

T97

142

T99

43

T100

28