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 LINE       1288
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T99,T100
1	0	1	Covered	T97,T99,T100
1	1	0	Covered	T155
1	1	1	Covered	T1,T3,T10

 LINE       1289
 EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T99,T100
1	0	1	Covered	T97,T99,T100
1	1	0	Covered	T113,T151,T156
1	1	1	Covered	T1,T3,T10

 LINE       1290
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T99,T100
1	0	1	Covered	T97,T99,T100
1	1	0	Covered	T102
1	1	1	Covered	T1,T3,T10

 LINE       1291
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T99,T100
1	0	1	Covered	T97,T99,T100
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       1292
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T99,T100
1	0	1	Covered	T97,T99,T100
1	1	0	Covered	T151,T147
1	1	1	Covered	T1,T3,T10

 LINE       1293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T99,T100
1	0	1	Covered	T97,T99,T100
1	1	0	Covered	T148,T152
1	1	1	Covered	T1,T3,T10

 LINE       1294
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T99,T100
1	0	1	Covered	T97,T99,T100
1	1	0	Covered	T102
1	1	1	Covered	T1,T3,T10