Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	60573171	12710	0	0
claim_transition_if_regwen_rd_A	60573171	789	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60573171	12710	0	0
T97	1521	135	0	0
T98	3833	0	0	0
T99	3799	0	0	0
T100	1014	0	0	0
T101	1387	14	0	0
T102	6108	3	0	0
T103	42283	0	0	0
T104	8010	0	0	0
T105	1756	0	0	0
T110	1962	0	0	0
T111	0	32	0	0
T112	0	4	0	0
T113	0	5	0	0
T135	0	846	0	0
T136	0	1037	0	0
T137	0	171	0	0
T168	0	29	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60573171	789	0	0
T101	1387	2	0	0
T102	6108	0	0	0
T103	42283	0	0	0
T104	8010	0	0	0
T105	1756	0	0	0
T110	1962	0	0	0
T111	2010	13	0	0
T112	0	32	0	0
T113	0	40	0	0
T119	0	47	0	0
T140	1006	0	0	0
T143	0	5	0	0
T157	65858	0	0	0
T158	1555	0	0	0
T169	0	13	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0