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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.34 97.29 95.70 91.98 100.00 96.13 98.48 94.82


Total test records in report: 984
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T766 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1834560447 Jan 03 01:14:16 PM PST 24 Jan 03 01:14:56 PM PST 24 701689074 ps
T767 /workspace/coverage/default/28.lc_ctrl_security_escalation.1316094054 Jan 03 01:14:43 PM PST 24 Jan 03 01:15:51 PM PST 24 5378005784 ps
T768 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.581900835 Jan 03 01:12:03 PM PST 24 Jan 03 01:12:47 PM PST 24 37766848 ps
T769 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1226110614 Jan 03 01:12:46 PM PST 24 Jan 03 01:13:28 PM PST 24 94077323 ps
T194 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1209836473 Jan 03 01:12:03 PM PST 24 Jan 03 01:12:47 PM PST 24 20079879 ps
T770 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2008780975 Jan 03 01:11:55 PM PST 24 Jan 03 01:13:27 PM PST 24 12247836223 ps
T771 /workspace/coverage/default/43.lc_ctrl_state_failure.3132093222 Jan 03 01:14:44 PM PST 24 Jan 03 01:15:59 PM PST 24 612944271 ps
T772 /workspace/coverage/default/36.lc_ctrl_smoke.2585281621 Jan 03 01:14:43 PM PST 24 Jan 03 01:15:41 PM PST 24 122902103 ps
T773 /workspace/coverage/default/7.lc_ctrl_jtag_access.3205539006 Jan 03 01:12:04 PM PST 24 Jan 03 01:12:49 PM PST 24 649849748 ps
T774 /workspace/coverage/default/5.lc_ctrl_prog_failure.2433435676 Jan 03 01:12:05 PM PST 24 Jan 03 01:12:52 PM PST 24 58130999 ps
T775 /workspace/coverage/default/41.lc_ctrl_stress_all.3082726129 Jan 03 01:14:34 PM PST 24 Jan 03 01:17:13 PM PST 24 12072377018 ps
T776 /workspace/coverage/default/37.lc_ctrl_sec_mubi.2071572168 Jan 03 01:14:19 PM PST 24 Jan 03 01:14:59 PM PST 24 340229686 ps
T777 /workspace/coverage/default/38.lc_ctrl_errors.1520727511 Jan 03 01:14:34 PM PST 24 Jan 03 01:15:28 PM PST 24 267559813 ps
T778 /workspace/coverage/default/39.lc_ctrl_jtag_access.580179461 Jan 03 01:14:47 PM PST 24 Jan 03 01:15:52 PM PST 24 1477270525 ps
T779 /workspace/coverage/default/4.lc_ctrl_prog_failure.4122449942 Jan 03 01:11:59 PM PST 24 Jan 03 01:12:38 PM PST 24 47765885 ps
T780 /workspace/coverage/default/12.lc_ctrl_state_failure.1874513429 Jan 03 01:12:56 PM PST 24 Jan 03 01:14:08 PM PST 24 351347185 ps
T121 /workspace/coverage/default/1.lc_ctrl_sec_cm.3238943406 Jan 03 01:11:47 PM PST 24 Jan 03 01:12:46 PM PST 24 707940760 ps
T781 /workspace/coverage/default/48.lc_ctrl_security_escalation.3686483192 Jan 03 01:14:15 PM PST 24 Jan 03 01:14:53 PM PST 24 261842172 ps
T782 /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2388363819 Jan 03 01:11:56 PM PST 24 Jan 03 01:12:53 PM PST 24 813269913 ps
T783 /workspace/coverage/default/22.lc_ctrl_alert_test.281605163 Jan 03 01:14:44 PM PST 24 Jan 03 01:15:38 PM PST 24 24456511 ps
T784 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4197619328 Jan 03 01:14:22 PM PST 24 Jan 03 01:15:02 PM PST 24 2100837978 ps
T785 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2410994214 Jan 03 01:14:37 PM PST 24 Jan 03 01:15:31 PM PST 24 533651667 ps
T786 /workspace/coverage/default/18.lc_ctrl_stress_all.3621300178 Jan 03 01:13:09 PM PST 24 Jan 03 01:15:07 PM PST 24 3186748242 ps
T787 /workspace/coverage/default/4.lc_ctrl_jtag_errors.799809057 Jan 03 01:12:03 PM PST 24 Jan 03 01:13:13 PM PST 24 3031591303 ps
T788 /workspace/coverage/default/30.lc_ctrl_prog_failure.1816088919 Jan 03 01:14:11 PM PST 24 Jan 03 01:14:41 PM PST 24 171401567 ps
T789 /workspace/coverage/default/40.lc_ctrl_errors.2588001378 Jan 03 01:14:45 PM PST 24 Jan 03 01:15:46 PM PST 24 225548200 ps
T790 /workspace/coverage/default/2.lc_ctrl_jtag_access.68991336 Jan 03 01:11:54 PM PST 24 Jan 03 01:12:38 PM PST 24 865074263 ps
T791 /workspace/coverage/default/38.lc_ctrl_jtag_access.984055577 Jan 03 01:14:40 PM PST 24 Jan 03 01:15:35 PM PST 24 1180316225 ps
T792 /workspace/coverage/default/11.lc_ctrl_security_escalation.2117813157 Jan 03 01:12:57 PM PST 24 Jan 03 01:13:42 PM PST 24 949928031 ps
T793 /workspace/coverage/default/1.lc_ctrl_sec_mubi.2641343458 Jan 03 01:11:56 PM PST 24 Jan 03 01:12:44 PM PST 24 245863606 ps
T794 /workspace/coverage/default/36.lc_ctrl_sec_mubi.1206636107 Jan 03 01:14:50 PM PST 24 Jan 03 01:16:00 PM PST 24 689577112 ps
T51 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4067135977 Jan 03 01:12:52 PM PST 24 Jan 03 01:13:32 PM PST 24 24538541 ps
T795 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.609901485 Jan 03 01:14:00 PM PST 24 Jan 03 01:14:33 PM PST 24 423193283 ps
T796 /workspace/coverage/default/15.lc_ctrl_jtag_access.4210526950 Jan 03 01:12:59 PM PST 24 Jan 03 01:13:44 PM PST 24 116801832 ps
T797 /workspace/coverage/default/39.lc_ctrl_errors.888139122 Jan 03 01:14:42 PM PST 24 Jan 03 01:15:45 PM PST 24 375781951 ps
T798 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3169147330 Jan 03 01:13:07 PM PST 24 Jan 03 01:13:56 PM PST 24 69377011 ps
T62 /workspace/coverage/default/11.lc_ctrl_errors.3624130809 Jan 03 01:13:09 PM PST 24 Jan 03 01:14:07 PM PST 24 347961318 ps
T799 /workspace/coverage/default/4.lc_ctrl_state_failure.3355311794 Jan 03 01:11:56 PM PST 24 Jan 03 01:13:01 PM PST 24 283208192 ps
T800 /workspace/coverage/default/35.lc_ctrl_alert_test.795624044 Jan 03 01:14:33 PM PST 24 Jan 03 01:15:15 PM PST 24 37260581 ps
T801 /workspace/coverage/default/20.lc_ctrl_prog_failure.662497393 Jan 03 01:13:54 PM PST 24 Jan 03 01:14:20 PM PST 24 43979664 ps
T802 /workspace/coverage/default/41.lc_ctrl_prog_failure.3287744381 Jan 03 01:14:21 PM PST 24 Jan 03 01:14:55 PM PST 24 1301041425 ps
T803 /workspace/coverage/default/26.lc_ctrl_sec_mubi.897213766 Jan 03 01:13:59 PM PST 24 Jan 03 01:14:32 PM PST 24 247843526 ps
T804 /workspace/coverage/default/34.lc_ctrl_prog_failure.2863223843 Jan 03 01:14:17 PM PST 24 Jan 03 01:14:50 PM PST 24 441376061 ps
T805 /workspace/coverage/default/45.lc_ctrl_state_failure.2515476199 Jan 03 01:14:19 PM PST 24 Jan 03 01:15:11 PM PST 24 290942104 ps
T86 /workspace/coverage/default/13.lc_ctrl_stress_all.2501806916 Jan 03 01:12:56 PM PST 24 Jan 03 01:14:39 PM PST 24 11135486328 ps
T806 /workspace/coverage/default/14.lc_ctrl_sec_token_mux.585483002 Jan 03 01:12:52 PM PST 24 Jan 03 01:13:39 PM PST 24 2560982850 ps
T807 /workspace/coverage/default/8.lc_ctrl_jtag_smoke.567731691 Jan 03 01:12:11 PM PST 24 Jan 03 01:13:01 PM PST 24 53912227 ps
T808 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1982426485 Jan 03 01:11:51 PM PST 24 Jan 03 01:13:47 PM PST 24 7898378648 ps
T809 /workspace/coverage/default/30.lc_ctrl_sec_mubi.3915192410 Jan 03 01:14:18 PM PST 24 Jan 03 01:14:59 PM PST 24 430761280 ps
T810 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2148410321 Jan 03 01:13:59 PM PST 24 Jan 03 01:14:30 PM PST 24 936689944 ps
T811 /workspace/coverage/default/4.lc_ctrl_smoke.1705503867 Jan 03 01:11:56 PM PST 24 Jan 03 01:12:35 PM PST 24 42057312 ps
T812 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3859283453 Jan 03 01:14:42 PM PST 24 Jan 03 01:15:37 PM PST 24 40393298 ps
T813 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3787760910 Jan 03 01:12:59 PM PST 24 Jan 03 01:13:49 PM PST 24 369284478 ps
T814 /workspace/coverage/default/32.lc_ctrl_prog_failure.4097149671 Jan 03 01:14:22 PM PST 24 Jan 03 01:14:56 PM PST 24 233887458 ps
T815 /workspace/coverage/default/9.lc_ctrl_state_post_trans.915029201 Jan 03 01:12:45 PM PST 24 Jan 03 01:13:29 PM PST 24 90266732 ps
T816 /workspace/coverage/default/29.lc_ctrl_smoke.498755901 Jan 03 01:14:48 PM PST 24 Jan 03 01:15:49 PM PST 24 148071752 ps
T817 /workspace/coverage/default/1.lc_ctrl_smoke.1778879864 Jan 03 01:11:53 PM PST 24 Jan 03 01:12:33 PM PST 24 34641388 ps
T818 /workspace/coverage/default/6.lc_ctrl_state_post_trans.4109685065 Jan 03 01:12:04 PM PST 24 Jan 03 01:12:54 PM PST 24 54819469 ps
T819 /workspace/coverage/default/7.lc_ctrl_state_post_trans.3841207022 Jan 03 01:12:05 PM PST 24 Jan 03 01:12:55 PM PST 24 190092301 ps
T820 /workspace/coverage/default/25.lc_ctrl_prog_failure.2779929559 Jan 03 01:13:56 PM PST 24 Jan 03 01:14:22 PM PST 24 116068114 ps
T132 /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.3696249556 Jan 03 01:14:39 PM PST 24 Jan 03 01:24:27 PM PST 24 84428651086 ps
T87 /workspace/coverage/default/46.lc_ctrl_stress_all.2821669490 Jan 03 01:14:41 PM PST 24 Jan 03 01:19:17 PM PST 24 6445092240 ps
T821 /workspace/coverage/default/43.lc_ctrl_alert_test.630647767 Jan 03 01:14:53 PM PST 24 Jan 03 01:15:55 PM PST 24 44261056 ps
T822 /workspace/coverage/default/43.lc_ctrl_sec_mubi.216439738 Jan 03 01:14:48 PM PST 24 Jan 03 01:15:56 PM PST 24 275594961 ps
T823 /workspace/coverage/default/34.lc_ctrl_errors.2893002307 Jan 03 01:14:20 PM PST 24 Jan 03 01:14:57 PM PST 24 194108406 ps
T824 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3880682330 Jan 03 01:11:55 PM PST 24 Jan 03 01:12:43 PM PST 24 158571758 ps
T88 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.429698462 Jan 03 01:12:03 PM PST 24 Jan 03 01:13:09 PM PST 24 353532263 ps
T825 /workspace/coverage/default/8.lc_ctrl_errors.3296524064 Jan 03 01:12:08 PM PST 24 Jan 03 01:13:06 PM PST 24 381787742 ps
T826 /workspace/coverage/default/46.lc_ctrl_prog_failure.3006789253 Jan 03 01:14:43 PM PST 24 Jan 03 01:15:39 PM PST 24 332325400 ps
T827 /workspace/coverage/default/47.lc_ctrl_security_escalation.29670644 Jan 03 01:14:58 PM PST 24 Jan 03 01:16:09 PM PST 24 6381733444 ps
T828 /workspace/coverage/default/8.lc_ctrl_prog_failure.4289048377 Jan 03 01:12:12 PM PST 24 Jan 03 01:13:02 PM PST 24 95675740 ps
T829 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2836998102 Jan 03 01:12:06 PM PST 24 Jan 03 01:13:09 PM PST 24 637880640 ps
T830 /workspace/coverage/default/32.lc_ctrl_jtag_access.3777987747 Jan 03 01:14:34 PM PST 24 Jan 03 01:15:24 PM PST 24 5511035935 ps
T831 /workspace/coverage/default/37.lc_ctrl_prog_failure.1728088183 Jan 03 01:14:21 PM PST 24 Jan 03 01:14:54 PM PST 24 66126733 ps
T832 /workspace/coverage/default/2.lc_ctrl_smoke.1741470605 Jan 03 01:11:59 PM PST 24 Jan 03 01:12:39 PM PST 24 112996073 ps
T833 /workspace/coverage/default/35.lc_ctrl_prog_failure.4276123204 Jan 03 01:14:20 PM PST 24 Jan 03 01:14:55 PM PST 24 83642301 ps
T834 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1214721504 Jan 03 01:11:51 PM PST 24 Jan 03 01:12:31 PM PST 24 94851044 ps
T835 /workspace/coverage/default/38.lc_ctrl_security_escalation.3897784983 Jan 03 01:14:36 PM PST 24 Jan 03 01:15:35 PM PST 24 1683713760 ps
T836 /workspace/coverage/default/49.lc_ctrl_stress_all.3472068165 Jan 03 01:14:33 PM PST 24 Jan 03 01:17:16 PM PST 24 3952884996 ps
T837 /workspace/coverage/default/33.lc_ctrl_stress_all.3866504361 Jan 03 01:14:16 PM PST 24 Jan 03 01:15:05 PM PST 24 1399781652 ps
T838 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1500560400 Jan 03 01:14:00 PM PST 24 Jan 03 01:14:24 PM PST 24 32721810 ps
T839 /workspace/coverage/default/3.lc_ctrl_smoke.4175501403 Jan 03 01:11:55 PM PST 24 Jan 03 01:12:35 PM PST 24 41990781 ps
T840 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1325554811 Jan 03 01:14:02 PM PST 24 Jan 03 01:14:33 PM PST 24 237035235 ps
T841 /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.534326696 Jan 03 01:12:54 PM PST 24 Jan 03 01:14:20 PM PST 24 909262703 ps
T842 /workspace/coverage/default/13.lc_ctrl_jtag_access.242290520 Jan 03 01:12:54 PM PST 24 Jan 03 01:13:36 PM PST 24 221546406 ps
T843 /workspace/coverage/default/9.lc_ctrl_jtag_access.3633594364 Jan 03 01:12:53 PM PST 24 Jan 03 01:13:35 PM PST 24 1043319513 ps
T844 /workspace/coverage/default/28.lc_ctrl_state_post_trans.122524157 Jan 03 01:14:42 PM PST 24 Jan 03 01:15:43 PM PST 24 384632408 ps
T89 /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1232461599 Jan 03 01:11:57 PM PST 24 Jan 03 01:12:43 PM PST 24 879591904 ps
T845 /workspace/coverage/default/49.lc_ctrl_state_failure.1600706441 Jan 03 01:14:37 PM PST 24 Jan 03 01:15:47 PM PST 24 690448859 ps
T846 /workspace/coverage/default/17.lc_ctrl_state_failure.302820906 Jan 03 01:13:08 PM PST 24 Jan 03 01:14:22 PM PST 24 425477615 ps
T847 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3065041996 Jan 03 01:14:20 PM PST 24 Jan 03 01:15:01 PM PST 24 749448302 ps
T848 /workspace/coverage/default/22.lc_ctrl_smoke.2861029419 Jan 03 01:14:17 PM PST 24 Jan 03 01:14:49 PM PST 24 185217319 ps
T849 /workspace/coverage/default/7.lc_ctrl_prog_failure.2863447944 Jan 03 01:12:09 PM PST 24 Jan 03 01:13:00 PM PST 24 351738994 ps
T850 /workspace/coverage/default/29.lc_ctrl_alert_test.3050911337 Jan 03 01:13:57 PM PST 24 Jan 03 01:14:21 PM PST 24 21685455 ps
T851 /workspace/coverage/default/37.lc_ctrl_state_failure.3556297354 Jan 03 01:13:57 PM PST 24 Jan 03 01:14:58 PM PST 24 285898370 ps
T852 /workspace/coverage/default/36.lc_ctrl_alert_test.898363341 Jan 03 01:14:01 PM PST 24 Jan 03 01:14:26 PM PST 24 13884841 ps
T853 /workspace/coverage/default/42.lc_ctrl_security_escalation.3474598500 Jan 03 01:14:42 PM PST 24 Jan 03 01:15:43 PM PST 24 1098866214 ps
T854 /workspace/coverage/default/4.lc_ctrl_jtag_access.526799272 Jan 03 01:12:00 PM PST 24 Jan 03 01:12:44 PM PST 24 324427634 ps
T855 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2095963634 Jan 03 01:11:51 PM PST 24 Jan 03 01:12:29 PM PST 24 11923364 ps
T856 /workspace/coverage/default/35.lc_ctrl_smoke.2366482050 Jan 03 01:14:40 PM PST 24 Jan 03 01:15:32 PM PST 24 91001299 ps
T857 /workspace/coverage/default/44.lc_ctrl_jtag_access.2728397982 Jan 03 01:14:21 PM PST 24 Jan 03 01:15:00 PM PST 24 3033500133 ps
T858 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3030226642 Jan 03 01:13:02 PM PST 24 Jan 03 01:13:52 PM PST 24 1580501824 ps
T859 /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3306593455 Jan 03 01:13:56 PM PST 24 Jan 03 01:14:20 PM PST 24 11507745 ps
T860 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1615834825 Jan 03 01:12:01 PM PST 24 Jan 03 01:12:52 PM PST 24 1422447314 ps
T861 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.403228623 Jan 03 01:11:51 PM PST 24 Jan 03 01:12:38 PM PST 24 636285141 ps
T862 /workspace/coverage/default/21.lc_ctrl_jtag_access.2108282306 Jan 03 01:14:16 PM PST 24 Jan 03 01:14:45 PM PST 24 48311248 ps
T863 /workspace/coverage/default/28.lc_ctrl_errors.192516952 Jan 03 01:14:43 PM PST 24 Jan 03 01:15:47 PM PST 24 200071569 ps
T864 /workspace/coverage/default/30.lc_ctrl_security_escalation.3013442402 Jan 03 01:14:12 PM PST 24 Jan 03 01:14:50 PM PST 24 1936110489 ps
T865 /workspace/coverage/default/4.lc_ctrl_security_escalation.949775489 Jan 03 01:12:02 PM PST 24 Jan 03 01:12:54 PM PST 24 472063968 ps
T866 /workspace/coverage/default/15.lc_ctrl_stress_all.636060462 Jan 03 01:12:57 PM PST 24 Jan 03 01:15:51 PM PST 24 10619292420 ps
T76 /workspace/coverage/default/25.lc_ctrl_alert_test.1323984834 Jan 03 01:13:56 PM PST 24 Jan 03 01:14:20 PM PST 24 15985854 ps
T867 /workspace/coverage/default/41.lc_ctrl_sec_mubi.1432444922 Jan 03 01:14:32 PM PST 24 Jan 03 01:15:20 PM PST 24 212021704 ps
T868 /workspace/coverage/default/26.lc_ctrl_state_failure.2446765209 Jan 03 01:13:59 PM PST 24 Jan 03 01:14:36 PM PST 24 169131376 ps
T869 /workspace/coverage/default/40.lc_ctrl_security_escalation.1615906267 Jan 03 01:14:53 PM PST 24 Jan 03 01:16:01 PM PST 24 1752948254 ps
T870 /workspace/coverage/default/24.lc_ctrl_state_post_trans.3737953873 Jan 03 01:13:43 PM PST 24 Jan 03 01:14:21 PM PST 24 193526338 ps
T871 /workspace/coverage/default/31.lc_ctrl_smoke.2538587602 Jan 03 01:14:18 PM PST 24 Jan 03 01:14:48 PM PST 24 29787739 ps
T872 /workspace/coverage/default/30.lc_ctrl_jtag_access.1174844457 Jan 03 01:14:20 PM PST 24 Jan 03 01:14:53 PM PST 24 314683031 ps
T873 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3352405694 Jan 03 01:14:24 PM PST 24 Jan 03 01:15:11 PM PST 24 1646687964 ps
T874 /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1052119720 Jan 03 01:11:50 PM PST 24 Jan 03 01:12:34 PM PST 24 1657486007 ps
T875 /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2671348217 Jan 03 01:13:04 PM PST 24 Jan 03 01:20:15 PM PST 24 19492218074 ps
T876 /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1369857882 Jan 03 01:14:40 PM PST 24 Jan 03 01:15:31 PM PST 24 31720329 ps
T877 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1286584134 Jan 03 01:13:04 PM PST 24 Jan 03 01:13:52 PM PST 24 21124246 ps
T878 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1698568793 Jan 03 01:14:01 PM PST 24 Jan 03 01:14:32 PM PST 24 981451725 ps
T879 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.259635913 Jan 03 01:14:51 PM PST 24 Jan 03 01:15:58 PM PST 24 1150024306 ps
T880 /workspace/coverage/default/30.lc_ctrl_errors.1381921828 Jan 03 01:14:13 PM PST 24 Jan 03 01:14:55 PM PST 24 1285713972 ps
T881 /workspace/coverage/default/34.lc_ctrl_state_post_trans.2153169697 Jan 03 01:14:20 PM PST 24 Jan 03 01:15:01 PM PST 24 344837728 ps
T882 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.600105665 Jan 03 01:12:53 PM PST 24 Jan 03 01:13:49 PM PST 24 436530461 ps
T883 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.463210268 Jan 03 01:11:56 PM PST 24 Jan 03 01:12:36 PM PST 24 274956918 ps
T197 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2258078149 Jan 03 01:11:56 PM PST 24 Jan 03 01:12:36 PM PST 24 13780880 ps
T884 /workspace/coverage/default/27.lc_ctrl_state_failure.934050193 Jan 03 01:14:18 PM PST 24 Jan 03 01:15:12 PM PST 24 246576576 ps
T885 /workspace/coverage/default/1.lc_ctrl_jtag_access.1415170759 Jan 03 01:11:58 PM PST 24 Jan 03 01:12:44 PM PST 24 768833826 ps
T886 /workspace/coverage/default/21.lc_ctrl_security_escalation.3865482250 Jan 03 01:14:21 PM PST 24 Jan 03 01:14:58 PM PST 24 383731678 ps
T887 /workspace/coverage/default/3.lc_ctrl_sec_mubi.197367991 Jan 03 01:11:56 PM PST 24 Jan 03 01:12:44 PM PST 24 228332841 ps
T77 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2187285598 Jan 03 01:12:50 PM PST 24 Jan 03 01:13:36 PM PST 24 2076544834 ps
T888 /workspace/coverage/default/22.lc_ctrl_state_failure.3785658048 Jan 03 01:14:24 PM PST 24 Jan 03 01:15:17 PM PST 24 1081479262 ps
T889 /workspace/coverage/default/34.lc_ctrl_sec_mubi.129179070 Jan 03 01:14:20 PM PST 24 Jan 03 01:14:59 PM PST 24 1089768602 ps
T890 /workspace/coverage/default/17.lc_ctrl_stress_all.1241236476 Jan 03 01:13:00 PM PST 24 Jan 03 01:16:54 PM PST 24 5162038337 ps
T891 /workspace/coverage/default/11.lc_ctrl_stress_all.4203568197 Jan 03 01:12:31 PM PST 24 Jan 03 01:15:40 PM PST 24 4257158246 ps
T892 /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.278638611 Jan 03 01:12:00 PM PST 24 Jan 03 01:12:45 PM PST 24 850096699 ps
T893 /workspace/coverage/default/45.lc_ctrl_prog_failure.1501107111 Jan 03 01:14:36 PM PST 24 Jan 03 01:15:23 PM PST 24 222334402 ps
T894 /workspace/coverage/default/26.lc_ctrl_smoke.3688988690 Jan 03 01:14:14 PM PST 24 Jan 03 01:14:43 PM PST 24 42028057 ps
T895 /workspace/coverage/default/9.lc_ctrl_alert_test.3669017896 Jan 03 01:12:54 PM PST 24 Jan 03 01:13:34 PM PST 24 66235558 ps
T896 /workspace/coverage/default/49.lc_ctrl_sec_mubi.3887822737 Jan 03 01:14:42 PM PST 24 Jan 03 01:15:45 PM PST 24 478841910 ps
T897 /workspace/coverage/default/46.lc_ctrl_sec_mubi.3596832136 Jan 03 01:14:45 PM PST 24 Jan 03 01:15:48 PM PST 24 1020704392 ps
T52 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2106020728 Jan 03 01:14:36 PM PST 24 Jan 03 01:15:22 PM PST 24 13627549 ps
T898 /workspace/coverage/default/46.lc_ctrl_state_post_trans.2835820520 Jan 03 01:14:34 PM PST 24 Jan 03 01:15:24 PM PST 24 343782057 ps
T899 /workspace/coverage/default/30.lc_ctrl_stress_all.1460256057 Jan 03 01:14:16 PM PST 24 Jan 03 01:15:22 PM PST 24 2483247126 ps
T900 /workspace/coverage/default/31.lc_ctrl_state_post_trans.2635692510 Jan 03 01:14:35 PM PST 24 Jan 03 01:15:27 PM PST 24 233644044 ps
T901 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.725127117 Jan 03 01:14:39 PM PST 24 Jan 03 01:15:40 PM PST 24 1136730470 ps
T902 /workspace/coverage/default/10.lc_ctrl_jtag_access.3991047179 Jan 03 01:13:05 PM PST 24 Jan 03 01:13:55 PM PST 24 959179753 ps
T903 /workspace/coverage/default/2.lc_ctrl_jtag_errors.3033666715 Jan 03 01:11:52 PM PST 24 Jan 03 01:12:57 PM PST 24 6349451128 ps
T904 /workspace/coverage/default/23.lc_ctrl_stress_all.316845737 Jan 03 01:13:48 PM PST 24 Jan 03 01:16:02 PM PST 24 4840816397 ps
T905 /workspace/coverage/default/31.lc_ctrl_prog_failure.2380339731 Jan 03 01:14:34 PM PST 24 Jan 03 01:15:19 PM PST 24 34418984 ps
T906 /workspace/coverage/default/48.lc_ctrl_prog_failure.1719744783 Jan 03 01:14:15 PM PST 24 Jan 03 01:14:44 PM PST 24 61503465 ps
T907 /workspace/coverage/default/29.lc_ctrl_security_escalation.3427681178 Jan 03 01:14:18 PM PST 24 Jan 03 01:14:55 PM PST 24 1224388301 ps
T78 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2684380454 Jan 03 01:12:52 PM PST 24 Jan 03 01:13:36 PM PST 24 394347861 ps
T908 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2428156059 Jan 03 01:12:35 PM PST 24 Jan 03 01:13:33 PM PST 24 3513662216 ps
T909 /workspace/coverage/default/8.lc_ctrl_alert_test.1424332745 Jan 03 01:12:46 PM PST 24 Jan 03 01:13:27 PM PST 24 21305374 ps
T910 /workspace/coverage/default/38.lc_ctrl_sec_mubi.3174851534 Jan 03 01:14:22 PM PST 24 Jan 03 01:15:02 PM PST 24 1911531903 ps
T911 /workspace/coverage/default/7.lc_ctrl_alert_test.3177375275 Jan 03 01:12:07 PM PST 24 Jan 03 01:12:54 PM PST 24 26105527 ps
T912 /workspace/coverage/default/0.lc_ctrl_security_escalation.1041804906 Jan 03 01:11:45 PM PST 24 Jan 03 01:12:31 PM PST 24 224288322 ps
T913 /workspace/coverage/default/10.lc_ctrl_alert_test.4092478722 Jan 03 01:12:56 PM PST 24 Jan 03 01:13:36 PM PST 24 42941569 ps
T914 /workspace/coverage/default/7.lc_ctrl_stress_all.989172521 Jan 03 01:12:13 PM PST 24 Jan 03 01:14:45 PM PST 24 4467988894 ps
T915 /workspace/coverage/default/27.lc_ctrl_sec_mubi.206415213 Jan 03 01:14:41 PM PST 24 Jan 03 01:15:44 PM PST 24 2845844888 ps
T916 /workspace/coverage/default/45.lc_ctrl_stress_all.3245463630 Jan 03 01:14:43 PM PST 24 Jan 03 01:17:56 PM PST 24 8447306453 ps
T917 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3754654543 Jan 03 01:14:48 PM PST 24 Jan 03 01:15:57 PM PST 24 575291340 ps
T918 /workspace/coverage/default/34.lc_ctrl_stress_all.1975524735 Jan 03 01:14:21 PM PST 24 Jan 03 01:18:14 PM PST 24 7079074738 ps
T919 /workspace/coverage/default/37.lc_ctrl_smoke.928108181 Jan 03 01:13:59 PM PST 24 Jan 03 01:14:24 PM PST 24 47889275 ps
T920 /workspace/coverage/default/22.lc_ctrl_sec_mubi.297517750 Jan 03 01:14:22 PM PST 24 Jan 03 01:15:03 PM PST 24 384843603 ps
T122 /workspace/coverage/default/4.lc_ctrl_sec_cm.2758943209 Jan 03 01:12:05 PM PST 24 Jan 03 01:13:14 PM PST 24 1079148969 ps
T921 /workspace/coverage/default/22.lc_ctrl_state_post_trans.3846260458 Jan 03 01:14:34 PM PST 24 Jan 03 01:15:24 PM PST 24 87060552 ps
T922 /workspace/coverage/default/27.lc_ctrl_security_escalation.2241168061 Jan 03 01:14:23 PM PST 24 Jan 03 01:15:07 PM PST 24 1201517061 ps
T923 /workspace/coverage/default/2.lc_ctrl_alert_test.438076305 Jan 03 01:11:54 PM PST 24 Jan 03 01:12:33 PM PST 24 17855763 ps
T924 /workspace/coverage/default/16.lc_ctrl_jtag_errors.2329833166 Jan 03 01:12:54 PM PST 24 Jan 03 01:14:05 PM PST 24 1986676866 ps
T925 /workspace/coverage/default/0.lc_ctrl_state_post_trans.1840288768 Jan 03 01:11:48 PM PST 24 Jan 03 01:12:27 PM PST 24 86911014 ps
T926 /workspace/coverage/default/3.lc_ctrl_jtag_priority.3549505575 Jan 03 01:11:56 PM PST 24 Jan 03 01:12:36 PM PST 24 197230137 ps
T927 /workspace/coverage/default/12.lc_ctrl_state_post_trans.125699871 Jan 03 01:12:50 PM PST 24 Jan 03 01:13:32 PM PST 24 282857075 ps
T928 /workspace/coverage/default/25.lc_ctrl_state_failure.2678478745 Jan 03 01:13:43 PM PST 24 Jan 03 01:14:35 PM PST 24 200862837 ps
T929 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1738962899 Jan 03 01:12:56 PM PST 24 Jan 03 01:13:38 PM PST 24 190742668 ps
T930 /workspace/coverage/default/34.lc_ctrl_state_failure.1176141401 Jan 03 01:14:17 PM PST 24 Jan 03 01:15:14 PM PST 24 361631200 ps
T931 /workspace/coverage/default/20.lc_ctrl_state_failure.53207101 Jan 03 01:13:44 PM PST 24 Jan 03 01:14:42 PM PST 24 1349891874 ps
T932 /workspace/coverage/default/4.lc_ctrl_sec_mubi.346792500 Jan 03 01:12:01 PM PST 24 Jan 03 01:12:52 PM PST 24 312991089 ps
T933 /workspace/coverage/default/10.lc_ctrl_prog_failure.1380761592 Jan 03 01:12:55 PM PST 24 Jan 03 01:13:36 PM PST 24 996558139 ps
T934 /workspace/coverage/default/23.lc_ctrl_prog_failure.2446052517 Jan 03 01:14:23 PM PST 24 Jan 03 01:14:58 PM PST 24 113803526 ps
T935 /workspace/coverage/default/29.lc_ctrl_state_post_trans.577186117 Jan 03 01:14:53 PM PST 24 Jan 03 01:16:02 PM PST 24 78391985 ps
T936 /workspace/coverage/default/17.lc_ctrl_jtag_errors.3917423254 Jan 03 01:12:52 PM PST 24 Jan 03 01:13:54 PM PST 24 5273952642 ps
T937 /workspace/coverage/default/49.lc_ctrl_jtag_access.368955450 Jan 03 01:14:42 PM PST 24 Jan 03 01:15:42 PM PST 24 952198821 ps
T938 /workspace/coverage/default/38.lc_ctrl_smoke.546369828 Jan 03 01:14:33 PM PST 24 Jan 03 01:15:16 PM PST 24 125693617 ps
T939 /workspace/coverage/default/39.lc_ctrl_smoke.4106941008 Jan 03 01:14:46 PM PST 24 Jan 03 01:15:42 PM PST 24 13117186 ps
T940 /workspace/coverage/default/40.lc_ctrl_alert_test.702011948 Jan 03 01:14:19 PM PST 24 Jan 03 01:14:49 PM PST 24 59935330 ps
T941 /workspace/coverage/default/13.lc_ctrl_sec_mubi.2963627545 Jan 03 01:12:53 PM PST 24 Jan 03 01:13:46 PM PST 24 1746831420 ps
T942 /workspace/coverage/default/25.lc_ctrl_state_post_trans.1828146854 Jan 03 01:13:43 PM PST 24 Jan 03 01:14:20 PM PST 24 243669132 ps
T943 /workspace/coverage/default/45.lc_ctrl_jtag_access.3287743406 Jan 03 01:14:20 PM PST 24 Jan 03 01:15:03 PM PST 24 2382975931 ps
T944 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1011217395 Jan 03 01:13:08 PM PST 24 Jan 03 01:14:04 PM PST 24 515653606 ps
T945 /workspace/coverage/default/20.lc_ctrl_alert_test.3860065424 Jan 03 01:14:16 PM PST 24 Jan 03 01:14:45 PM PST 24 17024405 ps
T946 /workspace/coverage/default/36.lc_ctrl_state_post_trans.1118079287 Jan 03 01:14:45 PM PST 24 Jan 03 01:15:45 PM PST 24 94436116 ps
T947 /workspace/coverage/default/17.lc_ctrl_prog_failure.3069937320 Jan 03 01:13:02 PM PST 24 Jan 03 01:13:50 PM PST 24 271694497 ps
T948 /workspace/coverage/default/3.lc_ctrl_jtag_access.548522780 Jan 03 01:11:57 PM PST 24 Jan 03 01:12:44 PM PST 24 420068885 ps
T949 /workspace/coverage/default/36.lc_ctrl_security_escalation.1191461232 Jan 03 01:14:38 PM PST 24 Jan 03 01:15:34 PM PST 24 1575141300 ps
T950 /workspace/coverage/default/28.lc_ctrl_smoke.2887411711 Jan 03 01:14:40 PM PST 24 Jan 03 01:15:33 PM PST 24 51530014 ps
T951 /workspace/coverage/default/14.lc_ctrl_smoke.2171725985 Jan 03 01:12:49 PM PST 24 Jan 03 01:13:30 PM PST 24 25338330 ps
T952 /workspace/coverage/default/1.lc_ctrl_prog_failure.4251154627 Jan 03 01:11:53 PM PST 24 Jan 03 01:12:34 PM PST 24 126385013 ps
T953 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.895454327 Jan 03 01:13:09 PM PST 24 Jan 03 01:15:04 PM PST 24 27436368480 ps
T954 /workspace/coverage/default/20.lc_ctrl_errors.1498658110 Jan 03 01:13:45 PM PST 24 Jan 03 01:14:37 PM PST 24 8031375861 ps
T955 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.605779550 Jan 03 01:14:42 PM PST 24 Jan 03 01:15:42 PM PST 24 605718683 ps
T956 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4136667489 Jan 03 01:14:00 PM PST 24 Jan 03 01:14:24 PM PST 24 40176302 ps
T957 /workspace/coverage/default/8.lc_ctrl_jtag_errors.943496990 Jan 03 01:12:42 PM PST 24 Jan 03 01:13:50 PM PST 24 6602928780 ps
T958 /workspace/coverage/default/21.lc_ctrl_smoke.3458594814 Jan 03 01:14:01 PM PST 24 Jan 03 01:14:27 PM PST 24 11701072 ps
T959 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1692901622 Jan 03 01:11:51 PM PST 24 Jan 03 01:12:31 PM PST 24 2989805581 ps
T960 /workspace/coverage/default/46.lc_ctrl_state_failure.1194686626 Jan 03 01:14:36 PM PST 24 Jan 03 01:15:49 PM PST 24 194702917 ps
T961 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.946447252 Jan 03 01:14:18 PM PST 24 Jan 03 01:15:01 PM PST 24 318192797 ps
T962 /workspace/coverage/default/24.lc_ctrl_errors.1618566492 Jan 03 01:13:56 PM PST 24 Jan 03 01:14:38 PM PST 24 461626450 ps
T963 /workspace/coverage/default/23.lc_ctrl_alert_test.3045822217 Jan 03 01:13:54 PM PST 24 Jan 03 01:14:19 PM PST 24 79468249 ps
T964 /workspace/coverage/default/49.lc_ctrl_alert_test.1729300481 Jan 03 01:14:43 PM PST 24 Jan 03 01:15:38 PM PST 24 60488504 ps
T965 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.993203003 Jan 03 01:12:03 PM PST 24 Jan 03 01:12:49 PM PST 24 800611654 ps
T966 /workspace/coverage/default/11.lc_ctrl_jtag_access.1585789973 Jan 03 01:12:49 PM PST 24 Jan 03 01:13:40 PM PST 24 910670382 ps
T967 /workspace/coverage/default/5.lc_ctrl_sec_mubi.2571908490 Jan 03 01:11:59 PM PST 24 Jan 03 01:12:51 PM PST 24 998685845 ps
T968 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3890086350 Jan 03 01:12:50 PM PST 24 Jan 03 01:13:31 PM PST 24 29705216 ps
T969 /workspace/coverage/default/44.lc_ctrl_state_failure.1139557421 Jan 03 01:14:53 PM PST 24 Jan 03 01:16:24 PM PST 24 1002320845 ps
T970 /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1248254958 Jan 03 01:14:18 PM PST 24 Jan 03 01:14:57 PM PST 24 1184135331 ps
T971 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2006503990 Jan 03 01:14:38 PM PST 24 Jan 03 01:15:37 PM PST 24 387525005 ps
T972 /workspace/coverage/default/20.lc_ctrl_smoke.533841159 Jan 03 01:13:37 PM PST 24 Jan 03 01:14:13 PM PST 24 468079022 ps
T973 /workspace/coverage/default/30.lc_ctrl_smoke.42015521 Jan 03 01:13:59 PM PST 24 Jan 03 01:14:26 PM PST 24 412244296 ps
T974 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.402741549 Jan 03 01:12:08 PM PST 24 Jan 03 01:13:04 PM PST 24 416947460 ps
T975 /workspace/coverage/default/29.lc_ctrl_state_failure.2956366400 Jan 03 01:14:49 PM PST 24 Jan 03 01:16:13 PM PST 24 438713697 ps
T976 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.380806235 Jan 03 01:12:05 PM PST 24 Jan 03 01:12:52 PM PST 24 64584756 ps
T977 /workspace/coverage/default/36.lc_ctrl_jtag_access.1141849175 Jan 03 01:13:59 PM PST 24 Jan 03 01:14:25 PM PST 24 66158644 ps
T978 /workspace/coverage/default/0.lc_ctrl_jtag_priority.96269856 Jan 03 01:11:51 PM PST 24 Jan 03 01:12:31 PM PST 24 106868547 ps
T979 /workspace/coverage/default/9.lc_ctrl_errors.879183987 Jan 03 01:12:45 PM PST 24 Jan 03 01:13:45 PM PST 24 2066168582 ps
T980 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.835677175 Jan 03 01:11:57 PM PST 24 Jan 03 01:12:36 PM PST 24 24856930 ps
T981 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1258015933 Jan 03 01:12:50 PM PST 24 Jan 03 01:13:41 PM PST 24 2757889202 ps
T982 /workspace/coverage/default/40.lc_ctrl_sec_mubi.1713573800 Jan 03 01:14:53 PM PST 24 Jan 03 01:16:06 PM PST 24 305991053 ps
T983 /workspace/coverage/default/12.lc_ctrl_jtag_access.951139667 Jan 03 01:12:54 PM PST 24 Jan 03 01:13:35 PM PST 24 145840467 ps
T984 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3979973564 Jan 03 01:01:46 PM PST 24 Jan 03 01:03:01 PM PST 24 18667607 ps

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4247843035
Short name T64
Test name
Test status
Simulation time 5959650469 ps
CPU time 9.88 seconds
Started Jan 03 01:01:45 PM PST 24
Finished Jan 03 01:03:07 PM PST 24
Peak memory 208196 kb
Host smart-972222df-9559-454e-8c70-fd2a4977019c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247843035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4247843035
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.322787921
Short name T4
Test name
Test status
Simulation time 5266676287 ps
CPU time 156.36 seconds
Started Jan 03 01:12:06 PM PST 24
Finished Jan 03 01:15:28 PM PST 24
Peak memory 271756 kb
Host smart-9a1b2318-9d8d-4069-99df-7cbe7564443f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322787921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.322787921
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.768240898
Short name T102
Test name
Test status
Simulation time 96964822 ps
CPU time 2.7 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 217640 kb
Host smart-d513ead0-488f-475f-b68a-aa48ac9df7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768240898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.768240898
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.542636963
Short name T137
Test name
Test status
Simulation time 50430904 ps
CPU time 2.42 seconds
Started Jan 03 01:01:40 PM PST 24
Finished Jan 03 01:02:54 PM PST 24
Peak memory 220356 kb
Host smart-a34b37a9-7a0c-4f5b-b057-0555a46dcb9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542636
963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.542636963
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3247676966
Short name T53
Test name
Test status
Simulation time 251823961 ps
CPU time 8.09 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:48 PM PST 24
Peak memory 218188 kb
Host smart-016cdb56-d009-451a-8d0a-e5d4609e0dbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247676966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3247676966
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.4007303244
Short name T59
Test name
Test status
Simulation time 41311633429 ps
CPU time 748.21 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:25:00 PM PST 24
Peak memory 287332 kb
Host smart-09dfb607-322b-49a0-b475-c7cba7b1cf8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4007303244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.4007303244
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3313992517
Short name T111
Test name
Test status
Simulation time 80469093 ps
CPU time 1.2 seconds
Started Jan 03 01:02:01 PM PST 24
Finished Jan 03 01:03:11 PM PST 24
Peak memory 218768 kb
Host smart-43b62722-eb77-4f03-a6ac-ca04aafdf64d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313992517 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3313992517
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.216141542
Short name T14
Test name
Test status
Simulation time 410048913 ps
CPU time 10.78 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:15:03 PM PST 24
Peak memory 218156 kb
Host smart-7e974d80-770d-499a-b7eb-847e888689df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216141542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.216141542
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1142878642
Short name T104
Test name
Test status
Simulation time 84332108 ps
CPU time 1.58 seconds
Started Jan 03 01:01:53 PM PST 24
Finished Jan 03 01:03:05 PM PST 24
Peak memory 210744 kb
Host smart-d4504daf-f38c-4f58-bfbd-c5079228d50c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142878642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1142878642
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3934651544
Short name T135
Test name
Test status
Simulation time 45660088 ps
CPU time 3.35 seconds
Started Jan 03 01:01:54 PM PST 24
Finished Jan 03 01:03:09 PM PST 24
Peak memory 216944 kb
Host smart-941734ee-15d1-48da-9c48-0329de473dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934651544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3934651544
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.383836087
Short name T39
Test name
Test status
Simulation time 12046938 ps
CPU time 0.93 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:27 PM PST 24
Peak memory 208376 kb
Host smart-0f67de5d-7360-46d3-be4a-94d7ffcd9e72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383836087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.383836087
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3374524515
Short name T3
Test name
Test status
Simulation time 1346604600 ps
CPU time 11.65 seconds
Started Jan 03 01:12:44 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 218108 kb
Host smart-0efb8775-6af7-44ee-82c4-2429cd314401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374524515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
374524515
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3286020257
Short name T100
Test name
Test status
Simulation time 27416900 ps
CPU time 0.86 seconds
Started Jan 03 01:02:02 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 209056 kb
Host smart-6bda3b9d-c304-4763-a143-09c33fa72a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286020257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3286020257
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.460672582
Short name T37
Test name
Test status
Simulation time 5110211851 ps
CPU time 171.86 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:15:23 PM PST 24
Peak memory 284044 kb
Host smart-01f2ea4d-8480-40f4-8c7e-2865c5651e5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460672582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.460672582
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3893812362
Short name T108
Test name
Test status
Simulation time 114329039 ps
CPU time 23.98 seconds
Started Jan 03 01:11:52 PM PST 24
Finished Jan 03 01:12:53 PM PST 24
Peak memory 268116 kb
Host smart-7e833c96-e190-4d17-9a21-a31442797af0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893812362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3893812362
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3547216484
Short name T90
Test name
Test status
Simulation time 1366568400 ps
CPU time 9.84 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 218228 kb
Host smart-a2420ba1-d1bf-4e06-b5c0-5a4631300c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547216484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3547216484
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1613385718
Short name T144
Test name
Test status
Simulation time 109244251 ps
CPU time 2.9 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 222104 kb
Host smart-4dd59e71-a310-4204-bd95-9df215cc34d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613385718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1613385718
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1074236961
Short name T54
Test name
Test status
Simulation time 21598529536 ps
CPU time 176.44 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:18:30 PM PST 24
Peak memory 270428 kb
Host smart-a24f4951-f49f-4c5e-b11d-5e14f2968ff3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074236961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1074236961
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2469869320
Short name T178
Test name
Test status
Simulation time 14588980 ps
CPU time 0.93 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 209652 kb
Host smart-004cf66f-79fc-41b9-8323-f73dd54ee77b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469869320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2469869320
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3560875561
Short name T327
Test name
Test status
Simulation time 65015638 ps
CPU time 1.04 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:31 PM PST 24
Peak memory 209716 kb
Host smart-000e9df6-0b5f-4649-a201-d268fa639856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560875561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3560875561
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.776794890
Short name T57
Test name
Test status
Simulation time 435828020 ps
CPU time 17.53 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:15:12 PM PST 24
Peak memory 219260 kb
Host smart-67891279-7073-4145-bce0-ea6184e2f740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776794890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.776794890
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1209753831
Short name T23
Test name
Test status
Simulation time 968463245 ps
CPU time 7.06 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 209648 kb
Host smart-8125b9b8-95b6-4e1d-827b-cdeac30a3783
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209753831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.1209753831
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1817955073
Short name T151
Test name
Test status
Simulation time 725310121 ps
CPU time 3.15 seconds
Started Jan 03 01:02:04 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 221900 kb
Host smart-52c8ccc7-6390-4469-bda6-d8faae4a2424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817955073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1817955073
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3553016366
Short name T148
Test name
Test status
Simulation time 81530921 ps
CPU time 2.54 seconds
Started Jan 03 01:02:05 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 221612 kb
Host smart-0cf58c88-2e8c-4ef3-b884-692a79bf2b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553016366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3553016366
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4067135977
Short name T51
Test name
Test status
Simulation time 24538541 ps
CPU time 0.92 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:32 PM PST 24
Peak memory 208344 kb
Host smart-3b5549b0-4e1e-40c2-8993-737208a6c5bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067135977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4067135977
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3185028612
Short name T65
Test name
Test status
Simulation time 19888336118 ps
CPU time 171.79 seconds
Started Jan 03 01:13:44 PM PST 24
Finished Jan 03 01:17:04 PM PST 24
Peak memory 283936 kb
Host smart-39fb399f-58c8-4805-8cfe-a9fd80c84be5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185028612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3185028612
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.791372022
Short name T149
Test name
Test status
Simulation time 47376520 ps
CPU time 1.73 seconds
Started Jan 03 01:02:11 PM PST 24
Finished Jan 03 01:03:18 PM PST 24
Peak memory 220976 kb
Host smart-1cb09021-8e3f-4ffe-ba1c-c767f2a23167
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791372022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.791372022
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.869178573
Short name T381
Test name
Test status
Simulation time 14450893 ps
CPU time 0.95 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:33 PM PST 24
Peak memory 208448 kb
Host smart-8ccf1479-1297-415e-8bfd-7d3b1615b4aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869178573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.869178573
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3939752073
Short name T136
Test name
Test status
Simulation time 49406458 ps
CPU time 2.93 seconds
Started Jan 03 01:02:05 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 218740 kb
Host smart-9460116c-b912-4ef8-bc2f-d512e753eabf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939752073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3939752073
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2893188620
Short name T153
Test name
Test status
Simulation time 102693216 ps
CPU time 1.88 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 221744 kb
Host smart-fcaf4fa7-42fb-4935-b1ed-74f129eecd78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893188620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2893188620
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1959643806
Short name T152
Test name
Test status
Simulation time 126639029 ps
CPU time 3.56 seconds
Started Jan 03 01:02:03 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 221440 kb
Host smart-04d091e7-78d2-4761-a99b-18e4841d5337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959643806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1959643806
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3230247364
Short name T195
Test name
Test status
Simulation time 35264623 ps
CPU time 0.92 seconds
Started Jan 03 01:11:48 PM PST 24
Finished Jan 03 01:12:25 PM PST 24
Peak memory 209612 kb
Host smart-9229a578-d047-4050-8a59-2cce7e6d7f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230247364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3230247364
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2258078149
Short name T197
Test name
Test status
Simulation time 13780880 ps
CPU time 0.85 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:36 PM PST 24
Peak memory 209452 kb
Host smart-e9f7b570-6e0a-4261-95d7-6d0186fa18b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258078149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2258078149
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1209836473
Short name T194
Test name
Test status
Simulation time 20079879 ps
CPU time 0.9 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:47 PM PST 24
Peak memory 209664 kb
Host smart-44701bf4-77f5-41e6-96bc-bea9e9b0789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209836473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1209836473
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3616345184
Short name T167
Test name
Test status
Simulation time 709823879 ps
CPU time 4.53 seconds
Started Jan 03 01:01:42 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 209464 kb
Host smart-6c027f10-abd0-49ae-be0c-571e87045337
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616345184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3616345184
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1210076938
Short name T146
Test name
Test status
Simulation time 117434053 ps
CPU time 4.24 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:03 PM PST 24
Peak memory 217836 kb
Host smart-e8326696-2677-44ec-9b19-ba4448e3b0ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210076938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1210076938
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2992122694
Short name T155
Test name
Test status
Simulation time 69830956 ps
CPU time 2.69 seconds
Started Jan 03 01:01:50 PM PST 24
Finished Jan 03 01:03:04 PM PST 24
Peak memory 217752 kb
Host smart-31ff1652-d468-47c3-9a72-35e286c1fbb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992122694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2992122694
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1853821950
Short name T147
Test name
Test status
Simulation time 519438248 ps
CPU time 2.72 seconds
Started Jan 03 01:01:37 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 221820 kb
Host smart-5e1bc46f-341b-43a6-93ee-4caf8c46810d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853821950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1853821950
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3624130809
Short name T62
Test name
Test status
Simulation time 347961318 ps
CPU time 11.47 seconds
Started Jan 03 01:13:09 PM PST 24
Finished Jan 03 01:14:07 PM PST 24
Peak memory 218260 kb
Host smart-5f6aff00-ee6d-432e-9b88-8b78ac12afb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624130809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3624130809
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2197155205
Short name T110
Test name
Test status
Simulation time 40065413 ps
CPU time 1.48 seconds
Started Jan 03 01:01:32 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 211284 kb
Host smart-4858c230-d088-429e-b7ed-832c3d7460d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197155205 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2197155205
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3167513912
Short name T93
Test name
Test status
Simulation time 42936560 ps
CPU time 1.69 seconds
Started Jan 03 01:11:48 PM PST 24
Finished Jan 03 01:12:25 PM PST 24
Peak memory 218280 kb
Host smart-c40dcc95-fd9a-4748-9cfd-534aea88a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167513912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3167513912
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3515602218
Short name T208
Test name
Test status
Simulation time 49087159 ps
CPU time 1.49 seconds
Started Jan 03 01:01:42 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 217900 kb
Host smart-deeda359-fcad-4038-9624-a3cb1c4508a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351560
2218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3515602218
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1254262567
Short name T139
Test name
Test status
Simulation time 119229671 ps
CPU time 1.01 seconds
Started Jan 03 01:01:36 PM PST 24
Finished Jan 03 01:02:49 PM PST 24
Peak memory 209504 kb
Host smart-a88b144a-01f8-477f-8d65-3eb4c0e43721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254262567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1254262567
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1617473231
Short name T184
Test name
Test status
Simulation time 111561438 ps
CPU time 0.89 seconds
Started Jan 03 01:01:36 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 208360 kb
Host smart-49b68a75-b2fb-4ee2-9c8a-3d26051695e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617473231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1617473231
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2914503217
Short name T256
Test name
Test status
Simulation time 62636559 ps
CPU time 1.11 seconds
Started Jan 03 01:01:31 PM PST 24
Finished Jan 03 01:02:44 PM PST 24
Peak memory 209540 kb
Host smart-93e3f6fd-b36f-4cd2-ad08-34d300c56b97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914503217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2914503217
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.753881837
Short name T171
Test name
Test status
Simulation time 98414963 ps
CPU time 1.17 seconds
Started Jan 03 01:01:30 PM PST 24
Finished Jan 03 01:02:41 PM PST 24
Peak memory 211512 kb
Host smart-f087a71f-28ac-44f3-94b3-42c548349b7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753881837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.753881837
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1953325905
Short name T276
Test name
Test status
Simulation time 14033127 ps
CPU time 1.14 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 217940 kb
Host smart-af0929dd-fa8b-4b56-b2d8-9014a90d863e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953325905 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1953325905
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.801022504
Short name T158
Test name
Test status
Simulation time 16391221 ps
CPU time 1.07 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 209548 kb
Host smart-0804594a-4115-4046-aee3-4c0dd7c38ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801022504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.801022504
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2927222077
Short name T274
Test name
Test status
Simulation time 32488594 ps
CPU time 0.92 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 207812 kb
Host smart-a3ff50b3-8044-40a1-9d2b-1eacfac3c69d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927222077 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2927222077
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1511858572
Short name T239
Test name
Test status
Simulation time 5872830909 ps
CPU time 33.69 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 208420 kb
Host smart-6f30fee5-7597-443f-a765-eaa864664e00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511858572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1511858572
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.534818385
Short name T289
Test name
Test status
Simulation time 2474683127 ps
CPU time 4.38 seconds
Started Jan 03 01:01:42 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 210988 kb
Host smart-1d2d283c-0888-4fea-838e-6ed33ec89acd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534818385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.534818385
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.404991354
Short name T295
Test name
Test status
Simulation time 75761763 ps
CPU time 2.2 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 209404 kb
Host smart-551ebc9e-ed13-4403-a270-90d9ab11ed31
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404991354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.404991354
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2164589509
Short name T228
Test name
Test status
Simulation time 191071411 ps
CPU time 2.02 seconds
Started Jan 03 01:01:34 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 209548 kb
Host smart-32126705-1c26-4502-9c5e-b798c9b838ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164589509 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2164589509
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.661154450
Short name T272
Test name
Test status
Simulation time 99527183 ps
CPU time 2.36 seconds
Started Jan 03 01:01:41 PM PST 24
Finished Jan 03 01:02:56 PM PST 24
Peak memory 217700 kb
Host smart-5cf8b849-3e6e-4b86-a1ad-afcbe7a02bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661154450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.661154450
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2213445222
Short name T156
Test name
Test status
Simulation time 44867286 ps
CPU time 1.83 seconds
Started Jan 03 01:01:42 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 221560 kb
Host smart-aa568836-a9e1-4755-9bf4-25273eb9a0a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213445222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2213445222
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3914445112
Short name T175
Test name
Test status
Simulation time 59082435 ps
CPU time 1.24 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 209540 kb
Host smart-3b377276-aa16-4bc2-a1b9-7ca2454038e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914445112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3914445112
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.959628146
Short name T291
Test name
Test status
Simulation time 29374401 ps
CPU time 1.43 seconds
Started Jan 03 01:01:33 PM PST 24
Finished Jan 03 01:02:46 PM PST 24
Peak memory 209612 kb
Host smart-078d8601-bfb6-4dd1-b2fd-5e68568a76ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959628146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.959628146
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4172769738
Short name T182
Test name
Test status
Simulation time 50779708 ps
CPU time 1.08 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 210224 kb
Host smart-cca01eea-6775-488b-87a9-9bf4180bd213
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172769738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.4172769738
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2306513156
Short name T218
Test name
Test status
Simulation time 48783511 ps
CPU time 1.36 seconds
Started Jan 03 01:01:36 PM PST 24
Finished Jan 03 01:02:49 PM PST 24
Peak memory 219252 kb
Host smart-8044a7e0-a14f-4206-ba4f-2aeb15bc753a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306513156 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2306513156
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1928661020
Short name T174
Test name
Test status
Simulation time 13213546 ps
CPU time 0.93 seconds
Started Jan 03 01:01:40 PM PST 24
Finished Jan 03 01:02:54 PM PST 24
Peak memory 209516 kb
Host smart-113e93ba-43f3-4aed-b25a-90cdad277b57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928661020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1928661020
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1647424479
Short name T292
Test name
Test status
Simulation time 107593552 ps
CPU time 1.75 seconds
Started Jan 03 01:01:31 PM PST 24
Finished Jan 03 01:02:44 PM PST 24
Peak memory 209436 kb
Host smart-3def6770-4e1d-40c6-8ff0-7b3085c3f952
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647424479 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1647424479
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1310911133
Short name T219
Test name
Test status
Simulation time 3100395942 ps
CPU time 7.47 seconds
Started Jan 03 01:01:42 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 209520 kb
Host smart-a887cfa8-e520-4175-b794-3bb8ad555a8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310911133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1310911133
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3696936156
Short name T157
Test name
Test status
Simulation time 686073007 ps
CPU time 7.55 seconds
Started Jan 03 01:01:49 PM PST 24
Finished Jan 03 01:03:08 PM PST 24
Peak memory 209460 kb
Host smart-24204159-ed27-4ad3-9d19-96971952e25c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696936156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3696936156
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.68804902
Short name T254
Test name
Test status
Simulation time 159971319 ps
CPU time 2.83 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:58 PM PST 24
Peak memory 218288 kb
Host smart-9b231533-e4a8-46d2-aaab-915461cbb505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688049
02 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.68804902
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1172195433
Short name T210
Test name
Test status
Simulation time 39007553 ps
CPU time 1.1 seconds
Started Jan 03 01:01:49 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 209380 kb
Host smart-f53870f0-0de1-4e97-a14c-402d8fadb46b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172195433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1172195433
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.355014736
Short name T285
Test name
Test status
Simulation time 48797122 ps
CPU time 1.94 seconds
Started Jan 03 01:01:32 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 211384 kb
Host smart-a5c0086e-90c2-47ee-a3a8-a48f99e6801b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355014736 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.355014736
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.806359299
Short name T235
Test name
Test status
Simulation time 20394726 ps
CPU time 1.16 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 211188 kb
Host smart-f179b67c-9bd0-48cf-8893-4fa9e14fd3aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806359299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.806359299
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1654383150
Short name T141
Test name
Test status
Simulation time 35018713 ps
CPU time 2.16 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 218752 kb
Host smart-a970ef2f-8aaa-4870-9cac-63049089c9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654383150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1654383150
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1736382431
Short name T215
Test name
Test status
Simulation time 47922525 ps
CPU time 1.81 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 221144 kb
Host smart-f7525918-4db3-4bb9-9fc8-8fcdcccedd0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736382431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1736382431
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4190851790
Short name T233
Test name
Test status
Simulation time 88807185 ps
CPU time 1.55 seconds
Started Jan 03 01:02:02 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 219196 kb
Host smart-a0ab503d-e963-4af7-ace9-0d9aa89eb778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190851790 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4190851790
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1778266177
Short name T282
Test name
Test status
Simulation time 38335523 ps
CPU time 0.77 seconds
Started Jan 03 01:02:05 PM PST 24
Finished Jan 03 01:03:14 PM PST 24
Peak memory 209348 kb
Host smart-b3c71c96-5463-4be7-b11b-30a970266486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778266177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1778266177
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1805207505
Short name T243
Test name
Test status
Simulation time 136536476 ps
CPU time 1.65 seconds
Started Jan 03 01:02:02 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 209456 kb
Host smart-901b0a20-55ed-446b-8422-368d5051ca9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805207505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1805207505
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2037407768
Short name T273
Test name
Test status
Simulation time 118233446 ps
CPU time 1.89 seconds
Started Jan 03 01:02:02 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 217556 kb
Host smart-4e4f832d-7ac5-4228-b6bc-1661e69f7e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037407768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2037407768
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4088511458
Short name T115
Test name
Test status
Simulation time 222906436 ps
CPU time 2.5 seconds
Started Jan 03 01:02:07 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 217672 kb
Host smart-fa927d84-237f-4edd-bedf-2e54e0371bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088511458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.4088511458
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.17879421
Short name T277
Test name
Test status
Simulation time 88956863 ps
CPU time 1.46 seconds
Started Jan 03 01:02:08 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 219176 kb
Host smart-ad71ba02-71a6-42a9-a3e3-95c3278084d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17879421 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.17879421
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3430468008
Short name T287
Test name
Test status
Simulation time 20152500 ps
CPU time 0.82 seconds
Started Jan 03 01:02:08 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 209400 kb
Host smart-5d732706-97d8-4e50-8534-3f55c2720ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430468008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3430468008
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2374328508
Short name T264
Test name
Test status
Simulation time 91429994 ps
CPU time 1.19 seconds
Started Jan 03 01:02:03 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 209468 kb
Host smart-2eaaa07b-6cc1-4245-92a7-f81d08a21af2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374328508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2374328508
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3055126881
Short name T269
Test name
Test status
Simulation time 647044604 ps
CPU time 3.24 seconds
Started Jan 03 01:02:07 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 217616 kb
Host smart-2c185b9f-f4c8-40d0-aace-2f25e6e00c88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055126881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3055126881
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.17978681
Short name T154
Test name
Test status
Simulation time 186096942 ps
CPU time 1.89 seconds
Started Jan 03 01:02:09 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 221612 kb
Host smart-ab99f042-0613-4766-9826-f846357612dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17978681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_e
rr.17978681
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.851984471
Short name T281
Test name
Test status
Simulation time 95472661 ps
CPU time 1.23 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 219200 kb
Host smart-834b6bc3-c26a-4b5a-adce-a68f5efad991
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851984471 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.851984471
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1646544009
Short name T296
Test name
Test status
Simulation time 42101113 ps
CPU time 0.92 seconds
Started Jan 03 01:02:10 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 208924 kb
Host smart-67b13c22-7e3b-40d2-ac7b-82a7f7577678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646544009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1646544009
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.45436795
Short name T290
Test name
Test status
Simulation time 122592457 ps
CPU time 1.26 seconds
Started Jan 03 01:02:10 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 211316 kb
Host smart-a276ec23-4a8c-43d6-b514-c628b6fa3b9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45436795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
same_csr_outstanding.45436795
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2263822259
Short name T138
Test name
Test status
Simulation time 85231248 ps
CPU time 2.73 seconds
Started Jan 03 01:02:15 PM PST 24
Finished Jan 03 01:03:24 PM PST 24
Peak memory 217676 kb
Host smart-146fff65-fc3c-40e0-9fb5-037948b7b71d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263822259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2263822259
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2439101186
Short name T101
Test name
Test status
Simulation time 86739613 ps
CPU time 1.13 seconds
Started Jan 03 01:02:04 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 217684 kb
Host smart-ee2f57cd-1073-4ad3-a9cf-93ac564f61cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439101186 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2439101186
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2026743223
Short name T118
Test name
Test status
Simulation time 57185168 ps
CPU time 1.11 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:14 PM PST 24
Peak memory 209580 kb
Host smart-e96a53bb-17a0-4748-95dd-2d24a530d5aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026743223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2026743223
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3926460210
Short name T187
Test name
Test status
Simulation time 154905651 ps
CPU time 1.46 seconds
Started Jan 03 01:02:04 PM PST 24
Finished Jan 03 01:03:14 PM PST 24
Peak memory 217620 kb
Host smart-8145a422-1105-4cd2-ba96-7b2595954684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926460210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3926460210
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3216634605
Short name T240
Test name
Test status
Simulation time 37428779 ps
CPU time 0.82 seconds
Started Jan 03 01:02:01 PM PST 24
Finished Jan 03 01:03:11 PM PST 24
Peak memory 209380 kb
Host smart-e4e459f4-4544-4f1a-9370-2c1b501b22f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216634605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3216634605
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2776178266
Short name T170
Test name
Test status
Simulation time 101077145 ps
CPU time 1.42 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 209548 kb
Host smart-0441435f-abd6-4996-ab5a-56eeaf8f97a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776178266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2776178266
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2928450768
Short name T250
Test name
Test status
Simulation time 81150756 ps
CPU time 1.76 seconds
Started Jan 03 01:02:03 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 217752 kb
Host smart-607fb4ff-fbeb-49ec-9627-e773bbb4915f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928450768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2928450768
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.236273839
Short name T203
Test name
Test status
Simulation time 41200824 ps
CPU time 1.24 seconds
Started Jan 03 01:02:04 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 217952 kb
Host smart-d879aa51-8713-4376-9884-51bd4fab74c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236273839 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.236273839
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4147122256
Short name T225
Test name
Test status
Simulation time 56011038 ps
CPU time 0.88 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 209476 kb
Host smart-b957ca0f-0eeb-46c0-86ff-000cd460369e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147122256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.4147122256
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3584158199
Short name T176
Test name
Test status
Simulation time 23645434 ps
CPU time 1.23 seconds
Started Jan 03 01:02:09 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 209676 kb
Host smart-651dfd74-c927-41d2-bdb2-cc7a34a3d6d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584158199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3584158199
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2950742863
Short name T253
Test name
Test status
Simulation time 28246525 ps
CPU time 1.87 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 217704 kb
Host smart-584fbf94-75da-45c3-99e1-a20be687491d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950742863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2950742863
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.263013953
Short name T193
Test name
Test status
Simulation time 79564761 ps
CPU time 1.19 seconds
Started Jan 03 01:02:09 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 219200 kb
Host smart-0e52d701-0b1a-47ae-af0c-c4804487e5ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263013953 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.263013953
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3032062656
Short name T169
Test name
Test status
Simulation time 189863713 ps
CPU time 1.02 seconds
Started Jan 03 01:02:01 PM PST 24
Finished Jan 03 01:03:11 PM PST 24
Peak memory 209564 kb
Host smart-f4c73194-842e-40e5-b3f9-c1fbbf6cadb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032062656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3032062656
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3311731775
Short name T205
Test name
Test status
Simulation time 17322722 ps
CPU time 1.06 seconds
Started Jan 03 01:02:03 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 209556 kb
Host smart-ffd3635f-61be-4eda-af22-184cb8dd18f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311731775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3311731775
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3157670334
Short name T172
Test name
Test status
Simulation time 211068691 ps
CPU time 1.57 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 217608 kb
Host smart-346d7989-e534-4c73-8800-c53c4dac675c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157670334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3157670334
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.4143433860
Short name T236
Test name
Test status
Simulation time 24278613 ps
CPU time 1.3 seconds
Started Jan 03 01:02:02 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 219104 kb
Host smart-5567c821-4b8c-4613-9843-409e79e25829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143433860 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.4143433860
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3176470602
Short name T301
Test name
Test status
Simulation time 47970719 ps
CPU time 0.82 seconds
Started Jan 03 01:02:02 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 209412 kb
Host smart-40c53ef9-4117-4d3f-9878-19bc216e4e86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176470602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3176470602
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3846736321
Short name T303
Test name
Test status
Simulation time 124344335 ps
CPU time 1.11 seconds
Started Jan 03 01:02:08 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 209556 kb
Host smart-6ad66cd3-4ecd-406a-9282-9c02b988dac8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846736321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3846736321
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1372885188
Short name T286
Test name
Test status
Simulation time 32038509 ps
CPU time 1.8 seconds
Started Jan 03 01:02:03 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 217812 kb
Host smart-d949dd09-d2db-483f-8ede-c9e280b4dd25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372885188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1372885188
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2082539700
Short name T294
Test name
Test status
Simulation time 66104612 ps
CPU time 1.5 seconds
Started Jan 03 01:02:16 PM PST 24
Finished Jan 03 01:03:23 PM PST 24
Peak memory 217796 kb
Host smart-b94da475-55da-4ff5-a5ee-957658300d9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082539700 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2082539700
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3370516840
Short name T280
Test name
Test status
Simulation time 28280457 ps
CPU time 0.83 seconds
Started Jan 03 01:02:03 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 208984 kb
Host smart-0932b793-0909-4804-a4b0-1078f5e3ce3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370516840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3370516840
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.603698725
Short name T260
Test name
Test status
Simulation time 52811062 ps
CPU time 0.99 seconds
Started Jan 03 01:02:02 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 209532 kb
Host smart-b5e2f47e-2031-498f-a429-2d0f376f952a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603698725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.603698725
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3211028909
Short name T112
Test name
Test status
Simulation time 67292849 ps
CPU time 2.5 seconds
Started Jan 03 01:02:07 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 217712 kb
Host smart-10f1e41e-18a7-49e9-af32-d56e9e11325d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211028909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3211028909
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.378801909
Short name T97
Test name
Test status
Simulation time 63498263 ps
CPU time 1.54 seconds
Started Jan 03 01:02:10 PM PST 24
Finished Jan 03 01:03:18 PM PST 24
Peak memory 219008 kb
Host smart-36f0d3b6-919b-4b16-9d3c-87e691589e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378801909 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.378801909
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.894502983
Short name T140
Test name
Test status
Simulation time 16799559 ps
CPU time 0.84 seconds
Started Jan 03 01:02:06 PM PST 24
Finished Jan 03 01:03:14 PM PST 24
Peak memory 208612 kb
Host smart-26750dd7-4985-4e94-8990-4b071a24bbdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894502983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.894502983
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3256723760
Short name T120
Test name
Test status
Simulation time 92291068 ps
CPU time 1.1 seconds
Started Jan 03 01:02:05 PM PST 24
Finished Jan 03 01:03:14 PM PST 24
Peak memory 209464 kb
Host smart-1bd08f5a-dae7-4f73-8dd6-3bf3933ab7e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256723760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3256723760
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1083983642
Short name T247
Test name
Test status
Simulation time 22917801 ps
CPU time 1.41 seconds
Started Jan 03 01:02:09 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 217668 kb
Host smart-2fc5f56d-a600-4d40-9032-082aa254ca84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083983642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1083983642
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1101278466
Short name T189
Test name
Test status
Simulation time 84334248 ps
CPU time 0.98 seconds
Started Jan 03 01:01:49 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 208484 kb
Host smart-9edb3a72-6030-4b6f-802d-725915130e72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101278466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1101278466
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.151671265
Short name T214
Test name
Test status
Simulation time 28006999 ps
CPU time 1.44 seconds
Started Jan 03 01:01:49 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 209572 kb
Host smart-56d71570-ce33-48bb-b80b-ab4202c3f712
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151671265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.151671265
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3575244558
Short name T192
Test name
Test status
Simulation time 15326225 ps
CPU time 0.92 seconds
Started Jan 03 01:01:32 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 209816 kb
Host smart-2bd35a70-0cf5-4386-9260-99e1d04cda28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575244558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3575244558
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3073772460
Short name T217
Test name
Test status
Simulation time 64961618 ps
CPU time 0.98 seconds
Started Jan 03 01:01:32 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 218020 kb
Host smart-16df9ba5-3d87-44aa-9a07-8b45faeae206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073772460 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3073772460
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.647900235
Short name T180
Test name
Test status
Simulation time 16495663 ps
CPU time 1.03 seconds
Started Jan 03 01:01:41 PM PST 24
Finished Jan 03 01:02:55 PM PST 24
Peak memory 209584 kb
Host smart-ad0d7af3-48a7-4bdb-88f0-31f1c42afe8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647900235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.647900235
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2026890211
Short name T271
Test name
Test status
Simulation time 234533537 ps
CPU time 1.22 seconds
Started Jan 03 01:01:39 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 209392 kb
Host smart-a62d232f-b5fd-4f6f-8689-b4fa36f1610f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026890211 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2026890211
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3204328268
Short name T245
Test name
Test status
Simulation time 258115101 ps
CPU time 3.17 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 209496 kb
Host smart-51b7c484-a18e-4af8-b5f6-d6cd35b4ed38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204328268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3204328268
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.133323343
Short name T216
Test name
Test status
Simulation time 1209695297 ps
CPU time 16.23 seconds
Started Jan 03 01:01:48 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 208492 kb
Host smart-f75fea74-2f21-412c-a1e2-ea3a1f6b6966
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133323343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.133323343
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4281379688
Short name T116
Test name
Test status
Simulation time 91072742 ps
CPU time 1.42 seconds
Started Jan 03 01:01:42 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 210592 kb
Host smart-3b1e1591-fdc2-45a1-9d9b-1dd39757c612
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281379688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4281379688
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.25987244
Short name T244
Test name
Test status
Simulation time 39713814 ps
CPU time 1.76 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:02:58 PM PST 24
Peak memory 219728 kb
Host smart-af38c537-ae26-4d17-9676-7136898b0a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259872
44 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.25987244
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2344051201
Short name T220
Test name
Test status
Simulation time 194087982 ps
CPU time 1.14 seconds
Started Jan 03 01:01:40 PM PST 24
Finished Jan 03 01:02:53 PM PST 24
Peak memory 209524 kb
Host smart-40ca18ce-ced9-4d63-9193-1e2b487bbd44
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344051201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2344051201
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2610462083
Short name T230
Test name
Test status
Simulation time 17307612 ps
CPU time 0.99 seconds
Started Jan 03 01:01:49 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 209032 kb
Host smart-527c5e62-071d-45ae-8827-bb41d766e0e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610462083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2610462083
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1910184848
Short name T142
Test name
Test status
Simulation time 165400337 ps
CPU time 1.66 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 217664 kb
Host smart-cdcdad74-7efe-4aaa-88fc-1e56fca426e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910184848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1910184848
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1714584043
Short name T119
Test name
Test status
Simulation time 67168640 ps
CPU time 2.07 seconds
Started Jan 03 01:01:32 PM PST 24
Finished Jan 03 01:02:46 PM PST 24
Peak memory 217744 kb
Host smart-847bef83-45ec-48a1-9122-e10335191f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714584043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1714584043
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4201110537
Short name T188
Test name
Test status
Simulation time 50708611 ps
CPU time 1.25 seconds
Started Jan 03 01:01:39 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 208844 kb
Host smart-adefa221-266b-4578-8014-face66462e71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201110537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4201110537
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1230664905
Short name T99
Test name
Test status
Simulation time 38023228 ps
CPU time 1.68 seconds
Started Jan 03 01:01:39 PM PST 24
Finished Jan 03 01:02:53 PM PST 24
Peak memory 208492 kb
Host smart-b196bf04-1c70-4f1f-9ac5-a13577368c81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230664905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1230664905
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1553523011
Short name T186
Test name
Test status
Simulation time 103449825 ps
CPU time 1.01 seconds
Started Jan 03 01:01:45 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 209908 kb
Host smart-d52b60a8-b5ab-4214-9eed-d70dc512ee9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553523011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1553523011
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.20520463
Short name T223
Test name
Test status
Simulation time 88037659 ps
CPU time 1.37 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:02:58 PM PST 24
Peak memory 217784 kb
Host smart-5c87e049-fb66-4f95-8282-5b26c583aea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20520463 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.20520463
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4177499420
Short name T181
Test name
Test status
Simulation time 14642251 ps
CPU time 1.04 seconds
Started Jan 03 01:01:40 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 209532 kb
Host smart-346a12c0-a1d6-41d7-bfd1-2d0c75283a13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177499420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4177499420
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2834663576
Short name T98
Test name
Test status
Simulation time 639111061 ps
CPU time 1.51 seconds
Started Jan 03 01:01:52 PM PST 24
Finished Jan 03 01:03:04 PM PST 24
Peak memory 209372 kb
Host smart-2b08ba2b-b1e9-4ea9-86d3-e2aa2a2b9bbd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834663576 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2834663576
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2528128967
Short name T211
Test name
Test status
Simulation time 1335086396 ps
CPU time 6.33 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:05 PM PST 24
Peak memory 209480 kb
Host smart-de152ba4-85a2-48af-a36f-744e47062768
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528128967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2528128967
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1333969848
Short name T202
Test name
Test status
Simulation time 22133728054 ps
CPU time 10.91 seconds
Started Jan 03 01:01:36 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 209548 kb
Host smart-1f993a0c-aabf-425f-8ff6-221612a7f7b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333969848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1333969848
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2919706040
Short name T190
Test name
Test status
Simulation time 749979980 ps
CPU time 1.52 seconds
Started Jan 03 01:01:38 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 210636 kb
Host smart-2619494b-3abd-4a4a-99cb-ef86fa904004
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919706040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2919706040
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.871137047
Short name T275
Test name
Test status
Simulation time 31346635 ps
CPU time 1.47 seconds
Started Jan 03 01:01:35 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 209616 kb
Host smart-0a9dc113-16a9-4134-be3a-ebbf6ac59a4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871137
047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.871137047
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.585745281
Short name T166
Test name
Test status
Simulation time 217710407 ps
CPU time 2 seconds
Started Jan 03 01:01:50 PM PST 24
Finished Jan 03 01:03:04 PM PST 24
Peak memory 209484 kb
Host smart-25b5a464-b762-429d-8aab-5060810842b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585745281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.585745281
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2658318518
Short name T173
Test name
Test status
Simulation time 17277193 ps
CPU time 0.98 seconds
Started Jan 03 01:01:50 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 209624 kb
Host smart-e23f1db5-cb0b-48df-b0e3-158ef857f1fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658318518 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2658318518
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1764205666
Short name T246
Test name
Test status
Simulation time 46911297 ps
CPU time 1.89 seconds
Started Jan 03 01:01:50 PM PST 24
Finished Jan 03 01:03:03 PM PST 24
Peak memory 211388 kb
Host smart-eb1912d0-53d4-4c5e-a5cd-c7df9bfcfb9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764205666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1764205666
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1205016828
Short name T145
Test name
Test status
Simulation time 97692312 ps
CPU time 3.42 seconds
Started Jan 03 01:01:31 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 217736 kb
Host smart-d6c34bbe-ffa6-4d4d-b8ce-b39ce302926b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205016828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1205016828
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4175788945
Short name T117
Test name
Test status
Simulation time 242942374 ps
CPU time 2.19 seconds
Started Jan 03 01:01:54 PM PST 24
Finished Jan 03 01:03:08 PM PST 24
Peak memory 220120 kb
Host smart-a042b8d4-a67e-47a5-999a-cdc201839c93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175788945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.4175788945
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4114230235
Short name T224
Test name
Test status
Simulation time 87144893 ps
CPU time 0.98 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 209480 kb
Host smart-c866bd24-eeed-4ff9-9950-ba7ce22fb71d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114230235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4114230235
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2645800816
Short name T105
Test name
Test status
Simulation time 73217630 ps
CPU time 1.28 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 209484 kb
Host smart-e3c4b52c-be71-4323-aa48-55524f149413
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645800816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2645800816
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3484507142
Short name T262
Test name
Test status
Simulation time 22159700 ps
CPU time 1.42 seconds
Started Jan 03 01:01:49 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 218968 kb
Host smart-d45100ff-f67f-4373-8517-8c7f9ec1a82a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484507142 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3484507142
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3979973564
Short name T984
Test name
Test status
Simulation time 18667607 ps
CPU time 0.89 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 209460 kb
Host smart-c4601f70-7fcd-45e1-9725-0ae92ef2304c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979973564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3979973564
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2856181348
Short name T185
Test name
Test status
Simulation time 213004709 ps
CPU time 1.01 seconds
Started Jan 03 01:01:50 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 207812 kb
Host smart-1c177550-6bff-4a78-8132-b15b961b768e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856181348 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2856181348
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.844166894
Short name T213
Test name
Test status
Simulation time 710168362 ps
CPU time 5.63 seconds
Started Jan 03 01:01:55 PM PST 24
Finished Jan 03 01:03:12 PM PST 24
Peak memory 208420 kb
Host smart-0c1d9768-2183-4ed6-98f0-3d7d12ccbdeb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844166894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.844166894
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.713109067
Short name T161
Test name
Test status
Simulation time 418811414 ps
CPU time 9.86 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:08 PM PST 24
Peak memory 208380 kb
Host smart-80639da9-3871-4acf-91e7-6043ffe09eeb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713109067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.713109067
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2888832110
Short name T257
Test name
Test status
Simulation time 94760974 ps
CPU time 1.68 seconds
Started Jan 03 01:01:53 PM PST 24
Finished Jan 03 01:03:05 PM PST 24
Peak memory 210908 kb
Host smart-3f30d7d2-a049-4211-8dd1-3b9927bcf81a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888832110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2888832110
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3003028236
Short name T222
Test name
Test status
Simulation time 213444976 ps
CPU time 1.22 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 218852 kb
Host smart-241dac27-0340-48db-a891-d7cca0503745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300302
8236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3003028236
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3791163047
Short name T165
Test name
Test status
Simulation time 37755539 ps
CPU time 1.38 seconds
Started Jan 03 01:01:47 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 209424 kb
Host smart-8cb11234-b1fd-4dc1-abeb-f9435c2e473a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791163047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3791163047
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3015821773
Short name T300
Test name
Test status
Simulation time 52402883 ps
CPU time 1.39 seconds
Started Jan 03 01:01:49 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 209600 kb
Host smart-c886fc6d-c597-4cd7-8fba-84bce55be79c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015821773 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3015821773
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2991737079
Short name T302
Test name
Test status
Simulation time 90753454 ps
CPU time 1.32 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 211456 kb
Host smart-ca168b12-78e2-447f-a65a-ffaf723556cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991737079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2991737079
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2938150280
Short name T143
Test name
Test status
Simulation time 434866680 ps
CPU time 2.59 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 217620 kb
Host smart-152f4854-3146-4a88-bcfc-2e9b68b4f887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938150280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2938150280
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4170875732
Short name T305
Test name
Test status
Simulation time 28590202 ps
CPU time 1.64 seconds
Started Jan 03 01:01:54 PM PST 24
Finished Jan 03 01:03:08 PM PST 24
Peak memory 218176 kb
Host smart-5b7bf69a-e2d3-4f61-b525-13c5e5ea36d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170875732 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4170875732
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3380344545
Short name T177
Test name
Test status
Simulation time 37718547 ps
CPU time 0.85 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 209388 kb
Host smart-486a6927-1222-4e64-84ca-c4943837b459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380344545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3380344545
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1900779562
Short name T207
Test name
Test status
Simulation time 213193654 ps
CPU time 1.24 seconds
Started Jan 03 01:01:40 PM PST 24
Finished Jan 03 01:02:53 PM PST 24
Peak memory 207716 kb
Host smart-3f88ef85-7972-43f9-8f88-936db5a18775
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900779562 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1900779562
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3353540102
Short name T160
Test name
Test status
Simulation time 293283149 ps
CPU time 2.54 seconds
Started Jan 03 01:01:36 PM PST 24
Finished Jan 03 01:02:51 PM PST 24
Peak memory 209384 kb
Host smart-78fce1c7-f269-4777-8a1f-afe983d08656
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353540102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3353540102
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.649496647
Short name T265
Test name
Test status
Simulation time 219562046 ps
CPU time 2.98 seconds
Started Jan 03 01:01:45 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 210812 kb
Host smart-36340936-5de4-423e-a1d8-07ffcd91e5aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649496647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.649496647
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3566708858
Short name T268
Test name
Test status
Simulation time 121494072 ps
CPU time 1.38 seconds
Started Jan 03 01:01:40 PM PST 24
Finished Jan 03 01:02:53 PM PST 24
Peak memory 218988 kb
Host smart-405d2032-17e6-4152-b5e1-737864125893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356670
8858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3566708858
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2966208648
Short name T267
Test name
Test status
Simulation time 193497279 ps
CPU time 1.42 seconds
Started Jan 03 01:01:32 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 209440 kb
Host smart-a582599c-76b7-4e10-a181-a4113e34023d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966208648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2966208648
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1724544627
Short name T299
Test name
Test status
Simulation time 54811255 ps
CPU time 1.2 seconds
Started Jan 03 01:01:38 PM PST 24
Finished Jan 03 01:02:51 PM PST 24
Peak memory 209196 kb
Host smart-4f4b6c90-5155-481a-b948-4d5c9b2d48e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724544627 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1724544627
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1786713259
Short name T251
Test name
Test status
Simulation time 100188035 ps
CPU time 2.04 seconds
Started Jan 03 01:01:39 PM PST 24
Finished Jan 03 01:02:53 PM PST 24
Peak memory 211292 kb
Host smart-3fa4f13d-253a-488f-8927-66e73d0e625d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786713259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1786713259
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2362824648
Short name T263
Test name
Test status
Simulation time 172954121 ps
CPU time 2.26 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:58 PM PST 24
Peak memory 217720 kb
Host smart-fceb7442-ba5c-4f1e-a7a3-efff3e404cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362824648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2362824648
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1249793902
Short name T168
Test name
Test status
Simulation time 21291525 ps
CPU time 1.06 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 218788 kb
Host smart-19e70d72-af17-4309-be86-0e1422cf151f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249793902 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1249793902
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.627327476
Short name T183
Test name
Test status
Simulation time 40388630 ps
CPU time 0.8 seconds
Started Jan 03 01:01:37 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 209396 kb
Host smart-712a9b37-6a53-4fa9-a058-2d4470b4810d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627327476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.627327476
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1676683750
Short name T234
Test name
Test status
Simulation time 307442480 ps
CPU time 1.05 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:02:41 PM PST 24
Peak memory 207708 kb
Host smart-4d303972-c130-4734-bb76-c0b2a25604ea
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676683750 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1676683750
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1383677794
Short name T252
Test name
Test status
Simulation time 3287952024 ps
CPU time 4.23 seconds
Started Jan 03 01:01:47 PM PST 24
Finished Jan 03 01:03:03 PM PST 24
Peak memory 208540 kb
Host smart-a186da22-ef0e-495f-8d42-ce2cb39c4546
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383677794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1383677794
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1783938697
Short name T283
Test name
Test status
Simulation time 950080022 ps
CPU time 22.78 seconds
Started Jan 03 01:01:48 PM PST 24
Finished Jan 03 01:03:22 PM PST 24
Peak memory 209384 kb
Host smart-bf98cfbe-46e9-4488-a42c-e13a70496f7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783938697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1783938697
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2062305363
Short name T284
Test name
Test status
Simulation time 97605959 ps
CPU time 1.17 seconds
Started Jan 03 01:01:48 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 210664 kb
Host smart-e5f674a0-6385-4c84-8e2f-bfba68f29114
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062305363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2062305363
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.572855381
Short name T255
Test name
Test status
Simulation time 62535784 ps
CPU time 2.74 seconds
Started Jan 03 01:01:37 PM PST 24
Finished Jan 03 01:02:51 PM PST 24
Peak memory 218476 kb
Host smart-8dd1665f-1fe5-4764-bc40-a327bcd887ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572855
381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.572855381
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2404064891
Short name T261
Test name
Test status
Simulation time 74082444 ps
CPU time 1.76 seconds
Started Jan 03 01:01:36 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 209452 kb
Host smart-ec53adaa-d9fb-4ea2-ae67-cc8685de28fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404064891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2404064891
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1584283343
Short name T238
Test name
Test status
Simulation time 28921441 ps
CPU time 1.16 seconds
Started Jan 03 01:01:45 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 209504 kb
Host smart-1de30922-3a5f-492f-9f12-ef6d5b21d86d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584283343 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1584283343
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1046241170
Short name T191
Test name
Test status
Simulation time 28949743 ps
CPU time 1.17 seconds
Started Jan 03 01:01:47 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 209616 kb
Host smart-ef9232da-44f8-4508-8bd9-ecbaa28636ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046241170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1046241170
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.346705265
Short name T231
Test name
Test status
Simulation time 149649576 ps
CPU time 2.05 seconds
Started Jan 03 01:01:49 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 217828 kb
Host smart-250984b8-c010-41cb-b3fc-4a1dc21c2456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346705265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.346705265
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3923836020
Short name T293
Test name
Test status
Simulation time 26048915 ps
CPU time 1.2 seconds
Started Jan 03 01:01:45 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 218572 kb
Host smart-d1eac576-7ae0-4ee0-85d2-03de78fa97f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923836020 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3923836020
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3943592110
Short name T179
Test name
Test status
Simulation time 44653024 ps
CPU time 0.9 seconds
Started Jan 03 01:01:53 PM PST 24
Finished Jan 03 01:03:06 PM PST 24
Peak memory 209336 kb
Host smart-d197aa96-b92e-4777-91a2-9666d13a1133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943592110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3943592110
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1393168210
Short name T163
Test name
Test status
Simulation time 22875065 ps
CPU time 0.84 seconds
Started Jan 03 01:01:51 PM PST 24
Finished Jan 03 01:03:03 PM PST 24
Peak memory 209352 kb
Host smart-7861aabb-c7bc-410c-a2c5-6840a70a0c7e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393168210 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1393168210
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.674402386
Short name T206
Test name
Test status
Simulation time 1692346063 ps
CPU time 4.76 seconds
Started Jan 03 01:01:54 PM PST 24
Finished Jan 03 01:03:11 PM PST 24
Peak memory 208016 kb
Host smart-9accaa2f-f7b7-4052-b47d-005b05ca2ff3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674402386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.674402386
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3561989036
Short name T204
Test name
Test status
Simulation time 7229650283 ps
CPU time 37.51 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:03:36 PM PST 24
Peak memory 208368 kb
Host smart-93baf5af-0352-4061-b71b-cee9b3684c8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561989036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3561989036
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1167513980
Short name T232
Test name
Test status
Simulation time 217956410 ps
CPU time 1.18 seconds
Started Jan 03 01:01:45 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 210516 kb
Host smart-7215418e-7caf-4137-865a-c4af3c68e681
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167513980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1167513980
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2234987719
Short name T279
Test name
Test status
Simulation time 37410132 ps
CPU time 1.58 seconds
Started Jan 03 01:01:46 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 219156 kb
Host smart-887b7df6-94b1-4d0c-92e2-0284b32428df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223498
7719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2234987719
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2722101196
Short name T162
Test name
Test status
Simulation time 530041278 ps
CPU time 1.89 seconds
Started Jan 03 01:01:50 PM PST 24
Finished Jan 03 01:03:03 PM PST 24
Peak memory 209500 kb
Host smart-c7aa77d7-f7f3-4f43-8bb4-62ac170f9e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722101196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2722101196
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.436605863
Short name T297
Test name
Test status
Simulation time 123753292 ps
CPU time 1.43 seconds
Started Jan 03 01:01:56 PM PST 24
Finished Jan 03 01:03:08 PM PST 24
Peak memory 211548 kb
Host smart-a2a0c9cc-1a59-4b7e-b89f-f0419e550be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436605863 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.436605863
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3451458223
Short name T226
Test name
Test status
Simulation time 63848799 ps
CPU time 1.44 seconds
Started Jan 03 01:01:54 PM PST 24
Finished Jan 03 01:03:07 PM PST 24
Peak memory 209508 kb
Host smart-fd1644bf-d5f5-4b6f-84a0-0894bb016721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451458223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3451458223
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2005268267
Short name T248
Test name
Test status
Simulation time 134531071 ps
CPU time 1.87 seconds
Started Jan 03 01:02:00 PM PST 24
Finished Jan 03 01:03:11 PM PST 24
Peak memory 217980 kb
Host smart-c83ebc08-eb41-4d63-b560-229875c37384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005268267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2005268267
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4065993101
Short name T150
Test name
Test status
Simulation time 458341460 ps
CPU time 3.93 seconds
Started Jan 03 01:01:31 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 217768 kb
Host smart-830448ca-2df2-4ce7-88da-7f81c874a590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065993101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.4065993101
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1470780950
Short name T227
Test name
Test status
Simulation time 100122822 ps
CPU time 1.26 seconds
Started Jan 03 01:01:35 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 218852 kb
Host smart-53014148-dc8b-476c-a40d-1b96bd496eec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470780950 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1470780950
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.4182856504
Short name T270
Test name
Test status
Simulation time 39804041 ps
CPU time 0.78 seconds
Started Jan 03 01:01:50 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 208556 kb
Host smart-70ed19a8-40ba-4d55-b21c-4a5451d0f1f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182856504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.4182856504
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.788160640
Short name T237
Test name
Test status
Simulation time 54792256 ps
CPU time 1.84 seconds
Started Jan 03 01:01:45 PM PST 24
Finished Jan 03 01:03:00 PM PST 24
Peak memory 209040 kb
Host smart-b7c39ba1-855e-466a-90ed-03e04b256059
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788160640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.788160640
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4007427093
Short name T278
Test name
Test status
Simulation time 827168267 ps
CPU time 5.41 seconds
Started Jan 03 01:01:52 PM PST 24
Finished Jan 03 01:03:09 PM PST 24
Peak memory 209448 kb
Host smart-34da5ad4-cedd-4ea4-be5e-0e29c8b4285f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007427093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4007427093
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3014953568
Short name T103
Test name
Test status
Simulation time 681995794 ps
CPU time 4.65 seconds
Started Jan 03 01:01:48 PM PST 24
Finished Jan 03 01:03:04 PM PST 24
Peak memory 209408 kb
Host smart-2637af1f-1a3a-42da-b3a5-ba3fdeeaf47e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014953568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3014953568
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.908559722
Short name T209
Test name
Test status
Simulation time 47164753 ps
CPU time 1.29 seconds
Started Jan 03 01:01:38 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 210712 kb
Host smart-09efb13a-bbce-427d-8aab-3f1759a26b7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908559722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.908559722
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3416777512
Short name T242
Test name
Test status
Simulation time 40661997 ps
CPU time 1.17 seconds
Started Jan 03 01:01:33 PM PST 24
Finished Jan 03 01:02:46 PM PST 24
Peak memory 209432 kb
Host smart-961817b7-bec7-4f49-898e-4463fcb4035c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416777512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3416777512
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2079220044
Short name T288
Test name
Test status
Simulation time 21382173 ps
CPU time 1.17 seconds
Started Jan 03 01:01:50 PM PST 24
Finished Jan 03 01:03:02 PM PST 24
Peak memory 211080 kb
Host smart-45dc8959-4292-4794-9134-7a423d565207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079220044 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2079220044
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3646335376
Short name T114
Test name
Test status
Simulation time 98785822 ps
CPU time 1.37 seconds
Started Jan 03 01:01:35 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 209524 kb
Host smart-82bd207d-2e5a-482e-8226-599b632c091a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646335376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3646335376
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2195481605
Short name T259
Test name
Test status
Simulation time 25565594 ps
CPU time 1.74 seconds
Started Jan 03 01:01:48 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 217716 kb
Host smart-2f51f693-f1bc-4550-bbf7-3fa7ee4156bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195481605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2195481605
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2364830961
Short name T113
Test name
Test status
Simulation time 115590291 ps
CPU time 1.75 seconds
Started Jan 03 01:01:48 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 221256 kb
Host smart-9c4eabc6-01d3-4f8a-ab6e-af14b0da5590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364830961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2364830961
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3561658382
Short name T304
Test name
Test status
Simulation time 22096402 ps
CPU time 1.12 seconds
Started Jan 03 01:02:00 PM PST 24
Finished Jan 03 01:03:11 PM PST 24
Peak memory 218804 kb
Host smart-9c9f74f8-758f-4fd6-b7e0-03d4e921f15c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561658382 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3561658382
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4036792737
Short name T241
Test name
Test status
Simulation time 63946775 ps
CPU time 0.89 seconds
Started Jan 03 01:01:35 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 209548 kb
Host smart-4fa667b5-d42d-4199-9592-3d38aee63c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036792737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.4036792737
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1314838519
Short name T266
Test name
Test status
Simulation time 302521737 ps
CPU time 1.09 seconds
Started Jan 03 01:01:38 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 209412 kb
Host smart-a74dcf9d-6f14-40dd-9b2d-b51914dbaa3a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314838519 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1314838519
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3098929026
Short name T164
Test name
Test status
Simulation time 361712133 ps
CPU time 4.42 seconds
Started Jan 03 01:01:44 PM PST 24
Finished Jan 03 01:03:01 PM PST 24
Peak memory 208400 kb
Host smart-e5855d8d-486b-4f4e-93ea-e5af580d5a1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098929026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3098929026
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.189770738
Short name T159
Test name
Test status
Simulation time 2404982839 ps
CPU time 25.06 seconds
Started Jan 03 01:01:38 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 209448 kb
Host smart-42a4cd84-5fc8-4542-bca6-c4a72ce9fc68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189770738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.189770738
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3895008971
Short name T229
Test name
Test status
Simulation time 346023058 ps
CPU time 1.59 seconds
Started Jan 03 01:01:38 PM PST 24
Finished Jan 03 01:02:51 PM PST 24
Peak memory 210544 kb
Host smart-08a9db42-438c-4e27-b5d7-15f3c39363b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895008971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3895008971
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3463259918
Short name T221
Test name
Test status
Simulation time 120333956 ps
CPU time 2.08 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:58 PM PST 24
Peak memory 217780 kb
Host smart-25441a5a-c2bf-436d-ba04-b78556e6c07e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346325
9918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3463259918
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1148272156
Short name T249
Test name
Test status
Simulation time 39563486 ps
CPU time 1.53 seconds
Started Jan 03 01:01:42 PM PST 24
Finished Jan 03 01:02:57 PM PST 24
Peak memory 209352 kb
Host smart-1fbec112-120f-4aae-baca-b0f6b9c62932
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148272156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1148272156
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1219645934
Short name T258
Test name
Test status
Simulation time 29641590 ps
CPU time 0.93 seconds
Started Jan 03 01:01:39 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 209608 kb
Host smart-f98056cd-0bef-4770-985d-3605008e2565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219645934 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1219645934
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2492473882
Short name T212
Test name
Test status
Simulation time 149726575 ps
CPU time 1.99 seconds
Started Jan 03 01:01:54 PM PST 24
Finished Jan 03 01:03:08 PM PST 24
Peak memory 210832 kb
Host smart-abc2fc75-349f-4636-aa7c-eebaba6731d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492473882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2492473882
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.571288393
Short name T298
Test name
Test status
Simulation time 55511316 ps
CPU time 2.56 seconds
Started Jan 03 01:01:33 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 217700 kb
Host smart-91a13029-23ba-4694-9fb8-d92c4cad08b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571288393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.571288393
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1645664622
Short name T392
Test name
Test status
Simulation time 39594673 ps
CPU time 0.82 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:34 PM PST 24
Peak memory 209508 kb
Host smart-14d6e232-f804-451b-a9f5-56ce4cb5c9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645664622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1645664622
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1139385925
Short name T450
Test name
Test status
Simulation time 406351673 ps
CPU time 10.45 seconds
Started Jan 03 01:11:48 PM PST 24
Finished Jan 03 01:12:34 PM PST 24
Peak memory 218144 kb
Host smart-26c854b1-fec4-42ce-b475-71234d545f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139385925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1139385925
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2236288876
Short name T532
Test name
Test status
Simulation time 1110024290 ps
CPU time 14.27 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:40 PM PST 24
Peak memory 209620 kb
Host smart-86857326-91b6-4b9a-aa6c-b48879c4efdf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236288876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.2236288876
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3824573883
Short name T628
Test name
Test status
Simulation time 5235106594 ps
CPU time 20.2 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:12:54 PM PST 24
Peak memory 218184 kb
Host smart-60324f19-a902-4d06-bcb6-34e80361a826
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824573883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3824573883
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.96269856
Short name T978
Test name
Test status
Simulation time 106868547 ps
CPU time 1.75 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:31 PM PST 24
Peak memory 209640 kb
Host smart-7852e101-d1b4-4e7b-8b99-49d684f612bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96269856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_pr
iority.96269856
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3487735143
Short name T634
Test name
Test status
Simulation time 2266530802 ps
CPU time 10.44 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:39 PM PST 24
Peak memory 218164 kb
Host smart-909517e3-afac-44d6-9dc5-a8a60cf4af3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487735143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3487735143
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3679628519
Short name T475
Test name
Test status
Simulation time 10659507763 ps
CPU time 12.66 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 213580 kb
Host smart-bb243b4c-6a3d-410c-a177-60e1ed30b162
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679628519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3679628519
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3200133876
Short name T73
Test name
Test status
Simulation time 553550339 ps
CPU time 14.54 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:45 PM PST 24
Peak memory 213660 kb
Host smart-836d8217-91e2-49f0-a48d-9a88ed04555a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200133876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3200133876
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1982426485
Short name T808
Test name
Test status
Simulation time 7898378648 ps
CPU time 77.69 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:13:47 PM PST 24
Peak memory 276432 kb
Host smart-6bda7989-7e88-4fed-ab46-169ab50e2dde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982426485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1982426485
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1886747376
Short name T502
Test name
Test status
Simulation time 325614417 ps
CPU time 10.69 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:39 PM PST 24
Peak memory 251172 kb
Host smart-31a57ccb-1725-4f0c-ba3c-65fbe156428d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886747376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1886747376
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.962689905
Short name T81
Test name
Test status
Simulation time 337690534 ps
CPU time 9.63 seconds
Started Jan 03 01:11:47 PM PST 24
Finished Jan 03 01:12:33 PM PST 24
Peak memory 214116 kb
Host smart-a8b5298f-cdca-4aaa-93cf-0bd45df13389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962689905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.962689905
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2570627416
Short name T496
Test name
Test status
Simulation time 330064282 ps
CPU time 10.43 seconds
Started Jan 03 01:11:52 PM PST 24
Finished Jan 03 01:12:40 PM PST 24
Peak memory 218868 kb
Host smart-91494da5-2d00-492c-9ba6-bc5cfb0e1a38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570627416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2570627416
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1653718539
Short name T379
Test name
Test status
Simulation time 398401037 ps
CPU time 11.97 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:43 PM PST 24
Peak memory 218192 kb
Host smart-8eb4e3d2-2d0f-46fe-ad59-532aed263849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653718539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1653718539
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2619095059
Short name T641
Test name
Test status
Simulation time 1401463060 ps
CPU time 6.81 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:38 PM PST 24
Peak memory 218144 kb
Host smart-377ab78b-7d07-4079-a624-125cf03587e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619095059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
619095059
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1041804906
Short name T912
Test name
Test status
Simulation time 224288322 ps
CPU time 9.86 seconds
Started Jan 03 01:11:45 PM PST 24
Finished Jan 03 01:12:31 PM PST 24
Peak memory 218224 kb
Host smart-09366bbd-6918-485d-99cd-1c1297aede6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041804906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1041804906
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3405354837
Short name T564
Test name
Test status
Simulation time 151163983 ps
CPU time 2.26 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:28 PM PST 24
Peak memory 213996 kb
Host smart-9b773f78-6bab-4820-872e-c1135fab10cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405354837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3405354837
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2303009554
Short name T535
Test name
Test status
Simulation time 766841845 ps
CPU time 29.91 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:55 PM PST 24
Peak memory 251064 kb
Host smart-c14b4e92-a5f5-4e25-aee7-41266d6cbf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303009554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2303009554
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1840288768
Short name T925
Test name
Test status
Simulation time 86911014 ps
CPU time 3.37 seconds
Started Jan 03 01:11:48 PM PST 24
Finished Jan 03 01:12:27 PM PST 24
Peak memory 222028 kb
Host smart-2b277074-f6e7-4f22-8853-be29010e2ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840288768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1840288768
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.14687573
Short name T375
Test name
Test status
Simulation time 41770757 ps
CPU time 0.91 seconds
Started Jan 03 01:11:59 PM PST 24
Finished Jan 03 01:12:39 PM PST 24
Peak memory 209648 kb
Host smart-a6e9b237-904f-40a0-927b-56cf0bd98b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14687573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.14687573
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2971693482
Short name T48
Test name
Test status
Simulation time 319540361 ps
CPU time 9.73 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:40 PM PST 24
Peak memory 218156 kb
Host smart-5c55e24a-45b2-4808-a717-cc1c5e08e493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971693482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2971693482
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1415170759
Short name T885
Test name
Test status
Simulation time 768833826 ps
CPU time 8.36 seconds
Started Jan 03 01:11:58 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 209632 kb
Host smart-367bc17b-53bd-470b-8884-dd441bbb8816
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415170759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.1415170759
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.487513851
Short name T20
Test name
Test status
Simulation time 2142076738 ps
CPU time 28.6 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:13:03 PM PST 24
Peak memory 218044 kb
Host smart-30046c5f-131a-4ac7-b898-7f55bd6e4c8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487513851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.487513851
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.4160096567
Short name T560
Test name
Test status
Simulation time 388722787 ps
CPU time 9.96 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 217948 kb
Host smart-1888eaf3-00b4-4987-977e-3cd4b1ca58f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160096567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.4160096567
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2388363819
Short name T782
Test name
Test status
Simulation time 813269913 ps
CPU time 19.64 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:53 PM PST 24
Peak memory 218156 kb
Host smart-472a108e-6d89-4bb4-a519-fe96ddaf18ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388363819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2388363819
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1443705631
Short name T721
Test name
Test status
Simulation time 20216595214 ps
CPU time 29.27 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:13:04 PM PST 24
Peak memory 213820 kb
Host smart-549c1cfa-1034-42bf-b96a-6dea06613797
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443705631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1443705631
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2938275262
Short name T677
Test name
Test status
Simulation time 263622849 ps
CPU time 7.48 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:12:41 PM PST 24
Peak memory 213556 kb
Host smart-1fc044be-0da8-4849-9ac8-bf799a6e4fb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938275262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2938275262
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2008780975
Short name T770
Test name
Test status
Simulation time 12247836223 ps
CPU time 54.76 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:13:27 PM PST 24
Peak memory 275736 kb
Host smart-daf94e08-840f-49c4-b3e5-1a7bbcc998c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008780975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2008780975
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3704643467
Short name T420
Test name
Test status
Simulation time 444157533 ps
CPU time 12.18 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:12:45 PM PST 24
Peak memory 245528 kb
Host smart-cb3db4a0-12e8-432b-9dbd-0a25adb706c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704643467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3704643467
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4251154627
Short name T952
Test name
Test status
Simulation time 126385013 ps
CPU time 3.27 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:34 PM PST 24
Peak memory 218160 kb
Host smart-763ef4c8-309f-42fb-a30c-2f0f1c27fb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251154627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4251154627
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.403228623
Short name T861
Test name
Test status
Simulation time 636285141 ps
CPU time 9.08 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:38 PM PST 24
Peak memory 214188 kb
Host smart-15e25130-bc7c-477e-a7e6-9417a87bde51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403228623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.403228623
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3238943406
Short name T121
Test name
Test status
Simulation time 707940760 ps
CPU time 22.95 seconds
Started Jan 03 01:11:47 PM PST 24
Finished Jan 03 01:12:46 PM PST 24
Peak memory 272836 kb
Host smart-fd786c70-77e8-4d1d-91c2-64f8e46cc0b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238943406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3238943406
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2641343458
Short name T793
Test name
Test status
Simulation time 245863606 ps
CPU time 10.08 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 219232 kb
Host smart-b11fe56f-5b47-4bdf-9014-48acc64bcece
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641343458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2641343458
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1468602215
Short name T49
Test name
Test status
Simulation time 1042774380 ps
CPU time 9.13 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:40 PM PST 24
Peak memory 218056 kb
Host smart-b0136966-0c5b-4f59-9c03-47a7efb75028
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468602215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1468602215
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1264982029
Short name T711
Test name
Test status
Simulation time 574703032 ps
CPU time 13.93 seconds
Started Jan 03 01:12:00 PM PST 24
Finished Jan 03 01:12:53 PM PST 24
Peak memory 218168 kb
Host smart-ab36cfba-2ab6-4640-b9e1-31f729c85424
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264982029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
264982029
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.638271236
Short name T575
Test name
Test status
Simulation time 240979998 ps
CPU time 7.24 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:41 PM PST 24
Peak memory 218224 kb
Host smart-11c7b48c-dac9-48e6-be4b-94d507658549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638271236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.638271236
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1778879864
Short name T817
Test name
Test status
Simulation time 34641388 ps
CPU time 2.07 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:33 PM PST 24
Peak memory 213596 kb
Host smart-e7ebb14a-6cdb-4951-8669-429e9fb5f82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778879864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1778879864
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.4008971103
Short name T452
Test name
Test status
Simulation time 682359743 ps
CPU time 29.31 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:13:01 PM PST 24
Peak memory 251164 kb
Host smart-0639e2d3-affb-417f-bba3-41e3896bef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008971103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.4008971103
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3733957722
Short name T672
Test name
Test status
Simulation time 93574506 ps
CPU time 8.19 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:41 PM PST 24
Peak memory 251204 kb
Host smart-bd1ddc70-8fff-4991-a09e-2bfd74cca866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733957722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3733957722
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.811125940
Short name T383
Test name
Test status
Simulation time 11307258102 ps
CPU time 337.78 seconds
Started Jan 03 01:11:59 PM PST 24
Finished Jan 03 01:18:15 PM PST 24
Peak memory 283968 kb
Host smart-2920b94e-bf26-4472-bece-469483d103e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811125940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.811125940
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1032607808
Short name T515
Test name
Test status
Simulation time 13308487 ps
CPU time 0.94 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:12:33 PM PST 24
Peak memory 211700 kb
Host smart-e619a154-f4bf-4c68-99be-366a4c2a55d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032607808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1032607808
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.4092478722
Short name T913
Test name
Test status
Simulation time 42941569 ps
CPU time 0.94 seconds
Started Jan 03 01:12:56 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 209724 kb
Host smart-35ec6891-8f97-47cc-b591-9b3a19d2cf83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092478722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4092478722
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.222135039
Short name T60
Test name
Test status
Simulation time 393559205 ps
CPU time 12.97 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:13:50 PM PST 24
Peak memory 218164 kb
Host smart-18f77e90-2099-4172-a549-430625745817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222135039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.222135039
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3991047179
Short name T902
Test name
Test status
Simulation time 959179753 ps
CPU time 3.21 seconds
Started Jan 03 01:13:05 PM PST 24
Finished Jan 03 01:13:55 PM PST 24
Peak memory 209688 kb
Host smart-55e1f06c-ce10-4a6e-acbc-0e38917a412b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991047179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.3991047179
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2260662229
Short name T632
Test name
Test status
Simulation time 2896707230 ps
CPU time 38.85 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:14:21 PM PST 24
Peak memory 218264 kb
Host smart-3c4459cc-fcac-4087-bda9-22de1defb853
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260662229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2260662229
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1738962899
Short name T929
Test name
Test status
Simulation time 190742668 ps
CPU time 4.12 seconds
Started Jan 03 01:12:56 PM PST 24
Finished Jan 03 01:13:38 PM PST 24
Peak memory 218112 kb
Host smart-c78359c4-3102-4a0c-8bd0-35f6ae7347a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738962899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1738962899
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3787760910
Short name T813
Test name
Test status
Simulation time 369284478 ps
CPU time 9.92 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:49 PM PST 24
Peak memory 213424 kb
Host smart-dda32600-3684-4ea9-9a48-b87cacf495f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787760910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3787760910
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.534326696
Short name T841
Test name
Test status
Simulation time 909262703 ps
CPU time 47.32 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:14:20 PM PST 24
Peak memory 267408 kb
Host smart-3b6387a0-9141-421d-a68d-ed76771f1442
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534326696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.534326696
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3778830431
Short name T597
Test name
Test status
Simulation time 2315389024 ps
CPU time 11.65 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:52 PM PST 24
Peak memory 247356 kb
Host smart-fa5a2ccd-1948-4bf6-959a-c800a8b4fcf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778830431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3778830431
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1380761592
Short name T933
Test name
Test status
Simulation time 996558139 ps
CPU time 2.79 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 218156 kb
Host smart-5e5bd349-bf47-4880-adbe-6b23d813808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380761592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1380761592
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.528419728
Short name T483
Test name
Test status
Simulation time 683464998 ps
CPU time 13.42 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:13:56 PM PST 24
Peak memory 218184 kb
Host smart-0b6f5af1-ef70-4c76-89a3-99b8dccdaa61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528419728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.528419728
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1262387452
Short name T438
Test name
Test status
Simulation time 308478990 ps
CPU time 11.83 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:45 PM PST 24
Peak memory 218152 kb
Host smart-a500474e-f4df-4dd2-a8a3-4d571e01912b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262387452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1262387452
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1189498356
Short name T461
Test name
Test status
Simulation time 723240943 ps
CPU time 12.88 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:45 PM PST 24
Peak memory 218136 kb
Host smart-7e346799-e624-4a5b-bb11-796a1646150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189498356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1189498356
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.108901415
Short name T600
Test name
Test status
Simulation time 23028307 ps
CPU time 1.01 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:34 PM PST 24
Peak memory 213028 kb
Host smart-bff035f2-23a9-42ec-b0f1-0204d9fab69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108901415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.108901415
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3308270346
Short name T700
Test name
Test status
Simulation time 1000613811 ps
CPU time 30.37 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:14:01 PM PST 24
Peak memory 251104 kb
Host smart-23c7456a-b25a-48d2-8b4c-8113a85e1fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308270346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3308270346
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.527777964
Short name T340
Test name
Test status
Simulation time 92294105 ps
CPU time 7.89 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 251200 kb
Host smart-2ed389ec-0225-4cd8-ad64-b29a60cd3ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527777964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.527777964
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3527615484
Short name T19
Test name
Test status
Simulation time 15714980652 ps
CPU time 263.47 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:18:01 PM PST 24
Peak memory 284044 kb
Host smart-a6a5207c-add0-4632-8aef-2be8431690c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527615484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3527615484
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1585789973
Short name T966
Test name
Test status
Simulation time 910670382 ps
CPU time 11.56 seconds
Started Jan 03 01:12:49 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 209676 kb
Host smart-e7071716-66bd-4f2c-9e93-44c00e38064b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585789973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.1585789973
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.528577243
Short name T563
Test name
Test status
Simulation time 5899566972 ps
CPU time 37.37 seconds
Started Jan 03 01:12:44 PM PST 24
Finished Jan 03 01:14:02 PM PST 24
Peak memory 218644 kb
Host smart-9f57cd94-5036-4c2b-8b69-7300d78197f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528577243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.528577243
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1226110614
Short name T769
Test name
Test status
Simulation time 94077323 ps
CPU time 2.27 seconds
Started Jan 03 01:12:46 PM PST 24
Finished Jan 03 01:13:28 PM PST 24
Peak memory 218140 kb
Host smart-7d4ba473-1c70-4699-a97e-142cca7e57ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226110614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1226110614
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3030226642
Short name T858
Test name
Test status
Simulation time 1580501824 ps
CPU time 5.77 seconds
Started Jan 03 01:13:02 PM PST 24
Finished Jan 03 01:13:52 PM PST 24
Peak memory 213212 kb
Host smart-9f80385d-9946-474a-bf9e-67a98c394662
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030226642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3030226642
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3637408816
Short name T354
Test name
Test status
Simulation time 4721941421 ps
CPU time 83.25 seconds
Started Jan 03 01:12:46 PM PST 24
Finished Jan 03 01:14:49 PM PST 24
Peak memory 278796 kb
Host smart-040696d4-3dfd-4fb7-962d-d59422f2f5c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637408816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3637408816
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1171561955
Short name T594
Test name
Test status
Simulation time 2536031279 ps
CPU time 14.82 seconds
Started Jan 03 01:12:44 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 251196 kb
Host smart-a57c91ea-4fb2-408b-9cb7-9317e323f99e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171561955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1171561955
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2470377778
Short name T10
Test name
Test status
Simulation time 80406494 ps
CPU time 3.8 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 218172 kb
Host smart-fa12b41c-eccb-4fe6-84a2-117aee818433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470377778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2470377778
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.619962988
Short name T621
Test name
Test status
Simulation time 1565911523 ps
CPU time 16.24 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:13:47 PM PST 24
Peak memory 218244 kb
Host smart-fe2474f5-4680-4272-8a92-e7f67e564aa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619962988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.619962988
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1405948330
Short name T50
Test name
Test status
Simulation time 665906866 ps
CPU time 11.29 seconds
Started Jan 03 01:12:33 PM PST 24
Finished Jan 03 01:13:29 PM PST 24
Peak memory 218144 kb
Host smart-65d31618-f89c-4786-badc-862d4cedce98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405948330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1405948330
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.492555616
Short name T519
Test name
Test status
Simulation time 1039407072 ps
CPU time 7.33 seconds
Started Jan 03 01:12:38 PM PST 24
Finished Jan 03 01:13:29 PM PST 24
Peak memory 218176 kb
Host smart-6dda49cb-3e7b-4b75-a002-9a62597cf268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492555616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.492555616
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2117813157
Short name T792
Test name
Test status
Simulation time 949928031 ps
CPU time 6.68 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 218236 kb
Host smart-672c54f1-658a-4dfe-96f9-48671e23ebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117813157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2117813157
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2687423571
Short name T424
Test name
Test status
Simulation time 1375765676 ps
CPU time 3.36 seconds
Started Jan 03 01:13:08 PM PST 24
Finished Jan 03 01:13:58 PM PST 24
Peak memory 214420 kb
Host smart-a7c52209-ed72-4628-8cc5-0aea183be193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687423571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2687423571
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.600802345
Short name T537
Test name
Test status
Simulation time 1004419151 ps
CPU time 21.26 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:13:57 PM PST 24
Peak memory 251100 kb
Host smart-3adfee40-82f4-477e-aaf4-eb7b5f4169b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600802345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.600802345
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1260649980
Short name T614
Test name
Test status
Simulation time 45804790 ps
CPU time 7.59 seconds
Started Jan 03 01:13:08 PM PST 24
Finished Jan 03 01:14:02 PM PST 24
Peak memory 251040 kb
Host smart-968e0a24-0c17-4ef6-88cb-aef8ed65a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260649980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1260649980
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4203568197
Short name T891
Test name
Test status
Simulation time 4257158246 ps
CPU time 143.57 seconds
Started Jan 03 01:12:31 PM PST 24
Finished Jan 03 01:15:40 PM PST 24
Peak memory 282048 kb
Host smart-2e7ed562-ada4-4a85-bb90-aac9730148e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203568197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4203568197
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1286584134
Short name T877
Test name
Test status
Simulation time 21124246 ps
CPU time 1.47 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:13:52 PM PST 24
Peak memory 212472 kb
Host smart-3b0c3d8d-e1cd-429d-a79d-12daa8463185
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286584134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1286584134
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3883587396
Short name T462
Test name
Test status
Simulation time 29740333 ps
CPU time 0.93 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:34 PM PST 24
Peak memory 209632 kb
Host smart-117bf986-a91a-45f3-ac39-1b5618c7a6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883587396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3883587396
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1144216811
Short name T674
Test name
Test status
Simulation time 1401876851 ps
CPU time 8.22 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 218248 kb
Host smart-308c9654-effb-4f95-9355-c51e23fdf3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144216811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1144216811
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.951139667
Short name T983
Test name
Test status
Simulation time 145840467 ps
CPU time 1.59 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:35 PM PST 24
Peak memory 209680 kb
Host smart-de1ad67a-4481-4b6f-9e2e-d575128fcda5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951139667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_ac
cess.951139667
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.599146921
Short name T426
Test name
Test status
Simulation time 4296146774 ps
CPU time 31.89 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:14:03 PM PST 24
Peak memory 218180 kb
Host smart-4c7dd787-f3cf-49ec-a1b0-f2052e1f8271
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599146921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.599146921
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2028831139
Short name T417
Test name
Test status
Simulation time 4444166798 ps
CPU time 7.4 seconds
Started Jan 03 01:12:56 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 218184 kb
Host smart-5d7a653d-69cf-481f-856b-e5b78d4eb88c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028831139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2028831139
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.288050420
Short name T602
Test name
Test status
Simulation time 768129521 ps
CPU time 6.79 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 213584 kb
Host smart-de079f33-1216-47c3-ba42-52f5b9dce004
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288050420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
288050420
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.521186650
Short name T762
Test name
Test status
Simulation time 1907614056 ps
CPU time 51.39 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:14:24 PM PST 24
Peak memory 267456 kb
Host smart-6950cdb7-2eb0-4fc0-a0af-fc2582ef9b31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521186650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.521186650
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3261865898
Short name T467
Test name
Test status
Simulation time 463212179 ps
CPU time 12.17 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:43 PM PST 24
Peak memory 249200 kb
Host smart-699e4b25-a265-4af1-9c5a-2c914bcbf893
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261865898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3261865898
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2742325560
Short name T660
Test name
Test status
Simulation time 90064356 ps
CPU time 3.9 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 218196 kb
Host smart-a50d0651-5619-4e96-9571-493d41454e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742325560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2742325560
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.923394846
Short name T387
Test name
Test status
Simulation time 400495159 ps
CPU time 10.1 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:41 PM PST 24
Peak memory 218092 kb
Host smart-13445afd-be9b-43be-9670-e1ac75ce4c2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923394846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.923394846
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1334081589
Short name T702
Test name
Test status
Simulation time 1020286664 ps
CPU time 11.83 seconds
Started Jan 03 01:12:56 PM PST 24
Finished Jan 03 01:13:47 PM PST 24
Peak memory 218172 kb
Host smart-4b3d3d0e-a31b-4b96-9a8f-227a0405b72e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334081589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1334081589
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3928280439
Short name T757
Test name
Test status
Simulation time 227167831 ps
CPU time 8.98 seconds
Started Jan 03 01:12:56 PM PST 24
Finished Jan 03 01:13:44 PM PST 24
Peak memory 218144 kb
Host smart-9dca303d-f3e9-453e-b18c-1c26d9732d9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928280439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3928280439
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1371012500
Short name T662
Test name
Test status
Simulation time 743195562 ps
CPU time 6.75 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 218312 kb
Host smart-d46e3aa9-9628-4a02-bb71-a46fa8597139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371012500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1371012500
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.4029654257
Short name T336
Test name
Test status
Simulation time 195660415 ps
CPU time 2.56 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:13:32 PM PST 24
Peak memory 214016 kb
Host smart-dd3fdaa6-1258-437b-aa00-b8bd115595a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029654257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.4029654257
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1874513429
Short name T780
Test name
Test status
Simulation time 351347185 ps
CPU time 34.3 seconds
Started Jan 03 01:12:56 PM PST 24
Finished Jan 03 01:14:08 PM PST 24
Peak memory 251024 kb
Host smart-7efc146c-71a5-4062-be5d-9413ca80bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874513429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1874513429
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.125699871
Short name T927
Test name
Test status
Simulation time 282857075 ps
CPU time 3.04 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:32 PM PST 24
Peak memory 226620 kb
Host smart-4d405168-aeb2-4b04-97b6-cfb96f0b8a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125699871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.125699871
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.592699314
Short name T717
Test name
Test status
Simulation time 28340622568 ps
CPU time 303.65 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:18:37 PM PST 24
Peak memory 447816 kb
Host smart-1a93e67d-6c15-4526-a3e1-e6fe68c5233f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592699314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.592699314
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1856136556
Short name T510
Test name
Test status
Simulation time 21443226 ps
CPU time 1.13 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:30 PM PST 24
Peak memory 209712 kb
Host smart-83750cae-9856-4542-9e1f-a45cd57576ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856136556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1856136556
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.4108751854
Short name T421
Test name
Test status
Simulation time 280051107 ps
CPU time 13.5 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 218212 kb
Host smart-20a49018-1ec8-4e59-8794-88213adb1dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108751854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.4108751854
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.242290520
Short name T842
Test name
Test status
Simulation time 221546406 ps
CPU time 3.6 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 209628 kb
Host smart-4522818b-407e-4c8d-a835-7fec1e635d31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242290520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ac
cess.242290520
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.495086156
Short name T551
Test name
Test status
Simulation time 3769446786 ps
CPU time 56.49 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:14:28 PM PST 24
Peak memory 219260 kb
Host smart-a2c8f355-da56-4d22-861d-229a286a23f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495086156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.495086156
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.710741944
Short name T558
Test name
Test status
Simulation time 98286841 ps
CPU time 3.19 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:34 PM PST 24
Peak memory 218052 kb
Host smart-9396956e-d914-4b8b-a44f-44c05ff299e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710741944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.710741944
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2684380454
Short name T78
Test name
Test status
Simulation time 394347861 ps
CPU time 4.76 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 213040 kb
Host smart-9e0faa6d-eb92-43db-a93a-2b6126204bce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684380454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2684380454
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2467900355
Short name T404
Test name
Test status
Simulation time 3392759676 ps
CPU time 56.91 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:14:27 PM PST 24
Peak memory 267484 kb
Host smart-0c9bb065-0993-4d82-bf55-0223d319de7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467900355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2467900355
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1824099830
Short name T618
Test name
Test status
Simulation time 2560899175 ps
CPU time 38.76 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:14:08 PM PST 24
Peak memory 251168 kb
Host smart-29bc4f2e-83d4-4268-8321-4ea2b5811e12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824099830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1824099830
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3262318914
Short name T372
Test name
Test status
Simulation time 93193992 ps
CPU time 4.14 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:13:43 PM PST 24
Peak memory 218192 kb
Host smart-e1a35457-9109-449d-9474-1d516550aa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262318914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3262318914
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2963627545
Short name T941
Test name
Test status
Simulation time 1746831420 ps
CPU time 14.39 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:46 PM PST 24
Peak memory 218240 kb
Host smart-9ed3c5d8-9d1e-4e77-809d-833616a04d0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963627545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2963627545
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.508813604
Short name T389
Test name
Test status
Simulation time 443985708 ps
CPU time 12.03 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:41 PM PST 24
Peak memory 218148 kb
Host smart-7a6333dc-8a6a-4e58-a7ef-c589dcfe940a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508813604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.508813604
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.830759646
Short name T652
Test name
Test status
Simulation time 325020276 ps
CPU time 8.47 seconds
Started Jan 03 01:12:48 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 218116 kb
Host smart-06bca200-0b93-4a0d-8614-b5789deb6f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830759646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.830759646
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.348746589
Short name T509
Test name
Test status
Simulation time 880197379 ps
CPU time 14.63 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:13:51 PM PST 24
Peak memory 218176 kb
Host smart-ec82408a-6c8f-4d17-899f-aa2b37014167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348746589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.348746589
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3701686304
Short name T16
Test name
Test status
Simulation time 96887647 ps
CPU time 3.33 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:37 PM PST 24
Peak memory 213460 kb
Host smart-55762f25-aa22-46e9-b855-cf8c3c3dc638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701686304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3701686304
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2718174272
Short name T324
Test name
Test status
Simulation time 253017745 ps
CPU time 30.23 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:14:09 PM PST 24
Peak memory 251188 kb
Host smart-379c58a4-8db5-46cf-8d10-08bb79f569f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718174272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2718174272
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.561331337
Short name T346
Test name
Test status
Simulation time 172886259 ps
CPU time 3.42 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:43 PM PST 24
Peak memory 222212 kb
Host smart-e1bbcdd2-0d75-4683-984f-c4515901c6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561331337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.561331337
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2501806916
Short name T86
Test name
Test status
Simulation time 11135486328 ps
CPU time 65.24 seconds
Started Jan 03 01:12:56 PM PST 24
Finished Jan 03 01:14:39 PM PST 24
Peak memory 251272 kb
Host smart-eeb80ecf-5410-4794-bd21-b663ecd6b395
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501806916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2501806916
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3650015117
Short name T622
Test name
Test status
Simulation time 11465786 ps
CPU time 0.76 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 208360 kb
Host smart-2ed915f6-fd74-42a4-bf59-be124480a6fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650015117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3650015117
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3113066283
Short name T321
Test name
Test status
Simulation time 17920992 ps
CPU time 1.1 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:32 PM PST 24
Peak memory 208536 kb
Host smart-cd681613-c460-4f14-9b75-122a5b82f0b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113066283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3113066283
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.889503891
Short name T667
Test name
Test status
Simulation time 755734549 ps
CPU time 14.03 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:13:56 PM PST 24
Peak memory 218256 kb
Host smart-8bc45ff4-9447-4ace-a7be-b4cd98c8b421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889503891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.889503891
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3066466354
Short name T29
Test name
Test status
Simulation time 688219861 ps
CPU time 2.94 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:33 PM PST 24
Peak memory 209616 kb
Host smart-4973298f-c3f4-4755-bdc7-e2a81d41b2aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066466354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_a
ccess.3066466354
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1607009520
Short name T680
Test name
Test status
Simulation time 1681426463 ps
CPU time 49.12 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:14:40 PM PST 24
Peak memory 218112 kb
Host smart-ae5611f6-28fa-441f-98ec-cb35f9e05784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607009520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1607009520
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3286935776
Short name T358
Test name
Test status
Simulation time 1024197992 ps
CPU time 7.64 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 218104 kb
Host smart-76789f26-982d-4ec5-9149-761d669d4559
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286935776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3286935776
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.604065292
Short name T486
Test name
Test status
Simulation time 113202276 ps
CPU time 2.13 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:13:32 PM PST 24
Peak memory 212820 kb
Host smart-696fc817-31cb-4894-a28d-fe4fb1c88115
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604065292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
604065292
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.772510539
Short name T468
Test name
Test status
Simulation time 3461323930 ps
CPU time 110.99 seconds
Started Jan 03 01:12:49 PM PST 24
Finished Jan 03 01:15:19 PM PST 24
Peak memory 283848 kb
Host smart-3d964f95-27ca-4195-a232-a8fb848ea3f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772510539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.772510539
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3250823629
Short name T584
Test name
Test status
Simulation time 667203147 ps
CPU time 25.66 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:57 PM PST 24
Peak memory 251120 kb
Host smart-5145b1e2-24fc-4edd-8d33-95eb54cf1872
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250823629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3250823629
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1849458060
Short name T485
Test name
Test status
Simulation time 182286081 ps
CPU time 4.39 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:13:35 PM PST 24
Peak memory 218168 kb
Host smart-cd5fe312-de80-4336-9965-ffe38f898e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849458060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1849458060
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2603558302
Short name T604
Test name
Test status
Simulation time 554271302 ps
CPU time 12.68 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:46 PM PST 24
Peak memory 218212 kb
Host smart-f96aa1f0-b2ad-490e-8463-6452ca0a42a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603558302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2603558302
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.600105665
Short name T882
Test name
Test status
Simulation time 436530461 ps
CPU time 18.14 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:49 PM PST 24
Peak memory 218176 kb
Host smart-6ab3645a-134c-49f6-bbcc-bc56e3d60ccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600105665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.600105665
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.585483002
Short name T806
Test name
Test status
Simulation time 2560982850 ps
CPU time 8.37 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 218184 kb
Host smart-837ce5b1-a561-4014-83cb-1dbbb77a1d79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585483002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.585483002
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2171725985
Short name T951
Test name
Test status
Simulation time 25338330 ps
CPU time 1.72 seconds
Started Jan 03 01:12:49 PM PST 24
Finished Jan 03 01:13:30 PM PST 24
Peak memory 213456 kb
Host smart-8e83adc1-3187-4568-b3a6-7ef0bd1f99d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171725985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2171725985
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2371119215
Short name T676
Test name
Test status
Simulation time 888708913 ps
CPU time 23.18 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:52 PM PST 24
Peak memory 251080 kb
Host smart-a6871ddd-e091-4e9a-af85-03aa7841fd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371119215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2371119215
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2184529546
Short name T701
Test name
Test status
Simulation time 91562370 ps
CPU time 3.59 seconds
Started Jan 03 01:12:49 PM PST 24
Finished Jan 03 01:13:32 PM PST 24
Peak memory 222224 kb
Host smart-abe15179-4725-4fce-b645-7d069dd13148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184529546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2184529546
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2205395045
Short name T643
Test name
Test status
Simulation time 16584632826 ps
CPU time 84.38 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 283940 kb
Host smart-890e3653-aec9-4da1-a318-08a5a5da8914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205395045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2205395045
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3890086350
Short name T968
Test name
Test status
Simulation time 29705216 ps
CPU time 0.83 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:31 PM PST 24
Peak memory 208420 kb
Host smart-99dc80af-9bdd-4298-b786-849d52720952
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890086350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3890086350
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1650802603
Short name T451
Test name
Test status
Simulation time 126801024 ps
CPU time 1 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:35 PM PST 24
Peak memory 209744 kb
Host smart-a21ce0f1-4969-4af1-b4a9-e106daf5a06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650802603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1650802603
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2576046789
Short name T415
Test name
Test status
Simulation time 432645319 ps
CPU time 11.69 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:44 PM PST 24
Peak memory 218096 kb
Host smart-257d5a95-feca-4891-b7ad-4f8ca175e950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576046789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2576046789
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.4210526950
Short name T796
Test name
Test status
Simulation time 116801832 ps
CPU time 3.64 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:44 PM PST 24
Peak memory 209552 kb
Host smart-25d93acd-1df9-4e09-aa00-a3fb4d8484d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210526950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.4210526950
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1738911474
Short name T745
Test name
Test status
Simulation time 10750607268 ps
CPU time 37.78 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:14:11 PM PST 24
Peak memory 218320 kb
Host smart-1d0db5b2-dcf8-45f4-90e8-8dc437381846
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738911474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1738911474
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4267883992
Short name T326
Test name
Test status
Simulation time 4048836244 ps
CPU time 8.23 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:41 PM PST 24
Peak memory 218228 kb
Host smart-cb2e40b1-b2aa-42a7-b52f-c26d534ac74f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267883992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4267883992
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3829358457
Short name T445
Test name
Test status
Simulation time 317359415 ps
CPU time 4.83 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 213432 kb
Host smart-31831288-66f4-449d-bbd3-1163c51fb7d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829358457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3829358457
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3485139540
Short name T533
Test name
Test status
Simulation time 1500254448 ps
CPU time 51.52 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 253416 kb
Host smart-da89a87e-f251-4516-892f-567d627d0324
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485139540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3485139540
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.435052013
Short name T333
Test name
Test status
Simulation time 792965275 ps
CPU time 22.65 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:14:04 PM PST 24
Peak memory 250956 kb
Host smart-3f9b4883-e7ef-49fe-9118-556380543ab2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435052013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.435052013
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2322574156
Short name T765
Test name
Test status
Simulation time 402050001 ps
CPU time 1.97 seconds
Started Jan 03 01:13:03 PM PST 24
Finished Jan 03 01:13:50 PM PST 24
Peak memory 218148 kb
Host smart-d9b8a0d3-7231-4384-a52b-2dc51216f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322574156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2322574156
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2411926159
Short name T642
Test name
Test status
Simulation time 1507514268 ps
CPU time 15.68 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:48 PM PST 24
Peak memory 219220 kb
Host smart-b59375f9-fb3f-4dac-83f2-a7182139349c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411926159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2411926159
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.185856634
Short name T583
Test name
Test status
Simulation time 361675174 ps
CPU time 13.19 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:14:04 PM PST 24
Peak memory 218148 kb
Host smart-272283a8-2057-4263-9645-86cb6391ea06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185856634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.185856634
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.245608817
Short name T405
Test name
Test status
Simulation time 429466628 ps
CPU time 13.96 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:13:50 PM PST 24
Peak memory 218108 kb
Host smart-b0e8ad53-6f3b-4261-af0b-94c7616e7558
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245608817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.245608817
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1781946427
Short name T437
Test name
Test status
Simulation time 383031328 ps
CPU time 6.36 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:13:43 PM PST 24
Peak memory 218180 kb
Host smart-77d20d20-b3b8-4a8e-a037-24a5545ea5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781946427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1781946427
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.135613552
Short name T413
Test name
Test status
Simulation time 194514248 ps
CPU time 1.91 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:31 PM PST 24
Peak memory 213384 kb
Host smart-fed706e7-2b0b-4573-89a3-e3f875d2cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135613552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.135613552
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.385184565
Short name T553
Test name
Test status
Simulation time 185004223 ps
CPU time 20.33 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:14:00 PM PST 24
Peak memory 251084 kb
Host smart-b999aa1b-70d7-4324-b592-6d0325017781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385184565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.385184565
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2843601905
Short name T724
Test name
Test status
Simulation time 272639637 ps
CPU time 3.46 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:37 PM PST 24
Peak memory 222560 kb
Host smart-e06ecdda-e0f5-4c2c-b77e-72a3620dec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843601905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2843601905
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.636060462
Short name T866
Test name
Test status
Simulation time 10619292420 ps
CPU time 134.91 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:15:51 PM PST 24
Peak memory 283936 kb
Host smart-173e02b2-e8aa-4c42-af0c-5208bb19930d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636060462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.636060462
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.830729088
Short name T644
Test name
Test status
Simulation time 15154336 ps
CPU time 0.77 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:33 PM PST 24
Peak memory 208100 kb
Host smart-ce98e03b-65c1-4435-b1ce-a1e77b9a3476
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830729088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.830729088
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3785471911
Short name T596
Test name
Test status
Simulation time 56275139 ps
CPU time 1.07 seconds
Started Jan 03 01:13:02 PM PST 24
Finished Jan 03 01:13:47 PM PST 24
Peak memory 209708 kb
Host smart-3bec89f2-d8ab-4652-9b07-a5c633188cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785471911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3785471911
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3795091460
Short name T513
Test name
Test status
Simulation time 352876700 ps
CPU time 15.14 seconds
Started Jan 03 01:13:07 PM PST 24
Finished Jan 03 01:14:09 PM PST 24
Peak memory 218160 kb
Host smart-71e25894-bc00-419d-be70-5e1afda5513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795091460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3795091460
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2329833166
Short name T924
Test name
Test status
Simulation time 1986676866 ps
CPU time 31.77 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:14:05 PM PST 24
Peak memory 218196 kb
Host smart-62ff6cc3-0358-480b-bafe-a38b612534ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329833166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2329833166
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3712340827
Short name T443
Test name
Test status
Simulation time 159185963 ps
CPU time 2.35 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 218108 kb
Host smart-c341dd9a-5e03-4222-960a-2d732a7b8a63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712340827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3712340827
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.4045057645
Short name T610
Test name
Test status
Simulation time 340449824 ps
CPU time 9.78 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 213664 kb
Host smart-908a2369-a784-48c7-b472-adec8cb3b105
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045057645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.4045057645
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1212938300
Short name T465
Test name
Test status
Simulation time 8284664451 ps
CPU time 67.04 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:14:49 PM PST 24
Peak memory 272484 kb
Host smart-4ab5b039-9721-4c42-94f4-87f6359406f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212938300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1212938300
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3967308280
Short name T580
Test name
Test status
Simulation time 2123524389 ps
CPU time 21.58 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:14:04 PM PST 24
Peak memory 248360 kb
Host smart-35d6d1f7-c138-4e1a-bab6-bbb0892e0ebc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967308280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3967308280
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.842657211
Short name T504
Test name
Test status
Simulation time 75283382 ps
CPU time 2.07 seconds
Started Jan 03 01:13:07 PM PST 24
Finished Jan 03 01:13:57 PM PST 24
Peak memory 218148 kb
Host smart-8502db29-0468-4b15-ae26-05d1cced3c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842657211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.842657211
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1587841900
Short name T559
Test name
Test status
Simulation time 686135924 ps
CPU time 17.81 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:13:48 PM PST 24
Peak memory 219248 kb
Host smart-b765067a-00ec-4350-9d29-40d81377a255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587841900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1587841900
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2991388504
Short name T429
Test name
Test status
Simulation time 2447918017 ps
CPU time 14.46 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:13:57 PM PST 24
Peak memory 218248 kb
Host smart-53b8307a-ad77-49bf-9b64-41ccfa777763
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991388504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2991388504
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1011217395
Short name T944
Test name
Test status
Simulation time 515653606 ps
CPU time 9.76 seconds
Started Jan 03 01:13:08 PM PST 24
Finished Jan 03 01:14:04 PM PST 24
Peak memory 218096 kb
Host smart-300cea69-da05-43a2-9cb8-4852b691af90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011217395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1011217395
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.4151398284
Short name T554
Test name
Test status
Simulation time 297447322 ps
CPU time 8.2 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:13:50 PM PST 24
Peak memory 218216 kb
Host smart-a4d5f94a-e5a7-49da-ab98-c15d0fda5e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151398284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.4151398284
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2341238
Short name T334
Test name
Test status
Simulation time 250793961 ps
CPU time 5.08 seconds
Started Jan 03 01:13:05 PM PST 24
Finished Jan 03 01:13:57 PM PST 24
Peak memory 217824 kb
Host smart-d9951680-51da-4b79-9771-48f84303ddba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2341238
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.14282857
Short name T719
Test name
Test status
Simulation time 1105775902 ps
CPU time 30.06 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:14:09 PM PST 24
Peak memory 251108 kb
Host smart-5870ba2b-4091-46cd-9921-350f4978749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14282857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.14282857
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.4147083384
Short name T754
Test name
Test status
Simulation time 327945950 ps
CPU time 7.58 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:48 PM PST 24
Peak memory 250988 kb
Host smart-fc7d9f49-c2be-4c34-b5f6-471e7a3e7ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147083384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.4147083384
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2975544065
Short name T704
Test name
Test status
Simulation time 4223444303 ps
CPU time 69.66 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:14:49 PM PST 24
Peak memory 251236 kb
Host smart-4f862bc6-8a83-42f8-a92d-d6c6e42ea167
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975544065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2975544065
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2742353492
Short name T692
Test name
Test status
Simulation time 18705663 ps
CPU time 0.76 seconds
Started Jan 03 01:13:05 PM PST 24
Finished Jan 03 01:13:53 PM PST 24
Peak memory 207820 kb
Host smart-2bc4e8b8-f71b-4179-812f-2a65a3a12abf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742353492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2742353492
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2859140972
Short name T661
Test name
Test status
Simulation time 11497203 ps
CPU time 0.98 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 209664 kb
Host smart-2bec5b03-c2ba-400c-8ab7-69968e92af69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859140972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2859140972
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2002647133
Short name T339
Test name
Test status
Simulation time 998184951 ps
CPU time 12.83 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:44 PM PST 24
Peak memory 218280 kb
Host smart-eb46c83f-a080-4a79-b230-7c213a7f72bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002647133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2002647133
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1671238641
Short name T26
Test name
Test status
Simulation time 1866783608 ps
CPU time 11.41 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 209596 kb
Host smart-526027ae-34ea-4677-b682-c58032883fea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671238641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.1671238641
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3917423254
Short name T936
Test name
Test status
Simulation time 5273952642 ps
CPU time 22.5 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:54 PM PST 24
Peak memory 218504 kb
Host smart-246b08b1-9e62-46c0-b521-fa0d81b0cc99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917423254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3917423254
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2132283676
Short name T727
Test name
Test status
Simulation time 150399688 ps
CPU time 3.2 seconds
Started Jan 03 01:13:02 PM PST 24
Finished Jan 03 01:13:50 PM PST 24
Peak memory 218144 kb
Host smart-adb0fe21-33eb-4c89-8783-776a1ae09080
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132283676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2132283676
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3874788163
Short name T688
Test name
Test status
Simulation time 1714327215 ps
CPU time 6.16 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 213492 kb
Host smart-e99e2c94-619e-4bac-a487-7a3dc9008196
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874788163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3874788163
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.895454327
Short name T953
Test name
Test status
Simulation time 27436368480 ps
CPU time 68.7 seconds
Started Jan 03 01:13:09 PM PST 24
Finished Jan 03 01:15:04 PM PST 24
Peak memory 267564 kb
Host smart-28f1f9bd-570e-4b78-85af-9e00dcc93d3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895454327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.895454327
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.188603190
Short name T374
Test name
Test status
Simulation time 1527270266 ps
CPU time 12.93 seconds
Started Jan 03 01:12:56 PM PST 24
Finished Jan 03 01:13:47 PM PST 24
Peak memory 251148 kb
Host smart-ee480294-a240-4deb-b9c0-1ac7ff1d09cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188603190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.188603190
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3069937320
Short name T947
Test name
Test status
Simulation time 271694497 ps
CPU time 3.47 seconds
Started Jan 03 01:13:02 PM PST 24
Finished Jan 03 01:13:50 PM PST 24
Peak memory 218204 kb
Host smart-cd7c6390-514d-42fa-94a0-7bd33b015f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069937320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3069937320
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3089315413
Short name T361
Test name
Test status
Simulation time 217994991 ps
CPU time 8.94 seconds
Started Jan 03 01:13:03 PM PST 24
Finished Jan 03 01:13:57 PM PST 24
Peak memory 219228 kb
Host smart-25ccf491-0cf5-4c4c-a254-81da49254833
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089315413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3089315413
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.4187386373
Short name T579
Test name
Test status
Simulation time 1912455765 ps
CPU time 16.55 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:56 PM PST 24
Peak memory 218048 kb
Host smart-69e1ae97-462b-468f-829c-ce57358a6cab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187386373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.4187386373
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.669571185
Short name T678
Test name
Test status
Simulation time 2267781049 ps
CPU time 11.92 seconds
Started Jan 03 01:13:03 PM PST 24
Finished Jan 03 01:14:00 PM PST 24
Peak memory 218204 kb
Host smart-f474f83b-99e2-47e2-a6ed-0bff2dac515b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669571185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.669571185
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.345295104
Short name T728
Test name
Test status
Simulation time 483470020 ps
CPU time 10.64 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:44 PM PST 24
Peak memory 218304 kb
Host smart-e058632e-4b0f-4fff-acd8-7981cff58f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345295104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.345295104
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2044227695
Short name T71
Test name
Test status
Simulation time 21597731 ps
CPU time 1.27 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 213196 kb
Host smart-61294d0a-13f3-4b7c-ad7c-d6897477b842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044227695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2044227695
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.302820906
Short name T846
Test name
Test status
Simulation time 425477615 ps
CPU time 26.88 seconds
Started Jan 03 01:13:08 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 251144 kb
Host smart-3d103176-9e09-42d7-9a76-6a3a05364299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302820906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.302820906
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2837602003
Short name T319
Test name
Test status
Simulation time 106701321 ps
CPU time 8.67 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 251192 kb
Host smart-4cc5682c-7aa1-457c-93d4-68323439c071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837602003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2837602003
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1241236476
Short name T890
Test name
Test status
Simulation time 5162038337 ps
CPU time 192.5 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:16:54 PM PST 24
Peak memory 277296 kb
Host smart-64551951-ae80-4dcb-8ca8-c4c3927ad2d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241236476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1241236476
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2960679860
Short name T365
Test name
Test status
Simulation time 45461201 ps
CPU time 0.92 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:31 PM PST 24
Peak memory 211464 kb
Host smart-b6ff5b13-517f-4e67-99e0-042cc87d1cf8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960679860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2960679860
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1262801593
Short name T364
Test name
Test status
Simulation time 18944825 ps
CPU time 0.9 seconds
Started Jan 03 01:13:09 PM PST 24
Finished Jan 03 01:13:57 PM PST 24
Peak memory 209728 kb
Host smart-615444c1-29b3-4a94-8121-1e6fb71ccd39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262801593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1262801593
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3084703081
Short name T570
Test name
Test status
Simulation time 707564086 ps
CPU time 11.89 seconds
Started Jan 03 01:13:01 PM PST 24
Finished Jan 03 01:13:54 PM PST 24
Peak memory 218240 kb
Host smart-d01bc9c3-b2fe-4b00-a5e2-ac5d0f52174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084703081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3084703081
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3551249562
Short name T703
Test name
Test status
Simulation time 95189307 ps
CPU time 1.11 seconds
Started Jan 03 01:13:05 PM PST 24
Finished Jan 03 01:13:54 PM PST 24
Peak memory 209556 kb
Host smart-28c97d9c-a098-4d01-9ba5-315e917d0912
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551249562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.3551249562
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1726815147
Short name T343
Test name
Test status
Simulation time 7248745486 ps
CPU time 28.45 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:14:07 PM PST 24
Peak memory 218460 kb
Host smart-fb592f6c-71b9-4ac4-96a4-af60ca03f95b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726815147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1726815147
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3077835412
Short name T737
Test name
Test status
Simulation time 400098706 ps
CPU time 9.3 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:13:46 PM PST 24
Peak memory 218148 kb
Host smart-7e7c390e-9e12-4c57-8fb4-733bdc0946f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077835412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3077835412
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.291155804
Short name T82
Test name
Test status
Simulation time 391938885 ps
CPU time 5.19 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 213020 kb
Host smart-628797ca-d033-4624-bde3-e689c2b97c04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291155804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
291155804
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1032244928
Short name T657
Test name
Test status
Simulation time 972641638 ps
CPU time 46.21 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:14:26 PM PST 24
Peak memory 251032 kb
Host smart-49f42a67-1ca3-4665-95f8-33b489e58165
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032244928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1032244928
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2121086979
Short name T21
Test name
Test status
Simulation time 706507862 ps
CPU time 15.11 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:13:53 PM PST 24
Peak memory 251104 kb
Host smart-915ebc90-e3fe-4a28-8895-f3c7fe9efa80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121086979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2121086979
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3813347953
Short name T516
Test name
Test status
Simulation time 308958559 ps
CPU time 2.79 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 218192 kb
Host smart-95cb97fe-8b22-4030-80f3-ede5aa3986c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813347953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3813347953
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1503554799
Short name T58
Test name
Test status
Simulation time 1374057912 ps
CPU time 12.24 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:14:03 PM PST 24
Peak memory 219224 kb
Host smart-95aa50cd-abac-42aa-8fc5-fc2a106d45b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503554799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1503554799
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.993448547
Short name T309
Test name
Test status
Simulation time 326775383 ps
CPU time 9.93 seconds
Started Jan 03 01:13:07 PM PST 24
Finished Jan 03 01:14:04 PM PST 24
Peak memory 218104 kb
Host smart-204f3119-0c21-4c0a-acd3-962e700967b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993448547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.993448547
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1553012802
Short name T722
Test name
Test status
Simulation time 248270975 ps
CPU time 8.53 seconds
Started Jan 03 01:13:07 PM PST 24
Finished Jan 03 01:14:03 PM PST 24
Peak memory 218100 kb
Host smart-6aaa516e-a61a-43c6-aed0-852961595f38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553012802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1553012802
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1959020486
Short name T198
Test name
Test status
Simulation time 1198199313 ps
CPU time 8.7 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 218176 kb
Host smart-c931f941-17e9-4ce6-b67e-f33395f7ba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959020486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1959020486
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2760653604
Short name T633
Test name
Test status
Simulation time 44097473 ps
CPU time 2.77 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:13:53 PM PST 24
Peak memory 213616 kb
Host smart-97d89e9b-40fe-4841-bbf7-cb9fc24078c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760653604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2760653604
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2273912464
Short name T521
Test name
Test status
Simulation time 198928620 ps
CPU time 16.7 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:49 PM PST 24
Peak memory 251032 kb
Host smart-fa1d45e7-8642-46cb-a3f0-eb78b142eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273912464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2273912464
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2107485776
Short name T473
Test name
Test status
Simulation time 267410276 ps
CPU time 8.05 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:13:49 PM PST 24
Peak memory 251104 kb
Host smart-9229bc5b-ac88-44a6-93df-953239fcec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107485776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2107485776
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3621300178
Short name T786
Test name
Test status
Simulation time 3186748242 ps
CPU time 70.96 seconds
Started Jan 03 01:13:09 PM PST 24
Finished Jan 03 01:15:07 PM PST 24
Peak memory 250856 kb
Host smart-dd8bdaaf-c099-420a-bb0c-04768ec8ecf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621300178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3621300178
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2671348217
Short name T875
Test name
Test status
Simulation time 19492218074 ps
CPU time 384.42 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:20:15 PM PST 24
Peak memory 333320 kb
Host smart-5a52aa5b-9238-46cd-a384-d0d47abfe9f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2671348217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2671348217
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4082163061
Short name T363
Test name
Test status
Simulation time 40196465 ps
CPU time 0.85 seconds
Started Jan 03 01:12:57 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 208372 kb
Host smart-538d1adc-ad89-4780-af91-95355d7d2fa4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082163061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4082163061
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3214485644
Short name T492
Test name
Test status
Simulation time 75759900 ps
CPU time 0.88 seconds
Started Jan 03 01:13:43 PM PST 24
Finished Jan 03 01:14:13 PM PST 24
Peak memory 209624 kb
Host smart-e4334e20-4cd6-404d-8d4d-e0fcd33e684a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214485644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3214485644
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1638414798
Short name T743
Test name
Test status
Simulation time 1133883553 ps
CPU time 12.27 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:14:02 PM PST 24
Peak memory 218208 kb
Host smart-383ae476-bf8f-4aee-8588-fc616cf8e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638414798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1638414798
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3738670394
Short name T572
Test name
Test status
Simulation time 779261595 ps
CPU time 9.55 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:49 PM PST 24
Peak memory 209684 kb
Host smart-af12ca92-0937-4bc8-b9ae-33e9b80fc4ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738670394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.3738670394
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.127560913
Short name T55
Test name
Test status
Simulation time 2052074005 ps
CPU time 31.51 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 218132 kb
Host smart-cec15520-a7e7-4776-8a0a-72343d2e8b9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127560913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.127560913
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.516589602
Short name T419
Test name
Test status
Simulation time 3037564634 ps
CPU time 20.82 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:14:03 PM PST 24
Peak memory 218096 kb
Host smart-9a62f69b-8514-40df-be6f-5dc5cf3a46e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516589602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.516589602
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3169147330
Short name T798
Test name
Test status
Simulation time 69377011 ps
CPU time 1.58 seconds
Started Jan 03 01:13:07 PM PST 24
Finished Jan 03 01:13:56 PM PST 24
Peak memory 212708 kb
Host smart-a7c14589-8074-437b-85e4-f750c9e81c53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169147330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3169147330
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3728572869
Short name T388
Test name
Test status
Simulation time 1072902210 ps
CPU time 52.12 seconds
Started Jan 03 01:12:58 PM PST 24
Finished Jan 03 01:14:31 PM PST 24
Peak memory 251496 kb
Host smart-76146dc8-3353-434b-8f96-260a90d468ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728572869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3728572869
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1931995036
Short name T573
Test name
Test status
Simulation time 508092079 ps
CPU time 20.4 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:14:00 PM PST 24
Peak memory 251096 kb
Host smart-f0a88ee8-1a0b-48d1-b8b4-473efe1077cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931995036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1931995036
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1408494843
Short name T353
Test name
Test status
Simulation time 29951830 ps
CPU time 1.77 seconds
Started Jan 03 01:12:55 PM PST 24
Finished Jan 03 01:13:35 PM PST 24
Peak memory 218276 kb
Host smart-74eff235-2dc5-431d-a6fb-7eb7fb23855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408494843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1408494843
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1251823145
Short name T337
Test name
Test status
Simulation time 407045419 ps
CPU time 12.15 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:52 PM PST 24
Peak memory 219224 kb
Host smart-db9b4efc-facc-409f-a5ea-1486ba0aa49c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251823145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1251823145
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2577234030
Short name T371
Test name
Test status
Simulation time 593841334 ps
CPU time 20.99 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:14:03 PM PST 24
Peak memory 218168 kb
Host smart-91ee26ec-78fe-4559-bbe1-9b5e87d69ff0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577234030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2577234030
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.759008570
Short name T331
Test name
Test status
Simulation time 238207971 ps
CPU time 6.79 seconds
Started Jan 03 01:13:00 PM PST 24
Finished Jan 03 01:13:49 PM PST 24
Peak memory 218180 kb
Host smart-d8b9402b-5705-4f09-bdbc-cd9384261513
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759008570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.759008570
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2707324865
Short name T723
Test name
Test status
Simulation time 600987315 ps
CPU time 12.13 seconds
Started Jan 03 01:13:04 PM PST 24
Finished Jan 03 01:14:02 PM PST 24
Peak memory 218204 kb
Host smart-83b82661-a0fe-4181-bb84-c73b5bb0c204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707324865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2707324865
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3448289801
Short name T756
Test name
Test status
Simulation time 119120584 ps
CPU time 5.3 seconds
Started Jan 03 01:13:09 PM PST 24
Finished Jan 03 01:14:01 PM PST 24
Peak memory 214396 kb
Host smart-296f9890-cc8a-4c51-9ffe-2f066c219a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448289801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3448289801
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3369348520
Short name T484
Test name
Test status
Simulation time 977194550 ps
CPU time 24.62 seconds
Started Jan 03 01:13:08 PM PST 24
Finished Jan 03 01:14:19 PM PST 24
Peak memory 251084 kb
Host smart-300e225d-1b07-47fe-9cd7-179179ab29be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369348520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3369348520
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4009523065
Short name T744
Test name
Test status
Simulation time 194765015 ps
CPU time 8.43 seconds
Started Jan 03 01:12:59 PM PST 24
Finished Jan 03 01:13:48 PM PST 24
Peak memory 251204 kb
Host smart-6aa6ce15-4afa-4019-ad4f-a83bf55579de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009523065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4009523065
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.579193927
Short name T511
Test name
Test status
Simulation time 4118625175 ps
CPU time 86.47 seconds
Started Jan 03 01:13:01 PM PST 24
Finished Jan 03 01:15:11 PM PST 24
Peak memory 267588 kb
Host smart-8a481a24-6bbb-4641-a51d-be0208368914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579193927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.579193927
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2176391096
Short name T651
Test name
Test status
Simulation time 13429187 ps
CPU time 0.89 seconds
Started Jan 03 01:13:05 PM PST 24
Finished Jan 03 01:13:52 PM PST 24
Peak memory 207732 kb
Host smart-e8ecc4c9-c621-40d2-aa72-d695774029d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176391096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2176391096
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.438076305
Short name T923
Test name
Test status
Simulation time 17855763 ps
CPU time 1.08 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:33 PM PST 24
Peak memory 209716 kb
Host smart-e8e2680f-2dbd-4a48-b6ef-817a685852ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438076305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.438076305
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2095963634
Short name T855
Test name
Test status
Simulation time 11923364 ps
CPU time 0.94 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:29 PM PST 24
Peak memory 208164 kb
Host smart-cb2511ce-d7f5-4938-beec-9120697dbc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095963634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2095963634
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.110829912
Short name T735
Test name
Test status
Simulation time 1017079771 ps
CPU time 10.75 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:39 PM PST 24
Peak memory 218140 kb
Host smart-53cd2a1e-740d-4ab3-8a86-498a912ce5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110829912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.110829912
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.68991336
Short name T790
Test name
Test status
Simulation time 865074263 ps
CPU time 4.99 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:38 PM PST 24
Peak memory 209796 kb
Host smart-2d2c304f-e399-4486-8794-bc6e3600f2ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68991336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_acce
ss.68991336
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3033666715
Short name T903
Test name
Test status
Simulation time 6349451128 ps
CPU time 28.03 seconds
Started Jan 03 01:11:52 PM PST 24
Finished Jan 03 01:12:57 PM PST 24
Peak memory 218516 kb
Host smart-fc631d0e-e4c6-481d-9955-26eedabebdea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033666715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3033666715
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1039679206
Short name T6
Test name
Test status
Simulation time 186093775 ps
CPU time 2.92 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:34 PM PST 24
Peak memory 209756 kb
Host smart-6d1675b3-0b41-4d9a-84cb-a891bb7771df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039679206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.1039679206
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1214721504
Short name T834
Test name
Test status
Simulation time 94851044 ps
CPU time 2.38 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:31 PM PST 24
Peak memory 218096 kb
Host smart-06fc0e99-ec81-4495-9c36-236b43c18cf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214721504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1214721504
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2958551331
Short name T648
Test name
Test status
Simulation time 2079265782 ps
CPU time 17.46 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:48 PM PST 24
Peak memory 213244 kb
Host smart-82d01261-e33b-4527-a248-c9dbaadee58a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958551331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2958551331
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1692901622
Short name T959
Test name
Test status
Simulation time 2989805581 ps
CPU time 3.46 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:31 PM PST 24
Peak memory 213600 kb
Host smart-c645ec62-f4a1-4ffd-8c8d-f7a032be9787
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692901622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1692901622
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1259343574
Short name T607
Test name
Test status
Simulation time 7605555238 ps
CPU time 68.62 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:13:37 PM PST 24
Peak memory 283924 kb
Host smart-724b8b7e-f5c3-439d-8e50-8f926e043895
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259343574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1259343574
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1052119720
Short name T874
Test name
Test status
Simulation time 1657486007 ps
CPU time 8.23 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:34 PM PST 24
Peak memory 222656 kb
Host smart-cecd1de1-78cd-4b3c-aa23-d93eb5d49c2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052119720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1052119720
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3464026823
Short name T512
Test name
Test status
Simulation time 22076111 ps
CPU time 1.7 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:28 PM PST 24
Peak memory 218224 kb
Host smart-24a23035-6208-4dab-adf9-a9cfd3716a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464026823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3464026823
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.362593497
Short name T613
Test name
Test status
Simulation time 212135502 ps
CPU time 11.73 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:40 PM PST 24
Peak memory 213580 kb
Host smart-372512f1-1ccd-4e9a-ba40-67107b2908b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362593497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.362593497
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2307978236
Short name T106
Test name
Test status
Simulation time 196447644 ps
CPU time 23.93 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:59 PM PST 24
Peak memory 282048 kb
Host smart-f6b2d189-2e5f-4d12-a443-8021ec76e39b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307978236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2307978236
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1215809134
Short name T548
Test name
Test status
Simulation time 741746021 ps
CPU time 15.45 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:12:48 PM PST 24
Peak memory 218180 kb
Host smart-a86708be-be10-445f-9ec8-158169b177c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215809134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1215809134
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3994035378
Short name T33
Test name
Test status
Simulation time 591250169 ps
CPU time 12.14 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 218168 kb
Host smart-88460d07-8852-4150-9838-3501db1acdb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994035378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3994035378
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2132148751
Short name T555
Test name
Test status
Simulation time 1517475192 ps
CPU time 10.67 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:41 PM PST 24
Peak memory 218068 kb
Host smart-82e89a54-56f3-4864-b725-4a56a3108dca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132148751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
132148751
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.286627139
Short name T598
Test name
Test status
Simulation time 363848738 ps
CPU time 9.75 seconds
Started Jan 03 01:11:51 PM PST 24
Finished Jan 03 01:12:38 PM PST 24
Peak memory 218036 kb
Host smart-b90a4378-7fc1-4656-951c-007361352e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286627139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.286627139
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1741470605
Short name T832
Test name
Test status
Simulation time 112996073 ps
CPU time 1.45 seconds
Started Jan 03 01:11:59 PM PST 24
Finished Jan 03 01:12:39 PM PST 24
Peak memory 213144 kb
Host smart-b2c4ac14-0539-495a-83f7-6a9c89d6ccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741470605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1741470605
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3312349666
Short name T561
Test name
Test status
Simulation time 3091868255 ps
CPU time 25.79 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:51 PM PST 24
Peak memory 251224 kb
Host smart-9903e6eb-de02-40c4-8718-8c6ba3b851e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312349666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3312349666
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2366250135
Short name T470
Test name
Test status
Simulation time 1441697283 ps
CPU time 8.16 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:34 PM PST 24
Peak memory 251132 kb
Host smart-397429f7-ce88-4f47-bd81-81abe6877d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366250135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2366250135
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.663856262
Short name T528
Test name
Test status
Simulation time 6995712424 ps
CPU time 82.17 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:13:53 PM PST 24
Peak memory 276152 kb
Host smart-8dfb3d68-710b-42ac-aa27-2265c7a12b90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663856262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.663856262
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2473671137
Short name T710
Test name
Test status
Simulation time 11903714 ps
CPU time 0.87 seconds
Started Jan 03 01:11:50 PM PST 24
Finished Jan 03 01:12:27 PM PST 24
Peak memory 207820 kb
Host smart-124d0f05-f5a4-4aed-95db-471b34ec4b51
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473671137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2473671137
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3860065424
Short name T945
Test name
Test status
Simulation time 17024405 ps
CPU time 1.07 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:14:45 PM PST 24
Peak memory 209724 kb
Host smart-ae86bc9f-c3ab-4e0f-a599-5382f95924b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860065424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3860065424
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1498658110
Short name T954
Test name
Test status
Simulation time 8031375861 ps
CPU time 23.88 seconds
Started Jan 03 01:13:45 PM PST 24
Finished Jan 03 01:14:37 PM PST 24
Peak memory 218468 kb
Host smart-4271f5af-e176-476c-bdcc-40bfa568be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498658110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1498658110
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4159638262
Short name T7
Test name
Test status
Simulation time 11749940227 ps
CPU time 15.24 seconds
Started Jan 03 01:13:44 PM PST 24
Finished Jan 03 01:14:28 PM PST 24
Peak memory 209680 kb
Host smart-1c5b154b-1e0c-41fd-bd7c-f4a4146ebc67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159638262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.4159638262
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.662497393
Short name T801
Test name
Test status
Simulation time 43979664 ps
CPU time 1.94 seconds
Started Jan 03 01:13:54 PM PST 24
Finished Jan 03 01:14:20 PM PST 24
Peak memory 218252 kb
Host smart-4a695367-3522-45e7-88f0-02f37309564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662497393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.662497393
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3875622951
Short name T650
Test name
Test status
Simulation time 1389024232 ps
CPU time 19.68 seconds
Started Jan 03 01:13:55 PM PST 24
Finished Jan 03 01:14:38 PM PST 24
Peak memory 218712 kb
Host smart-458a44a5-86e9-4aca-a9f9-ce05fa8187a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875622951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3875622951
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2148410321
Short name T810
Test name
Test status
Simulation time 936689944 ps
CPU time 7.04 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:30 PM PST 24
Peak memory 218176 kb
Host smart-64405bd3-16b6-41e8-847d-05979f1409f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148410321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2148410321
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1267540037
Short name T574
Test name
Test status
Simulation time 1267069084 ps
CPU time 9.44 seconds
Started Jan 03 01:14:01 PM PST 24
Finished Jan 03 01:14:35 PM PST 24
Peak memory 218112 kb
Host smart-4006570e-cb83-4b48-ba55-f8b4b862b8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267540037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1267540037
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.132941019
Short name T91
Test name
Test status
Simulation time 452404168 ps
CPU time 6.03 seconds
Started Jan 03 01:13:44 PM PST 24
Finished Jan 03 01:14:19 PM PST 24
Peak memory 218204 kb
Host smart-9ee58fe6-ab46-40aa-a6b5-8a858a0305fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132941019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.132941019
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.533841159
Short name T972
Test name
Test status
Simulation time 468079022 ps
CPU time 2.25 seconds
Started Jan 03 01:13:37 PM PST 24
Finished Jan 03 01:14:13 PM PST 24
Peak memory 213744 kb
Host smart-17533f60-901e-4103-bade-4a90a45632c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533841159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.533841159
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.53207101
Short name T931
Test name
Test status
Simulation time 1349891874 ps
CPU time 29.39 seconds
Started Jan 03 01:13:44 PM PST 24
Finished Jan 03 01:14:42 PM PST 24
Peak memory 251144 kb
Host smart-176ed1ed-928c-44d3-8fa1-27642ea76ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53207101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.53207101
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.720122448
Short name T398
Test name
Test status
Simulation time 134383485 ps
CPU time 8.12 seconds
Started Jan 03 01:13:45 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 251208 kb
Host smart-d1996dff-f870-4c87-8b91-26c970deb3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720122448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.720122448
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4293758533
Short name T43
Test name
Test status
Simulation time 23511371 ps
CPU time 0.76 seconds
Started Jan 03 01:13:42 PM PST 24
Finished Jan 03 01:14:13 PM PST 24
Peak memory 208040 kb
Host smart-0d776e93-ae5f-4145-a87d-1e1808b6058e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293758533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.4293758533
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2997894135
Short name T311
Test name
Test status
Simulation time 57701034 ps
CPU time 0.92 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:48 PM PST 24
Peak memory 209672 kb
Host smart-706b00a3-f3fb-49a7-b9ee-04ba197e251f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997894135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2997894135
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1954244139
Short name T696
Test name
Test status
Simulation time 534048336 ps
CPU time 14.57 seconds
Started Jan 03 01:14:00 PM PST 24
Finished Jan 03 01:14:38 PM PST 24
Peak memory 218204 kb
Host smart-ed9bd24c-9772-4532-a45e-88efa34ca73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954244139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1954244139
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2108282306
Short name T862
Test name
Test status
Simulation time 48311248 ps
CPU time 1.21 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:14:45 PM PST 24
Peak memory 209608 kb
Host smart-430f7a73-c937-4b3c-840a-cf80a4884f20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108282306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.2108282306
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3277755656
Short name T732
Test name
Test status
Simulation time 71597789 ps
CPU time 3.53 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:51 PM PST 24
Peak memory 218264 kb
Host smart-f39921b2-ddc3-4dfd-a6a4-b8f7ebebd538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277755656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3277755656
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3065041996
Short name T847
Test name
Test status
Simulation time 749448302 ps
CPU time 10.25 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:01 PM PST 24
Peak memory 218124 kb
Host smart-05110287-0eb8-4e53-8399-7978b2e3e50d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065041996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3065041996
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3471053050
Short name T522
Test name
Test status
Simulation time 1035685636 ps
CPU time 7.14 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:54 PM PST 24
Peak memory 218116 kb
Host smart-07f4ff0a-18b5-4e7d-bce9-447c1d1ed22e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471053050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3471053050
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3865482250
Short name T886
Test name
Test status
Simulation time 383731678 ps
CPU time 7.08 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:14:58 PM PST 24
Peak memory 218148 kb
Host smart-072a10c0-8058-43aa-966f-d1b67bbe1c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865482250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3865482250
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3458594814
Short name T958
Test name
Test status
Simulation time 11701072 ps
CPU time 0.97 seconds
Started Jan 03 01:14:01 PM PST 24
Finished Jan 03 01:14:27 PM PST 24
Peak memory 208756 kb
Host smart-eebef90c-9c0b-43b1-aa98-75747d896338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458594814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3458594814
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3020708457
Short name T360
Test name
Test status
Simulation time 1995102589 ps
CPU time 25.27 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:46 PM PST 24
Peak memory 251108 kb
Host smart-4e4aa2b1-8ade-49de-b454-bf5e92e3036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020708457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3020708457
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3789382830
Short name T539
Test name
Test status
Simulation time 631197838 ps
CPU time 8.9 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:31 PM PST 24
Peak memory 251224 kb
Host smart-64037a19-86c3-40ee-9049-8b6a243f7fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789382830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3789382830
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.527388564
Short name T669
Test name
Test status
Simulation time 13064772576 ps
CPU time 355.34 seconds
Started Jan 03 01:14:10 PM PST 24
Finished Jan 03 01:20:32 PM PST 24
Peak memory 253700 kb
Host smart-52d8d2a1-1a4c-447a-a77a-f5af5eb09e0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527388564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.527388564
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3306593455
Short name T859
Test name
Test status
Simulation time 11507745 ps
CPU time 0.85 seconds
Started Jan 03 01:13:56 PM PST 24
Finished Jan 03 01:14:20 PM PST 24
Peak memory 208272 kb
Host smart-d06d56fa-d4a7-4893-8217-ae298105ea25
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306593455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3306593455
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.281605163
Short name T783
Test name
Test status
Simulation time 24456511 ps
CPU time 0.93 seconds
Started Jan 03 01:14:44 PM PST 24
Finished Jan 03 01:15:38 PM PST 24
Peak memory 209636 kb
Host smart-95b29003-1543-4530-824e-a65d1619c2eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281605163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.281605163
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.123756061
Short name T540
Test name
Test status
Simulation time 2989153035 ps
CPU time 8.18 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:31 PM PST 24
Peak memory 218292 kb
Host smart-2df64235-2436-4560-9fd1-bcc22687a6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123756061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.123756061
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2097929898
Short name T547
Test name
Test status
Simulation time 88329519 ps
CPU time 3.02 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:24 PM PST 24
Peak memory 209712 kb
Host smart-88a98320-2fd5-4235-a175-6d9a8f872e10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097929898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.2097929898
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.630009053
Short name T658
Test name
Test status
Simulation time 57869430 ps
CPU time 1.42 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 218224 kb
Host smart-fde15912-753c-4be5-8359-400d798c34dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630009053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.630009053
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.297517750
Short name T920
Test name
Test status
Simulation time 384843603 ps
CPU time 10.24 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:15:03 PM PST 24
Peak memory 219224 kb
Host smart-80c1cc4f-f402-40d3-bb40-0c1c9bcf9000
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297517750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.297517750
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4261732923
Short name T763
Test name
Test status
Simulation time 271953672 ps
CPU time 11.49 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:15:39 PM PST 24
Peak memory 218176 kb
Host smart-528191ff-26f4-45f2-bd9a-66ad08877e00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261732923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4261732923
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2006503990
Short name T971
Test name
Test status
Simulation time 387525005 ps
CPU time 10.09 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:37 PM PST 24
Peak memory 218196 kb
Host smart-d0547581-e9e5-412c-a535-28aacb0ea2df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006503990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2006503990
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1077681974
Short name T134
Test name
Test status
Simulation time 1661769698 ps
CPU time 21.21 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:10 PM PST 24
Peak memory 218204 kb
Host smart-79083d20-fba6-48e9-8e5a-cfae7d9c92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077681974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1077681974
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2861029419
Short name T848
Test name
Test status
Simulation time 185217319 ps
CPU time 2.88 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:49 PM PST 24
Peak memory 214328 kb
Host smart-53030d12-0838-4cdb-8b30-6a04be4a212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861029419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2861029419
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3785658048
Short name T888
Test name
Test status
Simulation time 1081479262 ps
CPU time 20.66 seconds
Started Jan 03 01:14:24 PM PST 24
Finished Jan 03 01:15:17 PM PST 24
Peak memory 251152 kb
Host smart-6071cb47-8343-4674-ad8c-9aa9e93688d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785658048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3785658048
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3846260458
Short name T921
Test name
Test status
Simulation time 87060552 ps
CPU time 9.74 seconds
Started Jan 03 01:14:34 PM PST 24
Finished Jan 03 01:15:24 PM PST 24
Peak memory 251184 kb
Host smart-4b470857-ef4b-4e6f-a72d-5320149adb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846260458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3846260458
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1235465337
Short name T442
Test name
Test status
Simulation time 10357944142 ps
CPU time 188.61 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:18:37 PM PST 24
Peak memory 251192 kb
Host smart-ddf2c815-9655-417e-ba6a-b75e6c96c1ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235465337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1235465337
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3195373011
Short name T687
Test name
Test status
Simulation time 114758379 ps
CPU time 1.23 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:47 PM PST 24
Peak memory 212668 kb
Host smart-95e8a397-5a1f-4bc8-a6e4-0e00c0a40f1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195373011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3195373011
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3045822217
Short name T963
Test name
Test status
Simulation time 79468249 ps
CPU time 1.25 seconds
Started Jan 03 01:13:54 PM PST 24
Finished Jan 03 01:14:19 PM PST 24
Peak memory 209708 kb
Host smart-2b23ba69-91f5-4b3d-ad85-fd0c124513c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045822217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3045822217
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.644488741
Short name T478
Test name
Test status
Simulation time 522958985 ps
CPU time 19.85 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:56 PM PST 24
Peak memory 218112 kb
Host smart-5a2d97fd-c410-46d1-8678-cd564d518a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644488741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.644488741
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3640766128
Short name T679
Test name
Test status
Simulation time 3581475421 ps
CPU time 6.93 seconds
Started Jan 03 01:13:55 PM PST 24
Finished Jan 03 01:14:26 PM PST 24
Peak memory 209712 kb
Host smart-e233551f-b217-4b0e-ad1f-d00f85206a0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640766128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.3640766128
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2446052517
Short name T934
Test name
Test status
Simulation time 113803526 ps
CPU time 2.02 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:14:58 PM PST 24
Peak memory 218204 kb
Host smart-02e5be6f-7dc4-4592-85bc-cc51b506c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446052517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2446052517
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1555707834
Short name T552
Test name
Test status
Simulation time 339258183 ps
CPU time 11.36 seconds
Started Jan 03 01:13:44 PM PST 24
Finished Jan 03 01:14:25 PM PST 24
Peak memory 219168 kb
Host smart-4087ef69-3d00-4baf-91e4-a20bcc213570
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555707834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1555707834
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.43667202
Short name T439
Test name
Test status
Simulation time 636477085 ps
CPU time 11.6 seconds
Started Jan 03 01:13:37 PM PST 24
Finished Jan 03 01:14:23 PM PST 24
Peak memory 218080 kb
Host smart-8e5ea8e3-7c98-4f84-8a5a-dbf4692eb7ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43667202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_dig
est.43667202
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2362229862
Short name T317
Test name
Test status
Simulation time 2831014451 ps
CPU time 10.58 seconds
Started Jan 03 01:13:38 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 218236 kb
Host smart-d4e1bb87-dea6-490a-8eae-adbc843f823b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362229862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2362229862
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.261026698
Short name T491
Test name
Test status
Simulation time 1491852602 ps
CPU time 12.55 seconds
Started Jan 03 01:14:45 PM PST 24
Finished Jan 03 01:15:52 PM PST 24
Peak memory 218148 kb
Host smart-05898b6d-0b25-45f5-babc-70db184cc5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261026698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.261026698
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2514618714
Short name T402
Test name
Test status
Simulation time 138144251 ps
CPU time 2.66 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:36 PM PST 24
Peak memory 214400 kb
Host smart-a3d6c30d-aab5-4209-9786-0ab97ae9a644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514618714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2514618714
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4139904133
Short name T366
Test name
Test status
Simulation time 357148794 ps
CPU time 19.29 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:56 PM PST 24
Peak memory 251100 kb
Host smart-c106d11a-1f03-4d92-826a-0e4aa417f191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139904133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4139904133
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1126224207
Short name T595
Test name
Test status
Simulation time 153629090 ps
CPU time 3.2 seconds
Started Jan 03 01:14:44 PM PST 24
Finished Jan 03 01:15:41 PM PST 24
Peak memory 222428 kb
Host smart-188c57a4-02bb-47d8-8ea4-e98dc09e02df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126224207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1126224207
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.316845737
Short name T904
Test name
Test status
Simulation time 4840816397 ps
CPU time 106.67 seconds
Started Jan 03 01:13:48 PM PST 24
Finished Jan 03 01:16:02 PM PST 24
Peak memory 277432 kb
Host smart-dfcfcb21-8cf2-47ef-af46-989fd68972db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316845737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.316845737
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1643368711
Short name T131
Test name
Test status
Simulation time 10465913288 ps
CPU time 363.2 seconds
Started Jan 03 01:13:57 PM PST 24
Finished Jan 03 01:20:23 PM PST 24
Peak memory 284044 kb
Host smart-c6b28529-6573-4a81-9937-264c55ca925a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1643368711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1643368711
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3859283453
Short name T812
Test name
Test status
Simulation time 40393298 ps
CPU time 0.83 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:37 PM PST 24
Peak memory 208132 kb
Host smart-b034690e-a459-4829-937b-f93aa59d868f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859283453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3859283453
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3441991951
Short name T630
Test name
Test status
Simulation time 16513321 ps
CPU time 0.87 seconds
Started Jan 03 01:14:02 PM PST 24
Finished Jan 03 01:14:28 PM PST 24
Peak memory 209636 kb
Host smart-f9df7b9d-5a9d-40f5-9b7c-554d69126b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441991951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3441991951
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1618566492
Short name T962
Test name
Test status
Simulation time 461626450 ps
CPU time 17.76 seconds
Started Jan 03 01:13:56 PM PST 24
Finished Jan 03 01:14:38 PM PST 24
Peak memory 218148 kb
Host smart-192f6c1d-a61e-483d-b9d5-313946b96c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618566492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1618566492
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3361578731
Short name T655
Test name
Test status
Simulation time 1025510438 ps
CPU time 6.62 seconds
Started Jan 03 01:13:55 PM PST 24
Finished Jan 03 01:14:25 PM PST 24
Peak memory 209620 kb
Host smart-efae1b44-c4a3-4b7a-b5a6-77d05925c7d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361578731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_a
ccess.3361578731
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.4226022112
Short name T400
Test name
Test status
Simulation time 84388795 ps
CPU time 4.03 seconds
Started Jan 03 01:13:44 PM PST 24
Finished Jan 03 01:14:16 PM PST 24
Peak memory 218180 kb
Host smart-64a50769-c3ce-4d66-97c6-7e336000f09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226022112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.4226022112
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1553815246
Short name T707
Test name
Test status
Simulation time 395629217 ps
CPU time 18.19 seconds
Started Jan 03 01:13:55 PM PST 24
Finished Jan 03 01:14:37 PM PST 24
Peak memory 219204 kb
Host smart-9b1d0324-9e4f-4d2f-bcc3-cc7b73040bfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553815246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1553815246
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2800471674
Short name T316
Test name
Test status
Simulation time 3268521103 ps
CPU time 24.79 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:47 PM PST 24
Peak memory 218228 kb
Host smart-26df36c3-17c7-490c-acad-c3956b363c8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800471674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2800471674
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1478943180
Short name T586
Test name
Test status
Simulation time 1463756694 ps
CPU time 12.96 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:35 PM PST 24
Peak memory 218164 kb
Host smart-62ddfc33-9746-4578-9260-9a307bd990f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478943180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1478943180
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3262367860
Short name T665
Test name
Test status
Simulation time 459222161 ps
CPU time 10.17 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:33 PM PST 24
Peak memory 218152 kb
Host smart-9a2b6b1a-9c08-45e1-83e1-ea6d7f55534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262367860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3262367860
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3472607318
Short name T714
Test name
Test status
Simulation time 402941651 ps
CPU time 3.66 seconds
Started Jan 03 01:13:42 PM PST 24
Finished Jan 03 01:14:16 PM PST 24
Peak memory 214032 kb
Host smart-6ecf0dea-93f1-4bfd-8c10-cf7142cd6eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472607318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3472607318
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4235827378
Short name T615
Test name
Test status
Simulation time 205428031 ps
CPU time 21.21 seconds
Started Jan 03 01:13:45 PM PST 24
Finished Jan 03 01:14:35 PM PST 24
Peak memory 251152 kb
Host smart-02632e9c-9a71-4f29-b951-5fad48c1aaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235827378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4235827378
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3737953873
Short name T870
Test name
Test status
Simulation time 193526338 ps
CPU time 8.92 seconds
Started Jan 03 01:13:43 PM PST 24
Finished Jan 03 01:14:21 PM PST 24
Peak memory 246320 kb
Host smart-3be635e3-b125-4669-8e7f-a8092f8e603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737953873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3737953873
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2851899634
Short name T706
Test name
Test status
Simulation time 39585730683 ps
CPU time 251.28 seconds
Started Jan 03 01:13:57 PM PST 24
Finished Jan 03 01:18:31 PM PST 24
Peak memory 447828 kb
Host smart-60ccdfdd-ccf5-4881-af1e-47577b9716ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851899634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2851899634
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3338617695
Short name T524
Test name
Test status
Simulation time 13646809 ps
CPU time 0.99 seconds
Started Jan 03 01:13:53 PM PST 24
Finished Jan 03 01:14:19 PM PST 24
Peak memory 208460 kb
Host smart-2ab0b4e6-8652-4d6a-b21d-c917e8329f12
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338617695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3338617695
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1323984834
Short name T76
Test name
Test status
Simulation time 15985854 ps
CPU time 0.88 seconds
Started Jan 03 01:13:56 PM PST 24
Finished Jan 03 01:14:20 PM PST 24
Peak memory 209660 kb
Host smart-750e5f7f-edbc-491f-b84f-1f08485d2dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323984834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1323984834
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2342123289
Short name T130
Test name
Test status
Simulation time 400087817 ps
CPU time 16.49 seconds
Started Jan 03 01:14:02 PM PST 24
Finished Jan 03 01:14:43 PM PST 24
Peak memory 218236 kb
Host smart-cb243fc6-fa48-4103-acc0-ea3ac4f698e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342123289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2342123289
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.158339252
Short name T28
Test name
Test status
Simulation time 1781639028 ps
CPU time 3.58 seconds
Started Jan 03 01:13:45 PM PST 24
Finished Jan 03 01:14:17 PM PST 24
Peak memory 209620 kb
Host smart-09b1e2d1-1211-4e8e-bb35-432779540f8c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158339252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_ac
cess.158339252
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2779929559
Short name T820
Test name
Test status
Simulation time 116068114 ps
CPU time 3.32 seconds
Started Jan 03 01:13:56 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 218216 kb
Host smart-abfeccf3-49c1-4fc1-b56b-941ef1a4c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779929559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2779929559
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1815978370
Short name T626
Test name
Test status
Simulation time 614077553 ps
CPU time 9.33 seconds
Started Jan 03 01:13:46 PM PST 24
Finished Jan 03 01:14:23 PM PST 24
Peak memory 218416 kb
Host smart-7453d0ce-55f1-4da5-ad3a-42c69936156e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815978370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1815978370
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3255724347
Short name T464
Test name
Test status
Simulation time 1963932728 ps
CPU time 15.25 seconds
Started Jan 03 01:13:56 PM PST 24
Finished Jan 03 01:14:35 PM PST 24
Peak memory 218072 kb
Host smart-b3213313-7329-41b2-8a23-aa72f23dc151
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255724347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3255724347
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1085887304
Short name T350
Test name
Test status
Simulation time 1166993606 ps
CPU time 7.74 seconds
Started Jan 03 01:13:44 PM PST 24
Finished Jan 03 01:14:20 PM PST 24
Peak memory 218088 kb
Host smart-dc20d063-78b5-4635-8e5f-7c4620c9ec89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085887304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1085887304
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1476881992
Short name T543
Test name
Test status
Simulation time 1554394465 ps
CPU time 13.43 seconds
Started Jan 03 01:13:44 PM PST 24
Finished Jan 03 01:14:27 PM PST 24
Peak memory 218144 kb
Host smart-dcd6c305-4ee8-4ca8-9461-acab6dc28d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476881992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1476881992
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.705169181
Short name T75
Test name
Test status
Simulation time 160111584 ps
CPU time 2.54 seconds
Started Jan 03 01:14:00 PM PST 24
Finished Jan 03 01:14:26 PM PST 24
Peak memory 213748 kb
Host smart-348013af-9af2-4fa2-b5ef-d61182aa46d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705169181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.705169181
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2678478745
Short name T928
Test name
Test status
Simulation time 200862837 ps
CPU time 22.72 seconds
Started Jan 03 01:13:43 PM PST 24
Finished Jan 03 01:14:35 PM PST 24
Peak memory 251124 kb
Host smart-c12fd9f9-9573-49e7-832a-1e0b019d7132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678478745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2678478745
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1828146854
Short name T942
Test name
Test status
Simulation time 243669132 ps
CPU time 7.58 seconds
Started Jan 03 01:13:43 PM PST 24
Finished Jan 03 01:14:20 PM PST 24
Peak memory 251232 kb
Host smart-3375af4e-79bb-4e3e-bbf6-c783aa7ab2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828146854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1828146854
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1718396605
Short name T416
Test name
Test status
Simulation time 41737594683 ps
CPU time 373.06 seconds
Started Jan 03 01:13:55 PM PST 24
Finished Jan 03 01:20:32 PM PST 24
Peak memory 446900 kb
Host smart-b3ad120e-92c3-4707-a174-37b850052e23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718396605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1718396605
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1500560400
Short name T838
Test name
Test status
Simulation time 32721810 ps
CPU time 0.85 seconds
Started Jan 03 01:14:00 PM PST 24
Finished Jan 03 01:14:24 PM PST 24
Peak memory 208076 kb
Host smart-3dc13828-f86a-4cd0-b47a-45492e9e5a59
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500560400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1500560400
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1626157664
Short name T603
Test name
Test status
Simulation time 118802323 ps
CPU time 1.36 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:47 PM PST 24
Peak memory 209620 kb
Host smart-5c28aeb8-64a4-4a36-aad4-8b98f3f13b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626157664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1626157664
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2353626938
Short name T356
Test name
Test status
Simulation time 341608435 ps
CPU time 13.27 seconds
Started Jan 03 01:13:57 PM PST 24
Finished Jan 03 01:14:33 PM PST 24
Peak memory 218172 kb
Host smart-cbcf11cf-858f-4015-a4d5-7cc98cbd6a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353626938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2353626938
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3529743326
Short name T546
Test name
Test status
Simulation time 387034278 ps
CPU time 5.2 seconds
Started Jan 03 01:14:14 PM PST 24
Finished Jan 03 01:14:47 PM PST 24
Peak memory 209652 kb
Host smart-5483fe02-78f2-4ceb-ac4a-b40bff25a94d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529743326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.3529743326
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3444679939
Short name T507
Test name
Test status
Simulation time 397851878 ps
CPU time 2.44 seconds
Started Jan 03 01:13:57 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 218132 kb
Host smart-d5eea666-2c9a-44ad-a817-851d57bde649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444679939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3444679939
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.897213766
Short name T803
Test name
Test status
Simulation time 247843526 ps
CPU time 9.38 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:32 PM PST 24
Peak memory 218188 kb
Host smart-1b8b8060-9ab0-4af5-8178-2a33453e1510
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897213766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.897213766
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.609901485
Short name T795
Test name
Test status
Simulation time 423193283 ps
CPU time 9.19 seconds
Started Jan 03 01:14:00 PM PST 24
Finished Jan 03 01:14:33 PM PST 24
Peak memory 218104 kb
Host smart-36cec416-e9fc-4d0a-b58c-c12c7070dddf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609901485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.609901485
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3659589682
Short name T397
Test name
Test status
Simulation time 1164236471 ps
CPU time 10.57 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 218152 kb
Host smart-71fb3b4d-b29a-4e68-9fd7-ea3cd830e2f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659589682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3659589682
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2239851637
Short name T433
Test name
Test status
Simulation time 2435694778 ps
CPU time 14.7 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:37 PM PST 24
Peak memory 218156 kb
Host smart-cbb7ccca-4696-4834-852e-87761d90ad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239851637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2239851637
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3688988690
Short name T894
Test name
Test status
Simulation time 42028057 ps
CPU time 1.83 seconds
Started Jan 03 01:14:14 PM PST 24
Finished Jan 03 01:14:43 PM PST 24
Peak memory 213204 kb
Host smart-299ad34c-d253-4cfb-a22e-4cc7e71291da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688988690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3688988690
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2446765209
Short name T868
Test name
Test status
Simulation time 169131376 ps
CPU time 13.62 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:36 PM PST 24
Peak memory 251120 kb
Host smart-3d6de995-7f5a-4bb4-81fd-039eff18e30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446765209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2446765209
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3155983867
Short name T201
Test name
Test status
Simulation time 496350069 ps
CPU time 7.27 seconds
Started Jan 03 01:13:57 PM PST 24
Finished Jan 03 01:14:28 PM PST 24
Peak memory 246504 kb
Host smart-bba708d1-250c-42a4-bb20-d52d0d78d4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155983867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3155983867
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4084631156
Short name T74
Test name
Test status
Simulation time 13037403411 ps
CPU time 192.6 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:18:00 PM PST 24
Peak memory 247444 kb
Host smart-00a36040-b9f8-4782-82e7-c39a44032699
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084631156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4084631156
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2336236835
Short name T531
Test name
Test status
Simulation time 54464001 ps
CPU time 0.96 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 212496 kb
Host smart-10c7a00a-2a79-4008-9dec-45304356ab89
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336236835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2336236835
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4206104847
Short name T675
Test name
Test status
Simulation time 40389645 ps
CPU time 0.81 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:30 PM PST 24
Peak memory 208140 kb
Host smart-6b2825ea-ed58-44e1-b5a2-bb3c3cc67ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206104847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4206104847
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.4043199383
Short name T482
Test name
Test status
Simulation time 1849297464 ps
CPU time 11.85 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:01 PM PST 24
Peak memory 218288 kb
Host smart-74352081-9ac7-46e0-8433-385ca21adb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043199383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.4043199383
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.4200463738
Short name T617
Test name
Test status
Simulation time 51896899 ps
CPU time 1.77 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:32 PM PST 24
Peak memory 209672 kb
Host smart-cefaada1-a321-4717-a836-9323ac2d93bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200463738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.4200463738
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1841088607
Short name T373
Test name
Test status
Simulation time 86348504 ps
CPU time 2.75 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:51 PM PST 24
Peak memory 218212 kb
Host smart-b81a0c1d-590a-4b4e-b3d4-3baec4585d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841088607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1841088607
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.206415213
Short name T915
Test name
Test status
Simulation time 2845844888 ps
CPU time 12.79 seconds
Started Jan 03 01:14:41 PM PST 24
Finished Jan 03 01:15:44 PM PST 24
Peak memory 219236 kb
Host smart-35e92fc6-84b6-40fd-ad9f-ffbafc6d51c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206415213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.206415213
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2599666315
Short name T344
Test name
Test status
Simulation time 399468090 ps
CPU time 9.09 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:15:50 PM PST 24
Peak memory 218116 kb
Host smart-20fbad62-1de5-4164-bd5b-048604b05ad5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599666315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2599666315
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.664298136
Short name T459
Test name
Test status
Simulation time 253363467 ps
CPU time 9.52 seconds
Started Jan 03 01:14:15 PM PST 24
Finished Jan 03 01:14:52 PM PST 24
Peak memory 218176 kb
Host smart-0c25f278-625d-4213-aef4-d1aea6aa7e1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664298136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.664298136
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2241168061
Short name T922
Test name
Test status
Simulation time 1201517061 ps
CPU time 10.73 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:15:07 PM PST 24
Peak memory 218200 kb
Host smart-a85ebd54-6bf5-4d61-ae73-65e188d8210a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241168061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2241168061
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.4110454435
Short name T432
Test name
Test status
Simulation time 55113168 ps
CPU time 2.28 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 213912 kb
Host smart-852aa876-3619-412c-8d0b-3db4e476fcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110454435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.4110454435
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.934050193
Short name T884
Test name
Test status
Simulation time 246576576 ps
CPU time 24.24 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:15:12 PM PST 24
Peak memory 251148 kb
Host smart-2c7d8683-1989-4fe0-b01a-da05673b9187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934050193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.934050193
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1449057652
Short name T503
Test name
Test status
Simulation time 459371417 ps
CPU time 8.21 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:56 PM PST 24
Peak memory 251188 kb
Host smart-2e4ef246-823b-4c31-98f0-eca419858b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449057652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1449057652
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.4086896896
Short name T508
Test name
Test status
Simulation time 1715275567 ps
CPU time 49.34 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:15:43 PM PST 24
Peak memory 251028 kb
Host smart-002c44cb-6854-426f-b4f6-5c7d1fd049a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086896896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.4086896896
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1993046692
Short name T526
Test name
Test status
Simulation time 56165646 ps
CPU time 0.76 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:51 PM PST 24
Peak memory 208108 kb
Host smart-3cf40754-c528-4238-ba27-3acb3ec01095
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993046692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1993046692
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3555705054
Short name T434
Test name
Test status
Simulation time 76613376 ps
CPU time 1.08 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:15:28 PM PST 24
Peak memory 209764 kb
Host smart-3decfa17-b73a-43cb-aeb2-d91acf1d1314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555705054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3555705054
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.192516952
Short name T863
Test name
Test status
Simulation time 200071569 ps
CPU time 10.15 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:47 PM PST 24
Peak memory 218244 kb
Host smart-cee03f5e-4b79-4d22-ab04-cc1c8d365f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192516952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.192516952
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4187195516
Short name T27
Test name
Test status
Simulation time 1733382337 ps
CPU time 4.98 seconds
Started Jan 03 01:14:44 PM PST 24
Finished Jan 03 01:15:42 PM PST 24
Peak memory 209680 kb
Host smart-bb2ab3ba-d688-4bef-a98b-80455ad94981
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187195516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.4187195516
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2763092430
Short name T357
Test name
Test status
Simulation time 112983560 ps
CPU time 2.61 seconds
Started Jan 03 01:14:24 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 218204 kb
Host smart-52098b61-e58a-437b-9709-a856b597882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763092430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2763092430
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2116077527
Short name T611
Test name
Test status
Simulation time 564845295 ps
CPU time 16.98 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:42 PM PST 24
Peak memory 218548 kb
Host smart-1c93f5f2-ae41-43be-9107-387804c0bc44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116077527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2116077527
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3754654543
Short name T917
Test name
Test status
Simulation time 575291340 ps
CPU time 12.17 seconds
Started Jan 03 01:14:48 PM PST 24
Finished Jan 03 01:15:57 PM PST 24
Peak memory 218172 kb
Host smart-6c86982c-684b-4d1d-ba1a-fcf763e14909
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754654543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3754654543
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1447540828
Short name T63
Test name
Test status
Simulation time 601854211 ps
CPU time 8.6 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:45 PM PST 24
Peak memory 218052 kb
Host smart-fd88a1a7-f5c8-49f4-8d68-5c30b8312f7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447540828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1447540828
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1316094054
Short name T767
Test name
Test status
Simulation time 5378005784 ps
CPU time 14.8 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:51 PM PST 24
Peak memory 218292 kb
Host smart-761a7169-411f-44f9-9532-10a8e1f4952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316094054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1316094054
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2887411711
Short name T950
Test name
Test status
Simulation time 51530014 ps
CPU time 3.29 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:33 PM PST 24
Peak memory 214728 kb
Host smart-e569a993-fed7-4e35-9f20-66133e9a3064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887411711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2887411711
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1772819273
Short name T95
Test name
Test status
Simulation time 505389017 ps
CPU time 20.34 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:10 PM PST 24
Peak memory 251084 kb
Host smart-4093c760-18e2-4cdb-a4bf-e19e8391b85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772819273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1772819273
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.122524157
Short name T844
Test name
Test status
Simulation time 384632408 ps
CPU time 6.77 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:43 PM PST 24
Peak memory 246948 kb
Host smart-12dcfea2-8222-453e-8ea5-257b36c3bc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122524157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.122524157
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1692443472
Short name T342
Test name
Test status
Simulation time 267299271797 ps
CPU time 573.46 seconds
Started Jan 03 01:14:50 PM PST 24
Finished Jan 03 01:25:23 PM PST 24
Peak memory 447848 kb
Host smart-d0ce629d-0c54-4231-b7e0-f780a5a5d602
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692443472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1692443472
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1673378899
Short name T399
Test name
Test status
Simulation time 14165177 ps
CPU time 0.95 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:14:57 PM PST 24
Peak memory 208476 kb
Host smart-2596cfcd-064f-4efb-8a23-0f02e079c578
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673378899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1673378899
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3050911337
Short name T850
Test name
Test status
Simulation time 21685455 ps
CPU time 0.94 seconds
Started Jan 03 01:13:57 PM PST 24
Finished Jan 03 01:14:21 PM PST 24
Peak memory 208408 kb
Host smart-7f9af7b6-9fa4-4a9f-acf4-06ceab36b56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050911337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3050911337
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1259166771
Short name T453
Test name
Test status
Simulation time 1259076666 ps
CPU time 13.05 seconds
Started Jan 03 01:14:14 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218168 kb
Host smart-96cb258b-fc83-47e1-8d3a-2d83303fa34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259166771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1259166771
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1157071878
Short name T733
Test name
Test status
Simulation time 1928617583 ps
CPU time 12.39 seconds
Started Jan 03 01:14:52 PM PST 24
Finished Jan 03 01:16:04 PM PST 24
Peak memory 209636 kb
Host smart-dc536181-e717-401a-93c5-340a5b57df1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157071878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.1157071878
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2544692980
Short name T456
Test name
Test status
Simulation time 88271541 ps
CPU time 3.18 seconds
Started Jan 03 01:14:57 PM PST 24
Finished Jan 03 01:16:03 PM PST 24
Peak memory 218136 kb
Host smart-2a73de5d-3d21-4d88-9ea2-370dacd6d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544692980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2544692980
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.4137939962
Short name T685
Test name
Test status
Simulation time 456943952 ps
CPU time 14.82 seconds
Started Jan 03 01:14:02 PM PST 24
Finished Jan 03 01:14:41 PM PST 24
Peak memory 218636 kb
Host smart-a85a05bb-320f-4b94-a434-408ebbede2d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137939962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.4137939962
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1856101566
Short name T313
Test name
Test status
Simulation time 1582001883 ps
CPU time 17.51 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:40 PM PST 24
Peak memory 218192 kb
Host smart-b3e656c8-eddd-4f61-9cc3-d89887e83e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856101566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1856101566
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1698568793
Short name T878
Test name
Test status
Simulation time 981451725 ps
CPU time 6.85 seconds
Started Jan 03 01:14:01 PM PST 24
Finished Jan 03 01:14:32 PM PST 24
Peak memory 218148 kb
Host smart-6398793d-8cac-4d59-8aeb-25f820184f5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698568793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1698568793
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3427681178
Short name T907
Test name
Test status
Simulation time 1224388301 ps
CPU time 7.11 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218228 kb
Host smart-3c42b4f7-3251-4ffb-a52d-7b7c796c0eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427681178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3427681178
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.498755901
Short name T816
Test name
Test status
Simulation time 148071752 ps
CPU time 2.85 seconds
Started Jan 03 01:14:48 PM PST 24
Finished Jan 03 01:15:49 PM PST 24
Peak memory 214040 kb
Host smart-ed192ed1-a452-4298-8e57-c15572e4cc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498755901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.498755901
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2956366400
Short name T975
Test name
Test status
Simulation time 438713697 ps
CPU time 25.1 seconds
Started Jan 03 01:14:49 PM PST 24
Finished Jan 03 01:16:13 PM PST 24
Peak memory 251196 kb
Host smart-3e8239e7-7060-4e8e-8976-85acdb91f743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956366400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2956366400
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.577186117
Short name T935
Test name
Test status
Simulation time 78391985 ps
CPU time 8.57 seconds
Started Jan 03 01:14:53 PM PST 24
Finished Jan 03 01:16:02 PM PST 24
Peak memory 251096 kb
Host smart-79aea33b-9ff9-4e9c-9b73-d0f1e9786884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577186117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.577186117
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.506824199
Short name T22
Test name
Test status
Simulation time 2116315565 ps
CPU time 54.99 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:15:17 PM PST 24
Peak memory 251216 kb
Host smart-fbd1a918-e8f2-410c-9979-624e3fc53412
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506824199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.506824199
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2805388147
Short name T70
Test name
Test status
Simulation time 59274519 ps
CPU time 0.92 seconds
Started Jan 03 01:14:48 PM PST 24
Finished Jan 03 01:15:47 PM PST 24
Peak memory 211364 kb
Host smart-abc4ac15-7c1e-4a15-bf10-0bddd9f68e2a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805388147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2805388147
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.941911803
Short name T529
Test name
Test status
Simulation time 14353922 ps
CPU time 0.93 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:12:36 PM PST 24
Peak memory 209660 kb
Host smart-f8f76413-bd6a-41eb-9751-0bfd579fd519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941911803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.941911803
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1664285496
Short name T671
Test name
Test status
Simulation time 15467852 ps
CPU time 0.86 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:34 PM PST 24
Peak memory 209564 kb
Host smart-0efdda78-8172-4cbf-aee7-53d700d90b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664285496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1664285496
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1679517714
Short name T659
Test name
Test status
Simulation time 284703014 ps
CPU time 10.5 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:42 PM PST 24
Peak memory 218076 kb
Host smart-8f90e77b-4485-459c-96c4-c052e30f4ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679517714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1679517714
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.548522780
Short name T948
Test name
Test status
Simulation time 420068885 ps
CPU time 9.35 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 209576 kb
Host smart-37c79667-dc59-4656-8cb6-443966539d1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548522780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_acc
ess.548522780
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.441838970
Short name T56
Test name
Test status
Simulation time 3994965588 ps
CPU time 28.24 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:13:01 PM PST 24
Peak memory 219232 kb
Host smart-290e9ce6-362e-4bd8-9859-de1e696df6f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441838970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.441838970
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3549505575
Short name T926
Test name
Test status
Simulation time 197230137 ps
CPU time 2.88 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:36 PM PST 24
Peak memory 209704 kb
Host smart-a605ac40-a2d6-4dbd-898f-4846b39e244f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549505575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.3549505575
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.463210268
Short name T883
Test name
Test status
Simulation time 274956918 ps
CPU time 2.01 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:36 PM PST 24
Peak memory 218160 kb
Host smart-da06a157-42c1-4c97-8165-53f902a2e06e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463210268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.463210268
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3079209881
Short name T352
Test name
Test status
Simulation time 12524047243 ps
CPU time 16.11 seconds
Started Jan 03 01:12:00 PM PST 24
Finished Jan 03 01:12:55 PM PST 24
Peak memory 213780 kb
Host smart-e5b8cd2b-8d13-448a-bef7-35fbc51139d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079209881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3079209881
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1017752004
Short name T382
Test name
Test status
Simulation time 204186183 ps
CPU time 3.9 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:12:36 PM PST 24
Peak memory 213268 kb
Host smart-8bca57c2-98c5-4d75-a3ae-c50b5c59811c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017752004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1017752004
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.226697829
Short name T2
Test name
Test status
Simulation time 925268355 ps
CPU time 25.46 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:59 PM PST 24
Peak memory 251064 kb
Host smart-e1ca9419-b3d3-486b-956b-ae6ae36b6e0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226697829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.226697829
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2413085423
Short name T755
Test name
Test status
Simulation time 1290631442 ps
CPU time 9.49 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 222644 kb
Host smart-87094b03-dae5-4fc2-ac12-ffe39284d3dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413085423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2413085423
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4124221622
Short name T412
Test name
Test status
Simulation time 38437995 ps
CPU time 2.54 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:36 PM PST 24
Peak memory 218228 kb
Host smart-3617c260-72b1-421e-aca3-178a8c5ca8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124221622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4124221622
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3880682330
Short name T824
Test name
Test status
Simulation time 158571758 ps
CPU time 9.8 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:12:43 PM PST 24
Peak memory 213408 kb
Host smart-7682fbb6-c8ea-4bb1-9842-dab8aae7b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880682330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3880682330
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2861146893
Short name T107
Test name
Test status
Simulation time 217292331 ps
CPU time 41.65 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:13:12 PM PST 24
Peak memory 273412 kb
Host smart-246f6fa5-7820-4fe8-9a4e-d79f4d4ecaeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861146893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2861146893
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.197367991
Short name T887
Test name
Test status
Simulation time 228332841 ps
CPU time 10.19 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 218212 kb
Host smart-32fe9149-97f1-4a7a-bd46-8548e90aa588
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197367991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.197367991
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3011895405
Short name T347
Test name
Test status
Simulation time 631083424 ps
CPU time 9.85 seconds
Started Jan 03 01:11:54 PM PST 24
Finished Jan 03 01:12:41 PM PST 24
Peak memory 218140 kb
Host smart-cc099576-85c0-4981-b6f9-ef10c8ef0ce9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011895405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3011895405
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.100011307
Short name T315
Test name
Test status
Simulation time 167436839 ps
CPU time 7.13 seconds
Started Jan 03 01:11:58 PM PST 24
Finished Jan 03 01:12:42 PM PST 24
Peak memory 218096 kb
Host smart-8d7ab422-a80e-41be-af6a-eed543da29da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100011307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.100011307
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2184506086
Short name T758
Test name
Test status
Simulation time 393905409 ps
CPU time 15.54 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:47 PM PST 24
Peak memory 218168 kb
Host smart-993b76fc-336c-46fb-9f90-ca70f8da1a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184506086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2184506086
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4175501403
Short name T839
Test name
Test status
Simulation time 41990781 ps
CPU time 2.89 seconds
Started Jan 03 01:11:55 PM PST 24
Finished Jan 03 01:12:35 PM PST 24
Peak memory 214360 kb
Host smart-81c52069-5401-4225-b576-14f90cc4f2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175501403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4175501403
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1578519325
Short name T488
Test name
Test status
Simulation time 220961012 ps
CPU time 21.04 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:52 PM PST 24
Peak memory 251036 kb
Host smart-431a36dc-f065-4696-99b3-d0bd27c898a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578519325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1578519325
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3911287213
Short name T427
Test name
Test status
Simulation time 491026923 ps
CPU time 7.26 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:12:37 PM PST 24
Peak memory 251072 kb
Host smart-fbb53424-9f8e-4cb4-be99-b256dbf45bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911287213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3911287213
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1172130914
Short name T638
Test name
Test status
Simulation time 1180210465 ps
CPU time 53.71 seconds
Started Jan 03 01:11:53 PM PST 24
Finished Jan 03 01:13:24 PM PST 24
Peak memory 251144 kb
Host smart-db398ed5-e170-4650-8881-66c2f396beb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172130914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1172130914
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1910285808
Short name T408
Test name
Test status
Simulation time 13130825 ps
CPU time 0.79 seconds
Started Jan 03 01:11:52 PM PST 24
Finished Jan 03 01:12:32 PM PST 24
Peak memory 208488 kb
Host smart-b28c836c-dce1-4fe2-a39e-a773de7a21f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910285808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1910285808
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3987823951
Short name T549
Test name
Test status
Simulation time 75737451 ps
CPU time 1.24 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 209708 kb
Host smart-103afb13-6516-45c3-858c-e1f4c6ab23f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987823951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3987823951
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1381921828
Short name T880
Test name
Test status
Simulation time 1285713972 ps
CPU time 14.07 seconds
Started Jan 03 01:14:13 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218232 kb
Host smart-f33140af-9d2a-4a8c-b71e-a906e3e1980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381921828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1381921828
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1174844457
Short name T872
Test name
Test status
Simulation time 314683031 ps
CPU time 3.43 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:53 PM PST 24
Peak memory 209692 kb
Host smart-32d48c43-3730-4032-872d-3ad54dce539f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174844457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.1174844457
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1816088919
Short name T788
Test name
Test status
Simulation time 171401567 ps
CPU time 2.75 seconds
Started Jan 03 01:14:11 PM PST 24
Finished Jan 03 01:14:41 PM PST 24
Peak memory 218168 kb
Host smart-6a6dd223-8c75-45b3-af85-a33a1c23807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816088919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1816088919
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3915192410
Short name T809
Test name
Test status
Simulation time 430761280 ps
CPU time 12.79 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 219180 kb
Host smart-828d596e-0284-4e79-bec2-f515de8e2d37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915192410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3915192410
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2473362992
Short name T384
Test name
Test status
Simulation time 1292811676 ps
CPU time 14.65 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:04 PM PST 24
Peak memory 218152 kb
Host smart-465aba5e-2747-43cb-b680-639798858be1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473362992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2473362992
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.4268312253
Short name T79
Test name
Test status
Simulation time 984197997 ps
CPU time 9.24 seconds
Started Jan 03 01:14:13 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 218148 kb
Host smart-e7debaf6-a1d9-4f54-8dbe-52ee6a254d24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268312253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
4268312253
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3013442402
Short name T864
Test name
Test status
Simulation time 1936110489 ps
CPU time 10.92 seconds
Started Jan 03 01:14:12 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 218172 kb
Host smart-a02b38fc-d3a2-46bd-a472-f0c9553db133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013442402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3013442402
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.42015521
Short name T973
Test name
Test status
Simulation time 412244296 ps
CPU time 3.15 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:26 PM PST 24
Peak memory 214080 kb
Host smart-689ac208-030c-4b6d-9474-ebb717785b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42015521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.42015521
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1661420480
Short name T403
Test name
Test status
Simulation time 265281656 ps
CPU time 24.64 seconds
Started Jan 03 01:14:01 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 246472 kb
Host smart-bac7b944-06f3-43f6-8775-bdc7fbc58e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661420480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1661420480
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2359953771
Short name T409
Test name
Test status
Simulation time 56880781 ps
CPU time 8.04 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:15:01 PM PST 24
Peak memory 251212 kb
Host smart-25d2e087-fe7b-4b02-94e4-79c70247bf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359953771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2359953771
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1460256057
Short name T899
Test name
Test status
Simulation time 2483247126 ps
CPU time 37.04 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:15:22 PM PST 24
Peak memory 226396 kb
Host smart-be972422-d95f-4951-81ee-e01b8424a490
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460256057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1460256057
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4136667489
Short name T956
Test name
Test status
Simulation time 40176302 ps
CPU time 0.88 seconds
Started Jan 03 01:14:00 PM PST 24
Finished Jan 03 01:14:24 PM PST 24
Peak memory 208180 kb
Host smart-d3e8e777-d278-4adb-827b-3204804a3205
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136667489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4136667489
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.4232904074
Short name T653
Test name
Test status
Simulation time 139131989 ps
CPU time 0.85 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 209692 kb
Host smart-31e6421d-02e7-444a-b034-25b589afc85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232904074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.4232904074
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2263566363
Short name T61
Test name
Test status
Simulation time 6360739629 ps
CPU time 24.17 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:15:16 PM PST 24
Peak memory 218228 kb
Host smart-0830a9f7-81dc-4306-aeab-2a68400c97e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263566363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2263566363
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2639331881
Short name T8
Test name
Test status
Simulation time 1601530197 ps
CPU time 22.39 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:15:09 PM PST 24
Peak memory 209676 kb
Host smart-e3e8ae17-e462-4b5e-9175-bdb7bd8a1aea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639331881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.2639331881
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2380339731
Short name T905
Test name
Test status
Simulation time 34418984 ps
CPU time 2.32 seconds
Started Jan 03 01:14:34 PM PST 24
Finished Jan 03 01:15:19 PM PST 24
Peak memory 218140 kb
Host smart-60d57242-f811-4597-9361-08709e0cfc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380339731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2380339731
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2302165738
Short name T32
Test name
Test status
Simulation time 946435084 ps
CPU time 12.68 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:58 PM PST 24
Peak memory 218160 kb
Host smart-a1365101-0a2f-4dcd-8d01-93c11233af9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302165738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2302165738
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4197619328
Short name T784
Test name
Test status
Simulation time 2100837978 ps
CPU time 7.42 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:15:02 PM PST 24
Peak memory 218156 kb
Host smart-48148329-b68d-4fd3-8ade-5d1a37f37037
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197619328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.4197619328
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2406963502
Short name T338
Test name
Test status
Simulation time 1002433526 ps
CPU time 17.5 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:08 PM PST 24
Peak memory 218160 kb
Host smart-ba80fc05-fa6d-46ae-865f-5d24c5e3b0c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406963502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2406963502
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1137954039
Short name T654
Test name
Test status
Simulation time 518648370 ps
CPU time 6.54 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:54 PM PST 24
Peak memory 218216 kb
Host smart-5fc953b5-08c6-417a-bdde-0d5b7157498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137954039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1137954039
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2538587602
Short name T871
Test name
Test status
Simulation time 29787739 ps
CPU time 2.26 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:48 PM PST 24
Peak memory 214196 kb
Host smart-35816174-6a5a-4f43-927c-07ccf7cb3a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538587602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2538587602
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3649989437
Short name T444
Test name
Test status
Simulation time 1210570067 ps
CPU time 31.86 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:15:19 PM PST 24
Peak memory 251160 kb
Host smart-195dcb74-a75f-488d-a74a-e9927c9ab8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649989437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3649989437
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2635692510
Short name T900
Test name
Test status
Simulation time 233644044 ps
CPU time 8.18 seconds
Started Jan 03 01:14:35 PM PST 24
Finished Jan 03 01:15:27 PM PST 24
Peak memory 251172 kb
Host smart-9b347727-8ed0-4a90-a669-c153113030b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635692510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2635692510
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1521615475
Short name T362
Test name
Test status
Simulation time 14321111632 ps
CPU time 79.82 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:16:14 PM PST 24
Peak memory 227460 kb
Host smart-ec2d301a-7631-4d3e-a5cd-4cd8cd582d37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521615475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1521615475
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2526345301
Short name T423
Test name
Test status
Simulation time 14850876 ps
CPU time 0.89 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:25 PM PST 24
Peak memory 208388 kb
Host smart-668ccc6e-8cb8-487a-aaba-fa2218a1e743
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526345301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2526345301
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1562633751
Short name T569
Test name
Test status
Simulation time 31524822 ps
CPU time 1.1 seconds
Started Jan 03 01:13:57 PM PST 24
Finished Jan 03 01:14:21 PM PST 24
Peak memory 208500 kb
Host smart-f6034370-8a8f-453b-8ac0-2c8f5303a74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562633751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1562633751
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.871976650
Short name T476
Test name
Test status
Simulation time 2148372856 ps
CPU time 11.23 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:34 PM PST 24
Peak memory 218352 kb
Host smart-f40aea72-ff89-4a5b-918a-b3eb3021a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871976650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.871976650
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3777987747
Short name T830
Test name
Test status
Simulation time 5511035935 ps
CPU time 7.07 seconds
Started Jan 03 01:14:34 PM PST 24
Finished Jan 03 01:15:24 PM PST 24
Peak memory 209688 kb
Host smart-4d7dbd6e-7d65-4461-b004-2db16cac16a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777987747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.3777987747
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.4097149671
Short name T814
Test name
Test status
Simulation time 233887458 ps
CPU time 3.36 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:14:56 PM PST 24
Peak memory 218228 kb
Host smart-aebf89e1-195d-4c37-85ef-861838238387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097149671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.4097149671
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2895867062
Short name T746
Test name
Test status
Simulation time 433870948 ps
CPU time 12.54 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:49 PM PST 24
Peak memory 218504 kb
Host smart-905c4be6-ff64-4258-84c4-525462ddd614
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895867062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2895867062
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4281736748
Short name T517
Test name
Test status
Simulation time 196191708 ps
CPU time 9.63 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:46 PM PST 24
Peak memory 218156 kb
Host smart-7a166862-e4cd-4bd8-8d03-099c6d041b92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281736748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4281736748
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1633620927
Short name T471
Test name
Test status
Simulation time 1528456081 ps
CPU time 13.95 seconds
Started Jan 03 01:14:41 PM PST 24
Finished Jan 03 01:15:45 PM PST 24
Peak memory 217640 kb
Host smart-a22bb328-ad29-4db9-81c8-4e5c4cb3dabd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633620927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1633620927
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1337613502
Short name T591
Test name
Test status
Simulation time 503694188 ps
CPU time 9.56 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:46 PM PST 24
Peak memory 218240 kb
Host smart-88331734-0354-41b3-a4a6-68a6dd00fb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337613502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1337613502
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.517285525
Short name T640
Test name
Test status
Simulation time 620469962 ps
CPU time 2.43 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:29 PM PST 24
Peak memory 213856 kb
Host smart-2752dbb6-3ad0-4167-9f7f-3a9e08e728d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517285525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.517285525
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1298171121
Short name T386
Test name
Test status
Simulation time 933709383 ps
CPU time 20.1 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:16:01 PM PST 24
Peak memory 250716 kb
Host smart-a7725f25-4f53-41de-87a6-aa0a55f06473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298171121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1298171121
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.211781671
Short name T764
Test name
Test status
Simulation time 310773064 ps
CPU time 9.39 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:15:06 PM PST 24
Peak memory 251216 kb
Host smart-e9cab864-ab01-45f4-91d0-650dad6a237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211781671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.211781671
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1108658867
Short name T80
Test name
Test status
Simulation time 18746040299 ps
CPU time 56.08 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:16:23 PM PST 24
Peak memory 248520 kb
Host smart-87ac64b6-022e-4362-964a-ad09b745e9ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108658867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1108658867
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.3696249556
Short name T132
Test name
Test status
Simulation time 84428651086 ps
CPU time 540.1 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:24:27 PM PST 24
Peak memory 496136 kb
Host smart-85820c69-a7f1-48a4-aa08-64020ed81a42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3696249556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.3696249556
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1369857882
Short name T876
Test name
Test status
Simulation time 31720329 ps
CPU time 0.95 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:31 PM PST 24
Peak memory 208396 kb
Host smart-af95eb1f-f657-4b1b-a854-52d00c3b8f63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369857882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1369857882
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.122021466
Short name T576
Test name
Test status
Simulation time 54150525 ps
CPU time 0.98 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:48 PM PST 24
Peak memory 208452 kb
Host smart-46d6168a-2e3b-403e-b90e-c01b5999de86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122021466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.122021466
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1594606061
Short name T627
Test name
Test status
Simulation time 929225991 ps
CPU time 12.62 seconds
Started Jan 03 01:14:01 PM PST 24
Finished Jan 03 01:14:37 PM PST 24
Peak memory 218216 kb
Host smart-aa0a1f6a-b9a6-4102-99e4-a1117f21b488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594606061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1594606061
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.768175190
Short name T699
Test name
Test status
Simulation time 285755523 ps
CPU time 7.74 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:30 PM PST 24
Peak memory 209600 kb
Host smart-c53a8be6-165f-4ca7-8e6f-947fec856fb0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768175190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_ac
cess.768175190
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1405222230
Short name T13
Test name
Test status
Simulation time 42566047 ps
CPU time 2.42 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:14:47 PM PST 24
Peak memory 218168 kb
Host smart-d540e1ba-5f60-4920-9a86-ede390b64675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405222230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1405222230
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2118151156
Short name T599
Test name
Test status
Simulation time 1241861608 ps
CPU time 18.89 seconds
Started Jan 03 01:14:00 PM PST 24
Finished Jan 03 01:14:42 PM PST 24
Peak memory 219292 kb
Host smart-852a5aec-2093-4159-b007-b44175f9c219
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118151156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2118151156
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3144880649
Short name T489
Test name
Test status
Simulation time 367105234 ps
CPU time 8.76 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:15:01 PM PST 24
Peak memory 218164 kb
Host smart-22252ea4-a231-4f46-b52c-d5f3310f6458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144880649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3144880649
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1325554811
Short name T840
Test name
Test status
Simulation time 237035235 ps
CPU time 6.66 seconds
Started Jan 03 01:14:02 PM PST 24
Finished Jan 03 01:14:33 PM PST 24
Peak memory 218104 kb
Host smart-54482cfc-d9d4-41ca-aaf3-46351b1dd3fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325554811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1325554811
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4241898841
Short name T469
Test name
Test status
Simulation time 1577421105 ps
CPU time 12.54 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:35 PM PST 24
Peak memory 218152 kb
Host smart-3cdd1cf2-6d39-424f-b726-2043405f68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241898841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4241898841
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2897332139
Short name T725
Test name
Test status
Simulation time 43657058 ps
CPU time 1.33 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:27 PM PST 24
Peak memory 213232 kb
Host smart-9969e0fb-0111-4b3f-b2b9-bcc4681df9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897332139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2897332139
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3898432307
Short name T608
Test name
Test status
Simulation time 1155536556 ps
CPU time 23.24 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:46 PM PST 24
Peak memory 251116 kb
Host smart-d49a6822-14f0-4ee3-b6ac-70cc0717e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898432307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3898432307
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1503816707
Short name T606
Test name
Test status
Simulation time 71303475 ps
CPU time 2.8 seconds
Started Jan 03 01:14:00 PM PST 24
Finished Jan 03 01:14:27 PM PST 24
Peak memory 221844 kb
Host smart-0968a6fe-7d91-4feb-9d5e-11a5f37bf3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503816707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1503816707
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3866504361
Short name T837
Test name
Test status
Simulation time 1399781652 ps
CPU time 20.36 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:15:05 PM PST 24
Peak memory 218168 kb
Host smart-42c668b2-1bfa-4f14-b174-81d0925a389e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866504361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3866504361
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3072312156
Short name T448
Test name
Test status
Simulation time 13442700 ps
CPU time 0.75 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:22 PM PST 24
Peak memory 208120 kb
Host smart-50291be3-436d-4505-af99-7cd420562306
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072312156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3072312156
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3361144606
Short name T11
Test name
Test status
Simulation time 93604554 ps
CPU time 1.69 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:30 PM PST 24
Peak memory 209684 kb
Host smart-a8c0c63c-3889-4799-a6d1-6b47458d48a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361144606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3361144606
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2893002307
Short name T823
Test name
Test status
Simulation time 194108406 ps
CPU time 8.11 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:57 PM PST 24
Peak memory 218228 kb
Host smart-21401a2a-1f05-4b08-acf1-2c75ca56671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893002307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2893002307
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4289648317
Short name T18
Test name
Test status
Simulation time 263420783 ps
CPU time 2.12 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:14:53 PM PST 24
Peak memory 209620 kb
Host smart-1de91fb7-decf-478f-b522-e318ce0fb094
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289648317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.4289648317
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2863223843
Short name T804
Test name
Test status
Simulation time 441376061 ps
CPU time 4.01 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 218208 kb
Host smart-300b9a44-ab56-4957-bf62-69da0889b2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863223843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2863223843
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.129179070
Short name T889
Test name
Test status
Simulation time 1089768602 ps
CPU time 8.48 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 218200 kb
Host smart-335ec350-7b07-49eb-b001-f841af5e0590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129179070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.129179070
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1834560447
Short name T766
Test name
Test status
Simulation time 701689074 ps
CPU time 12.09 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:14:56 PM PST 24
Peak memory 218080 kb
Host smart-ee926c1e-4565-4911-9acd-7b8100457b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834560447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1834560447
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2882140376
Short name T307
Test name
Test status
Simulation time 528654571 ps
CPU time 6.62 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218204 kb
Host smart-37bcf4bc-c0a3-45de-a8c7-2343229837ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882140376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2882140376
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4178375080
Short name T199
Test name
Test status
Simulation time 707641878 ps
CPU time 5.54 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:15:00 PM PST 24
Peak memory 218116 kb
Host smart-619ef0fd-910c-4d30-9167-ebe1578edf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178375080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4178375080
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3069361930
Short name T38
Test name
Test status
Simulation time 155271668 ps
CPU time 1.65 seconds
Started Jan 03 01:14:11 PM PST 24
Finished Jan 03 01:14:40 PM PST 24
Peak memory 213476 kb
Host smart-eeeb6ab6-2da0-4be4-962e-afc359da25de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069361930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3069361930
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1176141401
Short name T930
Test name
Test status
Simulation time 361631200 ps
CPU time 28.02 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:15:14 PM PST 24
Peak memory 251168 kb
Host smart-ec7148d5-6970-4201-8779-a0458c26ec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176141401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1176141401
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2153169697
Short name T881
Test name
Test status
Simulation time 344837728 ps
CPU time 11.05 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:01 PM PST 24
Peak memory 251172 kb
Host smart-a99e04db-ad08-46cc-be1e-2b30e94bb61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153169697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2153169697
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1975524735
Short name T918
Test name
Test status
Simulation time 7079074738 ps
CPU time 201.73 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:18:14 PM PST 24
Peak memory 267652 kb
Host smart-1dc9937a-c648-471a-86fd-3a4fe1477be6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975524735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1975524735
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4081605741
Short name T42
Test name
Test status
Simulation time 13182354 ps
CPU time 0.94 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:48 PM PST 24
Peak memory 208160 kb
Host smart-3547674f-94b1-4466-b4af-c9bd1dfa33a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081605741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4081605741
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.795624044
Short name T800
Test name
Test status
Simulation time 37260581 ps
CPU time 0.86 seconds
Started Jan 03 01:14:33 PM PST 24
Finished Jan 03 01:15:15 PM PST 24
Peak memory 209552 kb
Host smart-505f24ec-495a-44e8-aad1-7846cbaf366f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795624044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.795624044
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1885371531
Short name T631
Test name
Test status
Simulation time 286840541 ps
CPU time 11.63 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:40 PM PST 24
Peak memory 218256 kb
Host smart-afe28c12-8bdf-4c07-a547-a49cd73c52d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885371531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1885371531
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.736106515
Short name T69
Test name
Test status
Simulation time 641895000 ps
CPU time 7.58 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:41 PM PST 24
Peak memory 209760 kb
Host smart-2b58711d-128b-46c5-bdc1-7acd1b5afce2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736106515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_ac
cess.736106515
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4276123204
Short name T833
Test name
Test status
Simulation time 83642301 ps
CPU time 4.29 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218208 kb
Host smart-d06cbd3b-d375-4deb-bb9d-c9ae200f19ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276123204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4276123204
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4063282277
Short name T125
Test name
Test status
Simulation time 4171952088 ps
CPU time 17.75 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:15:02 PM PST 24
Peak memory 219356 kb
Host smart-2e8cff56-cf57-426a-b31c-e0f42e183c2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063282277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4063282277
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2848608025
Short name T393
Test name
Test status
Simulation time 605208713 ps
CPU time 11.56 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:15:08 PM PST 24
Peak memory 218148 kb
Host smart-daafc4fd-beb4-49ff-9572-1653587610f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848608025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2848608025
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.316586070
Short name T753
Test name
Test status
Simulation time 294094518 ps
CPU time 7.16 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:15:03 PM PST 24
Peak memory 218216 kb
Host smart-2d00ad30-53b1-4dab-8560-79e74249a6b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316586070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.316586070
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1498049101
Short name T726
Test name
Test status
Simulation time 2118171762 ps
CPU time 11.83 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:46 PM PST 24
Peak memory 218236 kb
Host smart-e36eaa20-fb88-47d1-9b72-9ff6692bc4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498049101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1498049101
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2366482050
Short name T856
Test name
Test status
Simulation time 91001299 ps
CPU time 3.24 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:32 PM PST 24
Peak memory 214112 kb
Host smart-e382c2fa-f988-41ee-b334-01253e1d68b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366482050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2366482050
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2153627295
Short name T689
Test name
Test status
Simulation time 304300759 ps
CPU time 22.98 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:15:50 PM PST 24
Peak memory 251156 kb
Host smart-4c532a91-989a-41fc-b765-a8db1cf30964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153627295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2153627295
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1554616712
Short name T494
Test name
Test status
Simulation time 61087593 ps
CPU time 3.79 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:14:56 PM PST 24
Peak memory 222284 kb
Host smart-05b825fa-c1cf-455a-ac50-05d5c90228e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554616712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1554616712
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2106020728
Short name T52
Test name
Test status
Simulation time 13627549 ps
CPU time 1.06 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:22 PM PST 24
Peak memory 211544 kb
Host smart-7f68049e-06d2-44fa-adfd-3dfed7e69bac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106020728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2106020728
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.898363341
Short name T852
Test name
Test status
Simulation time 13884841 ps
CPU time 0.82 seconds
Started Jan 03 01:14:01 PM PST 24
Finished Jan 03 01:14:26 PM PST 24
Peak memory 209504 kb
Host smart-2381340e-bfde-4adf-bad1-4fe29e57d801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898363341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.898363341
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1917184518
Short name T370
Test name
Test status
Simulation time 1573314921 ps
CPU time 15.31 seconds
Started Jan 03 01:14:41 PM PST 24
Finished Jan 03 01:15:46 PM PST 24
Peak memory 218208 kb
Host smart-9793f09d-c6b3-47f2-aa33-a4c9bd845562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917184518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1917184518
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1141849175
Short name T977
Test name
Test status
Simulation time 66158644 ps
CPU time 2.18 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:25 PM PST 24
Peak memory 209628 kb
Host smart-7e12d41c-7e8a-411b-b532-00d006fc5cee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141849175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.1141849175
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2967913683
Short name T378
Test name
Test status
Simulation time 55889357 ps
CPU time 2.35 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:23 PM PST 24
Peak memory 218156 kb
Host smart-8e507d09-d0ac-4231-960f-fd05da37e020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967913683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2967913683
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1206636107
Short name T794
Test name
Test status
Simulation time 689577112 ps
CPU time 10.54 seconds
Started Jan 03 01:14:50 PM PST 24
Finished Jan 03 01:16:00 PM PST 24
Peak memory 218196 kb
Host smart-e4ad5029-260e-4a03-bfb6-b2b93a642bc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206636107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1206636107
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.4077636149
Short name T647
Test name
Test status
Simulation time 779400011 ps
CPU time 8.55 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:54 PM PST 24
Peak memory 218132 kb
Host smart-53ee4a51-aa44-4df8-8e1c-bf62608f9d23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077636149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.4077636149
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.350439247
Short name T620
Test name
Test status
Simulation time 767598492 ps
CPU time 8.68 seconds
Started Jan 03 01:13:58 PM PST 24
Finished Jan 03 01:14:31 PM PST 24
Peak memory 218124 kb
Host smart-b31a0be5-ce22-4698-9509-f184ac7b193c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350439247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.350439247
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1191461232
Short name T949
Test name
Test status
Simulation time 1575141300 ps
CPU time 8.8 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:34 PM PST 24
Peak memory 218208 kb
Host smart-1c763fd0-a8bf-41ea-93d8-6ab634298d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191461232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1191461232
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2585281621
Short name T772
Test name
Test status
Simulation time 122902103 ps
CPU time 4.27 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:41 PM PST 24
Peak memory 214252 kb
Host smart-726476ce-3b07-44a5-8bd7-945b03cd5446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585281621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2585281621
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3181014674
Short name T12
Test name
Test status
Simulation time 227283564 ps
CPU time 18.75 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:15:46 PM PST 24
Peak memory 251184 kb
Host smart-ead2b4db-acd2-4bf1-b62e-3b99e892f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181014674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3181014674
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1118079287
Short name T946
Test name
Test status
Simulation time 94436116 ps
CPU time 6.18 seconds
Started Jan 03 01:14:45 PM PST 24
Finished Jan 03 01:15:45 PM PST 24
Peak memory 246276 kb
Host smart-e77bb47b-dcbb-45c2-8b43-b548213bf780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118079287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1118079287
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3121825883
Short name T495
Test name
Test status
Simulation time 6071779884 ps
CPU time 55.3 seconds
Started Jan 03 01:14:01 PM PST 24
Finished Jan 03 01:15:21 PM PST 24
Peak memory 247820 kb
Host smart-34ab709d-1ebe-44db-9632-1df36f3db511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121825883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3121825883
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2989234300
Short name T673
Test name
Test status
Simulation time 35491931 ps
CPU time 0.9 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:26 PM PST 24
Peak memory 208180 kb
Host smart-b53e4c6b-59a2-4a80-8d7d-fad4bd617c34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989234300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2989234300
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3210902484
Short name T712
Test name
Test status
Simulation time 15670326 ps
CPU time 1.05 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 209672 kb
Host smart-f9c3ce7d-f4fc-4e23-89dc-a182e86a9267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210902484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3210902484
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3818710538
Short name T523
Test name
Test status
Simulation time 285112485 ps
CPU time 9.04 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218172 kb
Host smart-34118bb2-f1f3-4204-b9b8-f5025e2142db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818710538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3818710538
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.252574265
Short name T748
Test name
Test status
Simulation time 2627698638 ps
CPU time 11.11 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:14:56 PM PST 24
Peak memory 209708 kb
Host smart-3b6cbeed-803f-4ce8-8caf-0ce595530313
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252574265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_ac
cess.252574265
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1728088183
Short name T831
Test name
Test status
Simulation time 66126733 ps
CPU time 3.28 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:14:54 PM PST 24
Peak memory 218140 kb
Host smart-75b62290-29a3-4b11-8837-b0283a74a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728088183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1728088183
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2071572168
Short name T776
Test name
Test status
Simulation time 340229686 ps
CPU time 10.53 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 218612 kb
Host smart-ddb5bef3-b6b1-4755-a3ba-a9f080ed34b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071572168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2071572168
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2581846698
Short name T682
Test name
Test status
Simulation time 4515311880 ps
CPU time 12.37 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:15:03 PM PST 24
Peak memory 218212 kb
Host smart-312ffdbb-4ce7-4e61-b2f5-b19256170b00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581846698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2581846698
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2508251567
Short name T351
Test name
Test status
Simulation time 800817626 ps
CPU time 7.28 seconds
Started Jan 03 01:14:24 PM PST 24
Finished Jan 03 01:15:04 PM PST 24
Peak memory 218160 kb
Host smart-fe12e581-7049-435b-b1a8-fb0c12c16103
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508251567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2508251567
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1008460282
Short name T368
Test name
Test status
Simulation time 849421539 ps
CPU time 8.27 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 218164 kb
Host smart-0747ab85-bc13-47ae-af47-67f9060ed08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008460282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1008460282
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.928108181
Short name T919
Test name
Test status
Simulation time 47889275 ps
CPU time 1.59 seconds
Started Jan 03 01:13:59 PM PST 24
Finished Jan 03 01:14:24 PM PST 24
Peak memory 213604 kb
Host smart-7593cd15-ad3b-4990-8af4-791c70f3f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928108181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.928108181
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3556297354
Short name T851
Test name
Test status
Simulation time 285898370 ps
CPU time 37.29 seconds
Started Jan 03 01:13:57 PM PST 24
Finished Jan 03 01:14:58 PM PST 24
Peak memory 251120 kb
Host smart-1d36962d-1e10-4a30-a70b-818bbd5b9682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556297354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3556297354
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1523722709
Short name T694
Test name
Test status
Simulation time 95409774 ps
CPU time 7.87 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 251168 kb
Host smart-d01b5075-bcdf-459e-9286-e1f61cbbae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523722709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1523722709
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.46990721
Short name T740
Test name
Test status
Simulation time 7587506555 ps
CPU time 190.72 seconds
Started Jan 03 01:14:24 PM PST 24
Finished Jan 03 01:18:07 PM PST 24
Peak memory 278444 kb
Host smart-c6d8af91-e4d0-4ebf-8db6-55e5a23ca3bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46990721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.lc_ctrl_stress_all.46990721
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3303219064
Short name T418
Test name
Test status
Simulation time 17052903 ps
CPU time 1 seconds
Started Jan 03 01:14:01 PM PST 24
Finished Jan 03 01:14:25 PM PST 24
Peak memory 211540 kb
Host smart-10413d55-c1ee-4f1d-97a8-c572d831a3e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303219064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3303219064
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3871126920
Short name T609
Test name
Test status
Simulation time 125621089 ps
CPU time 1.07 seconds
Started Jan 03 01:14:44 PM PST 24
Finished Jan 03 01:15:38 PM PST 24
Peak memory 209724 kb
Host smart-a83a6f8f-f25c-4539-bf3d-9d4a0e2d9dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871126920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3871126920
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1520727511
Short name T777
Test name
Test status
Simulation time 267559813 ps
CPU time 11.79 seconds
Started Jan 03 01:14:34 PM PST 24
Finished Jan 03 01:15:28 PM PST 24
Peak memory 218216 kb
Host smart-c3c5a2cb-61d7-4720-96b1-4740733af901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520727511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1520727511
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.984055577
Short name T791
Test name
Test status
Simulation time 1180316225 ps
CPU time 6.67 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:35 PM PST 24
Peak memory 209596 kb
Host smart-9c667362-40c3-457c-ba17-1e7a85b5f068
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984055577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_ac
cess.984055577
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3107613281
Short name T716
Test name
Test status
Simulation time 453502830 ps
CPU time 3.37 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:14:56 PM PST 24
Peak memory 218196 kb
Host smart-34df223b-dfee-4988-bd38-5c3bc35fec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107613281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3107613281
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3174851534
Short name T910
Test name
Test status
Simulation time 1911531903 ps
CPU time 7.58 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:15:02 PM PST 24
Peak memory 218284 kb
Host smart-c40e5b76-dbcc-41ce-ba6f-4b23570e2d55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174851534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3174851534
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.725127117
Short name T901
Test name
Test status
Simulation time 1136730470 ps
CPU time 13.33 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:15:40 PM PST 24
Peak memory 218148 kb
Host smart-885d4fce-96fb-42a1-bf2a-489571bf57bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725127117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.725127117
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3352405694
Short name T873
Test name
Test status
Simulation time 1646687964 ps
CPU time 14.07 seconds
Started Jan 03 01:14:24 PM PST 24
Finished Jan 03 01:15:11 PM PST 24
Peak memory 218096 kb
Host smart-bb68a2c6-643a-48c2-963b-2fd4ba38dfbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352405694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3352405694
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3897784983
Short name T835
Test name
Test status
Simulation time 1683713760 ps
CPU time 13.86 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:35 PM PST 24
Peak memory 218148 kb
Host smart-41e07109-9a1f-4760-86bf-cb7d97ee8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897784983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3897784983
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.546369828
Short name T938
Test name
Test status
Simulation time 125693617 ps
CPU time 1.7 seconds
Started Jan 03 01:14:33 PM PST 24
Finished Jan 03 01:15:16 PM PST 24
Peak memory 213480 kb
Host smart-b79af57f-5fc5-4719-909f-b069d7f75420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546369828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.546369828
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2215884971
Short name T367
Test name
Test status
Simulation time 439942939 ps
CPU time 25.5 seconds
Started Jan 03 01:14:34 PM PST 24
Finished Jan 03 01:15:40 PM PST 24
Peak memory 251096 kb
Host smart-4975b2d6-5ca3-4617-ba98-f91b778f030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215884971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2215884971
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2355229155
Short name T330
Test name
Test status
Simulation time 245025589 ps
CPU time 7.16 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:52 PM PST 24
Peak memory 250936 kb
Host smart-5d12ceac-36b6-472c-b2f0-b2ba67571711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355229155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2355229155
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.86045533
Short name T505
Test name
Test status
Simulation time 40225798705 ps
CPU time 181 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:17:57 PM PST 24
Peak memory 251272 kb
Host smart-081e0dcc-1ea6-4f70-b661-03e4d61348e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86045533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.lc_ctrl_stress_all.86045533
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3228053624
Short name T715
Test name
Test status
Simulation time 20931825 ps
CPU time 0.75 seconds
Started Jan 03 01:14:33 PM PST 24
Finished Jan 03 01:15:13 PM PST 24
Peak memory 208204 kb
Host smart-19f17a58-2a13-47c2-88ba-08da16f23375
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228053624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3228053624
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.4179980288
Short name T530
Test name
Test status
Simulation time 15137288 ps
CPU time 0.89 seconds
Started Jan 03 01:14:56 PM PST 24
Finished Jan 03 01:15:59 PM PST 24
Peak memory 209608 kb
Host smart-40697e37-41d7-4b69-9940-eb8515161a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179980288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.4179980288
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.888139122
Short name T797
Test name
Test status
Simulation time 375781951 ps
CPU time 11.66 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:45 PM PST 24
Peak memory 218184 kb
Host smart-b24f0190-0506-45e7-9570-aacd0b78f425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888139122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.888139122
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.580179461
Short name T778
Test name
Test status
Simulation time 1477270525 ps
CPU time 10.24 seconds
Started Jan 03 01:14:47 PM PST 24
Finished Jan 03 01:15:52 PM PST 24
Peak memory 209708 kb
Host smart-5c73361f-cdcc-447e-8285-f4a697529e71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580179461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_ac
cess.580179461
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3187324163
Short name T428
Test name
Test status
Simulation time 79800817 ps
CPU time 2.57 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:28 PM PST 24
Peak memory 218116 kb
Host smart-0d9e96e7-1de6-4ec4-a753-72381e1fa780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187324163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3187324163
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.671917961
Short name T590
Test name
Test status
Simulation time 323343162 ps
CPU time 10.37 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:40 PM PST 24
Peak memory 219232 kb
Host smart-0e8fcbe3-fde3-43cb-85f5-9185d9a95528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671917961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.671917961
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2771746541
Short name T328
Test name
Test status
Simulation time 280226881 ps
CPU time 10.27 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:44 PM PST 24
Peak memory 218136 kb
Host smart-59114916-2daa-411c-819d-173377952cdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771746541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2771746541
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1451670132
Short name T306
Test name
Test status
Simulation time 596747852 ps
CPU time 6.34 seconds
Started Jan 03 01:14:51 PM PST 24
Finished Jan 03 01:15:57 PM PST 24
Peak memory 218016 kb
Host smart-df109f4f-c750-43c1-9193-7238d00a0547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451670132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1451670132
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.719946941
Short name T527
Test name
Test status
Simulation time 820032580 ps
CPU time 15.45 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:41 PM PST 24
Peak memory 218128 kb
Host smart-adbf50e3-d8c7-4a12-9725-f66ba2c45a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719946941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.719946941
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.4106941008
Short name T939
Test name
Test status
Simulation time 13117186 ps
CPU time 1.15 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:15:42 PM PST 24
Peak memory 211852 kb
Host smart-6339225b-28e9-4c48-bda9-69f590adc6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106941008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.4106941008
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2983259148
Short name T534
Test name
Test status
Simulation time 368356807 ps
CPU time 31.45 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:16:08 PM PST 24
Peak memory 251144 kb
Host smart-ae137838-9d33-4f3c-9464-b89cbad695d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983259148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2983259148
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2752403388
Short name T578
Test name
Test status
Simulation time 208256240 ps
CPU time 2.68 seconds
Started Jan 03 01:14:44 PM PST 24
Finished Jan 03 01:15:40 PM PST 24
Peak memory 222264 kb
Host smart-195977af-1b6d-4cd3-8065-60a3053311a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752403388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2752403388
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1299434035
Short name T752
Test name
Test status
Simulation time 4018726311 ps
CPU time 155.28 seconds
Started Jan 03 01:14:55 PM PST 24
Finished Jan 03 01:18:31 PM PST 24
Peak memory 271408 kb
Host smart-ce76511d-ec52-46ee-808a-04de0ec28f83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299434035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1299434035
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3092237165
Short name T44
Test name
Test status
Simulation time 10892189 ps
CPU time 0.89 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:23 PM PST 24
Peak memory 208140 kb
Host smart-9e7a9ae7-bc9e-41ec-9fc5-1ceced8519aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092237165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3092237165
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.626334587
Short name T605
Test name
Test status
Simulation time 61184288 ps
CPU time 1 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:48 PM PST 24
Peak memory 209548 kb
Host smart-2516ffbe-1be8-43e8-b770-6a9e28dcf080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626334587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.626334587
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.835677175
Short name T980
Test name
Test status
Simulation time 24856930 ps
CPU time 0.8 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:12:36 PM PST 24
Peak memory 209444 kb
Host smart-178bece0-7a86-41f1-8dd5-1d62c4a92c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835677175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.835677175
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1347128797
Short name T664
Test name
Test status
Simulation time 1393061919 ps
CPU time 11.53 seconds
Started Jan 03 01:11:59 PM PST 24
Finished Jan 03 01:12:50 PM PST 24
Peak memory 218096 kb
Host smart-871c4ee6-183c-4465-9c9a-856cd1c3d6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347128797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1347128797
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.526799272
Short name T854
Test name
Test status
Simulation time 324427634 ps
CPU time 4.49 seconds
Started Jan 03 01:12:00 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 209628 kb
Host smart-98c36303-f20f-4c73-9533-14a5c8f9c908
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526799272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_acc
ess.526799272
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.799809057
Short name T787
Test name
Test status
Simulation time 3031591303 ps
CPU time 26.4 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:13:13 PM PST 24
Peak memory 219276 kb
Host smart-3071f461-5d77-4b6c-8cf8-7f0339e95a9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799809057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.799809057
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.4258506108
Short name T17
Test name
Test status
Simulation time 117153752 ps
CPU time 2.18 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:12:50 PM PST 24
Peak memory 208484 kb
Host smart-50f2682b-3130-4a95-8edd-faae024c5595
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258506108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.4258506108
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.278638611
Short name T892
Test name
Test status
Simulation time 850096699 ps
CPU time 6.88 seconds
Started Jan 03 01:12:00 PM PST 24
Finished Jan 03 01:12:45 PM PST 24
Peak memory 218028 kb
Host smart-0cb8af6a-4e43-4731-91bd-06e0b59bf9d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278638611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.278638611
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1934177283
Short name T718
Test name
Test status
Simulation time 2397013413 ps
CPU time 17.34 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:13:04 PM PST 24
Peak memory 213156 kb
Host smart-72a8b590-e9e4-4b14-87b7-8f8598e6bb8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934177283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1934177283
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1232461599
Short name T89
Test name
Test status
Simulation time 879591904 ps
CPU time 7.56 seconds
Started Jan 03 01:11:57 PM PST 24
Finished Jan 03 01:12:43 PM PST 24
Peak memory 213488 kb
Host smart-d75a1efa-5c72-47aa-9655-144e8bdc61bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232461599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1232461599
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2819476297
Short name T565
Test name
Test status
Simulation time 4854515463 ps
CPU time 75.86 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:14:02 PM PST 24
Peak memory 267576 kb
Host smart-c607d12a-179b-4b6d-ad79-2f4465be2c55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819476297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2819476297
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.189965187
Short name T589
Test name
Test status
Simulation time 2866681887 ps
CPU time 12.74 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:48 PM PST 24
Peak memory 247512 kb
Host smart-4462e740-e9d0-49a1-9acd-10c77c52d7ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189965187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.189965187
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4122449942
Short name T779
Test name
Test status
Simulation time 47765885 ps
CPU time 1.45 seconds
Started Jan 03 01:11:59 PM PST 24
Finished Jan 03 01:12:38 PM PST 24
Peak memory 218212 kb
Host smart-035a7e20-730a-4c17-86e2-d7c2d0369890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122449942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4122449942
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.322820341
Short name T729
Test name
Test status
Simulation time 214827769 ps
CPU time 5.66 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:12:50 PM PST 24
Peak memory 214080 kb
Host smart-dd696fbf-6624-4d1b-9a56-b1722bb62075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322820341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.322820341
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2758943209
Short name T122
Test name
Test status
Simulation time 1079148969 ps
CPU time 24.25 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:13:14 PM PST 24
Peak memory 284476 kb
Host smart-1be7204b-fdf2-4c08-a7c7-4c311160d058
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758943209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2758943209
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.346792500
Short name T932
Test name
Test status
Simulation time 312991089 ps
CPU time 12.18 seconds
Started Jan 03 01:12:01 PM PST 24
Finished Jan 03 01:12:52 PM PST 24
Peak memory 218212 kb
Host smart-27443532-6888-429d-9974-253bd74e15ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346792500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.346792500
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1092713043
Short name T585
Test name
Test status
Simulation time 550141114 ps
CPU time 19.52 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:13:06 PM PST 24
Peak memory 217944 kb
Host smart-dff44cec-754a-4769-8aa7-fb5890eff58e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092713043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1092713043
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1170367646
Short name T449
Test name
Test status
Simulation time 480287342 ps
CPU time 10.82 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:12:54 PM PST 24
Peak memory 218160 kb
Host smart-750d6c80-cd5a-400e-abce-b83240f24782
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170367646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
170367646
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.949775489
Short name T865
Test name
Test status
Simulation time 472063968 ps
CPU time 10.37 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:12:54 PM PST 24
Peak memory 218180 kb
Host smart-421d3752-f283-4f77-a55a-fb3b947cc0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949775489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.949775489
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1705503867
Short name T811
Test name
Test status
Simulation time 42057312 ps
CPU time 1.91 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:35 PM PST 24
Peak memory 213748 kb
Host smart-45ceeddb-9889-4d0d-89b3-071df7381027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705503867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1705503867
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3355311794
Short name T799
Test name
Test status
Simulation time 283208192 ps
CPU time 27.87 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:13:01 PM PST 24
Peak memory 251132 kb
Host smart-33e50bb1-2f58-4974-8ed3-d03ef5d3f611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355311794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3355311794
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.135227797
Short name T472
Test name
Test status
Simulation time 157439951 ps
CPU time 8.87 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:12:42 PM PST 24
Peak memory 250736 kb
Host smart-7ebf2d97-f715-4c8d-a4f9-e6969e3291a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135227797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.135227797
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4055003474
Short name T536
Test name
Test status
Simulation time 6000265655 ps
CPU time 202.35 seconds
Started Jan 03 01:11:56 PM PST 24
Finished Jan 03 01:15:57 PM PST 24
Peak memory 275948 kb
Host smart-bebf110f-46d4-4a91-9aa9-1b5cb7caa5df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055003474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4055003474
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2468098241
Short name T45
Test name
Test status
Simulation time 14997528 ps
CPU time 0.79 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:12:50 PM PST 24
Peak memory 208532 kb
Host smart-bbce5450-9a7f-4880-8f28-fdbdb8248abf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468098241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2468098241
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.702011948
Short name T940
Test name
Test status
Simulation time 59935330 ps
CPU time 0.93 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:49 PM PST 24
Peak memory 208312 kb
Host smart-6e8c2ebe-8f41-4af9-a009-911326113992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702011948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.702011948
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2588001378
Short name T789
Test name
Test status
Simulation time 225548200 ps
CPU time 7.7 seconds
Started Jan 03 01:14:45 PM PST 24
Finished Jan 03 01:15:46 PM PST 24
Peak memory 218256 kb
Host smart-d61005ea-1a87-4c1e-a944-924ad123b6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588001378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2588001378
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2405469963
Short name T506
Test name
Test status
Simulation time 1806774419 ps
CPU time 10.7 seconds
Started Jan 03 01:15:02 PM PST 24
Finished Jan 03 01:16:17 PM PST 24
Peak memory 209596 kb
Host smart-708a4be8-071c-4813-b6e9-12e77c14c946
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405469963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.2405469963
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2610016504
Short name T749
Test name
Test status
Simulation time 184458405 ps
CPU time 2.52 seconds
Started Jan 03 01:14:57 PM PST 24
Finished Jan 03 01:16:01 PM PST 24
Peak memory 218116 kb
Host smart-40b429f9-403e-443d-ba02-0f8954fe85c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610016504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2610016504
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1713573800
Short name T982
Test name
Test status
Simulation time 305991053 ps
CPU time 11.81 seconds
Started Jan 03 01:14:53 PM PST 24
Finished Jan 03 01:16:06 PM PST 24
Peak memory 219208 kb
Host smart-77f2dc31-4fbd-4707-aa55-c6d223672af0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713573800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1713573800
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2097236264
Short name T498
Test name
Test status
Simulation time 453441044 ps
CPU time 10.09 seconds
Started Jan 03 01:14:55 PM PST 24
Finished Jan 03 01:16:06 PM PST 24
Peak memory 218072 kb
Host smart-d4259d26-9de9-42b0-b16d-487f3f330062
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097236264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2097236264
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.106040235
Short name T520
Test name
Test status
Simulation time 734625659 ps
CPU time 7.56 seconds
Started Jan 03 01:15:07 PM PST 24
Finished Jan 03 01:16:20 PM PST 24
Peak memory 218140 kb
Host smart-74b16c13-ee7d-4e34-8fc3-c8e643d228a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106040235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.106040235
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1615906267
Short name T869
Test name
Test status
Simulation time 1752948254 ps
CPU time 7.59 seconds
Started Jan 03 01:14:53 PM PST 24
Finished Jan 03 01:16:01 PM PST 24
Peak memory 218180 kb
Host smart-e34d33d6-7d11-4f50-86fc-18b4e0831de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615906267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1615906267
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4234085359
Short name T499
Test name
Test status
Simulation time 47994103 ps
CPU time 3.33 seconds
Started Jan 03 01:14:49 PM PST 24
Finished Jan 03 01:15:51 PM PST 24
Peak memory 214436 kb
Host smart-34c01666-5ac0-4bb7-bec5-56b9264ae9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234085359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4234085359
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2569695650
Short name T684
Test name
Test status
Simulation time 1121486047 ps
CPU time 29.8 seconds
Started Jan 03 01:14:53 PM PST 24
Finished Jan 03 01:16:24 PM PST 24
Peak memory 251012 kb
Host smart-655659df-18ff-4a24-b9d2-59f12ee0cc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569695650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2569695650
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3900415863
Short name T738
Test name
Test status
Simulation time 236069118 ps
CPU time 6.28 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:15:46 PM PST 24
Peak memory 246688 kb
Host smart-12273a8f-e0c3-4817-bbf5-9b4d09800c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900415863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3900415863
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.693253367
Short name T588
Test name
Test status
Simulation time 14102811320 ps
CPU time 257.52 seconds
Started Jan 03 01:14:23 PM PST 24
Finished Jan 03 01:19:12 PM PST 24
Peak memory 316764 kb
Host smart-0e191d8d-9ef4-499a-9eb4-3be6eb2a0cfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693253367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.693253367
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2725125373
Short name T40
Test name
Test status
Simulation time 13462373 ps
CPU time 0.93 seconds
Started Jan 03 01:14:49 PM PST 24
Finished Jan 03 01:15:48 PM PST 24
Peak memory 211560 kb
Host smart-718cffeb-92b2-47d4-b39c-cff0fb66dc7a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725125373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2725125373
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.244456889
Short name T67
Test name
Test status
Simulation time 204778005 ps
CPU time 1.07 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:15:29 PM PST 24
Peak memory 209684 kb
Host smart-13520ce3-bdfa-47df-a3d5-b0fe7d252135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244456889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.244456889
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.4221705648
Short name T128
Test name
Test status
Simulation time 810979793 ps
CPU time 15.05 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:15:07 PM PST 24
Peak memory 218164 kb
Host smart-a4c88688-d076-4282-8e77-d88adc2c2719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221705648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4221705648
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3904333969
Short name T720
Test name
Test status
Simulation time 1343086267 ps
CPU time 7.16 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 209564 kb
Host smart-2f26d43c-ca4e-4a6a-95b3-7d28bed86367
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904333969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.3904333969
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3287744381
Short name T802
Test name
Test status
Simulation time 1301041425 ps
CPU time 3.26 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218264 kb
Host smart-b5dc30ae-9b3c-4911-9f3d-58cc8d0981be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287744381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3287744381
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1432444922
Short name T867
Test name
Test status
Simulation time 212021704 ps
CPU time 9.44 seconds
Started Jan 03 01:14:32 PM PST 24
Finished Jan 03 01:15:20 PM PST 24
Peak memory 218216 kb
Host smart-2cf7ece8-852f-4477-b286-408918503b46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432444922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1432444922
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2378261949
Short name T538
Test name
Test status
Simulation time 395920028 ps
CPU time 14.13 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:37 PM PST 24
Peak memory 218148 kb
Host smart-cda21ad2-12b1-467a-a50f-870a0822117e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378261949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2378261949
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1768345441
Short name T30
Test name
Test status
Simulation time 1775296042 ps
CPU time 9.73 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:57 PM PST 24
Peak memory 218040 kb
Host smart-c2e0c601-c819-4ee7-9b99-78b3c32cb91a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768345441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1768345441
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3050572284
Short name T129
Test name
Test status
Simulation time 112434661 ps
CPU time 2.53 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:53 PM PST 24
Peak memory 214044 kb
Host smart-1136b972-086c-4897-bebd-180571c59247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050572284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3050572284
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.359949531
Short name T369
Test name
Test status
Simulation time 591265969 ps
CPU time 20.52 seconds
Started Jan 03 01:14:24 PM PST 24
Finished Jan 03 01:15:17 PM PST 24
Peak memory 251152 kb
Host smart-e5658594-fa2d-4ea8-b068-f03cea349a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359949531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.359949531
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3556654248
Short name T666
Test name
Test status
Simulation time 305228186 ps
CPU time 6.48 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:52 PM PST 24
Peak memory 246068 kb
Host smart-a645b844-34a8-4b94-9357-a9fa33bbdf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556654248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3556654248
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3082726129
Short name T775
Test name
Test status
Simulation time 12072377018 ps
CPU time 117.42 seconds
Started Jan 03 01:14:34 PM PST 24
Finished Jan 03 01:17:13 PM PST 24
Peak memory 277972 kb
Host smart-cf8967b3-f034-4052-bab3-aff04c5544e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082726129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3082726129
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.600271279
Short name T46
Test name
Test status
Simulation time 34032080 ps
CPU time 0.85 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:51 PM PST 24
Peak memory 208372 kb
Host smart-49676672-406c-4ac3-892e-3c856bccdb5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600271279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.600271279
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.54761246
Short name T312
Test name
Test status
Simulation time 30853565 ps
CPU time 1.03 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:23 PM PST 24
Peak memory 209644 kb
Host smart-aa29cdeb-2a77-4e22-908b-43cc02e24e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54761246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.54761246
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.294889655
Short name T637
Test name
Test status
Simulation time 240523640 ps
CPU time 7.92 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:44 PM PST 24
Peak memory 218172 kb
Host smart-372d9923-abad-4c07-b0f7-34b1d90222e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294889655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.294889655
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3276523162
Short name T410
Test name
Test status
Simulation time 208609048 ps
CPU time 1.86 seconds
Started Jan 03 01:14:33 PM PST 24
Finished Jan 03 01:15:14 PM PST 24
Peak memory 209580 kb
Host smart-5bc32f5a-674d-4f5a-a8d0-5d9f1ca1d6fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276523162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.3276523162
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2405127641
Short name T1
Test name
Test status
Simulation time 104449224 ps
CPU time 2.13 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:49 PM PST 24
Peak memory 218084 kb
Host smart-9a6c974a-c994-43d1-955f-15eeb8bada8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405127641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2405127641
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.313367551
Short name T656
Test name
Test status
Simulation time 1204936888 ps
CPU time 9.87 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:31 PM PST 24
Peak memory 218636 kb
Host smart-32a754fd-fe0c-403f-99e1-6327e209d579
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313367551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.313367551
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2681643244
Short name T557
Test name
Test status
Simulation time 2202285208 ps
CPU time 11.77 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:45 PM PST 24
Peak memory 218212 kb
Host smart-3fe5eaf4-d4d0-48e5-b7ec-950aa30da26d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681643244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2681643244
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.605779550
Short name T955
Test name
Test status
Simulation time 605718683 ps
CPU time 7.62 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:42 PM PST 24
Peak memory 218148 kb
Host smart-47882802-1c91-4ac4-8e89-4de48b3ffc00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605779550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.605779550
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3474598500
Short name T853
Test name
Test status
Simulation time 1098866214 ps
CPU time 7.56 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:43 PM PST 24
Peak memory 218176 kb
Host smart-562c2c44-55e0-4ba9-b44d-f8efe7ba99b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474598500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3474598500
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2907241075
Short name T348
Test name
Test status
Simulation time 249337467 ps
CPU time 2.44 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 213932 kb
Host smart-0fa8a882-1df8-4dd8-b370-bcf304f3fde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907241075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2907241075
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1998597647
Short name T422
Test name
Test status
Simulation time 232027603 ps
CPU time 21.25 seconds
Started Jan 03 01:14:40 PM PST 24
Finished Jan 03 01:15:51 PM PST 24
Peak memory 251188 kb
Host smart-a79b0164-a884-4217-800e-c4a670f1c664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998597647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1998597647
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3174560825
Short name T556
Test name
Test status
Simulation time 87460066 ps
CPU time 6.78 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 250548 kb
Host smart-e8127149-c67a-4119-80cc-ed65f880bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174560825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3174560825
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.185728904
Short name T359
Test name
Test status
Simulation time 1417960850 ps
CPU time 29.37 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:16:06 PM PST 24
Peak memory 248604 kb
Host smart-de68f030-f9f0-4ffa-add5-8685880c2124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185728904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.185728904
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2417221171
Short name T500
Test name
Test status
Simulation time 12418276 ps
CPU time 1.07 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:34 PM PST 24
Peak memory 211456 kb
Host smart-7c1e8977-029c-4bbd-9fcd-16606d81c6c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417221171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2417221171
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.630647767
Short name T821
Test name
Test status
Simulation time 44261056 ps
CPU time 0.84 seconds
Started Jan 03 01:14:53 PM PST 24
Finished Jan 03 01:15:55 PM PST 24
Peak memory 209524 kb
Host smart-be0d849e-6e49-4a25-99ae-53fdcaaf2a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630647767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.630647767
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3607639473
Short name T390
Test name
Test status
Simulation time 398231098 ps
CPU time 12.23 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:15:52 PM PST 24
Peak memory 218204 kb
Host smart-3c68d562-d4db-4a18-9702-791c920e7e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607639473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3607639473
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3198040320
Short name T619
Test name
Test status
Simulation time 1028421437 ps
CPU time 5.95 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:15:46 PM PST 24
Peak memory 209704 kb
Host smart-31b14ee8-07c0-418c-8193-3a742e6a8311
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198040320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.3198040320
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2846968580
Short name T436
Test name
Test status
Simulation time 54101371 ps
CPU time 2.85 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:15:43 PM PST 24
Peak memory 218140 kb
Host smart-bb8e9811-2345-44e3-8627-3aa3e622e420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846968580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2846968580
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.216439738
Short name T822
Test name
Test status
Simulation time 275594961 ps
CPU time 10.36 seconds
Started Jan 03 01:14:48 PM PST 24
Finished Jan 03 01:15:56 PM PST 24
Peak memory 219152 kb
Host smart-c41b01e1-d891-4216-8bda-6a53493e9459
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216439738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.216439738
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3783808231
Short name T320
Test name
Test status
Simulation time 328658486 ps
CPU time 10.68 seconds
Started Jan 03 01:14:52 PM PST 24
Finished Jan 03 01:16:03 PM PST 24
Peak memory 218032 kb
Host smart-e14219c8-1505-4219-90a5-87e3b163a97e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783808231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3783808231
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.616748205
Short name T663
Test name
Test status
Simulation time 682032313 ps
CPU time 10.9 seconds
Started Jan 03 01:14:55 PM PST 24
Finished Jan 03 01:16:07 PM PST 24
Peak memory 218184 kb
Host smart-6f11f011-af37-44ba-8943-ec1cca91959d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616748205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.616748205
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3655925203
Short name T479
Test name
Test status
Simulation time 1212458323 ps
CPU time 10.35 seconds
Started Jan 03 01:14:41 PM PST 24
Finished Jan 03 01:15:41 PM PST 24
Peak memory 218156 kb
Host smart-7cacae4f-76bf-49cf-9173-613f1467558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655925203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3655925203
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2440138202
Short name T430
Test name
Test status
Simulation time 344753187 ps
CPU time 3.24 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:24 PM PST 24
Peak memory 214552 kb
Host smart-76955543-8e1e-43f0-9b86-e5b1b1e68137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440138202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2440138202
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3132093222
Short name T771
Test name
Test status
Simulation time 612944271 ps
CPU time 22.72 seconds
Started Jan 03 01:14:44 PM PST 24
Finished Jan 03 01:15:59 PM PST 24
Peak memory 251156 kb
Host smart-ea28497e-d1dc-4b8d-984b-6ccc68bb0bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132093222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3132093222
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2666283911
Short name T577
Test name
Test status
Simulation time 541582703 ps
CPU time 3.06 seconds
Started Jan 03 01:14:35 PM PST 24
Finished Jan 03 01:15:22 PM PST 24
Peak memory 218144 kb
Host smart-80cce1c7-3527-4b4d-bfce-c958e7b230ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666283911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2666283911
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.573106806
Short name T341
Test name
Test status
Simulation time 72083935021 ps
CPU time 153.39 seconds
Started Jan 03 01:14:47 PM PST 24
Finished Jan 03 01:18:15 PM PST 24
Peak memory 277836 kb
Host smart-4d689c91-8de9-4a81-ba0b-96ca1dac5c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573106806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.573106806
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2833764443
Short name T567
Test name
Test status
Simulation time 64762515 ps
CPU time 0.84 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:36 PM PST 24
Peak memory 208376 kb
Host smart-dcf23e98-5aa4-4114-a867-b34308fe35ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833764443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2833764443
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2327958117
Short name T639
Test name
Test status
Simulation time 20013616 ps
CPU time 0.92 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:49 PM PST 24
Peak memory 208288 kb
Host smart-dc44ede7-eab0-4024-83c5-bdc48f2ac9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327958117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2327958117
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.635501394
Short name T713
Test name
Test status
Simulation time 1349399314 ps
CPU time 16.85 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:07 PM PST 24
Peak memory 218220 kb
Host smart-5a7cff4a-4402-4ba4-8123-463237b81377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635501394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.635501394
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2728397982
Short name T857
Test name
Test status
Simulation time 3033500133 ps
CPU time 8.22 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:15:00 PM PST 24
Peak memory 209728 kb
Host smart-b72e3d34-709a-487c-8daf-9eef252c1aca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728397982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.2728397982
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1621714329
Short name T759
Test name
Test status
Simulation time 80414353 ps
CPU time 2.49 seconds
Started Jan 03 01:14:49 PM PST 24
Finished Jan 03 01:15:49 PM PST 24
Peak memory 218176 kb
Host smart-65535adc-cfbd-40e1-aa9d-5ed27b05b5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621714329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1621714329
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1324921028
Short name T542
Test name
Test status
Simulation time 734705212 ps
CPU time 13.15 seconds
Started Jan 03 01:14:21 PM PST 24
Finished Jan 03 01:15:04 PM PST 24
Peak memory 219224 kb
Host smart-db2dfd5e-8877-40f8-bdeb-2060e2c68a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324921028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1324921028
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.946447252
Short name T961
Test name
Test status
Simulation time 318192797 ps
CPU time 15.62 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:15:01 PM PST 24
Peak memory 218064 kb
Host smart-94d677fe-8567-440e-bf8f-53343fb9fc1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946447252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.946447252
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3345195577
Short name T625
Test name
Test status
Simulation time 1799267404 ps
CPU time 9.09 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218076 kb
Host smart-d431f0c4-6a2e-4c9c-b211-bcfe520b7329
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345195577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3345195577
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1657968733
Short name T501
Test name
Test status
Simulation time 4741501182 ps
CPU time 8.69 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 218212 kb
Host smart-1ecd301b-fbb9-4535-90fb-be85875563e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657968733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1657968733
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.578517356
Short name T345
Test name
Test status
Simulation time 158068679 ps
CPU time 2.56 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:39 PM PST 24
Peak memory 213892 kb
Host smart-8887ccdf-0605-4b82-8b56-3365b41e12c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578517356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.578517356
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1139557421
Short name T969
Test name
Test status
Simulation time 1002320845 ps
CPU time 29.64 seconds
Started Jan 03 01:14:53 PM PST 24
Finished Jan 03 01:16:24 PM PST 24
Peak memory 251060 kb
Host smart-0e019690-4395-47d7-8767-9f85f8338c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139557421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1139557421
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2417344544
Short name T96
Test name
Test status
Simulation time 1474483481 ps
CPU time 7.49 seconds
Started Jan 03 01:14:49 PM PST 24
Finished Jan 03 01:15:54 PM PST 24
Peak memory 246612 kb
Host smart-ec315d4a-3292-49df-b929-c3306c4c1aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417344544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2417344544
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1791626128
Short name T329
Test name
Test status
Simulation time 21431899465 ps
CPU time 193.26 seconds
Started Jan 03 01:14:32 PM PST 24
Finished Jan 03 01:18:25 PM PST 24
Peak memory 251304 kb
Host smart-b9598293-82a6-419f-b612-b7797da62e7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791626128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1791626128
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2315643551
Short name T670
Test name
Test status
Simulation time 18517697 ps
CPU time 0.86 seconds
Started Jan 03 01:14:55 PM PST 24
Finished Jan 03 01:15:57 PM PST 24
Peak memory 208332 kb
Host smart-af927137-2f00-4c02-9eee-45215b1bd333
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315643551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2315643551
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4137561056
Short name T109
Test name
Test status
Simulation time 75351320 ps
CPU time 1.09 seconds
Started Jan 03 01:14:32 PM PST 24
Finished Jan 03 01:15:12 PM PST 24
Peak memory 209704 kb
Host smart-a784395c-8da6-4cc6-a082-fda4189e88a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137561056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4137561056
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1906871605
Short name T47
Test name
Test status
Simulation time 410495245 ps
CPU time 12.46 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:36 PM PST 24
Peak memory 218116 kb
Host smart-9f60021f-ed34-417a-add5-f7cc086b8268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906871605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1906871605
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3287743406
Short name T943
Test name
Test status
Simulation time 2382975931 ps
CPU time 12.71 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:15:03 PM PST 24
Peak memory 209508 kb
Host smart-df77daee-cc12-4920-9a56-4c8fc7162fd6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287743406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.3287743406
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1501107111
Short name T893
Test name
Test status
Simulation time 222334402 ps
CPU time 2.43 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:23 PM PST 24
Peak memory 218208 kb
Host smart-54428542-d14e-488c-bf4d-a8731262a706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501107111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1501107111
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2914477335
Short name T480
Test name
Test status
Simulation time 771224185 ps
CPU time 13.06 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:36 PM PST 24
Peak memory 218776 kb
Host smart-1a095b6c-0497-4e25-9a98-63abceb5b4b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914477335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2914477335
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1385807007
Short name T518
Test name
Test status
Simulation time 1874133000 ps
CPU time 12.38 seconds
Started Jan 03 01:14:41 PM PST 24
Finished Jan 03 01:15:44 PM PST 24
Peak memory 217516 kb
Host smart-3a2190e2-1b95-4c2f-9300-5eb289ea02c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385807007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1385807007
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2309989483
Short name T335
Test name
Test status
Simulation time 394935013 ps
CPU time 13.12 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:15:54 PM PST 24
Peak memory 217792 kb
Host smart-24656782-120f-4ee8-a068-c734bc9bbb3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309989483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2309989483
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3918008325
Short name T133
Test name
Test status
Simulation time 214056778 ps
CPU time 8.43 seconds
Started Jan 03 01:14:35 PM PST 24
Finished Jan 03 01:15:27 PM PST 24
Peak memory 218200 kb
Host smart-1d40c924-1adf-496a-b5eb-7c2f72d71550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918008325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3918008325
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1117503337
Short name T31
Test name
Test status
Simulation time 130123888 ps
CPU time 1.3 seconds
Started Jan 03 01:14:22 PM PST 24
Finished Jan 03 01:14:56 PM PST 24
Peak memory 213292 kb
Host smart-489e7356-5076-411b-886f-ddb1cccbad3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117503337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1117503337
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2515476199
Short name T805
Test name
Test status
Simulation time 290942104 ps
CPU time 22.79 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:15:11 PM PST 24
Peak memory 251032 kb
Host smart-7b2322d8-f36b-415a-b112-e78d824340ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515476199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2515476199
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3052974529
Short name T94
Test name
Test status
Simulation time 296130947 ps
CPU time 7.21 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:30 PM PST 24
Peak memory 250668 kb
Host smart-510aa39f-6763-4d55-b5e2-8f7ec42564ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052974529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3052974529
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3245463630
Short name T916
Test name
Test status
Simulation time 8447306453 ps
CPU time 139.33 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:17:56 PM PST 24
Peak memory 251232 kb
Host smart-b6dd41c3-d371-40c8-ad33-5b17b4554620
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245463630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3245463630
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3876708460
Short name T708
Test name
Test status
Simulation time 13830017 ps
CPU time 0.78 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:48 PM PST 24
Peak memory 208512 kb
Host smart-541e38c2-2171-458d-8fbc-88ba99701c0f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876708460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3876708460
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1000016308
Short name T72
Test name
Test status
Simulation time 38526602 ps
CPU time 0.89 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:24 PM PST 24
Peak memory 208392 kb
Host smart-8ac9c906-ed63-4d99-b1d7-867e3205bc6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000016308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1000016308
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3383525301
Short name T550
Test name
Test status
Simulation time 1250017057 ps
CPU time 13.35 seconds
Started Jan 03 01:14:41 PM PST 24
Finished Jan 03 01:15:44 PM PST 24
Peak memory 218220 kb
Host smart-7cd09839-c570-4ce4-9c99-6357852daf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383525301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3383525301
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1787250928
Short name T25
Test name
Test status
Simulation time 1600464232 ps
CPU time 2.7 seconds
Started Jan 03 01:14:44 PM PST 24
Finished Jan 03 01:15:40 PM PST 24
Peak memory 209604 kb
Host smart-e3351617-d149-4625-9305-f59f4bcf034b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787250928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_a
ccess.1787250928
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3006789253
Short name T826
Test name
Test status
Simulation time 332325400 ps
CPU time 1.95 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:39 PM PST 24
Peak memory 218200 kb
Host smart-8ba8137b-860d-47fa-bfe1-6505cab59cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006789253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3006789253
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3596832136
Short name T897
Test name
Test status
Simulation time 1020704392 ps
CPU time 10.15 seconds
Started Jan 03 01:14:45 PM PST 24
Finished Jan 03 01:15:48 PM PST 24
Peak memory 218156 kb
Host smart-c29a6373-b146-4286-a2ca-365e5782e9e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596832136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3596832136
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1551426463
Short name T460
Test name
Test status
Simulation time 497749499 ps
CPU time 16.21 seconds
Started Jan 03 01:14:46 PM PST 24
Finished Jan 03 01:15:57 PM PST 24
Peak memory 218144 kb
Host smart-8e494aea-3a93-454e-913f-da966c9f7ad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551426463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1551426463
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3547475008
Short name T731
Test name
Test status
Simulation time 259674190 ps
CPU time 6.46 seconds
Started Jan 03 01:14:39 PM PST 24
Finished Jan 03 01:15:34 PM PST 24
Peak memory 218108 kb
Host smart-827c43f7-34f7-439b-afdd-a00c772b5a73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547475008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3547475008
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2959385000
Short name T68
Test name
Test status
Simulation time 4552237334 ps
CPU time 8.17 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:45 PM PST 24
Peak memory 218308 kb
Host smart-1b3c1f55-8302-4038-8ddc-814d632905aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959385000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2959385000
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.665322193
Short name T66
Test name
Test status
Simulation time 51055705 ps
CPU time 1.21 seconds
Started Jan 03 01:14:38 PM PST 24
Finished Jan 03 01:15:27 PM PST 24
Peak memory 213356 kb
Host smart-bbfcc61d-c22b-41be-acd6-f1b8b368fa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665322193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.665322193
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1194686626
Short name T960
Test name
Test status
Simulation time 194702917 ps
CPU time 28.67 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:49 PM PST 24
Peak memory 251188 kb
Host smart-cac68b27-8e78-443c-b7c1-b268c1d8c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194686626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1194686626
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2835820520
Short name T898
Test name
Test status
Simulation time 343782057 ps
CPU time 7.85 seconds
Started Jan 03 01:14:34 PM PST 24
Finished Jan 03 01:15:24 PM PST 24
Peak memory 251200 kb
Host smart-0da7ffcd-9570-47ae-bee9-8dd6c2e496fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835820520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2835820520
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2821669490
Short name T87
Test name
Test status
Simulation time 6445092240 ps
CPU time 225.88 seconds
Started Jan 03 01:14:41 PM PST 24
Finished Jan 03 01:19:17 PM PST 24
Peak memory 273292 kb
Host smart-54975287-b781-45f9-8c36-376d0e8889cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821669490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2821669490
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2222000291
Short name T545
Test name
Test status
Simulation time 30140312 ps
CPU time 0.74 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:22 PM PST 24
Peak memory 207796 kb
Host smart-f8f4791f-9af2-40ab-be62-bfeb63181a44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222000291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2222000291
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1618476501
Short name T582
Test name
Test status
Simulation time 22270322 ps
CPU time 0.84 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 208256 kb
Host smart-89409d56-83f2-44cc-be5b-5d242a292128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618476501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1618476501
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1107793007
Short name T349
Test name
Test status
Simulation time 876003186 ps
CPU time 10.54 seconds
Started Jan 03 01:14:49 PM PST 24
Finished Jan 03 01:15:57 PM PST 24
Peak memory 218260 kb
Host smart-98a4c03a-c845-48ef-9f50-fc8dcf4cc358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107793007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1107793007
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.438261893
Short name T9
Test name
Test status
Simulation time 424578287 ps
CPU time 9.41 seconds
Started Jan 03 01:15:06 PM PST 24
Finished Jan 03 01:16:19 PM PST 24
Peak memory 209684 kb
Host smart-fc8e466f-2c58-4b15-8e78-c0f291cf80c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438261893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_ac
cess.438261893
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.544495983
Short name T697
Test name
Test status
Simulation time 317985471 ps
CPU time 2.61 seconds
Started Jan 03 01:14:44 PM PST 24
Finished Jan 03 01:15:39 PM PST 24
Peak memory 218256 kb
Host smart-e11042ff-8eea-4d98-a706-21147b8d236e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544495983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.544495983
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.4062916901
Short name T487
Test name
Test status
Simulation time 607992114 ps
CPU time 13.38 seconds
Started Jan 03 01:14:50 PM PST 24
Finished Jan 03 01:16:02 PM PST 24
Peak memory 219204 kb
Host smart-33cee24e-23a5-4058-a72b-debd56ec93c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062916901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.4062916901
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.259635913
Short name T879
Test name
Test status
Simulation time 1150024306 ps
CPU time 7.92 seconds
Started Jan 03 01:14:51 PM PST 24
Finished Jan 03 01:15:58 PM PST 24
Peak memory 218116 kb
Host smart-79624ab4-53d1-4907-b795-ef1bffb3797e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259635913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.259635913
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2871486288
Short name T435
Test name
Test status
Simulation time 220153952 ps
CPU time 5.88 seconds
Started Jan 03 01:14:58 PM PST 24
Finished Jan 03 01:16:06 PM PST 24
Peak memory 218072 kb
Host smart-8db3d547-8514-40ae-9463-3a20cb23e874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871486288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2871486288
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.29670644
Short name T827
Test name
Test status
Simulation time 6381733444 ps
CPU time 9.8 seconds
Started Jan 03 01:14:58 PM PST 24
Finished Jan 03 01:16:09 PM PST 24
Peak memory 218272 kb
Host smart-fa30af87-f5bb-461c-91a5-58a84c37ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29670644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.29670644
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3984816507
Short name T562
Test name
Test status
Simulation time 18527373 ps
CPU time 1.33 seconds
Started Jan 03 01:14:48 PM PST 24
Finished Jan 03 01:15:45 PM PST 24
Peak memory 213380 kb
Host smart-581d3ff5-4747-40aa-ac97-0dc557d356f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984816507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3984816507
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1438233140
Short name T709
Test name
Test status
Simulation time 285403721 ps
CPU time 36.16 seconds
Started Jan 03 01:14:50 PM PST 24
Finished Jan 03 01:16:24 PM PST 24
Peak memory 251100 kb
Host smart-0fb448e0-5916-4051-85f3-ce4bfe5c0dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438233140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1438233140
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.457114347
Short name T736
Test name
Test status
Simulation time 106027698 ps
CPU time 6.81 seconds
Started Jan 03 01:15:00 PM PST 24
Finished Jan 03 01:16:11 PM PST 24
Peak memory 250704 kb
Host smart-28bf7cf8-10f7-4a78-a388-7272906b4763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457114347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.457114347
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3453725778
Short name T691
Test name
Test status
Simulation time 4999583605 ps
CPU time 56.39 seconds
Started Jan 03 01:15:00 PM PST 24
Finished Jan 03 01:16:59 PM PST 24
Peak memory 226448 kb
Host smart-6f66a6b1-3b71-4fc1-8712-389a6b6627ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453725778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3453725778
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.272222841
Short name T742
Test name
Test status
Simulation time 41510940 ps
CPU time 0.74 seconds
Started Jan 03 01:14:56 PM PST 24
Finished Jan 03 01:15:58 PM PST 24
Peak memory 207972 kb
Host smart-718d560b-fde6-4c49-bea1-65652d0c2c45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272222841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.272222841
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2256556393
Short name T310
Test name
Test status
Simulation time 22557933 ps
CPU time 0.9 seconds
Started Jan 03 01:14:35 PM PST 24
Finished Jan 03 01:15:21 PM PST 24
Peak memory 209716 kb
Host smart-9f450ee9-fbd0-4b3f-a2e5-afa133c0f7fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256556393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2256556393
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2694609459
Short name T314
Test name
Test status
Simulation time 230906855 ps
CPU time 10.61 seconds
Started Jan 03 01:14:16 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 218180 kb
Host smart-d1e0711d-3986-4211-a823-d5a914c13480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694609459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2694609459
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2690315106
Short name T616
Test name
Test status
Simulation time 1673987338 ps
CPU time 6.51 seconds
Started Jan 03 01:14:15 PM PST 24
Finished Jan 03 01:14:49 PM PST 24
Peak memory 209584 kb
Host smart-48a2a368-2614-4261-a2fb-a73e794a83bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690315106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.2690315106
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1719744783
Short name T906
Test name
Test status
Simulation time 61503465 ps
CPU time 1.52 seconds
Started Jan 03 01:14:15 PM PST 24
Finished Jan 03 01:14:44 PM PST 24
Peak memory 218152 kb
Host smart-ba758cbd-1088-468e-bf02-70df2c1eaab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719744783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1719744783
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1560848098
Short name T394
Test name
Test status
Simulation time 1895966136 ps
CPU time 20.46 seconds
Started Jan 03 01:14:34 PM PST 24
Finished Jan 03 01:15:36 PM PST 24
Peak memory 219268 kb
Host smart-3842dd0b-4f0a-4079-b8c0-331ad0b6560c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560848098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1560848098
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4053922978
Short name T490
Test name
Test status
Simulation time 883484663 ps
CPU time 9.68 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:58 PM PST 24
Peak memory 218100 kb
Host smart-86fd8abf-17e0-4be7-9394-1804c51d23e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053922978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4053922978
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1248254958
Short name T970
Test name
Test status
Simulation time 1184135331 ps
CPU time 9.48 seconds
Started Jan 03 01:14:18 PM PST 24
Finished Jan 03 01:14:57 PM PST 24
Peak memory 218144 kb
Host smart-468f8760-a8b9-40a1-a6c7-fb8a25fbd801
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248254958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1248254958
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3686483192
Short name T781
Test name
Test status
Simulation time 261842172 ps
CPU time 10.39 seconds
Started Jan 03 01:14:15 PM PST 24
Finished Jan 03 01:14:53 PM PST 24
Peak memory 218232 kb
Host smart-8d8dd27f-943f-4c2d-9d70-08ef4d7a3b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686483192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3686483192
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3002421789
Short name T83
Test name
Test status
Simulation time 176014192 ps
CPU time 2.28 seconds
Started Jan 03 01:14:15 PM PST 24
Finished Jan 03 01:14:44 PM PST 24
Peak memory 213948 kb
Host smart-a10ba558-fef6-4e4d-b11f-67c95ccb1b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002421789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3002421789
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.22687016
Short name T741
Test name
Test status
Simulation time 266142572 ps
CPU time 30.8 seconds
Started Jan 03 01:14:24 PM PST 24
Finished Jan 03 01:15:27 PM PST 24
Peak memory 251152 kb
Host smart-4edb7b47-395c-4c1b-a240-c4adf801ecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22687016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.22687016
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1114669373
Short name T431
Test name
Test status
Simulation time 1026939918 ps
CPU time 2.8 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:14:52 PM PST 24
Peak memory 222196 kb
Host smart-a3e1229a-41b1-4077-972c-255d7a661a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114669373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1114669373
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3423432367
Short name T645
Test name
Test status
Simulation time 4585997047 ps
CPU time 156.42 seconds
Started Jan 03 01:14:20 PM PST 24
Finished Jan 03 01:17:27 PM PST 24
Peak memory 283160 kb
Host smart-aea47b4b-9afc-4cb7-8775-e6441544ec97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423432367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3423432367
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.4128111421
Short name T41
Test name
Test status
Simulation time 19032827 ps
CPU time 0.99 seconds
Started Jan 03 01:14:17 PM PST 24
Finished Jan 03 01:14:47 PM PST 24
Peak memory 212508 kb
Host smart-80273cc9-abc0-4669-b5b5-061e404f8010
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128111421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.4128111421
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1729300481
Short name T964
Test name
Test status
Simulation time 60488504 ps
CPU time 1.22 seconds
Started Jan 03 01:14:43 PM PST 24
Finished Jan 03 01:15:38 PM PST 24
Peak memory 209764 kb
Host smart-47a368a6-4dde-43f8-9a89-e657fc3c2ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729300481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1729300481
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1171569104
Short name T629
Test name
Test status
Simulation time 981552948 ps
CPU time 21.86 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:58 PM PST 24
Peak memory 218240 kb
Host smart-0191eb4e-464e-434e-99f8-da31708348fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171569104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1171569104
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.368955450
Short name T937
Test name
Test status
Simulation time 952198821 ps
CPU time 8.48 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:42 PM PST 24
Peak memory 209628 kb
Host smart-0af76204-9f18-4fb0-9c21-1d27215324db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368955450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_ac
cess.368955450
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1795521454
Short name T514
Test name
Test status
Simulation time 168645511 ps
CPU time 3.2 seconds
Started Jan 03 01:14:33 PM PST 24
Finished Jan 03 01:15:16 PM PST 24
Peak memory 218220 kb
Host smart-31bda4eb-6a40-48ce-b90e-4eb74f65d656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795521454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1795521454
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3887822737
Short name T896
Test name
Test status
Simulation time 478841910 ps
CPU time 11.3 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:45 PM PST 24
Peak memory 218248 kb
Host smart-4d46a47f-5f0d-454f-98f6-57c1286c4bc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887822737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3887822737
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.454490687
Short name T481
Test name
Test status
Simulation time 264503210 ps
CPU time 11.59 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:32 PM PST 24
Peak memory 218100 kb
Host smart-46d80fa0-e43c-4758-8db3-4fe99d5d164a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454490687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.454490687
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2410994214
Short name T785
Test name
Test status
Simulation time 533651667 ps
CPU time 9.81 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:31 PM PST 24
Peak memory 218104 kb
Host smart-70278353-5e47-48b3-80c8-7aa4e1356e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410994214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2410994214
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.693033037
Short name T200
Test name
Test status
Simulation time 1484300987 ps
CPU time 8.67 seconds
Started Jan 03 01:14:42 PM PST 24
Finished Jan 03 01:15:44 PM PST 24
Peak memory 218244 kb
Host smart-39d48120-fb2a-4b6c-9d87-a3c6aeb96926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693033037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.693033037
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3715958722
Short name T457
Test name
Test status
Simulation time 119892028 ps
CPU time 2.19 seconds
Started Jan 03 01:14:19 PM PST 24
Finished Jan 03 01:14:50 PM PST 24
Peak memory 213584 kb
Host smart-144abbde-69fe-4147-b569-5b43317e37d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715958722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3715958722
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1600706441
Short name T845
Test name
Test status
Simulation time 690448859 ps
CPU time 24.61 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:47 PM PST 24
Peak memory 251192 kb
Host smart-052487ea-b677-49c6-b8b0-8bc77573964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600706441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1600706441
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.4085082666
Short name T635
Test name
Test status
Simulation time 117967968 ps
CPU time 7.16 seconds
Started Jan 03 01:14:36 PM PST 24
Finished Jan 03 01:15:28 PM PST 24
Peak memory 251176 kb
Host smart-13081990-06a2-471a-b6e2-31db6539df62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085082666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.4085082666
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3472068165
Short name T836
Test name
Test status
Simulation time 3952884996 ps
CPU time 122.96 seconds
Started Jan 03 01:14:33 PM PST 24
Finished Jan 03 01:17:16 PM PST 24
Peak memory 276752 kb
Host smart-c63231d4-3a09-4a61-b432-ae422322643b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472068165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3472068165
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2884943485
Short name T124
Test name
Test status
Simulation time 15387112 ps
CPU time 0.99 seconds
Started Jan 03 01:14:37 PM PST 24
Finished Jan 03 01:15:24 PM PST 24
Peak memory 208184 kb
Host smart-38722559-8606-4962-a848-04eba6480f9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884943485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2884943485
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1199245434
Short name T35
Test name
Test status
Simulation time 38597088 ps
CPU time 0.9 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 208452 kb
Host smart-f8dc254b-de85-49c8-953f-9bf75dddc23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199245434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1199245434
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.948712654
Short name T325
Test name
Test status
Simulation time 15825481 ps
CPU time 0.94 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:12:50 PM PST 24
Peak memory 209628 kb
Host smart-72d264a8-84fa-445c-bf27-27c7959a8980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948712654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.948712654
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.390326166
Short name T463
Test name
Test status
Simulation time 298709310 ps
CPU time 13.73 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:13:00 PM PST 24
Peak memory 218140 kb
Host smart-92c29900-d931-42c1-baed-ec58d1ec97a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390326166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.390326166
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2112123062
Short name T761
Test name
Test status
Simulation time 779819030 ps
CPU time 5.05 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:12:55 PM PST 24
Peak memory 209684 kb
Host smart-52ce9faf-1484-4e4e-98d5-0df040ec2f4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112123062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ac
cess.2112123062
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2516358195
Short name T126
Test name
Test status
Simulation time 1639478104 ps
CPU time 30.42 seconds
Started Jan 03 01:12:00 PM PST 24
Finished Jan 03 01:13:09 PM PST 24
Peak memory 218112 kb
Host smart-48d38bc8-29c9-45b6-aeef-d7bfd7b7d886
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516358195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2516358195
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.243487988
Short name T730
Test name
Test status
Simulation time 1433537010 ps
CPU time 9.41 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:12:59 PM PST 24
Peak memory 209664 kb
Host smart-9cb3cb5f-fc3a-42f9-8c6c-0a8f491f5c00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243487988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_p
riority.243487988
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3649479392
Short name T686
Test name
Test status
Simulation time 1065131105 ps
CPU time 4.88 seconds
Started Jan 03 01:12:00 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 218080 kb
Host smart-410bdd7f-9512-4e3a-a0de-b997dcd9b656
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649479392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3649479392
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3422174581
Short name T85
Test name
Test status
Simulation time 3583198336 ps
CPU time 18.62 seconds
Started Jan 03 01:12:01 PM PST 24
Finished Jan 03 01:13:00 PM PST 24
Peak memory 213868 kb
Host smart-0e363d47-e840-4e97-8597-2559711f96c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422174581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3422174581
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3189086752
Short name T34
Test name
Test status
Simulation time 332457025 ps
CPU time 4.24 seconds
Started Jan 03 01:11:58 PM PST 24
Finished Jan 03 01:12:40 PM PST 24
Peak memory 213136 kb
Host smart-ad0727e1-f1d3-4e41-a7f7-c1bb1a896c3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189086752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3189086752
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.927520428
Short name T493
Test name
Test status
Simulation time 1635580013 ps
CPU time 27.89 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:13:16 PM PST 24
Peak memory 249940 kb
Host smart-ff218df4-9c8a-49f7-9f0e-2ca6e463ce45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927520428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.927520428
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2578351542
Short name T414
Test name
Test status
Simulation time 392919308 ps
CPU time 12.48 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:59 PM PST 24
Peak memory 223768 kb
Host smart-1a2eedad-5068-47fa-a540-f996b1ebb4b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578351542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2578351542
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2433435676
Short name T774
Test name
Test status
Simulation time 58130999 ps
CPU time 1.81 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:12:52 PM PST 24
Peak memory 218212 kb
Host smart-fa376d1e-1cde-4c4a-986e-8d61c7d0a293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433435676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2433435676
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.429698462
Short name T88
Test name
Test status
Simulation time 353532263 ps
CPU time 22.66 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:13:09 PM PST 24
Peak memory 213724 kb
Host smart-47a51fe0-9877-416b-a1d5-8cd1b836f5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429698462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.429698462
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2571908490
Short name T967
Test name
Test status
Simulation time 998685845 ps
CPU time 13.39 seconds
Started Jan 03 01:11:59 PM PST 24
Finished Jan 03 01:12:51 PM PST 24
Peak memory 218160 kb
Host smart-0ff75c24-f546-4f51-a128-f94776b017c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571908490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2571908490
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2902447194
Short name T497
Test name
Test status
Simulation time 409716143 ps
CPU time 9.56 seconds
Started Jan 03 01:11:59 PM PST 24
Finished Jan 03 01:12:47 PM PST 24
Peak memory 218076 kb
Host smart-fa1be773-e020-4bea-abc0-e0ba8e2e5f13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902447194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2902447194
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3304068298
Short name T396
Test name
Test status
Simulation time 1761801854 ps
CPU time 8.32 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:12:51 PM PST 24
Peak memory 218116 kb
Host smart-137b1b46-1210-41a7-9ca2-1e8683dffb54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304068298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
304068298
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1846895677
Short name T425
Test name
Test status
Simulation time 471172777 ps
CPU time 9.58 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:56 PM PST 24
Peak memory 218180 kb
Host smart-82bf30c6-504b-4f9b-b30c-084fd95625b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846895677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1846895677
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2476622988
Short name T385
Test name
Test status
Simulation time 83903594 ps
CPU time 2.4 seconds
Started Jan 03 01:12:00 PM PST 24
Finished Jan 03 01:12:42 PM PST 24
Peak memory 213992 kb
Host smart-69888b01-59e7-4c23-82dd-dff87a6aa5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476622988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2476622988
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2114861666
Short name T355
Test name
Test status
Simulation time 250624268 ps
CPU time 20.96 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:13:06 PM PST 24
Peak memory 243796 kb
Host smart-4dac45d7-baff-4c18-ab4f-3484e06efd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114861666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2114861666
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.363811011
Short name T391
Test name
Test status
Simulation time 118540198 ps
CPU time 3.79 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:49 PM PST 24
Peak memory 222372 kb
Host smart-3a970850-0a38-4e13-a22e-42f0baf57b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363811011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.363811011
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1607293883
Short name T474
Test name
Test status
Simulation time 16025194174 ps
CPU time 111.85 seconds
Started Jan 03 01:11:58 PM PST 24
Finished Jan 03 01:14:28 PM PST 24
Peak memory 277660 kb
Host smart-48d91a90-6dfe-47c2-bc64-49abe5a18bf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607293883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1607293883
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.581900835
Short name T768
Test name
Test status
Simulation time 37766848 ps
CPU time 0.86 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:47 PM PST 24
Peak memory 208124 kb
Host smart-4db6c90d-03b3-4a4e-bef0-96f750970071
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581900835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.581900835
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3861390843
Short name T571
Test name
Test status
Simulation time 90796519 ps
CPU time 0.96 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:12:51 PM PST 24
Peak memory 208376 kb
Host smart-30f1aa54-dd66-493c-b6e9-d96a7894c7fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861390843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3861390843
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1298472199
Short name T446
Test name
Test status
Simulation time 411751565 ps
CPU time 11.65 seconds
Started Jan 03 01:12:06 PM PST 24
Finished Jan 03 01:13:04 PM PST 24
Peak memory 217956 kb
Host smart-18ea4cd6-caa5-4977-891b-4e1a87d072b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298472199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1298472199
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1431018948
Short name T24
Test name
Test status
Simulation time 711145074 ps
CPU time 4.14 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:12:47 PM PST 24
Peak memory 209680 kb
Host smart-2878422d-5954-43d1-8489-ae2125202139
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431018948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.1431018948
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1009568631
Short name T690
Test name
Test status
Simulation time 6691573201 ps
CPU time 53.67 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 218332 kb
Host smart-577c4f48-7e71-43ef-a91d-6bf02ea742f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009568631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1009568631
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.243570284
Short name T458
Test name
Test status
Simulation time 127310925 ps
CPU time 3.72 seconds
Started Jan 03 01:12:01 PM PST 24
Finished Jan 03 01:12:44 PM PST 24
Peak memory 209696 kb
Host smart-ca55f29a-2e0c-4edc-8408-f444a23d169e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243570284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_p
riority.243570284
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.600587319
Short name T747
Test name
Test status
Simulation time 878218399 ps
CPU time 6.54 seconds
Started Jan 03 01:12:01 PM PST 24
Finished Jan 03 01:12:48 PM PST 24
Peak memory 218160 kb
Host smart-358819b0-a2ed-439a-ac07-a36f1b2abb5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600587319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.600587319
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2836998102
Short name T829
Test name
Test status
Simulation time 637880640 ps
CPU time 18.07 seconds
Started Jan 03 01:12:06 PM PST 24
Finished Jan 03 01:13:09 PM PST 24
Peak memory 213028 kb
Host smart-764dbf2b-1644-4868-88b5-65e088539f85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836998102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2836998102
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3795116
Short name T5
Test name
Test status
Simulation time 817526727 ps
CPU time 4.02 seconds
Started Jan 03 01:12:15 PM PST 24
Finished Jan 03 01:13:07 PM PST 24
Peak memory 212196 kb
Host smart-541c2031-14ad-4b5b-8821-2d33835ca55d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.3795116
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2189221291
Short name T760
Test name
Test status
Simulation time 5716234015 ps
CPU time 41.9 seconds
Started Jan 03 01:12:16 PM PST 24
Finished Jan 03 01:13:46 PM PST 24
Peak memory 277160 kb
Host smart-8be8d1fe-b7a3-4382-a0c7-9becd0618807
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189221291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2189221291
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3850640563
Short name T568
Test name
Test status
Simulation time 1321286179 ps
CPU time 11.72 seconds
Started Jan 03 01:12:15 PM PST 24
Finished Jan 03 01:13:14 PM PST 24
Peak memory 223584 kb
Host smart-aefdbec2-48cb-4f98-a427-a66062660fae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850640563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3850640563
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2187867602
Short name T308
Test name
Test status
Simulation time 329333881 ps
CPU time 3.18 seconds
Started Jan 03 01:12:15 PM PST 24
Finished Jan 03 01:13:06 PM PST 24
Peak memory 217536 kb
Host smart-33f8cf3f-a2eb-455d-b862-ebf8fb6dee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187867602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2187867602
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1732600743
Short name T734
Test name
Test status
Simulation time 348163379 ps
CPU time 11.91 seconds
Started Jan 03 01:12:06 PM PST 24
Finished Jan 03 01:13:04 PM PST 24
Peak memory 213380 kb
Host smart-03404f47-44fc-406a-936f-a602fc90b3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732600743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1732600743
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1263966457
Short name T376
Test name
Test status
Simulation time 2981079038 ps
CPU time 11.49 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:58 PM PST 24
Peak memory 219684 kb
Host smart-5389589e-7276-48f2-a767-a05712c75843
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263966457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1263966457
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1025234452
Short name T636
Test name
Test status
Simulation time 484614828 ps
CPU time 8.66 seconds
Started Jan 03 01:12:07 PM PST 24
Finished Jan 03 01:13:01 PM PST 24
Peak memory 218096 kb
Host smart-218cc5e4-583d-444c-b7b2-9aefef9888b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025234452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1025234452
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.536579268
Short name T15
Test name
Test status
Simulation time 1053049194 ps
CPU time 6.13 seconds
Started Jan 03 01:12:07 PM PST 24
Finished Jan 03 01:12:59 PM PST 24
Peak memory 218156 kb
Host smart-18cca346-b478-4645-88af-677039d69aba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536579268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.536579268
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.985660363
Short name T693
Test name
Test status
Simulation time 5152094734 ps
CPU time 6.2 seconds
Started Jan 03 01:12:15 PM PST 24
Finished Jan 03 01:13:09 PM PST 24
Peak memory 217952 kb
Host smart-442bb172-35ff-4ac6-b246-427d8492375c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985660363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.985660363
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3682866739
Short name T123
Test name
Test status
Simulation time 19461328 ps
CPU time 1.51 seconds
Started Jan 03 01:11:58 PM PST 24
Finished Jan 03 01:12:38 PM PST 24
Peak memory 213156 kb
Host smart-2f943e9a-a2cf-433a-b1c9-ef00467d0919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682866739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3682866739
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.285181836
Short name T455
Test name
Test status
Simulation time 319975657 ps
CPU time 30.15 seconds
Started Jan 03 01:12:06 PM PST 24
Finished Jan 03 01:13:21 PM PST 24
Peak memory 251140 kb
Host smart-bf3f2bd5-e7bf-46e3-a1fc-e30413db1f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285181836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.285181836
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.4109685065
Short name T818
Test name
Test status
Simulation time 54819469 ps
CPU time 7.12 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:12:54 PM PST 24
Peak memory 251336 kb
Host smart-ed57ef64-26a4-424d-8cd2-014949974cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109685065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.4109685065
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.986456064
Short name T441
Test name
Test status
Simulation time 13652118 ps
CPU time 0.79 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:47 PM PST 24
Peak memory 208356 kb
Host smart-7f1f3e7b-8337-4f95-9cfb-f3ecf20504ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986456064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.986456064
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3177375275
Short name T911
Test name
Test status
Simulation time 26105527 ps
CPU time 0.87 seconds
Started Jan 03 01:12:07 PM PST 24
Finished Jan 03 01:12:54 PM PST 24
Peak memory 208224 kb
Host smart-905a27d8-f68e-40cd-bfed-e6985430edf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177375275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3177375275
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1305932220
Short name T612
Test name
Test status
Simulation time 25378296 ps
CPU time 0.78 seconds
Started Jan 03 01:13:12 PM PST 24
Finished Jan 03 01:13:59 PM PST 24
Peak memory 208528 kb
Host smart-d4177170-18b1-42a1-bb56-d05e50f9ee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305932220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1305932220
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2584815604
Short name T380
Test name
Test status
Simulation time 1075985837 ps
CPU time 10.27 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:13:00 PM PST 24
Peak memory 218092 kb
Host smart-92eef4aa-f7fa-4cba-bec9-ef8df36eede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584815604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2584815604
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3205539006
Short name T773
Test name
Test status
Simulation time 649849748 ps
CPU time 2.26 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:12:49 PM PST 24
Peak memory 209604 kb
Host smart-81bbe336-439a-466e-9e56-a836fc94c6de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205539006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.3205539006
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4083951291
Short name T454
Test name
Test status
Simulation time 35522477439 ps
CPU time 58.94 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:13:49 PM PST 24
Peak memory 218308 kb
Host smart-2d238853-4258-44ab-8810-a8371d9ca818
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083951291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4083951291
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2622787016
Short name T466
Test name
Test status
Simulation time 1617506811 ps
CPU time 5.43 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:12:53 PM PST 24
Peak memory 217864 kb
Host smart-0561b886-f204-40e5-817a-afa62e85a8b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622787016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.2622787016
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.380806235
Short name T976
Test name
Test status
Simulation time 64584756 ps
CPU time 1.9 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:12:52 PM PST 24
Peak memory 217752 kb
Host smart-cbf053f3-0d1a-4157-b438-85541a60013e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380806235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.380806235
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1402681794
Short name T705
Test name
Test status
Simulation time 3943378154 ps
CPU time 22.19 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:13:12 PM PST 24
Peak memory 213548 kb
Host smart-feec88fd-b24c-4d71-aca8-97235a03b2ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402681794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1402681794
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.993203003
Short name T965
Test name
Test status
Simulation time 800611654 ps
CPU time 2.64 seconds
Started Jan 03 01:12:03 PM PST 24
Finished Jan 03 01:12:49 PM PST 24
Peak memory 212676 kb
Host smart-6f5f6c45-7fad-4ade-81bb-da5293943caf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993203003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.993203003
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3587324622
Short name T401
Test name
Test status
Simulation time 1198830456 ps
CPU time 38.12 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:13:23 PM PST 24
Peak memory 267516 kb
Host smart-02ad657f-c829-41e3-9d22-1d620746aa57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587324622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3587324622
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.4088711387
Short name T739
Test name
Test status
Simulation time 1741147074 ps
CPU time 10.88 seconds
Started Jan 03 01:11:58 PM PST 24
Finished Jan 03 01:12:47 PM PST 24
Peak memory 250540 kb
Host smart-582a0fa7-7d79-4572-8851-f9cbd323bf8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088711387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.4088711387
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2863447944
Short name T849
Test name
Test status
Simulation time 351738994 ps
CPU time 4.15 seconds
Started Jan 03 01:12:09 PM PST 24
Finished Jan 03 01:13:00 PM PST 24
Peak memory 218136 kb
Host smart-edd5677e-586c-4b88-bcad-485f7f7d4fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863447944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2863447944
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3982671540
Short name T411
Test name
Test status
Simulation time 434066486 ps
CPU time 5.1 seconds
Started Jan 03 01:12:16 PM PST 24
Finished Jan 03 01:13:09 PM PST 24
Peak memory 213664 kb
Host smart-79a2d2d2-2255-4845-b3ea-f342f95b6c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982671540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3982671540
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1523716745
Short name T592
Test name
Test status
Simulation time 1300549575 ps
CPU time 11.55 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:13:01 PM PST 24
Peak memory 218528 kb
Host smart-7439b6fa-156e-4548-aa84-75c2e710f693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523716745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1523716745
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.402741549
Short name T974
Test name
Test status
Simulation time 416947460 ps
CPU time 9 seconds
Started Jan 03 01:12:08 PM PST 24
Finished Jan 03 01:13:04 PM PST 24
Peak memory 218112 kb
Host smart-60de80f0-1a91-48e3-b90d-3f6c1ca19066
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402741549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.402741549
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1615834825
Short name T860
Test name
Test status
Simulation time 1422447314 ps
CPU time 12.57 seconds
Started Jan 03 01:12:01 PM PST 24
Finished Jan 03 01:12:52 PM PST 24
Peak memory 218092 kb
Host smart-51309c81-fc4d-463f-a4c4-06dfd0d3f5f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615834825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
615834825
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2629977562
Short name T751
Test name
Test status
Simulation time 1118057509 ps
CPU time 8.67 seconds
Started Jan 03 01:12:07 PM PST 24
Finished Jan 03 01:13:02 PM PST 24
Peak memory 218092 kb
Host smart-2610a90b-e808-4daf-80c1-f78e75266839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629977562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2629977562
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1952782129
Short name T447
Test name
Test status
Simulation time 37630367 ps
CPU time 1.48 seconds
Started Jan 03 01:12:02 PM PST 24
Finished Jan 03 01:12:45 PM PST 24
Peak memory 213548 kb
Host smart-52aeaffd-5516-412f-9311-2eabb33f7c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952782129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1952782129
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.871922131
Short name T581
Test name
Test status
Simulation time 465771833 ps
CPU time 19.3 seconds
Started Jan 03 01:12:04 PM PST 24
Finished Jan 03 01:13:07 PM PST 24
Peak memory 251068 kb
Host smart-b1e67784-856f-43da-8077-10dcc7a2092f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871922131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.871922131
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3841207022
Short name T819
Test name
Test status
Simulation time 190092301 ps
CPU time 5.71 seconds
Started Jan 03 01:12:05 PM PST 24
Finished Jan 03 01:12:55 PM PST 24
Peak memory 246392 kb
Host smart-52f5d747-3e47-438a-9c0e-0af379d8bb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841207022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3841207022
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.989172521
Short name T914
Test name
Test status
Simulation time 4467988894 ps
CPU time 103.93 seconds
Started Jan 03 01:12:13 PM PST 24
Finished Jan 03 01:14:45 PM PST 24
Peak memory 251284 kb
Host smart-482efd57-06d2-4f05-af93-a686c9a2cdc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989172521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.989172521
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1383790543
Short name T646
Test name
Test status
Simulation time 13915507 ps
CPU time 0.88 seconds
Started Jan 03 01:12:15 PM PST 24
Finished Jan 03 01:13:03 PM PST 24
Peak memory 207888 kb
Host smart-230075e9-6989-46c8-b80b-f946c13d1a20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383790543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1383790543
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1424332745
Short name T909
Test name
Test status
Simulation time 21305374 ps
CPU time 1.2 seconds
Started Jan 03 01:12:46 PM PST 24
Finished Jan 03 01:13:27 PM PST 24
Peak memory 209740 kb
Host smart-bc39a220-61ad-4388-be4d-b71b3dec64eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424332745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1424332745
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2466697340
Short name T196
Test name
Test status
Simulation time 32320791 ps
CPU time 0.79 seconds
Started Jan 03 01:12:08 PM PST 24
Finished Jan 03 01:12:56 PM PST 24
Peak memory 209396 kb
Host smart-f6bd8397-ba3c-4c6b-8ecd-c7d6f47f3690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466697340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2466697340
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3296524064
Short name T825
Test name
Test status
Simulation time 381787742 ps
CPU time 11.69 seconds
Started Jan 03 01:12:08 PM PST 24
Finished Jan 03 01:13:06 PM PST 24
Peak memory 218136 kb
Host smart-b36dca42-5041-427c-b875-a9a4386fa48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296524064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3296524064
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4047880872
Short name T649
Test name
Test status
Simulation time 277141231 ps
CPU time 4.08 seconds
Started Jan 03 01:12:44 PM PST 24
Finished Jan 03 01:13:29 PM PST 24
Peak memory 209612 kb
Host smart-fbdb7d63-28d6-4230-bcff-803d55517855
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047880872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.4047880872
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.943496990
Short name T957
Test name
Test status
Simulation time 6602928780 ps
CPU time 26.04 seconds
Started Jan 03 01:12:42 PM PST 24
Finished Jan 03 01:13:50 PM PST 24
Peak memory 219148 kb
Host smart-7a7f47fa-e0d9-4bca-87c9-9fdcbeafa8f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943496990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.943496990
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3511545499
Short name T395
Test name
Test status
Simulation time 401941724 ps
CPU time 4.68 seconds
Started Jan 03 01:12:46 PM PST 24
Finished Jan 03 01:13:31 PM PST 24
Peak memory 209640 kb
Host smart-41265732-2a33-412e-982c-4224ead4fa25
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511545499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.3511545499
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2550948978
Short name T541
Test name
Test status
Simulation time 1144441775 ps
CPU time 7.09 seconds
Started Jan 03 01:12:34 PM PST 24
Finished Jan 03 01:13:26 PM PST 24
Peak memory 218160 kb
Host smart-50ad8f85-d6b1-41d5-b216-54101cf9507b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550948978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2550948978
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1906814584
Short name T525
Test name
Test status
Simulation time 10144376696 ps
CPU time 31.61 seconds
Started Jan 03 01:12:44 PM PST 24
Finished Jan 03 01:13:57 PM PST 24
Peak memory 213792 kb
Host smart-731fd0a0-2d0c-4240-a63a-e5541628cd71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906814584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1906814584
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.567731691
Short name T807
Test name
Test status
Simulation time 53912227 ps
CPU time 2.15 seconds
Started Jan 03 01:12:11 PM PST 24
Finished Jan 03 01:13:01 PM PST 24
Peak memory 212740 kb
Host smart-ba0126b3-4aaa-4cf8-b33f-2529f5cf47fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567731691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.567731691
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.61144868
Short name T318
Test name
Test status
Simulation time 11161191209 ps
CPU time 39.39 seconds
Started Jan 03 01:12:45 PM PST 24
Finished Jan 03 01:14:05 PM PST 24
Peak memory 251232 kb
Host smart-2bb98752-c631-4446-82cb-0c7257fffde9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61144868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
state_failure.61144868
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3840789252
Short name T322
Test name
Test status
Simulation time 915219493 ps
CPU time 12.53 seconds
Started Jan 03 01:12:45 PM PST 24
Finished Jan 03 01:13:38 PM PST 24
Peak memory 247248 kb
Host smart-f2794889-def2-4c84-9f77-fea2fe5a1abc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840789252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3840789252
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4289048377
Short name T828
Test name
Test status
Simulation time 95675740 ps
CPU time 2.77 seconds
Started Jan 03 01:12:12 PM PST 24
Finished Jan 03 01:13:02 PM PST 24
Peak memory 218252 kb
Host smart-78e3c5a4-2947-4f59-9bed-a092dc5fba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289048377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4289048377
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4003433292
Short name T440
Test name
Test status
Simulation time 341173747 ps
CPU time 19.35 seconds
Started Jan 03 01:12:06 PM PST 24
Finished Jan 03 01:13:12 PM PST 24
Peak memory 214156 kb
Host smart-73bbed1b-6a86-4231-b081-91cd678bf698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003433292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4003433292
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1826858264
Short name T750
Test name
Test status
Simulation time 758168702 ps
CPU time 10.03 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:41 PM PST 24
Peak memory 219284 kb
Host smart-fcbf7108-2ab4-4a01-b89e-4b71b5c2a57f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826858264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1826858264
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2428156059
Short name T908
Test name
Test status
Simulation time 3513662216 ps
CPU time 14.44 seconds
Started Jan 03 01:12:35 PM PST 24
Finished Jan 03 01:13:33 PM PST 24
Peak memory 218132 kb
Host smart-ed404fdf-6eba-4f4d-ab65-3bb0559573ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428156059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2428156059
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2924694308
Short name T406
Test name
Test status
Simulation time 249574547 ps
CPU time 9.88 seconds
Started Jan 03 01:12:08 PM PST 24
Finished Jan 03 01:13:05 PM PST 24
Peak memory 218140 kb
Host smart-a79223cd-26a9-493c-ad3d-21941594a058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924694308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2924694308
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.972180821
Short name T92
Test name
Test status
Simulation time 100526492 ps
CPU time 2.12 seconds
Started Jan 03 01:12:07 PM PST 24
Finished Jan 03 01:12:55 PM PST 24
Peak memory 213920 kb
Host smart-3db7af4f-1fa1-4917-b08f-c4fc30131b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972180821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.972180821
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3171041017
Short name T36
Test name
Test status
Simulation time 289629934 ps
CPU time 24.9 seconds
Started Jan 03 01:12:08 PM PST 24
Finished Jan 03 01:13:20 PM PST 24
Peak memory 251076 kb
Host smart-ae7fcc1a-9294-403a-9cfb-52a4a1317468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171041017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3171041017
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.4182864373
Short name T683
Test name
Test status
Simulation time 164254883 ps
CPU time 2.95 seconds
Started Jan 03 01:12:07 PM PST 24
Finished Jan 03 01:12:56 PM PST 24
Peak memory 221888 kb
Host smart-dd97140f-a7c2-4269-9bb2-884ffd5ad933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182864373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4182864373
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3650693832
Short name T323
Test name
Test status
Simulation time 7351892287 ps
CPU time 47.77 seconds
Started Jan 03 01:12:33 PM PST 24
Finished Jan 03 01:14:05 PM PST 24
Peak memory 275852 kb
Host smart-c5fc3b83-0068-4623-a300-6bd571d63158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650693832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3650693832
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1536169123
Short name T544
Test name
Test status
Simulation time 19576437 ps
CPU time 0.86 seconds
Started Jan 03 01:12:08 PM PST 24
Finished Jan 03 01:12:56 PM PST 24
Peak memory 208108 kb
Host smart-1bf77127-eddd-4caa-af35-42e068158971
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536169123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1536169123
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3669017896
Short name T895
Test name
Test status
Simulation time 66235558 ps
CPU time 0.84 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:34 PM PST 24
Peak memory 208336 kb
Host smart-79e4569e-bd75-4c75-9f59-2b23f54e3192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669017896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3669017896
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1617729001
Short name T623
Test name
Test status
Simulation time 25797868 ps
CPU time 0.83 seconds
Started Jan 03 01:12:44 PM PST 24
Finished Jan 03 01:13:26 PM PST 24
Peak memory 209396 kb
Host smart-c5cb2b6a-4531-4556-86af-d4d3cd011bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617729001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1617729001
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.879183987
Short name T979
Test name
Test status
Simulation time 2066168582 ps
CPU time 19.32 seconds
Started Jan 03 01:12:45 PM PST 24
Finished Jan 03 01:13:45 PM PST 24
Peak memory 218216 kb
Host smart-5fbb6de7-9e11-4685-8602-d6ca782bf6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879183987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.879183987
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3633594364
Short name T843
Test name
Test status
Simulation time 1043319513 ps
CPU time 3.31 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:35 PM PST 24
Peak memory 209792 kb
Host smart-6336930f-bda7-41f2-847f-eb9196c1ce17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633594364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.3633594364
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.7389866
Short name T695
Test name
Test status
Simulation time 21017894821 ps
CPU time 22.86 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:54 PM PST 24
Peak memory 218240 kb
Host smart-91e405aa-95ad-4e1f-8494-3d22988116e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7389866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_error
s.7389866
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.925320773
Short name T477
Test name
Test status
Simulation time 1785659175 ps
CPU time 2.81 seconds
Started Jan 03 01:12:52 PM PST 24
Finished Jan 03 01:13:34 PM PST 24
Peak memory 209664 kb
Host smart-0770a78a-395e-4c01-a9e3-e304a272243a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925320773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_p
riority.925320773
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.249713612
Short name T698
Test name
Test status
Simulation time 730756329 ps
CPU time 10.05 seconds
Started Jan 03 01:12:34 PM PST 24
Finished Jan 03 01:13:29 PM PST 24
Peak memory 218104 kb
Host smart-e72b74b3-9808-4231-9e10-1619248ff458
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249713612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.249713612
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3935909379
Short name T601
Test name
Test status
Simulation time 4979836760 ps
CPU time 31.4 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:14:02 PM PST 24
Peak memory 213832 kb
Host smart-2a3cbffb-0d9c-42cb-ba46-d2dc00628e63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935909379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3935909379
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2187285598
Short name T77
Test name
Test status
Simulation time 2076544834 ps
CPU time 7.01 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 213376 kb
Host smart-c5b98cc5-93b8-4ce6-a51e-7e63049b3c26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187285598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2187285598
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2649558933
Short name T668
Test name
Test status
Simulation time 6708111393 ps
CPU time 48.56 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:14:19 PM PST 24
Peak memory 283896 kb
Host smart-108eba5f-d2aa-4b66-801a-a7be6094dd48
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649558933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2649558933
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1258015933
Short name T981
Test name
Test status
Simulation time 2757889202 ps
CPU time 11.23 seconds
Started Jan 03 01:12:50 PM PST 24
Finished Jan 03 01:13:41 PM PST 24
Peak memory 218252 kb
Host smart-c88b3db5-49ed-45d9-be82-fe186fc1a82e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258015933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1258015933
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2758717370
Short name T127
Test name
Test status
Simulation time 277774934 ps
CPU time 2.83 seconds
Started Jan 03 01:12:45 PM PST 24
Finished Jan 03 01:13:29 PM PST 24
Peak memory 218280 kb
Host smart-4bb46b20-2254-4d23-911a-1b3fc0f3f39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758717370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2758717370
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3443986353
Short name T84
Test name
Test status
Simulation time 1241775161 ps
CPU time 11.69 seconds
Started Jan 03 01:12:39 PM PST 24
Finished Jan 03 01:13:34 PM PST 24
Peak memory 214188 kb
Host smart-04943248-479e-4432-bfef-4e202dda8557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443986353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3443986353
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.279900573
Short name T377
Test name
Test status
Simulation time 644308355 ps
CPU time 10.26 seconds
Started Jan 03 01:12:53 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 219176 kb
Host smart-ac828df3-d68c-4fca-90d7-90d8df599eb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279900573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.279900573
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2911725205
Short name T681
Test name
Test status
Simulation time 440607154 ps
CPU time 9.77 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:13:43 PM PST 24
Peak memory 218120 kb
Host smart-c43f8e39-1d73-47ca-83ac-42df1cdcb0c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911725205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2911725205
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1299984352
Short name T593
Test name
Test status
Simulation time 281344884 ps
CPU time 11.09 seconds
Started Jan 03 01:12:51 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 218184 kb
Host smart-484c34f1-5fac-4a81-9a2a-302350269437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299984352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
299984352
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1249798968
Short name T587
Test name
Test status
Simulation time 1470580703 ps
CPU time 10.02 seconds
Started Jan 03 01:12:33 PM PST 24
Finished Jan 03 01:13:27 PM PST 24
Peak memory 218164 kb
Host smart-a63081e7-8dea-4601-9207-68b304b1c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249798968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1249798968
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1264995554
Short name T332
Test name
Test status
Simulation time 55499027 ps
CPU time 1.89 seconds
Started Jan 03 01:12:45 PM PST 24
Finished Jan 03 01:13:28 PM PST 24
Peak memory 213856 kb
Host smart-484a6573-542c-45fe-8ef8-5e7b82c12e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264995554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1264995554
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3283411626
Short name T407
Test name
Test status
Simulation time 166972568 ps
CPU time 16.14 seconds
Started Jan 03 01:12:49 PM PST 24
Finished Jan 03 01:13:45 PM PST 24
Peak memory 251084 kb
Host smart-1b4f7c43-60f7-4e1d-9c48-027e537a2e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283411626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3283411626
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.915029201
Short name T815
Test name
Test status
Simulation time 90266732 ps
CPU time 3.72 seconds
Started Jan 03 01:12:45 PM PST 24
Finished Jan 03 01:13:29 PM PST 24
Peak memory 226588 kb
Host smart-41c1371b-e32a-4bad-8e6b-e7855f3a718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915029201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.915029201
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1836139518
Short name T566
Test name
Test status
Simulation time 1491075903 ps
CPU time 69.46 seconds
Started Jan 03 01:12:54 PM PST 24
Finished Jan 03 01:14:43 PM PST 24
Peak memory 269952 kb
Host smart-3b8d7d48-b7d9-469f-92cb-2c47b21a7961
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836139518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1836139518
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3442323396
Short name T624
Test name
Test status
Simulation time 14495022 ps
CPU time 0.75 seconds
Started Jan 03 01:12:34 PM PST 24
Finished Jan 03 01:13:19 PM PST 24
Peak memory 208176 kb
Host smart-91ff8274-a419-454c-ae27-ba64e4ca627e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442323396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3442323396
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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