LC_CTRL Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: 748235cbb6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.300s	119.121us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	98.415us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	16.391us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.680s	38.023us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.250s	50.709us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.640s	28.590us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	16.391us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	50.709us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.050s	344.838us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.660s	353.532us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	11.923us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.390s	182.286us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.170s	6.361ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_prog_failure	4.390s	182.286us	50	50	100.00
		lc_ctrl_errors	24.170s	6.361ms	50	50	100.00
		lc_ctrl_security_escalation	21.210s	1.662ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.850m	3.461ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.820s	3.038ms	20	20	100.00
		lc_ctrl_jtag_errors	58.940s	35.522ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.540s	553.550us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	38.760s	2.561ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.820s	3.038ms	20	20	100.00
		lc_ctrl_jtag_errors	58.940s	35.522ms	20	20	100.00
		lc_ctrl_jtag_access	22.390s	1.602ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.610s	10.144ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.380s	2.475ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.200s	75.762us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	37.510s	7.230ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	7.470s	3.100ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.020s	191.071us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.830s	159.971us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.840s	54.792us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	9.960s	388.723us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.470s	21.124us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.558m	267.299ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.690s	93.605us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.420s	97.692us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.420s	97.692us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	98.415us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	16.391us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	50.709us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.040s	100.188us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	98.415us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	16.391us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	50.709us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.040s	100.188us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
		lc_ctrl_tl_intg_err	4.240s	117.434us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.240s	117.434us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.660s	353.532us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.290s	285.898us	50	50	100.00
		lc_ctrl_sec_cm	41.650s	217.292us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.210s	1.662ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.050s	344.838us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	38.760s	2.561ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.460s	1.896ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.460s	1.896ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.790s	3.269ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.500s	1.002ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.500s	1.002ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	18.280m	109.003ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			984	1030	95.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.34	97.29	95.70	91.98	100.00	96.13	98.48	94.82

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.32635738440839769020523822473894317791714147141477933815048001035018600971976
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a237cd31-f6b6-4343-84a7-80f9f9887d47
      

    • 7.lc_ctrl_stress_all_with_rand_reset.9517919727160452266855689104754632483136660528700893102712604573534095953223
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:e58ae2ce-bb7d-4a20-b543-e13483891083
      

    • ... and 19 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 13 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.115647859383218515400326613678568175270573031479020805067077667826074352340517
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:fcee07f4-2e40-4eba-a859-16c344789fef
      

    • 5.lc_ctrl_stress_all_with_rand_reset.20344880694712967583993063137306105955165626086147597700705038965626753698976
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:59c4e4d2-a091-4564-a00a-2a2903b5a390
      

    • ... and 11 more failures.

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 7 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 7 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.86598678157419850977848105858851983865735186565580974464911587432400345591801
      Line 1411, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 765187252 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x8a0d4600
        UVM_INFO @ 765187252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.101675062570843312338028921654512384634519271120749262053731067523511568491207
      Line 32953, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 109002751331 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x8c5561c
        UVM_INFO @ 109002751331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.36643719854703724432502673998475420661049463210540993795828266591484618903173
      Line 18597, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 79895755001 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
        UVM_INFO @ 79895755001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.lc_ctrl_stress_all_with_rand_reset.9321539833872345970596653751319767772021920030136959342935555199935222220450
      Line 606, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 350900068 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
        UVM_INFO @ 350900068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.10886504055998259390786710890312701062506905148572738607503968433984951254163
      Line 987, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2424545022 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked0
        UVM_INFO @ 2424545022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.98713367794261779463513947925273280388682017047145489926955349455575306874482
      Line 333, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3186798260 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 3186798260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:371) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: lc_ctrl_reg_block.lc_transition_cnt has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 47.lc_ctrl_stress_all_with_rand_reset.55373532081938258923335538076156944544291111068751074998780682587516133662764
      Line 8593, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5109121404 ps: (lc_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (19 [0x13] vs 31 [0x1f]) reg name: lc_ctrl_reg_block.lc_transition_cnt
        UVM_INFO @ 5109121404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.01.01_00.49.32
• 2023.12.28_03.23.05
• 2023.12.25_01.25.43
• 2023.12.21_00.15.46
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