Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63499253

1

T1

35629

T83

3301

T84

2613

auto[1]

1200620

1

T1

1386

T10

297

T5

98

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63468748

1

T1

36223

T83

3301

T84

2613

auto[1]

1231125

1

T1

792

T10

297

T5

296

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5437798	1			T1	5544		T83	104		T84	112
auto[IdleSt]	14642531	1			T1	2303		T83	3197		T84	2501
auto[ClkMuxSt]	29717	1			T1	51		T2	91		T4	76
auto[CntIncrSt]	29508	1			T1	51		T2	91		T4	76
auto[CntProgSt]	1480326	1			T1	11129		T2	182		T4	1926
auto[TransCheckSt]	22987	1			T1	38		T2	91		T4	76
auto[TokenHashSt]	21328914	1			T1	418		T2	990		T4	701
auto[FlashRmaSt]	23297	1			T1	100		T4	65		T8	46
auto[TokenCheck0St]	10167	1			T1	34		T4	24		T8	30
auto[TokenCheck1St]	7318	1			T1	20		T4	6		T8	12
auto[TransProgSt]	375706	1			T1	7134		T9	1333		T10	129
auto[PostTransSt]	8588856	1			T1	6576		T2	15727		T4	12023
auto[ScrapSt]	101820	1			T87	2999		T102	323		T103	857
auto[EscalateSt]	5129757	1			T1	2952		T10	892		T5	3921
auto[InvalidSt]	7489765	1			T1	665		T5	4006		T11	1494

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1406	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7489765	1			T1	665		T5	4006		T11	1494
EscalateSt	5129757	1			T1	2952		T10	892		T5	3921
ScrapSt	101820	1			T87	2999		T102	323		T103	857
PostTransSt	8588856	1			T1	6576		T2	15727		T4	12023
TransProgSt	375706	1			T1	7134		T9	1333		T10	129
TokenCheck1St	7318	1			T1	20		T4	6		T8	12
TokenCheck0St	10167	1			T1	34		T4	24		T8	30
FlashRmaSt	23297	1			T1	100		T4	65		T8	46
TokenHashSt	21328914	1			T1	418		T2	990		T4	701
TransCheckSt	22987	1			T1	38		T2	91		T4	76
CntProgSt	1480326	1			T1	11129		T2	182		T4	1926
CntIncrSt	29508	1			T1	51		T2	91		T4	76
ClkMuxSt	29717	1			T1	51		T2	91		T4	76
IdleSt	14642531	1			T1	2303		T83	3197		T84	2501
ResetSt	5437798	1			T1	5544		T83	104		T84	112
arcs[ResetSt=>IdleSt]	43273	1			T1	61		T83	2		T84	3
arcs[IdleSt=>ScrapSt]	215	1			T87	1		T102	1		T103	2
arcs[IdleSt=>ClkMuxSt]	29573	1			T1	51		T2	91		T4	76
arcs[ClkMuxSt=>CntIncrSt]	29508	1			T1	51		T2	91		T4	76
arcs[CntIncrSt=>PostTransSt]	1464	1			T10	11		T14	9		T15	7
arcs[CntIncrSt=>CntProgSt]	27994	1			T1	51		T2	91		T4	76
arcs[CntProgSt=>PostTransSt]	3870	1			T1	13		T10	6		T11	9
arcs[CntProgSt=>TransCheckSt]	22987	1			T1	38		T2	91		T4	76
arcs[TransCheckSt=>PostTransSt]	3106	1			T4	42		T8	42		T10	1
arcs[TransCheckSt=>TokenHashSt]	19772	1			T1	38		T2	91		T4	34
arcs[TokenHashSt=>PostTransSt]	8861	1			T1	4		T2	91		T4	10
arcs[TokenHashSt=>FlashRmaSt]	10279	1			T1	34		T4	24		T8	30
arcs[FlashRmaSt=>TokenCheck0St]	10167	1			T1	34		T4	24		T8	30
arcs[TokenCheck0St=>PostTransSt]	2816	1			T1	14		T4	18		T8	18
arcs[TokenCheck0St=>TokenCheck1St]	7318	1			T1	20		T4	6		T8	12
arcs[TokenCheck1St=>PostTransSt]	632	1			T1	1		T4	6		T8	12
arcs[TransProgSt=>PostTransSt]	5761	1			T1	19		T9	8		T10	9
arcs[IdleSt=>EscalateSt]	189	1			T47	5		T35	4		T49	9
arcs[ClkMuxSt=>EscalateSt]	65	1			T12	1		T47	2		T35	3
arcs[CntIncrSt=>EscalateSt]	50	1			T12	1		T35	2		T48	2
arcs[CntProgSt=>EscalateSt]	1136	1			T12	44		T47	14		T35	34
arcs[TransCheckSt=>EscalateSt]	109	1			T12	1		T53	9		T49	2
arcs[TokenHashSt=>EscalateSt]	619	1			T12	13		T47	7		T35	6
arcs[FlashRmaSt=>EscalateSt]	112	1			T12	6		T47	5		T35	3
arcs[TokenCheck0St=>EscalateSt]	33	1			T12	2		T35	1		T49	1
arcs[TokenCheck1St=>EscalateSt]	137	1			T12	2		T47	2		T35	2
arcs[TransProgSt=>EscalateSt]	788	1			T12	24		T47	12		T35	24
arcs[PostTransSt=>EscalateSt]	4077	1			T1	13		T10	6		T11	9
arcs[InvalidSt=>EscalateSt]	11217	1			T1	9		T5	4		T11	19

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5437640	1			T1	5544		T83	104		T84	112
auto[0]	auto[IdleSt]	14642412	1			T1	2303		T83	3197		T84	2501
auto[0]	auto[ClkMuxSt]	29670	1			T1	51		T2	91		T4	76
auto[0]	auto[CntIncrSt]	29472	1			T1	51		T2	91		T4	76
auto[0]	auto[CntProgSt]	1479612	1			T1	11129		T2	182		T4	1926
auto[0]	auto[TransCheckSt]	22908	1			T1	38		T2	91		T4	76
auto[0]	auto[TokenHashSt]	21328495	1			T1	418		T2	990		T4	701
auto[0]	auto[FlashRmaSt]	23231	1			T1	100		T4	65		T8	46
auto[0]	auto[TokenCheck0St]	10142	1			T1	34		T4	24		T8	30
auto[0]	auto[TokenCheck1St]	7227	1			T1	20		T4	6		T8	12
auto[0]	auto[TransProgSt]	375175	1			T1	7134		T9	1333		T10	129
auto[0]	auto[PostTransSt]	8586801	1			T1	6567		T2	15727		T4	12023
auto[0]	auto[ScrapSt]	101787	1			T87	2999		T102	323		T103	857
auto[0]	auto[EscalateSt]	3939093	1			T1	1580		T10	598		T5	3824
auto[0]	auto[InvalidSt]	7484182	1			T1	660		T5	4005		T11	1481
auto[1]	auto[ResetSt]	158	1			T12	2		T47	1		T35	7
auto[1]	auto[IdleSt]	119	1			T47	3		T35	3		T49	4
auto[1]	auto[ClkMuxSt]	47	1			T12	1		T47	1		T35	1
auto[1]	auto[CntIncrSt]	36	1			T12	1		T35	2		T48	1
auto[1]	auto[CntProgSt]	714	1			T12	21		T47	10		T35	21
auto[1]	auto[TransCheckSt]	79	1			T12	1		T53	7		T49	1
auto[1]	auto[TokenHashSt]	419	1			T12	6		T47	7		T35	4
auto[1]	auto[FlashRmaSt]	66	1			T12	2		T47	4		T35	2
auto[1]	auto[TokenCheck0St]	25	1			T12	1		T35	1		T49	1
auto[1]	auto[TokenCheck1St]	91	1			T12	1		T47	2		T35	1
auto[1]	auto[TransProgSt]	531	1			T12	14		T47	6		T35	20
auto[1]	auto[PostTransSt]	2055	1			T1	9		T10	3		T11	4
auto[1]	auto[ScrapSt]	33	1			T12	2		T47	1		T35	1
auto[1]	auto[EscalateSt]	1190664	1			T1	1372		T10	294		T5	97
auto[1]	auto[InvalidSt]	5583	1			T1	5		T5	1		T11	13

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5437610	1			T1	5544		T83	104		T84	112
auto[0]	auto[IdleSt]	14642404	1			T1	2303		T83	3197		T84	2501
auto[0]	auto[ClkMuxSt]	29682	1			T1	51		T2	91		T4	76
auto[0]	auto[CntIncrSt]	29479	1			T1	51		T2	91		T4	76
auto[0]	auto[CntProgSt]	1479541	1			T1	11129		T2	182		T4	1926
auto[0]	auto[TransCheckSt]	22914	1			T1	38		T2	91		T4	76
auto[0]	auto[TokenHashSt]	21328501	1			T1	418		T2	990		T4	701
auto[0]	auto[FlashRmaSt]	23221	1			T1	100		T4	65		T8	46
auto[0]	auto[TokenCheck0St]	10147	1			T1	34		T4	24		T8	30
auto[0]	auto[TokenCheck1St]	7223	1			T1	20		T4	6		T8	12
auto[0]	auto[TransProgSt]	375183	1			T1	7134		T9	1333		T10	129
auto[0]	auto[PostTransSt]	8586772	1			T1	6572		T2	15727		T4	12023
auto[0]	auto[ScrapSt]	101782	1			T87	2999		T102	323		T103	857
auto[0]	auto[EscalateSt]	3908752	1			T1	2168		T10	598		T5	3628
auto[0]	auto[InvalidSt]	7484131	1			T1	661		T5	4003		T11	1488
auto[1]	auto[ResetSt]	188	1			T12	2		T47	1		T35	5
auto[1]	auto[IdleSt]	127	1			T47	2		T35	3		T49	6
auto[1]	auto[ClkMuxSt]	35	1			T12	1		T47	1		T35	2
auto[1]	auto[CntIncrSt]	29	1			T35	1		T48	1		T180	1
auto[1]	auto[CntProgSt]	785	1			T12	29		T47	8		T35	25
auto[1]	auto[TransCheckSt]	73	1			T53	5		T49	1		T48	11
auto[1]	auto[TokenHashSt]	413	1			T12	8		T47	4		T35	3
auto[1]	auto[FlashRmaSt]	76	1			T12	5		T47	3		T35	2
auto[1]	auto[TokenCheck0St]	20	1			T12	1		T35	1		T49	1
auto[1]	auto[TokenCheck1St]	95	1			T12	2		T47	2		T35	1
auto[1]	auto[TransProgSt]	523	1			T12	17		T47	9		T35	16
auto[1]	auto[PostTransSt]	2084	1			T1	4		T10	3		T11	5
auto[1]	auto[ScrapSt]	38	1			T47	1		T53	1		T49	1
auto[1]	auto[EscalateSt]	1221005	1			T1	784		T10	294		T5	293
auto[1]	auto[InvalidSt]	5634	1			T1	4		T5	3		T11	6