Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1051812	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1245498

1

T1

1736

T83

25

T84

365

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1998565	1			T1	2719		T83	5		T84	109
values[0x0]	149022	1			T1	247		T83	9		T84	139
values[0x1]	149723	1			T1	233		T83	11		T84	154

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	833877	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1463433

1

T1

2044

T83

25

T84

376

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8351	1			T87	1		T91	1		T102	4
valid_sources[0x01]	8776	1			T1	15		T91	2		T96	2
valid_sources[0x02]	9978	1			T1	88		T84	2		T87	1
valid_sources[0x03]	10317	1			T1	8		T87	1		T91	2
valid_sources[0x04]	8148	1			T1	32		T89	4		T91	2
valid_sources[0x05]	8080	1			T91	3		T96	1		T118	1
valid_sources[0x06]	8396	1			T84	3		T91	2		T96	2
valid_sources[0x07]	11143	1			T84	2		T91	6		T96	1
valid_sources[0x08]	7975	1			T87	1		T91	3		T96	1
valid_sources[0x09]	8066	1			T84	1		T91	2		T96	1
valid_sources[0x0a]	8102	1			T1	8		T84	2		T87	1
valid_sources[0x0b]	7998	1			T91	1		T158	2		T140	1
valid_sources[0x0c]	8327	1			T1	13		T84	1		T91	2
valid_sources[0x0d]	23835	1			T1	16		T84	1		T87	7
valid_sources[0x0e]	8510	1			T84	1		T87	1		T90	9
valid_sources[0x0f]	8340	1			T1	60		T87	2		T91	4
valid_sources[0x10]	11014	1			T84	2		T91	4		T96	1
valid_sources[0x11]	8545	1			T1	10		T84	4		T87	3
valid_sources[0x12]	8254	1			T87	2		T91	2		T96	3
valid_sources[0x13]	8275	1			T84	2		T87	1		T91	3
valid_sources[0x14]	8089	1			T1	55		T84	1		T90	4
valid_sources[0x15]	8076	1			T84	1		T87	2		T91	2
valid_sources[0x16]	7842	1			T84	3		T96	3		T102	17
valid_sources[0x17]	9381	1			T84	4		T91	6		T113	65
valid_sources[0x18]	7867	1			T1	11		T87	1		T91	3
valid_sources[0x19]	9716	1			T1	13		T84	3		T91	4
valid_sources[0x1a]	11959	1			T1	7		T84	1		T87	1
valid_sources[0x1b]	8506	1			T87	1		T91	3		T117	3
valid_sources[0x1c]	8479	1			T84	5		T91	6		T96	1
valid_sources[0x1d]	7841	1			T84	1		T87	2		T91	2
valid_sources[0x1e]	8127	1			T87	2		T90	1		T91	2
valid_sources[0x1f]	9065	1			T1	18		T84	1		T87	2
valid_sources[0x20]	8142	1			T1	12		T87	3		T91	4
valid_sources[0x21]	8530	1			T1	27		T84	1		T87	1
valid_sources[0x22]	8541	1			T84	1		T87	2		T96	1
valid_sources[0x23]	8105	1			T84	1		T87	2		T133	1
valid_sources[0x24]	12763	1			T1	38		T87	3		T91	3
valid_sources[0x25]	9571	1			T1	9		T84	2		T87	3
valid_sources[0x26]	8481	1			T84	1		T87	3		T90	13
valid_sources[0x27]	9378	1			T1	6		T84	1		T91	1
valid_sources[0x28]	7926	1			T1	6		T84	5		T91	1
valid_sources[0x29]	8439	1			T1	54		T84	2		T113	9
valid_sources[0x2a]	8410	1			T1	26		T84	4		T87	1
valid_sources[0x2b]	8242	1			T1	3		T84	1		T96	1
valid_sources[0x2c]	8001	1			T1	8		T84	3		T87	2
valid_sources[0x2d]	11496	1			T1	14		T84	2		T91	1
valid_sources[0x2e]	8178	1			T1	13		T84	2		T87	2
valid_sources[0x2f]	8025	1			T1	16		T84	1		T87	1
valid_sources[0x30]	13669	1			T1	60		T90	9		T98	2
valid_sources[0x31]	7995	1			T1	1		T84	2		T90	9
valid_sources[0x32]	8174	1			T1	31		T84	5		T87	1
valid_sources[0x33]	8245	1			T1	14		T84	1		T91	1
valid_sources[0x34]	8580	1			T1	36		T84	1		T87	3
valid_sources[0x35]	8240	1			T1	12		T84	3		T87	1
valid_sources[0x36]	8194	1			T87	3		T91	2		T96	1
valid_sources[0x37]	8488	1			T1	23		T84	2		T91	5
valid_sources[0x38]	8332	1			T1	1		T84	2		T87	1
valid_sources[0x39]	7856	1			T1	7		T84	3		T87	1
valid_sources[0x3a]	8884	1			T1	27		T87	2		T91	2
valid_sources[0x3b]	8227	1			T84	11		T87	2		T91	2
valid_sources[0x3c]	8859	1			T84	1		T96	2		T157	2
valid_sources[0x3d]	8138	1			T84	3		T87	3		T91	3
valid_sources[0x3e]	8249	1			T91	3		T117	1		T158	2
valid_sources[0x3f]	11861	1			T1	6		T87	3		T91	2
valid_sources[0x40]	8403	1			T1	24		T87	1		T91	3
valid_sources[0x41]	9394	1			T1	22		T87	1		T91	3
valid_sources[0x42]	8101	1			T1	10		T84	2		T87	2
valid_sources[0x43]	8240	1			T1	14		T84	1		T87	1
valid_sources[0x44]	14585	1			T1	7		T84	1		T91	5
valid_sources[0x45]	7972	1			T84	1		T91	3		T133	1
valid_sources[0x46]	8546	1			T1	48		T91	2		T156	3
valid_sources[0x47]	8181	1			T1	3		T87	1		T90	23
valid_sources[0x48]	8183	1			T1	11		T84	1		T87	1
valid_sources[0x49]	7817	1			T1	12		T91	1		T96	1
valid_sources[0x4a]	8192	1			T84	1		T91	1		T96	1
valid_sources[0x4b]	8358	1			T84	2		T91	4		T133	1
valid_sources[0x4c]	10933	1			T84	1		T87	1		T91	6
valid_sources[0x4d]	8085	1			T1	7		T83	13		T84	6
valid_sources[0x4e]	8094	1			T1	1		T84	1		T87	4
valid_sources[0x4f]	7929	1			T1	25		T91	2		T96	1
valid_sources[0x50]	8932	1			T1	12		T84	1		T87	1
valid_sources[0x51]	8042	1			T84	3		T91	1		T96	3
valid_sources[0x52]	8327	1			T1	38		T84	4		T87	2
valid_sources[0x53]	9471	1			T1	33		T84	3		T87	3
valid_sources[0x54]	8260	1			T84	1		T87	3		T91	3
valid_sources[0x55]	8406	1			T87	1		T91	2		T96	1
valid_sources[0x56]	8285	1			T87	1		T91	5		T158	2
valid_sources[0x57]	12022	1			T1	30		T87	1		T91	3
valid_sources[0x58]	8215	1			T84	2		T87	1		T91	1
valid_sources[0x59]	7754	1			T84	1		T87	1		T91	4
valid_sources[0x5a]	12772	1			T1	28		T84	3		T91	2
valid_sources[0x5b]	7986	1			T84	4		T91	2		T96	1
valid_sources[0x5c]	8448	1			T1	2		T84	2		T87	1
valid_sources[0x5d]	13184	1			T87	1		T91	3		T96	1
valid_sources[0x5e]	10668	1			T1	12		T87	1		T91	5
valid_sources[0x5f]	9798	1			T87	3		T91	2		T96	2
valid_sources[0x60]	36525	1			T84	2		T87	1		T91	5
valid_sources[0x61]	8277	1			T1	25		T87	3		T91	3
valid_sources[0x62]	7946	1			T1	3		T84	3		T91	1
valid_sources[0x63]	9039	1			T1	14		T84	1		T87	1
valid_sources[0x64]	9026	1			T84	4		T87	1		T91	3
valid_sources[0x65]	8446	1			T1	17		T84	2		T87	5
valid_sources[0x66]	8172	1			T1	13		T91	2		T96	2
valid_sources[0x67]	8296	1			T1	47		T84	1		T91	3
valid_sources[0x68]	8225	1			T1	61		T84	3		T87	1
valid_sources[0x69]	8336	1			T87	1		T91	2		T96	3
valid_sources[0x6a]	11430	1			T87	2		T91	3		T96	2
valid_sources[0x6b]	12777	1			T1	2		T84	1		T91	6
valid_sources[0x6c]	7937	1			T1	11		T84	3		T87	3
valid_sources[0x6d]	8250	1			T1	11		T84	2		T91	2
valid_sources[0x6e]	8177	1			T91	1		T96	1		T133	3
valid_sources[0x6f]	8133	1			T1	16		T84	5		T87	1
valid_sources[0x70]	8385	1			T90	3		T91	4		T98	12
valid_sources[0x71]	9423	1			T1	9		T84	2		T87	1
valid_sources[0x72]	9405	1			T87	2		T91	1		T117	1
valid_sources[0x73]	8538	1			T1	5		T87	1		T117	1
valid_sources[0x74]	9050	1			T1	28		T84	2		T91	3
valid_sources[0x75]	8299	1			T1	6		T84	2		T91	3
valid_sources[0x76]	8236	1			T1	7		T84	1		T87	1
valid_sources[0x77]	8104	1			T1	30		T84	1		T87	2
valid_sources[0x78]	9463	1			T1	16		T84	1		T87	2
valid_sources[0x79]	9198	1			T87	2		T91	7		T96	1
valid_sources[0x7a]	8657	1			T1	12		T87	1		T113	3
valid_sources[0x7b]	8138	1			T1	18		T84	4		T91	2
valid_sources[0x7c]	8213	1			T1	1		T84	1		T87	1
valid_sources[0x7d]	7890	1			T1	52		T84	3		T87	1
valid_sources[0x7e]	8532	1			T87	4		T91	3		T96	1
valid_sources[0x7f]	8442	1			T1	21		T84	4		T91	2
valid_sources[0x80]	8760	1			T1	8		T84	2		T87	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

988488

1

T1

1323

T83

5

T84

97

values[0x0]

all_enables

biggest_size

129154

1

T1

206

T83

9

T84

133

values[0x1]

all_enables

biggest_size

127856

1

T1

207

T83

11

T84

135