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 LINE       1288
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T84,T87
1	0	1	Covered	T1,T84,T87
1	1	0	Covered	T132,T119
1	1	1	Covered	T1,T2,T4

 LINE       1289
 EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T84,T87
1	0	1	Covered	T1,T84,T87
1	1	0	Covered	T115,T116,T122
1	1	1	Covered	T1,T2,T4

 LINE       1290
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T84,T87
1	0	1	Covered	T1,T84,T87
1	1	0	Covered	T131,T125,T126
1	1	1	Covered	T1,T2,T4

 LINE       1291
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T84,T87
1	0	1	Covered	T1,T84,T87
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       1292
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T84,T87
1	0	1	Covered	T1,T84,T87
1	1	0	Covered	T127,T126
1	1	1	Covered	T1,T2,T4

 LINE       1293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T84,T87
1	0	1	Covered	T1,T83,T84
1	1	0	Covered	T102,T131,T97
1	1	1	Covered	T1,T2,T4

 LINE       1294
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T84,T87
1	0	1	Covered	T1,T84,T87
1	1	0	Covered	T115,T97
1	1	1	Covered	T1,T2,T4