Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	64699598	14843	0	0
claim_transition_if_regwen_rd_A	64699598	1128	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64699598	14843	0	0
T83	3300	10	0	0
T84	2613	216	0	0
T91	4591	853	0	0
T96	2634	66	0	0
T102	5901	7	0	0
T113	3157	512	0	0
T117	5900	344	0	0
T118	10216	663	0	0
T123	8882	721	0	0
T138	0	43	0	0
T147	1384	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64699598	1128	0	0
T87	3104	140	0	0
T98	1568	2	0	0
T103	11029	77	0	0
T118	10216	0	0	0
T123	8882	0	0	0
T138	3662	2	0	0
T139	8483	0	0	0
T140	3962	12	0	0
T144	0	4	0	0
T147	1384	0	0	0
T148	0	12	0	0
T149	0	4	0	0
T150	0	4	0	0
T151	0	10	0	0
T152	1120	0	0	0