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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.38 97.29 95.97 91.98 100.00 96.13 98.48 94.82


Total test records in report: 984
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T759 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2496793735 Jan 07 01:03:03 PM PST 24 Jan 07 01:03:42 PM PST 24 3990589175 ps
T760 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1025417159 Jan 07 01:02:53 PM PST 24 Jan 07 01:03:33 PM PST 24 560150568 ps
T761 /workspace/coverage/default/35.lc_ctrl_state_post_trans.366653461 Jan 07 01:03:33 PM PST 24 Jan 07 01:03:52 PM PST 24 162749042 ps
T762 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1287117485 Jan 07 01:01:46 PM PST 24 Jan 07 01:02:16 PM PST 24 768265451 ps
T763 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4275446919 Jan 07 01:01:54 PM PST 24 Jan 07 01:02:13 PM PST 24 13233959 ps
T764 /workspace/coverage/default/34.lc_ctrl_sec_mubi.134914508 Jan 07 01:03:17 PM PST 24 Jan 07 01:03:52 PM PST 24 886045726 ps
T765 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1594134564 Jan 07 01:02:11 PM PST 24 Jan 07 01:02:25 PM PST 24 219726775 ps
T766 /workspace/coverage/default/45.lc_ctrl_alert_test.2638971347 Jan 07 01:04:33 PM PST 24 Jan 07 01:04:38 PM PST 24 29084141 ps
T767 /workspace/coverage/default/24.lc_ctrl_jtag_access.648643625 Jan 07 01:03:13 PM PST 24 Jan 07 01:03:37 PM PST 24 294350630 ps
T768 /workspace/coverage/default/49.lc_ctrl_alert_test.1502271474 Jan 07 01:04:18 PM PST 24 Jan 07 01:04:23 PM PST 24 158503486 ps
T769 /workspace/coverage/default/1.lc_ctrl_alert_test.396074925 Jan 07 01:01:39 PM PST 24 Jan 07 01:02:05 PM PST 24 21514690 ps
T770 /workspace/coverage/default/49.lc_ctrl_errors.841263876 Jan 07 01:04:19 PM PST 24 Jan 07 01:04:34 PM PST 24 1373367043 ps
T771 /workspace/coverage/default/37.lc_ctrl_errors.1109487980 Jan 07 01:03:52 PM PST 24 Jan 07 01:04:07 PM PST 24 363262016 ps
T772 /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2559607181 Jan 07 01:01:57 PM PST 24 Jan 07 01:02:15 PM PST 24 21755410 ps
T773 /workspace/coverage/default/17.lc_ctrl_smoke.1125157621 Jan 07 01:03:03 PM PST 24 Jan 07 01:03:30 PM PST 24 24987160 ps
T774 /workspace/coverage/default/42.lc_ctrl_errors.4185241956 Jan 07 01:04:14 PM PST 24 Jan 07 01:04:29 PM PST 24 437333182 ps
T775 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3697328148 Jan 07 01:01:54 PM PST 24 Jan 07 01:02:34 PM PST 24 3837890277 ps
T776 /workspace/coverage/default/17.lc_ctrl_stress_all.597242874 Jan 07 01:03:17 PM PST 24 Jan 07 01:05:18 PM PST 24 4105698353 ps
T777 /workspace/coverage/default/14.lc_ctrl_sec_mubi.353958869 Jan 07 01:02:51 PM PST 24 Jan 07 01:03:38 PM PST 24 286450371 ps
T778 /workspace/coverage/default/26.lc_ctrl_state_post_trans.1575927209 Jan 07 01:03:15 PM PST 24 Jan 07 01:03:42 PM PST 24 127404400 ps
T779 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2609884021 Jan 07 01:03:15 PM PST 24 Jan 07 01:03:37 PM PST 24 33901226 ps
T780 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3327863522 Jan 07 01:03:17 PM PST 24 Jan 07 01:04:18 PM PST 24 24154950228 ps
T781 /workspace/coverage/default/7.lc_ctrl_errors.1477585111 Jan 07 01:01:57 PM PST 24 Jan 07 01:02:23 PM PST 24 993971336 ps
T782 /workspace/coverage/default/25.lc_ctrl_state_post_trans.3966443943 Jan 07 01:03:15 PM PST 24 Jan 07 01:03:43 PM PST 24 210825532 ps
T783 /workspace/coverage/default/5.lc_ctrl_security_escalation.1726121497 Jan 07 01:01:51 PM PST 24 Jan 07 01:02:22 PM PST 24 338984572 ps
T784 /workspace/coverage/default/29.lc_ctrl_stress_all.3379314930 Jan 07 01:03:33 PM PST 24 Jan 07 01:04:36 PM PST 24 9645974798 ps
T785 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2376034856 Jan 07 01:02:14 PM PST 24 Jan 07 01:02:27 PM PST 24 1286360678 ps
T786 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2661657943 Jan 07 01:02:11 PM PST 24 Jan 07 01:02:58 PM PST 24 4438812317 ps
T787 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2775551615 Jan 07 01:03:42 PM PST 24 Jan 07 01:04:00 PM PST 24 499130085 ps
T788 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3749778292 Jan 07 01:01:47 PM PST 24 Jan 07 01:02:31 PM PST 24 2956992618 ps
T789 /workspace/coverage/default/23.lc_ctrl_sec_mubi.375582123 Jan 07 01:03:13 PM PST 24 Jan 07 01:03:45 PM PST 24 319960638 ps
T790 /workspace/coverage/default/32.lc_ctrl_errors.224684423 Jan 07 01:03:34 PM PST 24 Jan 07 01:04:00 PM PST 24 1820266562 ps
T791 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1793572218 Jan 07 01:03:07 PM PST 24 Jan 07 01:03:36 PM PST 24 1032909986 ps
T792 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3054208056 Jan 07 01:01:29 PM PST 24 Jan 07 01:01:58 PM PST 24 11784970 ps
T793 /workspace/coverage/default/37.lc_ctrl_smoke.2493366748 Jan 07 01:03:39 PM PST 24 Jan 07 01:03:50 PM PST 24 39245387 ps
T794 /workspace/coverage/default/35.lc_ctrl_sec_mubi.2764213442 Jan 07 01:03:30 PM PST 24 Jan 07 01:04:01 PM PST 24 317175565 ps
T795 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3775399765 Jan 07 01:01:48 PM PST 24 Jan 07 01:02:11 PM PST 24 38371749 ps
T796 /workspace/coverage/default/9.lc_ctrl_jtag_errors.2566576232 Jan 07 01:02:14 PM PST 24 Jan 07 01:02:48 PM PST 24 1640863138 ps
T797 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1802380924 Jan 07 01:01:54 PM PST 24 Jan 07 01:02:24 PM PST 24 343878065 ps
T798 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2162266468 Jan 07 01:02:15 PM PST 24 Jan 07 01:02:25 PM PST 24 442515995 ps
T799 /workspace/coverage/default/46.lc_ctrl_alert_test.3163039425 Jan 07 01:03:40 PM PST 24 Jan 07 01:03:50 PM PST 24 69966241 ps
T800 /workspace/coverage/default/36.lc_ctrl_prog_failure.963256231 Jan 07 01:03:47 PM PST 24 Jan 07 01:03:56 PM PST 24 136784565 ps
T801 /workspace/coverage/default/2.lc_ctrl_jtag_priority.3575195129 Jan 07 01:01:44 PM PST 24 Jan 07 01:02:12 PM PST 24 267419447 ps
T802 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3267190710 Jan 07 01:01:44 PM PST 24 Jan 07 01:02:28 PM PST 24 3974200167 ps
T803 /workspace/coverage/default/41.lc_ctrl_jtag_access.2451912195 Jan 07 01:04:02 PM PST 24 Jan 07 01:04:10 PM PST 24 999024780 ps
T804 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1690553687 Jan 07 01:03:34 PM PST 24 Jan 07 01:03:46 PM PST 24 33810396 ps
T805 /workspace/coverage/default/48.lc_ctrl_smoke.3265410054 Jan 07 01:03:57 PM PST 24 Jan 07 01:04:11 PM PST 24 770937977 ps
T806 /workspace/coverage/default/42.lc_ctrl_alert_test.1843147895 Jan 07 01:04:27 PM PST 24 Jan 07 01:04:31 PM PST 24 30984970 ps
T807 /workspace/coverage/default/42.lc_ctrl_state_failure.1290994920 Jan 07 01:04:10 PM PST 24 Jan 07 01:04:36 PM PST 24 199099675 ps
T808 /workspace/coverage/default/11.lc_ctrl_alert_test.2017879839 Jan 07 01:02:13 PM PST 24 Jan 07 01:02:20 PM PST 24 109190939 ps
T809 /workspace/coverage/default/34.lc_ctrl_stress_all.3834300535 Jan 07 01:03:23 PM PST 24 Jan 07 01:04:46 PM PST 24 3236319490 ps
T810 /workspace/coverage/default/19.lc_ctrl_security_escalation.3426389354 Jan 07 01:03:20 PM PST 24 Jan 07 01:03:57 PM PST 24 6505981335 ps
T811 /workspace/coverage/default/12.lc_ctrl_alert_test.1323994318 Jan 07 01:02:13 PM PST 24 Jan 07 01:02:19 PM PST 24 30220412 ps
T812 /workspace/coverage/default/24.lc_ctrl_security_escalation.12847325 Jan 07 01:03:11 PM PST 24 Jan 07 01:03:42 PM PST 24 351154583 ps
T80 /workspace/coverage/default/20.lc_ctrl_stress_all.3115879062 Jan 07 01:03:14 PM PST 24 Jan 07 01:05:32 PM PST 24 12183212890 ps
T813 /workspace/coverage/default/31.lc_ctrl_smoke.4036332799 Jan 07 01:03:29 PM PST 24 Jan 07 01:03:44 PM PST 24 42937091 ps
T814 /workspace/coverage/default/23.lc_ctrl_state_failure.2997706998 Jan 07 01:02:52 PM PST 24 Jan 07 01:03:54 PM PST 24 3289237507 ps
T815 /workspace/coverage/default/24.lc_ctrl_sec_mubi.341663245 Jan 07 01:03:14 PM PST 24 Jan 07 01:03:51 PM PST 24 1206092078 ps
T816 /workspace/coverage/default/41.lc_ctrl_state_post_trans.2204475567 Jan 07 01:04:11 PM PST 24 Jan 07 01:04:20 PM PST 24 74126355 ps
T817 /workspace/coverage/default/12.lc_ctrl_sec_mubi.2070571668 Jan 07 01:02:14 PM PST 24 Jan 07 01:02:33 PM PST 24 1855007213 ps
T818 /workspace/coverage/default/40.lc_ctrl_smoke.3374380080 Jan 07 01:03:44 PM PST 24 Jan 07 01:03:53 PM PST 24 37878571 ps
T819 /workspace/coverage/default/48.lc_ctrl_sec_mubi.774236397 Jan 07 01:03:53 PM PST 24 Jan 07 01:04:08 PM PST 24 1364553692 ps
T820 /workspace/coverage/default/39.lc_ctrl_security_escalation.608858720 Jan 07 01:03:40 PM PST 24 Jan 07 01:04:00 PM PST 24 409665814 ps
T821 /workspace/coverage/default/28.lc_ctrl_state_post_trans.2772422856 Jan 07 01:03:19 PM PST 24 Jan 07 01:03:49 PM PST 24 89528138 ps
T822 /workspace/coverage/default/32.lc_ctrl_state_post_trans.724892245 Jan 07 01:03:29 PM PST 24 Jan 07 01:03:47 PM PST 24 698606948 ps
T823 /workspace/coverage/default/5.lc_ctrl_errors.4109564373 Jan 07 01:01:52 PM PST 24 Jan 07 01:02:25 PM PST 24 697839372 ps
T824 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.337903774 Jan 07 01:02:55 PM PST 24 Jan 07 01:03:59 PM PST 24 2925866357 ps
T825 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2150751753 Jan 07 01:02:51 PM PST 24 Jan 07 01:04:05 PM PST 24 5449331799 ps
T826 /workspace/coverage/default/35.lc_ctrl_prog_failure.3132039508 Jan 07 01:03:18 PM PST 24 Jan 07 01:03:41 PM PST 24 316593041 ps
T153 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2057881166 Jan 07 01:03:17 PM PST 24 Jan 07 01:17:30 PM PST 24 81290376228 ps
T827 /workspace/coverage/default/9.lc_ctrl_alert_test.2525368470 Jan 07 01:02:13 PM PST 24 Jan 07 01:02:19 PM PST 24 116089691 ps
T828 /workspace/coverage/default/43.lc_ctrl_errors.618647771 Jan 07 01:03:39 PM PST 24 Jan 07 01:04:02 PM PST 24 1644457825 ps
T829 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3875670611 Jan 07 01:01:35 PM PST 24 Jan 07 01:02:44 PM PST 24 5706637631 ps
T830 /workspace/coverage/default/16.lc_ctrl_state_post_trans.35229639 Jan 07 01:03:03 PM PST 24 Jan 07 01:03:35 PM PST 24 72530458 ps
T831 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2381482979 Jan 07 01:01:39 PM PST 24 Jan 07 01:02:07 PM PST 24 118532870 ps
T832 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1262891484 Jan 07 01:01:43 PM PST 24 Jan 07 01:02:28 PM PST 24 565914586 ps
T833 /workspace/coverage/default/11.lc_ctrl_stress_all.995200053 Jan 07 01:02:14 PM PST 24 Jan 07 01:04:10 PM PST 24 9177437913 ps
T834 /workspace/coverage/default/17.lc_ctrl_jtag_errors.767486136 Jan 07 01:03:16 PM PST 24 Jan 07 01:04:10 PM PST 24 8489726821 ps
T835 /workspace/coverage/default/30.lc_ctrl_smoke.2101345269 Jan 07 01:03:32 PM PST 24 Jan 07 01:03:46 PM PST 24 588656044 ps
T836 /workspace/coverage/default/44.lc_ctrl_smoke.3636145013 Jan 07 01:03:49 PM PST 24 Jan 07 01:03:56 PM PST 24 45560955 ps
T837 /workspace/coverage/default/29.lc_ctrl_prog_failure.740436889 Jan 07 01:03:35 PM PST 24 Jan 07 01:03:49 PM PST 24 88863322 ps
T838 /workspace/coverage/default/17.lc_ctrl_sec_mubi.1933724544 Jan 07 01:03:16 PM PST 24 Jan 07 01:03:52 PM PST 24 376998720 ps
T839 /workspace/coverage/default/46.lc_ctrl_prog_failure.193679425 Jan 07 01:04:23 PM PST 24 Jan 07 01:04:29 PM PST 24 91181451 ps
T840 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2225934911 Jan 07 01:03:23 PM PST 24 Jan 07 01:03:53 PM PST 24 307423222 ps
T841 /workspace/coverage/default/6.lc_ctrl_jtag_access.4035702107 Jan 07 01:01:54 PM PST 24 Jan 07 01:02:16 PM PST 24 1315431519 ps
T842 /workspace/coverage/default/23.lc_ctrl_alert_test.2077595579 Jan 07 01:03:16 PM PST 24 Jan 07 01:03:38 PM PST 24 38791574 ps
T843 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.300129606 Jan 07 01:01:41 PM PST 24 Jan 07 01:02:19 PM PST 24 655317571 ps
T111 /workspace/coverage/default/6.lc_ctrl_stress_all.782398849 Jan 07 01:01:55 PM PST 24 Jan 07 01:05:55 PM PST 24 35308530024 ps
T844 /workspace/coverage/default/46.lc_ctrl_jtag_access.342328671 Jan 07 01:04:30 PM PST 24 Jan 07 01:04:35 PM PST 24 228315608 ps
T845 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2565538335 Jan 07 01:01:48 PM PST 24 Jan 07 01:02:11 PM PST 24 41116270 ps
T846 /workspace/coverage/default/27.lc_ctrl_errors.4278223506 Jan 07 01:03:18 PM PST 24 Jan 07 01:03:49 PM PST 24 1151454270 ps
T847 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.587799272 Jan 07 01:03:37 PM PST 24 Jan 07 01:03:54 PM PST 24 827294637 ps
T848 /workspace/coverage/default/10.lc_ctrl_security_escalation.1270349730 Jan 07 01:02:10 PM PST 24 Jan 07 01:02:24 PM PST 24 508548999 ps
T849 /workspace/coverage/default/26.lc_ctrl_security_escalation.640082662 Jan 07 01:03:11 PM PST 24 Jan 07 01:03:43 PM PST 24 1784112512 ps
T850 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.378290179 Jan 07 01:01:54 PM PST 24 Jan 07 01:02:20 PM PST 24 570137221 ps
T851 /workspace/coverage/default/30.lc_ctrl_prog_failure.2912383757 Jan 07 01:03:17 PM PST 24 Jan 07 01:03:40 PM PST 24 77208354 ps
T852 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3076037979 Jan 07 01:03:13 PM PST 24 Jan 07 01:03:47 PM PST 24 2299960302 ps
T853 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2188908689 Jan 07 01:02:11 PM PST 24 Jan 07 01:02:18 PM PST 24 23909140 ps
T854 /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2884996944 Jan 07 01:02:10 PM PST 24 Jan 07 01:02:56 PM PST 24 9842531445 ps
T855 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3876570693 Jan 07 01:03:47 PM PST 24 Jan 07 01:04:02 PM PST 24 463336320 ps
T856 /workspace/coverage/default/41.lc_ctrl_smoke.941583959 Jan 07 01:04:00 PM PST 24 Jan 07 01:04:06 PM PST 24 16388011 ps
T857 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3714480116 Jan 07 01:02:14 PM PST 24 Jan 07 01:02:35 PM PST 24 393843793 ps
T858 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1781380133 Jan 07 01:02:13 PM PST 24 Jan 07 01:02:31 PM PST 24 323250547 ps
T859 /workspace/coverage/default/37.lc_ctrl_prog_failure.2057653365 Jan 07 01:03:36 PM PST 24 Jan 07 01:03:48 PM PST 24 26591966 ps
T860 /workspace/coverage/default/6.lc_ctrl_errors.2526855477 Jan 07 01:01:57 PM PST 24 Jan 07 01:02:26 PM PST 24 568924391 ps
T861 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.946142355 Jan 07 01:01:36 PM PST 24 Jan 07 01:02:02 PM PST 24 12505003 ps
T862 /workspace/coverage/default/39.lc_ctrl_prog_failure.1562367704 Jan 07 01:03:36 PM PST 24 Jan 07 01:03:50 PM PST 24 58104924 ps
T863 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1971134842 Jan 07 01:03:17 PM PST 24 Jan 07 01:03:38 PM PST 24 41070643 ps
T864 /workspace/coverage/default/47.lc_ctrl_jtag_access.2664340214 Jan 07 01:03:46 PM PST 24 Jan 07 01:03:53 PM PST 24 297791583 ps
T865 /workspace/coverage/default/0.lc_ctrl_alert_test.968989633 Jan 07 01:01:29 PM PST 24 Jan 07 01:01:59 PM PST 24 101146780 ps
T866 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1597217943 Jan 07 01:01:48 PM PST 24 Jan 07 01:02:19 PM PST 24 1978570532 ps
T867 /workspace/coverage/default/34.lc_ctrl_state_post_trans.2458462448 Jan 07 01:03:20 PM PST 24 Jan 07 01:03:43 PM PST 24 79294264 ps
T868 /workspace/coverage/default/46.lc_ctrl_sec_mubi.3552759193 Jan 07 01:04:40 PM PST 24 Jan 07 01:04:51 PM PST 24 189309030 ps
T869 /workspace/coverage/default/4.lc_ctrl_sec_mubi.1602408864 Jan 07 01:01:54 PM PST 24 Jan 07 01:02:29 PM PST 24 419978888 ps
T870 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3201021539 Jan 07 01:03:07 PM PST 24 Jan 07 01:03:33 PM PST 24 103240209 ps
T104 /workspace/coverage/default/0.lc_ctrl_sec_cm.540727012 Jan 07 01:01:44 PM PST 24 Jan 07 01:02:36 PM PST 24 297596544 ps
T81 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1307792538 Jan 07 01:04:34 PM PST 24 Jan 07 01:04:39 PM PST 24 26131295 ps
T871 /workspace/coverage/default/27.lc_ctrl_jtag_access.2135241528 Jan 07 01:03:16 PM PST 24 Jan 07 01:03:42 PM PST 24 441027167 ps
T872 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2567822797 Jan 07 01:03:35 PM PST 24 Jan 07 01:03:47 PM PST 24 12348273 ps
T873 /workspace/coverage/default/2.lc_ctrl_errors.1441001428 Jan 07 01:01:37 PM PST 24 Jan 07 01:02:14 PM PST 24 1308037168 ps
T874 /workspace/coverage/default/25.lc_ctrl_errors.1027435371 Jan 07 01:03:13 PM PST 24 Jan 07 01:03:47 PM PST 24 483480315 ps
T875 /workspace/coverage/default/44.lc_ctrl_prog_failure.793443514 Jan 07 01:03:48 PM PST 24 Jan 07 01:04:01 PM PST 24 181923216 ps
T876 /workspace/coverage/default/38.lc_ctrl_security_escalation.263485521 Jan 07 01:03:42 PM PST 24 Jan 07 01:03:58 PM PST 24 498857582 ps
T877 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1492571936 Jan 07 01:01:33 PM PST 24 Jan 07 01:02:06 PM PST 24 15264228 ps
T878 /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2629553068 Jan 07 01:02:10 PM PST 24 Jan 07 01:02:18 PM PST 24 13030241 ps
T879 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.458829336 Jan 07 01:03:04 PM PST 24 Jan 07 01:03:50 PM PST 24 865118202 ps
T880 /workspace/coverage/default/13.lc_ctrl_prog_failure.2433979590 Jan 07 01:02:21 PM PST 24 Jan 07 01:02:25 PM PST 24 49032732 ps
T881 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4139806497 Jan 07 01:01:26 PM PST 24 Jan 07 01:02:10 PM PST 24 345486414 ps
T882 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2746771528 Jan 07 01:01:43 PM PST 24 Jan 07 01:02:25 PM PST 24 285411213 ps
T883 /workspace/coverage/default/22.lc_ctrl_sec_mubi.1728055550 Jan 07 01:03:34 PM PST 24 Jan 07 01:04:00 PM PST 24 284216170 ps
T884 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.532356812 Jan 07 01:04:06 PM PST 24 Jan 07 01:04:19 PM PST 24 1002392329 ps
T885 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2471390907 Jan 07 01:03:31 PM PST 24 Jan 07 01:03:46 PM PST 24 13370046 ps
T886 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2208971211 Jan 07 01:04:16 PM PST 24 Jan 07 01:04:20 PM PST 24 15677461 ps
T887 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2351573327 Jan 07 01:02:11 PM PST 24 Jan 07 01:02:20 PM PST 24 728959878 ps
T888 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.620970528 Jan 07 01:03:38 PM PST 24 Jan 07 01:03:49 PM PST 24 195519579 ps
T889 /workspace/coverage/default/13.lc_ctrl_security_escalation.2671051949 Jan 07 01:02:14 PM PST 24 Jan 07 01:02:33 PM PST 24 1606328321 ps
T890 /workspace/coverage/default/47.lc_ctrl_sec_mubi.3313463308 Jan 07 01:03:49 PM PST 24 Jan 07 01:04:07 PM PST 24 293408715 ps
T891 /workspace/coverage/default/31.lc_ctrl_state_failure.3261947937 Jan 07 01:03:24 PM PST 24 Jan 07 01:04:02 PM PST 24 272423068 ps
T892 /workspace/coverage/default/6.lc_ctrl_prog_failure.1361367515 Jan 07 01:01:52 PM PST 24 Jan 07 01:02:13 PM PST 24 93858271 ps
T893 /workspace/coverage/default/27.lc_ctrl_security_escalation.3990834923 Jan 07 01:03:18 PM PST 24 Jan 07 01:03:44 PM PST 24 886864610 ps
T894 /workspace/coverage/default/21.lc_ctrl_sec_mubi.1206702346 Jan 07 01:03:27 PM PST 24 Jan 07 01:03:53 PM PST 24 374898986 ps
T895 /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1876997853 Jan 07 01:03:28 PM PST 24 Jan 07 01:03:50 PM PST 24 940295751 ps
T896 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1859803284 Jan 07 01:02:16 PM PST 24 Jan 07 01:02:29 PM PST 24 322479213 ps
T897 /workspace/coverage/default/22.lc_ctrl_state_post_trans.3247534651 Jan 07 01:03:19 PM PST 24 Jan 07 01:03:45 PM PST 24 160949238 ps
T898 /workspace/coverage/default/7.lc_ctrl_prog_failure.475317691 Jan 07 01:01:49 PM PST 24 Jan 07 01:02:12 PM PST 24 14675140 ps
T899 /workspace/coverage/default/27.lc_ctrl_alert_test.2068036238 Jan 07 01:03:23 PM PST 24 Jan 07 01:03:41 PM PST 24 17377642 ps
T900 /workspace/coverage/default/13.lc_ctrl_jtag_access.3554437501 Jan 07 01:02:14 PM PST 24 Jan 07 01:02:23 PM PST 24 1333483167 ps
T901 /workspace/coverage/default/22.lc_ctrl_smoke.549402519 Jan 07 01:03:20 PM PST 24 Jan 07 01:03:41 PM PST 24 44232972 ps
T902 /workspace/coverage/default/32.lc_ctrl_smoke.3086903403 Jan 07 01:03:32 PM PST 24 Jan 07 01:03:47 PM PST 24 137784947 ps
T903 /workspace/coverage/default/6.lc_ctrl_state_failure.3938956732 Jan 07 01:01:52 PM PST 24 Jan 07 01:02:36 PM PST 24 5204996908 ps
T904 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2653625910 Jan 07 01:03:03 PM PST 24 Jan 07 01:04:09 PM PST 24 990616053 ps
T39 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2739831165 Jan 07 01:04:08 PM PST 24 Jan 07 01:04:12 PM PST 24 52360698 ps
T905 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.877530044 Jan 07 01:03:47 PM PST 24 Jan 07 01:04:07 PM PST 24 5738265953 ps
T906 /workspace/coverage/default/40.lc_ctrl_sec_mubi.1180483006 Jan 07 01:03:41 PM PST 24 Jan 07 01:03:59 PM PST 24 1631976557 ps
T112 /workspace/coverage/default/18.lc_ctrl_stress_all.497144642 Jan 07 01:03:28 PM PST 24 Jan 07 01:05:25 PM PST 24 20091164541 ps
T907 /workspace/coverage/default/48.lc_ctrl_prog_failure.2593323594 Jan 07 01:03:53 PM PST 24 Jan 07 01:03:58 PM PST 24 19855434 ps
T908 /workspace/coverage/default/36.lc_ctrl_state_post_trans.2237388618 Jan 07 01:03:32 PM PST 24 Jan 07 01:03:52 PM PST 24 99128598 ps
T909 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3115105158 Jan 07 01:02:52 PM PST 24 Jan 07 01:03:37 PM PST 24 643806802 ps
T910 /workspace/coverage/default/19.lc_ctrl_stress_all.3798690689 Jan 07 01:03:04 PM PST 24 Jan 07 01:06:08 PM PST 24 36514106299 ps
T911 /workspace/coverage/default/25.lc_ctrl_prog_failure.95558388 Jan 07 01:03:16 PM PST 24 Jan 07 01:03:39 PM PST 24 88886682 ps
T912 /workspace/coverage/default/16.lc_ctrl_smoke.3245249160 Jan 07 01:02:53 PM PST 24 Jan 07 01:03:27 PM PST 24 60056047 ps
T913 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1656433310 Jan 07 01:01:43 PM PST 24 Jan 07 01:02:10 PM PST 24 298710585 ps
T914 /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3579847731 Jan 07 01:03:50 PM PST 24 Jan 07 01:04:03 PM PST 24 961031937 ps
T915 /workspace/coverage/default/1.lc_ctrl_jtag_access.681966247 Jan 07 01:01:06 PM PST 24 Jan 07 01:02:15 PM PST 24 2333485031 ps
T916 /workspace/coverage/default/37.lc_ctrl_jtag_access.1629448653 Jan 07 01:03:58 PM PST 24 Jan 07 01:04:16 PM PST 24 2460320192 ps
T917 /workspace/coverage/default/11.lc_ctrl_sec_mubi.4244923374 Jan 07 01:02:11 PM PST 24 Jan 07 01:02:48 PM PST 24 2150702791 ps
T918 /workspace/coverage/default/5.lc_ctrl_sec_mubi.3917977505 Jan 07 01:01:51 PM PST 24 Jan 07 01:02:20 PM PST 24 1369255366 ps
T919 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.521066914 Jan 07 01:04:25 PM PST 24 Jan 07 01:04:40 PM PST 24 478157283 ps
T920 /workspace/coverage/default/17.lc_ctrl_state_post_trans.1259599319 Jan 07 01:03:04 PM PST 24 Jan 07 01:03:39 PM PST 24 120465360 ps
T921 /workspace/coverage/default/41.lc_ctrl_security_escalation.2862263310 Jan 07 01:04:01 PM PST 24 Jan 07 01:04:16 PM PST 24 595375472 ps
T922 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.803867825 Jan 07 01:01:50 PM PST 24 Jan 07 01:02:56 PM PST 24 1437386594 ps
T923 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4102057188 Jan 07 01:03:17 PM PST 24 Jan 07 01:03:45 PM PST 24 374605284 ps
T924 /workspace/coverage/default/38.lc_ctrl_jtag_access.1617976199 Jan 07 01:03:36 PM PST 24 Jan 07 01:03:53 PM PST 24 442554759 ps
T925 /workspace/coverage/default/36.lc_ctrl_stress_all.3739733437 Jan 07 01:03:31 PM PST 24 Jan 07 01:04:20 PM PST 24 563254148 ps
T926 /workspace/coverage/default/40.lc_ctrl_state_post_trans.3288273780 Jan 07 01:03:58 PM PST 24 Jan 07 01:04:05 PM PST 24 88421915 ps
T927 /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2614757358 Jan 07 01:03:10 PM PST 24 Jan 07 01:03:38 PM PST 24 126590836 ps
T928 /workspace/coverage/default/0.lc_ctrl_jtag_errors.3245649196 Jan 07 01:01:42 PM PST 24 Jan 07 01:03:05 PM PST 24 4164546958 ps
T929 /workspace/coverage/default/4.lc_ctrl_smoke.1571069337 Jan 07 01:01:32 PM PST 24 Jan 07 01:01:59 PM PST 24 119852798 ps
T930 /workspace/coverage/default/15.lc_ctrl_stress_all.4128972398 Jan 07 01:03:07 PM PST 24 Jan 07 01:04:32 PM PST 24 1539653507 ps
T931 /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3185848395 Jan 07 01:01:50 PM PST 24 Jan 07 01:02:12 PM PST 24 18786023 ps
T932 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1374802783 Jan 07 01:01:55 PM PST 24 Jan 07 01:02:26 PM PST 24 1786785603 ps
T933 /workspace/coverage/default/47.lc_ctrl_errors.1769510580 Jan 07 01:03:54 PM PST 24 Jan 07 01:04:08 PM PST 24 276132378 ps
T934 /workspace/coverage/default/43.lc_ctrl_smoke.261766662 Jan 07 01:04:23 PM PST 24 Jan 07 01:04:28 PM PST 24 19724658 ps
T935 /workspace/coverage/default/32.lc_ctrl_state_failure.2602109286 Jan 07 01:03:37 PM PST 24 Jan 07 01:04:20 PM PST 24 3035016771 ps
T936 /workspace/coverage/default/32.lc_ctrl_alert_test.994834874 Jan 07 01:03:32 PM PST 24 Jan 07 01:03:43 PM PST 24 50352163 ps
T937 /workspace/coverage/default/38.lc_ctrl_stress_all.2492986008 Jan 07 01:03:36 PM PST 24 Jan 07 01:05:14 PM PST 24 10898313419 ps
T938 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.76669362 Jan 07 01:01:23 PM PST 24 Jan 07 01:02:01 PM PST 24 1530739893 ps
T939 /workspace/coverage/default/36.lc_ctrl_smoke.1485322920 Jan 07 01:03:37 PM PST 24 Jan 07 01:03:50 PM PST 24 216393406 ps
T940 /workspace/coverage/default/23.lc_ctrl_prog_failure.3252267254 Jan 07 01:03:13 PM PST 24 Jan 07 01:03:38 PM PST 24 126880605 ps
T52 /workspace/coverage/default/1.lc_ctrl_sec_cm.3769689184 Jan 07 01:01:25 PM PST 24 Jan 07 01:02:30 PM PST 24 776305532 ps
T941 /workspace/coverage/default/2.lc_ctrl_smoke.134348777 Jan 07 01:01:40 PM PST 24 Jan 07 01:02:06 PM PST 24 28464777 ps
T942 /workspace/coverage/default/47.lc_ctrl_security_escalation.1738848581 Jan 07 01:03:40 PM PST 24 Jan 07 01:03:59 PM PST 24 799868013 ps
T943 /workspace/coverage/default/33.lc_ctrl_errors.438800448 Jan 07 01:03:34 PM PST 24 Jan 07 01:04:02 PM PST 24 541957988 ps
T944 /workspace/coverage/default/15.lc_ctrl_errors.3263105142 Jan 07 01:02:56 PM PST 24 Jan 07 01:03:42 PM PST 24 2184072725 ps
T945 /workspace/coverage/default/7.lc_ctrl_alert_test.3118991192 Jan 07 01:01:51 PM PST 24 Jan 07 01:02:12 PM PST 24 17338414 ps
T946 /workspace/coverage/default/26.lc_ctrl_sec_mubi.1195676629 Jan 07 01:03:16 PM PST 24 Jan 07 01:03:50 PM PST 24 1788778279 ps
T947 /workspace/coverage/default/6.lc_ctrl_security_escalation.2209036783 Jan 07 01:01:55 PM PST 24 Jan 07 01:02:22 PM PST 24 244631308 ps
T948 /workspace/coverage/default/1.lc_ctrl_errors.718824351 Jan 07 01:01:28 PM PST 24 Jan 07 01:02:05 PM PST 24 2168701361 ps
T949 /workspace/coverage/default/21.lc_ctrl_state_post_trans.1963490408 Jan 07 01:03:17 PM PST 24 Jan 07 01:03:43 PM PST 24 74544352 ps
T950 /workspace/coverage/default/17.lc_ctrl_jtag_access.3135155534 Jan 07 01:03:04 PM PST 24 Jan 07 01:03:37 PM PST 24 2892515376 ps
T951 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1541763850 Jan 07 01:03:20 PM PST 24 Jan 07 01:03:49 PM PST 24 350103310 ps
T952 /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1483754058 Jan 07 01:02:10 PM PST 24 Jan 07 01:02:33 PM PST 24 1277376558 ps
T953 /workspace/coverage/default/14.lc_ctrl_jtag_access.613716012 Jan 07 01:02:54 PM PST 24 Jan 07 01:03:35 PM PST 24 382335288 ps
T954 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3198980016 Jan 07 01:03:39 PM PST 24 Jan 07 01:03:58 PM PST 24 1425071386 ps
T955 /workspace/coverage/default/44.lc_ctrl_stress_all.2878376052 Jan 07 01:04:15 PM PST 24 Jan 07 01:05:42 PM PST 24 10660568649 ps
T956 /workspace/coverage/default/4.lc_ctrl_prog_failure.3008104879 Jan 07 01:01:55 PM PST 24 Jan 07 01:02:16 PM PST 24 72812839 ps
T957 /workspace/coverage/default/9.lc_ctrl_state_failure.3475454507 Jan 07 01:02:13 PM PST 24 Jan 07 01:02:56 PM PST 24 1445603146 ps
T958 /workspace/coverage/default/47.lc_ctrl_state_post_trans.1413538788 Jan 07 01:03:48 PM PST 24 Jan 07 01:04:00 PM PST 24 229943024 ps
T959 /workspace/coverage/default/7.lc_ctrl_jtag_errors.4130034041 Jan 07 01:01:51 PM PST 24 Jan 07 01:02:53 PM PST 24 6680560791 ps
T960 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2945678271 Jan 07 01:03:09 PM PST 24 Jan 07 01:04:46 PM PST 24 18352837182 ps
T961 /workspace/coverage/default/42.lc_ctrl_smoke.1074514227 Jan 07 01:04:19 PM PST 24 Jan 07 01:04:23 PM PST 24 51513422 ps
T962 /workspace/coverage/default/34.lc_ctrl_alert_test.3316719270 Jan 07 01:03:25 PM PST 24 Jan 07 01:03:41 PM PST 24 23419043 ps
T963 /workspace/coverage/default/48.lc_ctrl_stress_all.2295165674 Jan 07 01:04:07 PM PST 24 Jan 07 01:06:30 PM PST 24 65430010092 ps
T964 /workspace/coverage/default/9.lc_ctrl_prog_failure.2993206874 Jan 07 01:02:14 PM PST 24 Jan 07 01:02:22 PM PST 24 65125127 ps
T965 /workspace/coverage/default/43.lc_ctrl_prog_failure.685005913 Jan 07 01:03:40 PM PST 24 Jan 07 01:03:52 PM PST 24 189929933 ps
T966 /workspace/coverage/default/5.lc_ctrl_jtag_priority.3284239630 Jan 07 01:01:54 PM PST 24 Jan 07 01:02:18 PM PST 24 703717120 ps
T967 /workspace/coverage/default/2.lc_ctrl_jtag_access.1845373342 Jan 07 01:01:54 PM PST 24 Jan 07 01:02:28 PM PST 24 2548134687 ps
T968 /workspace/coverage/default/49.lc_ctrl_state_failure.1159885312 Jan 07 01:04:11 PM PST 24 Jan 07 01:04:38 PM PST 24 548607596 ps
T969 /workspace/coverage/default/48.lc_ctrl_alert_test.1672961605 Jan 07 01:03:53 PM PST 24 Jan 07 01:03:58 PM PST 24 77682408 ps
T970 /workspace/coverage/default/27.lc_ctrl_state_post_trans.826422093 Jan 07 01:03:18 PM PST 24 Jan 07 01:03:43 PM PST 24 112489609 ps
T971 /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1337090687 Jan 07 01:04:13 PM PST 24 Jan 07 01:04:27 PM PST 24 441216742 ps
T972 /workspace/coverage/default/19.lc_ctrl_smoke.1706810333 Jan 07 01:03:34 PM PST 24 Jan 07 01:03:47 PM PST 24 50767528 ps
T973 /workspace/coverage/default/35.lc_ctrl_security_escalation.3750009417 Jan 07 01:03:19 PM PST 24 Jan 07 01:03:47 PM PST 24 370379300 ps
T974 /workspace/coverage/default/16.lc_ctrl_jtag_access.843679601 Jan 07 01:03:03 PM PST 24 Jan 07 01:03:32 PM PST 24 145648937 ps
T975 /workspace/coverage/default/36.lc_ctrl_security_escalation.2095111371 Jan 07 01:03:41 PM PST 24 Jan 07 01:03:57 PM PST 24 965217838 ps
T976 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3041825783 Jan 07 01:03:13 PM PST 24 Jan 07 01:03:46 PM PST 24 1963927096 ps
T977 /workspace/coverage/default/29.lc_ctrl_smoke.3390449834 Jan 07 01:03:27 PM PST 24 Jan 07 01:03:42 PM PST 24 38874166 ps
T978 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.497016684 Jan 07 01:02:17 PM PST 24 Jan 07 01:02:28 PM PST 24 382742052 ps
T979 /workspace/coverage/default/43.lc_ctrl_jtag_access.3074031071 Jan 07 01:03:37 PM PST 24 Jan 07 01:03:52 PM PST 24 319370702 ps
T980 /workspace/coverage/default/20.lc_ctrl_state_failure.3128365529 Jan 07 01:03:06 PM PST 24 Jan 07 01:03:55 PM PST 24 2497000426 ps
T981 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3734788193 Jan 07 01:02:10 PM PST 24 Jan 07 01:02:27 PM PST 24 1472410421 ps
T982 /workspace/coverage/default/14.lc_ctrl_stress_all.1145948738 Jan 07 01:02:55 PM PST 24 Jan 07 01:06:33 PM PST 24 10719242475 ps
T983 /workspace/coverage/default/4.lc_ctrl_jtag_errors.3694224493 Jan 07 01:01:46 PM PST 24 Jan 07 01:02:46 PM PST 24 22486281999 ps
T984 /workspace/coverage/default/30.lc_ctrl_stress_all.1091304957 Jan 07 01:03:17 PM PST 24 Jan 07 01:05:59 PM PST 24 9596791121 ps

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.859342204
Short name T1
Test name
Test status
Simulation time 377718998 ps
CPU time 16.05 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:33 PM PST 24
Peak memory 218264 kb
Host smart-59ee0985-5645-4acb-baf0-09a38e0bddea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859342204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.859342204
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3269633429
Short name T14
Test name
Test status
Simulation time 14740436261 ps
CPU time 95.78 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:05:19 PM PST 24
Peak memory 268140 kb
Host smart-41452446-1408-4a13-bda1-d35fa51c1077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269633429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3269633429
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3951759568
Short name T85
Test name
Test status
Simulation time 91707529 ps
CPU time 1.63 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 210496 kb
Host smart-b3593667-af06-40a4-8cb2-f23229b3b844
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951759568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3951759568
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3891499705
Short name T12
Test name
Test status
Simulation time 363913543 ps
CPU time 10 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 218244 kb
Host smart-e64dab35-0de0-4c27-a995-ec11e0c89abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891499705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3891499705
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1071402175
Short name T91
Test name
Test status
Simulation time 93717948 ps
CPU time 2.98 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:10 PM PST 24
Peak memory 217940 kb
Host smart-c292a1aa-4453-485c-af72-3d71ec2ce7bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071402175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1071402175
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3051727070
Short name T55
Test name
Test status
Simulation time 16957774534 ps
CPU time 349.94 seconds
Started Jan 07 01:04:14 PM PST 24
Finished Jan 07 01:10:07 PM PST 24
Peak memory 284084 kb
Host smart-de2f7512-412f-42a4-9bd7-78828eef714c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3051727070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3051727070
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.855554376
Short name T28
Test name
Test status
Simulation time 119186117 ps
CPU time 0.74 seconds
Started Jan 07 01:03:11 PM PST 24
Finished Jan 07 01:03:35 PM PST 24
Peak memory 208404 kb
Host smart-ba0748dd-3656-4925-87c3-1f82b96288e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855554376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.855554376
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1284178387
Short name T102
Test name
Test status
Simulation time 59043123 ps
CPU time 2.2 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 221140 kb
Host smart-0a9354ed-6dfc-4f84-820e-cdc769317533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284178387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1284178387
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1995486013
Short name T51
Test name
Test status
Simulation time 162078620 ps
CPU time 21.9 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:35 PM PST 24
Peak memory 280640 kb
Host smart-0937e11d-2132-454e-a719-d3464d754c7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995486013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1995486013
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2670337109
Short name T101
Test name
Test status
Simulation time 27137647682 ps
CPU time 729.94 seconds
Started Jan 07 01:01:58 PM PST 24
Finished Jan 07 01:14:24 PM PST 24
Peak memory 274396 kb
Host smart-54567302-c42d-43b1-bf7f-b3e656dec537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2670337109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2670337109
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3954331111
Short name T180
Test name
Test status
Simulation time 1689525402 ps
CPU time 13.65 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:32 PM PST 24
Peak memory 218180 kb
Host smart-acd82bab-dfe1-4738-a17b-1aee735e3e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954331111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3954331111
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.543403712
Short name T98
Test name
Test status
Simulation time 65379955 ps
CPU time 1.12 seconds
Started Jan 07 01:17:23 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 211376 kb
Host smart-3d3bb3e5-6ea3-45c6-a734-90b447622c5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543403712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.543403712
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3962386694
Short name T4
Test name
Test status
Simulation time 1236650070 ps
CPU time 11.3 seconds
Started Jan 07 01:03:45 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 218052 kb
Host smart-d76e5431-23be-4911-b99d-85e102ddc5be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962386694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3962386694
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2057881166
Short name T153
Test name
Test status
Simulation time 81290376228 ps
CPU time 832.51 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:17:30 PM PST 24
Peak memory 464392 kb
Host smart-3e2b4389-cf45-4775-a105-bdb0f55a164f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2057881166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2057881166
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.809164036
Short name T158
Test name
Test status
Simulation time 38306649 ps
CPU time 1.82 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:55 PM PST 24
Peak memory 211460 kb
Host smart-09d1c90d-4ff0-4bfe-9c15-b6409099a58d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809164036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.809164036
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2620581676
Short name T3
Test name
Test status
Simulation time 3372943318 ps
CPU time 3.93 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 209792 kb
Host smart-e4fcc246-20b4-4419-adaa-edbfde46ecb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620581676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.2620581676
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1194894341
Short name T46
Test name
Test status
Simulation time 454614544475 ps
CPU time 3981.17 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 02:10:06 PM PST 24
Peak memory 808500 kb
Host smart-540adcfb-8fa7-4cc0-af53-236655c2832a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1194894341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1194894341
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.479617107
Short name T114
Test name
Test status
Simulation time 118967745 ps
CPU time 3.21 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 217392 kb
Host smart-6d7fbd72-c766-4173-a25f-a0708e8823d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479617107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.479617107
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2704117568
Short name T350
Test name
Test status
Simulation time 25239554 ps
CPU time 0.95 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 208468 kb
Host smart-045dee84-a9bf-44b3-94c2-3e2ebb268655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704117568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2704117568
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1935679958
Short name T336
Test name
Test status
Simulation time 2019383363 ps
CPU time 12.88 seconds
Started Jan 07 01:02:55 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 218168 kb
Host smart-8ace4451-a318-41ea-9545-9e3389d156dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935679958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1935679958
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1279944491
Short name T119
Test name
Test status
Simulation time 377701572 ps
CPU time 3.87 seconds
Started Jan 07 01:17:22 PM PST 24
Finished Jan 07 01:17:28 PM PST 24
Peak memory 222144 kb
Host smart-e1791f5c-a79f-41a2-a1ef-c3474a9ac4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279944491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1279944491
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4246737530
Short name T113
Test name
Test status
Simulation time 64457638 ps
CPU time 2.11 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:23 PM PST 24
Peak memory 217976 kb
Host smart-02599036-6fb5-4d2c-b426-79c37b241cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246737530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4246737530
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2129003616
Short name T115
Test name
Test status
Simulation time 56721306 ps
CPU time 2.04 seconds
Started Jan 07 01:18:07 PM PST 24
Finished Jan 07 01:18:12 PM PST 24
Peak memory 221652 kb
Host smart-d6db2b3c-5821-4a10-8540-4e0a861fb87f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129003616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2129003616
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2854927566
Short name T402
Test name
Test status
Simulation time 5563830327 ps
CPU time 48.47 seconds
Started Jan 07 01:01:44 PM PST 24
Finished Jan 07 01:02:56 PM PST 24
Peak memory 226368 kb
Host smart-828b06fc-32e3-4f63-a561-767f306b1ce5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854927566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2854927566
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2739831165
Short name T39
Test name
Test status
Simulation time 52360698 ps
CPU time 0.92 seconds
Started Jan 07 01:04:08 PM PST 24
Finished Jan 07 01:04:12 PM PST 24
Peak memory 212640 kb
Host smart-fea31d9b-f9b8-46c8-8eac-b977d67c14d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739831165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2739831165
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2600523106
Short name T138
Test name
Test status
Simulation time 38181453 ps
CPU time 1.3 seconds
Started Jan 07 01:17:32 PM PST 24
Finished Jan 07 01:17:34 PM PST 24
Peak memory 219840 kb
Host smart-12058016-a8bc-47ed-a6b2-f220ef3b3aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260052
3106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2600523106
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3121739882
Short name T125
Test name
Test status
Simulation time 444849162 ps
CPU time 2.82 seconds
Started Jan 07 01:18:06 PM PST 24
Finished Jan 07 01:18:11 PM PST 24
Peak memory 213116 kb
Host smart-15e7a640-bb5c-4e01-b1e5-d7cc10b6374d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121739882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3121739882
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.845783165
Short name T157
Test name
Test status
Simulation time 15629931 ps
CPU time 1.07 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:19 PM PST 24
Peak memory 208968 kb
Host smart-a268d47a-0f2c-48d1-8cff-e29f3cc8fcac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845783165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.845783165
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2397207276
Short name T120
Test name
Test status
Simulation time 214829137 ps
CPU time 2.79 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:23 PM PST 24
Peak memory 222160 kb
Host smart-14f58092-497a-4297-b673-ec10bbc9f540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397207276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2397207276
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1523490231
Short name T316
Test name
Test status
Simulation time 19119263 ps
CPU time 0.8 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 208044 kb
Host smart-ed68e0bb-50d2-48d8-8992-0a8b23d5ff91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523490231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1523490231
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.770355318
Short name T126
Test name
Test status
Simulation time 67880853 ps
CPU time 1.89 seconds
Started Jan 07 01:18:16 PM PST 24
Finished Jan 07 01:18:18 PM PST 24
Peak memory 221392 kb
Host smart-b2c1624a-68c3-4c91-952f-913c17b13b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770355318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.770355318
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.853952305
Short name T121
Test name
Test status
Simulation time 439282039 ps
CPU time 3.78 seconds
Started Jan 07 01:18:03 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 217708 kb
Host smart-2e028044-f556-4817-b940-0c4446ef3dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853952305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.853952305
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1428471937
Short name T178
Test name
Test status
Simulation time 12670924 ps
CPU time 0.8 seconds
Started Jan 07 01:01:42 PM PST 24
Finished Jan 07 01:02:07 PM PST 24
Peak memory 209656 kb
Host smart-48621f19-abe6-4444-b7fd-6f4957a17be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428471937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1428471937
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3215330033
Short name T179
Test name
Test status
Simulation time 28296385 ps
CPU time 0.77 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:11 PM PST 24
Peak memory 209332 kb
Host smart-c753c3da-07fa-432e-a2ad-ad84cfe67853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215330033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3215330033
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4224697797
Short name T62
Test name
Test status
Simulation time 129406180 ps
CPU time 0.79 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 209432 kb
Host smart-f67b4867-bcb0-4f74-81be-323a14512105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224697797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4224697797
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2149581648
Short name T204
Test name
Test status
Simulation time 347697277 ps
CPU time 1.54 seconds
Started Jan 07 01:17:25 PM PST 24
Finished Jan 07 01:17:28 PM PST 24
Peak memory 210900 kb
Host smart-58b179de-889e-4341-97ab-17845a673b51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149581648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2149581648
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1962151008
Short name T124
Test name
Test status
Simulation time 43543149 ps
CPU time 1.77 seconds
Started Jan 07 01:18:16 PM PST 24
Finished Jan 07 01:18:18 PM PST 24
Peak memory 217672 kb
Host smart-5e1457e9-6ee9-4f9d-91e9-45d3ec85f599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962151008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1962151008
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1669485382
Short name T103
Test name
Test status
Simulation time 111426022 ps
CPU time 4.16 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 217744 kb
Host smart-670c6cc7-e4a5-4c29-9af9-2c943161250f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669485382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1669485382
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3322262863
Short name T122
Test name
Test status
Simulation time 80837431 ps
CPU time 2.82 seconds
Started Jan 07 01:17:54 PM PST 24
Finished Jan 07 01:17:58 PM PST 24
Peak memory 221828 kb
Host smart-615866b7-5a88-4258-91ff-99b37b783c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322262863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3322262863
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.452933631
Short name T87
Test name
Test status
Simulation time 129391030 ps
CPU time 1.7 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 209444 kb
Host smart-4ebbdfee-f38e-4bf1-8679-f909c0b83ff7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452933631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.452933631
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1362423608
Short name T9
Test name
Test status
Simulation time 1202968535 ps
CPU time 19.12 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 214340 kb
Host smart-61bb35dd-bd76-4e1e-8dd8-fb0dd7f11523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362423608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1362423608
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3538908817
Short name T99
Test name
Test status
Simulation time 35527885 ps
CPU time 1.61 seconds
Started Jan 07 01:17:23 PM PST 24
Finished Jan 07 01:17:26 PM PST 24
Peak memory 208856 kb
Host smart-383ae826-cefc-4571-9f03-699b23f43c58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538908817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3538908817
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3957666847
Short name T243
Test name
Test status
Simulation time 30562435 ps
CPU time 1.83 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 209532 kb
Host smart-7a42386d-17d8-4a44-8d4c-e8e7edafda26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957666847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3957666847
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2025973378
Short name T160
Test name
Test status
Simulation time 19496402 ps
CPU time 1.22 seconds
Started Jan 07 01:17:18 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 218156 kb
Host smart-2d51c230-b683-4d96-9fe8-ec58046a26e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025973378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2025973378
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.737172521
Short name T289
Test name
Test status
Simulation time 17335132 ps
CPU time 1.47 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:22 PM PST 24
Peak memory 219348 kb
Host smart-9992425e-39a8-43b5-94dc-ce5b03b7fea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737172521 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.737172521
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3680538428
Short name T88
Test name
Test status
Simulation time 69805767 ps
CPU time 1.02 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:22 PM PST 24
Peak memory 207748 kb
Host smart-c18e3abc-ee7e-435b-8f92-27b72b066b4b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680538428 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3680538428
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1884011549
Short name T269
Test name
Test status
Simulation time 444508939 ps
CPU time 3.24 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:21 PM PST 24
Peak memory 209412 kb
Host smart-1c645ea3-924a-4c0a-aefe-08987f8d4bee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884011549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1884011549
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2498168406
Short name T286
Test name
Test status
Simulation time 671915965 ps
CPU time 7.25 seconds
Started Jan 07 01:17:23 PM PST 24
Finished Jan 07 01:17:31 PM PST 24
Peak memory 209412 kb
Host smart-142d09b2-d6f4-4b47-9b79-4282d135b0ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498168406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2498168406
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2570974841
Short name T189
Test name
Test status
Simulation time 252766617 ps
CPU time 2.13 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 210760 kb
Host smart-5d46f54d-a13e-41db-9817-81d3451571ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570974841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2570974841
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1852108630
Short name T203
Test name
Test status
Simulation time 39412033 ps
CPU time 1.61 seconds
Started Jan 07 01:17:18 PM PST 24
Finished Jan 07 01:17:21 PM PST 24
Peak memory 218948 kb
Host smart-ce7b1bef-b980-4975-8f8a-45f04ba7fe50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185210
8630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1852108630
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3923491447
Short name T287
Test name
Test status
Simulation time 62715654 ps
CPU time 2.07 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 209444 kb
Host smart-5984a0c4-ef05-4e6f-b8b1-9166192ba2fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923491447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3923491447
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1590882819
Short name T288
Test name
Test status
Simulation time 92626223 ps
CPU time 1.24 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 209544 kb
Host smart-5af5b44c-9883-4a6b-b044-c6101e1eb291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590882819 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1590882819
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3094648301
Short name T262
Test name
Test status
Simulation time 151472141 ps
CPU time 1.79 seconds
Started Jan 07 01:17:21 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 209488 kb
Host smart-3edb60e4-6e07-4da6-b944-94a508447731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094648301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3094648301
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3949431966
Short name T214
Test name
Test status
Simulation time 242622241 ps
CPU time 3.01 seconds
Started Jan 07 01:17:22 PM PST 24
Finished Jan 07 01:17:27 PM PST 24
Peak memory 217524 kb
Host smart-c9cea3ef-7bf7-4879-8913-aaf247411c32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949431966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3949431966
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1487891585
Short name T240
Test name
Test status
Simulation time 274171777 ps
CPU time 2.09 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 221904 kb
Host smart-9f85b237-f099-4f6e-ab94-ff5b3755a2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487891585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1487891585
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3511616675
Short name T164
Test name
Test status
Simulation time 35075662 ps
CPU time 1.24 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 209584 kb
Host smart-213d5e5d-85e0-4507-93f3-19d3e25ce9f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511616675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3511616675
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2249429359
Short name T159
Test name
Test status
Simulation time 26090040 ps
CPU time 1.85 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:22 PM PST 24
Peak memory 209472 kb
Host smart-3830c91b-760b-497b-9f3f-39ede4b37ffe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249429359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2249429359
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.346430689
Short name T172
Test name
Test status
Simulation time 29686268 ps
CPU time 1.07 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 209944 kb
Host smart-c700d0e7-7770-4759-bc99-7341d568e5d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346430689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.346430689
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3738160575
Short name T264
Test name
Test status
Simulation time 92047980 ps
CPU time 2.04 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 219036 kb
Host smart-d0ac1eb6-b53c-4ef3-b418-4aa730bef4ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738160575 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3738160575
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2195700418
Short name T165
Test name
Test status
Simulation time 14601219 ps
CPU time 1.03 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 209496 kb
Host smart-56084df5-f3ed-4d4b-8219-ac9882f99e98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195700418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2195700418
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2012286658
Short name T220
Test name
Test status
Simulation time 177492174 ps
CPU time 1.64 seconds
Started Jan 07 01:17:16 PM PST 24
Finished Jan 07 01:17:18 PM PST 24
Peak memory 209312 kb
Host smart-a0e9f6f3-41f3-4301-9e0d-6ab3208b25a4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012286658 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2012286658
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1140751119
Short name T282
Test name
Test status
Simulation time 1215609189 ps
CPU time 5.6 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:28 PM PST 24
Peak memory 209496 kb
Host smart-885197ed-0abd-433c-bf0a-d6ccd7f3e7b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140751119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1140751119
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1311496184
Short name T224
Test name
Test status
Simulation time 676824237 ps
CPU time 7.35 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:29 PM PST 24
Peak memory 209380 kb
Host smart-aabc5ebe-f05b-4756-9fc6-66bf66c019fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311496184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1311496184
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3768529319
Short name T276
Test name
Test status
Simulation time 129468567 ps
CPU time 1.7 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 209480 kb
Host smart-c50bd4f5-d2ae-4019-a7da-f98f7373372b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768529319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3768529319
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.387207935
Short name T161
Test name
Test status
Simulation time 73869828 ps
CPU time 1.16 seconds
Started Jan 07 01:17:21 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 209636 kb
Host smart-782858bb-e97b-479c-96e0-9460274c4844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387207935 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.387207935
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3586297905
Short name T173
Test name
Test status
Simulation time 69549404 ps
CPU time 1.4 seconds
Started Jan 07 01:17:23 PM PST 24
Finished Jan 07 01:17:26 PM PST 24
Peak memory 211452 kb
Host smart-39614a44-aca6-415a-98fe-b5b3cc2bc0c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586297905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3586297905
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3823606011
Short name T199
Test name
Test status
Simulation time 375340116 ps
CPU time 4.48 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:26 PM PST 24
Peak memory 217684 kb
Host smart-b23d3d3e-f8ee-4fcf-b307-5b5c5c745698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823606011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3823606011
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1621734263
Short name T151
Test name
Test status
Simulation time 24623139 ps
CPU time 1.24 seconds
Started Jan 07 01:18:17 PM PST 24
Finished Jan 07 01:18:21 PM PST 24
Peak memory 219280 kb
Host smart-528e644b-0d8c-431e-b60e-26f5c1636620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621734263 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1621734263
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2519361060
Short name T175
Test name
Test status
Simulation time 79285708 ps
CPU time 0.8 seconds
Started Jan 07 01:18:03 PM PST 24
Finished Jan 07 01:18:05 PM PST 24
Peak memory 209344 kb
Host smart-cc93c163-7478-4716-8e8f-40b7db33ce7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519361060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2519361060
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2659945936
Short name T176
Test name
Test status
Simulation time 31105048 ps
CPU time 1.62 seconds
Started Jan 07 01:18:06 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 209684 kb
Host smart-4ae9ce4a-1269-448e-8775-f340e42b5ba2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659945936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2659945936
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3600944874
Short name T155
Test name
Test status
Simulation time 76409442 ps
CPU time 2.67 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:10 PM PST 24
Peak memory 218944 kb
Host smart-6cf5e2bc-3f66-4d44-a219-e280f038e20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600944874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3600944874
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4002747033
Short name T128
Test name
Test status
Simulation time 102193444 ps
CPU time 4.09 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:12 PM PST 24
Peak memory 222112 kb
Host smart-00cdf5bd-3154-4dd1-a987-f427b441ef04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002747033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.4002747033
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3566788837
Short name T206
Test name
Test status
Simulation time 15046128 ps
CPU time 1.1 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 217844 kb
Host smart-1ebaf536-d7a8-43e8-94d1-45d7f0349e85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566788837 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3566788837
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1486494702
Short name T163
Test name
Test status
Simulation time 14781665 ps
CPU time 0.9 seconds
Started Jan 07 01:18:04 PM PST 24
Finished Jan 07 01:18:07 PM PST 24
Peak memory 209532 kb
Host smart-8fab33da-ed38-4015-9314-17e5b8871da7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486494702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1486494702
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.828224092
Short name T217
Test name
Test status
Simulation time 18696086 ps
CPU time 1.02 seconds
Started Jan 07 01:18:03 PM PST 24
Finished Jan 07 01:18:04 PM PST 24
Peak memory 209488 kb
Host smart-b11d6fc6-dca5-4056-8bab-a738ee5e602a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828224092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.828224092
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.469242659
Short name T212
Test name
Test status
Simulation time 86369497 ps
CPU time 1.54 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 217908 kb
Host smart-30a35ffe-9d29-4fee-b990-21b988a0620b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469242659 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.469242659
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3766886433
Short name T230
Test name
Test status
Simulation time 48986973 ps
CPU time 0.85 seconds
Started Jan 07 01:18:04 PM PST 24
Finished Jan 07 01:18:05 PM PST 24
Peak memory 209472 kb
Host smart-134e3de6-056f-46c5-8bc1-5cf86ee2c434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766886433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3766886433
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3154414940
Short name T140
Test name
Test status
Simulation time 41306708 ps
CPU time 1.82 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 211400 kb
Host smart-04013f85-cbf6-4737-8a2b-6d3c7e77b60a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154414940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3154414940
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3377981393
Short name T193
Test name
Test status
Simulation time 337450455 ps
CPU time 2.36 seconds
Started Jan 07 01:18:07 PM PST 24
Finished Jan 07 01:18:12 PM PST 24
Peak memory 217656 kb
Host smart-d7989c77-c3b6-42d7-902f-4b140cb1adee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377981393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3377981393
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2876765574
Short name T148
Test name
Test status
Simulation time 74431635 ps
CPU time 1.19 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 217780 kb
Host smart-adf75d9e-303d-40a7-9170-d4d718ff8502
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876765574 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2876765574
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1660959147
Short name T210
Test name
Test status
Simulation time 48827544 ps
CPU time 0.94 seconds
Started Jan 07 01:18:08 PM PST 24
Finished Jan 07 01:18:11 PM PST 24
Peak memory 208864 kb
Host smart-7e833666-a0f2-409c-a1dc-8aa7053d65fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660959147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1660959147
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3071103622
Short name T213
Test name
Test status
Simulation time 22872896 ps
CPU time 1.23 seconds
Started Jan 07 01:18:08 PM PST 24
Finished Jan 07 01:18:11 PM PST 24
Peak memory 209528 kb
Host smart-ee4a8847-c585-4369-ae1d-19b54ef65e79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071103622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3071103622
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3491657889
Short name T117
Test name
Test status
Simulation time 168583571 ps
CPU time 2.02 seconds
Started Jan 07 01:18:04 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 218288 kb
Host smart-13dd9d13-5760-4cfb-be5d-3f54634a0ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491657889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3491657889
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.565364534
Short name T132
Test name
Test status
Simulation time 83954553 ps
CPU time 2.27 seconds
Started Jan 07 01:18:06 PM PST 24
Finished Jan 07 01:18:12 PM PST 24
Peak memory 217688 kb
Host smart-7e8702d1-0cfe-4ad2-9e73-7b7db095d960
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565364534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.565364534
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2274579115
Short name T84
Test name
Test status
Simulation time 26683733 ps
CPU time 1.68 seconds
Started Jan 07 01:18:19 PM PST 24
Finished Jan 07 01:18:25 PM PST 24
Peak memory 223908 kb
Host smart-8dccbff9-881e-41a9-9c5a-379ff2d0b154
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274579115 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2274579115
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3149365217
Short name T229
Test name
Test status
Simulation time 34247709 ps
CPU time 0.87 seconds
Started Jan 07 01:18:07 PM PST 24
Finished Jan 07 01:18:11 PM PST 24
Peak memory 208920 kb
Host smart-f3549a26-9a45-41df-be81-b3f812914e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149365217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3149365217
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2419367180
Short name T244
Test name
Test status
Simulation time 38493290 ps
CPU time 1.25 seconds
Started Jan 07 01:18:19 PM PST 24
Finished Jan 07 01:18:25 PM PST 24
Peak memory 209664 kb
Host smart-2267e767-a9b2-4a31-b7c2-7ada60d2c7c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419367180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2419367180
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.861808332
Short name T271
Test name
Test status
Simulation time 401253264 ps
CPU time 4.32 seconds
Started Jan 07 01:18:17 PM PST 24
Finished Jan 07 01:18:22 PM PST 24
Peak memory 217748 kb
Host smart-8310f54b-cdb4-480e-b8d3-afffaca5bfa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861808332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.861808332
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1804400709
Short name T283
Test name
Test status
Simulation time 97588097 ps
CPU time 1.1 seconds
Started Jan 07 01:18:21 PM PST 24
Finished Jan 07 01:18:28 PM PST 24
Peak memory 217848 kb
Host smart-80aac651-dce0-424c-8208-fc6b2fe3405c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804400709 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1804400709
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4214835267
Short name T248
Test name
Test status
Simulation time 14771774 ps
CPU time 1.04 seconds
Started Jan 07 01:18:16 PM PST 24
Finished Jan 07 01:18:18 PM PST 24
Peak memory 209476 kb
Host smart-265406ac-e514-4d1e-ab75-9a0c859c1713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214835267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.4214835267
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.946034313
Short name T218
Test name
Test status
Simulation time 39597144 ps
CPU time 1.26 seconds
Started Jan 07 01:18:16 PM PST 24
Finished Jan 07 01:18:18 PM PST 24
Peak memory 209624 kb
Host smart-3c87e4b0-692e-4ade-8a90-87b0e7672306
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946034313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.946034313
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4117326296
Short name T123
Test name
Test status
Simulation time 422971889 ps
CPU time 3.07 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:25 PM PST 24
Peak memory 217724 kb
Host smart-e8fc0754-21ab-43ea-a981-827234708e40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117326296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4117326296
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2769788503
Short name T231
Test name
Test status
Simulation time 39709511 ps
CPU time 1.57 seconds
Started Jan 07 01:18:20 PM PST 24
Finished Jan 07 01:18:27 PM PST 24
Peak memory 219664 kb
Host smart-11d76a3d-8105-4cc6-987a-de6c7aa9b59c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769788503 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2769788503
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.300999035
Short name T145
Test name
Test status
Simulation time 22051421 ps
CPU time 0.84 seconds
Started Jan 07 01:18:19 PM PST 24
Finished Jan 07 01:18:25 PM PST 24
Peak memory 209420 kb
Host smart-a75de514-e21c-4818-b333-6efa9fcadb76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300999035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.300999035
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3303892564
Short name T268
Test name
Test status
Simulation time 55368046 ps
CPU time 1.4 seconds
Started Jan 07 01:18:20 PM PST 24
Finished Jan 07 01:18:27 PM PST 24
Peak memory 209560 kb
Host smart-6a922356-7dc4-4b4c-8a17-999437bb882b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303892564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3303892564
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.212722244
Short name T278
Test name
Test status
Simulation time 494073105 ps
CPU time 4.73 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:25 PM PST 24
Peak memory 217696 kb
Host smart-b63cbce9-a9d7-4190-b7a8-a4684c70b0e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212722244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.212722244
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3095303119
Short name T116
Test name
Test status
Simulation time 384745127 ps
CPU time 2.93 seconds
Started Jan 07 01:18:16 PM PST 24
Finished Jan 07 01:18:21 PM PST 24
Peak memory 221592 kb
Host smart-a1f62b54-306a-4c66-8fb3-47171ca1b8a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095303119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3095303119
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3517021849
Short name T263
Test name
Test status
Simulation time 29419941 ps
CPU time 1.25 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:21 PM PST 24
Peak memory 219684 kb
Host smart-2bb06aee-595c-439c-adae-9f1550a64ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517021849 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3517021849
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.890162775
Short name T198
Test name
Test status
Simulation time 111870463 ps
CPU time 0.88 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:23 PM PST 24
Peak memory 209564 kb
Host smart-acba2b83-785d-4928-a43b-61eb9db0d7a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890162775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.890162775
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4232417159
Short name T156
Test name
Test status
Simulation time 19409716 ps
CPU time 1.18 seconds
Started Jan 07 01:18:22 PM PST 24
Finished Jan 07 01:18:28 PM PST 24
Peak memory 209544 kb
Host smart-3f8e61d1-817d-4bfd-b614-a5a96c325e6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232417159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.4232417159
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2968576460
Short name T197
Test name
Test status
Simulation time 64370961 ps
CPU time 1.95 seconds
Started Jan 07 01:18:21 PM PST 24
Finished Jan 07 01:18:28 PM PST 24
Peak memory 217704 kb
Host smart-771b276c-3e5c-4b8f-a6b0-6498bc603a21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968576460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2968576460
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2116136496
Short name T130
Test name
Test status
Simulation time 107403469 ps
CPU time 2.16 seconds
Started Jan 07 01:18:17 PM PST 24
Finished Jan 07 01:18:20 PM PST 24
Peak memory 221292 kb
Host smart-c7baab29-0d22-4e8c-b359-e004b2bf83de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116136496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2116136496
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3070045871
Short name T254
Test name
Test status
Simulation time 108652597 ps
CPU time 1.53 seconds
Started Jan 07 01:18:19 PM PST 24
Finished Jan 07 01:18:26 PM PST 24
Peak memory 219764 kb
Host smart-e9ee82b9-b96a-4ad1-baa2-25d2797f9aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070045871 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3070045871
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.574591870
Short name T147
Test name
Test status
Simulation time 14448917 ps
CPU time 1.02 seconds
Started Jan 07 01:18:22 PM PST 24
Finished Jan 07 01:18:28 PM PST 24
Peak memory 209564 kb
Host smart-1368dd20-0489-4475-8add-ed3fdcc29d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574591870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.574591870
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3083758819
Short name T223
Test name
Test status
Simulation time 93588508 ps
CPU time 1.32 seconds
Started Jan 07 01:18:17 PM PST 24
Finished Jan 07 01:18:20 PM PST 24
Peak memory 208560 kb
Host smart-9b9db83a-f47e-46a9-b076-76a4f6dc567e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083758819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3083758819
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2702489223
Short name T267
Test name
Test status
Simulation time 458954830 ps
CPU time 4.38 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:24 PM PST 24
Peak memory 217560 kb
Host smart-d2fb9185-9a4e-4c66-bb58-4cc67a6b3e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702489223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2702489223
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1772710212
Short name T275
Test name
Test status
Simulation time 29040799 ps
CPU time 1.42 seconds
Started Jan 07 01:18:19 PM PST 24
Finished Jan 07 01:18:25 PM PST 24
Peak memory 222840 kb
Host smart-ce86892e-fed1-41e7-9c7a-07845611f313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772710212 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1772710212
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2374926508
Short name T166
Test name
Test status
Simulation time 45671724 ps
CPU time 0.86 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:21 PM PST 24
Peak memory 208956 kb
Host smart-61817990-718a-4a66-aa5b-72327a036b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374926508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2374926508
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3132331218
Short name T174
Test name
Test status
Simulation time 37151435 ps
CPU time 1.73 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:23 PM PST 24
Peak memory 211372 kb
Host smart-80ec3fbf-0d25-4c61-94cb-540e96c91f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132331218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3132331218
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1798240533
Short name T127
Test name
Test status
Simulation time 241919804 ps
CPU time 3.17 seconds
Started Jan 07 01:18:18 PM PST 24
Finished Jan 07 01:18:23 PM PST 24
Peak memory 221760 kb
Host smart-d8bd7db7-2ed8-4ed3-a1eb-ae2225ded044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798240533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1798240533
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.209480146
Short name T191
Test name
Test status
Simulation time 246632632 ps
CPU time 2.49 seconds
Started Jan 07 01:17:18 PM PST 24
Finished Jan 07 01:17:22 PM PST 24
Peak memory 209632 kb
Host smart-5da21829-dc83-414e-9fbb-5bd1e726d727
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209480146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.209480146
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3735884445
Short name T188
Test name
Test status
Simulation time 41145965 ps
CPU time 0.95 seconds
Started Jan 07 01:17:18 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 209688 kb
Host smart-07ad4511-8421-496b-bfe1-a600ea8ec110
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735884445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3735884445
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4266883543
Short name T208
Test name
Test status
Simulation time 42393044 ps
CPU time 1.46 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 217932 kb
Host smart-9cb546b0-1d60-4d7d-93a6-51bb30e9c196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266883543 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.4266883543
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4115942921
Short name T272
Test name
Test status
Simulation time 58563469 ps
CPU time 0.88 seconds
Started Jan 07 01:17:18 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 208972 kb
Host smart-18f2ddb8-170d-4a05-be12-4ba4963554a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115942921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4115942921
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3700200410
Short name T232
Test name
Test status
Simulation time 77467486 ps
CPU time 1.4 seconds
Started Jan 07 01:17:26 PM PST 24
Finished Jan 07 01:17:28 PM PST 24
Peak memory 209400 kb
Host smart-56dd6141-e7fb-4036-9e72-59dea88482bd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700200410 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3700200410
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4126090154
Short name T192
Test name
Test status
Simulation time 2296843480 ps
CPU time 4.88 seconds
Started Jan 07 01:17:16 PM PST 24
Finished Jan 07 01:17:21 PM PST 24
Peak memory 209488 kb
Host smart-85c0cc93-32e9-43d7-ae58-d7157b9bfb64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126090154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4126090154
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3544436938
Short name T245
Test name
Test status
Simulation time 1212257574 ps
CPU time 16.47 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:34 PM PST 24
Peak memory 209444 kb
Host smart-ccd88217-aec0-436d-981d-efe930d4567e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544436938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3544436938
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3299137045
Short name T260
Test name
Test status
Simulation time 57775020 ps
CPU time 1.3 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 210692 kb
Host smart-17913aae-2f08-4599-b36e-6bf1bcc1eaec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299137045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3299137045
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1464334906
Short name T228
Test name
Test status
Simulation time 210611949 ps
CPU time 1.49 seconds
Started Jan 07 01:17:18 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 209348 kb
Host smart-8bae91ea-060b-4a46-b2f7-e668631fb950
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464334906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1464334906
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3100032831
Short name T270
Test name
Test status
Simulation time 68728744 ps
CPU time 1.69 seconds
Started Jan 07 01:17:22 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 208960 kb
Host smart-20826aa1-3710-4c57-93f8-9f94c6613c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100032831 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3100032831
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3457414703
Short name T290
Test name
Test status
Simulation time 166696676 ps
CPU time 1.35 seconds
Started Jan 07 01:17:22 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 211204 kb
Host smart-40e92824-f3af-420e-a578-4fcbbb02a279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457414703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3457414703
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1264521865
Short name T168
Test name
Test status
Simulation time 85870590 ps
CPU time 3.67 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 217792 kb
Host smart-a3e2a058-90b8-46ea-9189-c746104908fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264521865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1264521865
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.887579170
Short name T152
Test name
Test status
Simulation time 22445208 ps
CPU time 1.05 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:22 PM PST 24
Peak memory 209436 kb
Host smart-609aa1c6-13c2-4a82-a54a-466f35200f17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887579170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.887579170
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2098931226
Short name T274
Test name
Test status
Simulation time 62375607 ps
CPU time 1.71 seconds
Started Jan 07 01:17:26 PM PST 24
Finished Jan 07 01:17:29 PM PST 24
Peak memory 209568 kb
Host smart-986bf4b4-5f45-4c41-a044-3e9ebf938366
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098931226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2098931226
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.431401940
Short name T265
Test name
Test status
Simulation time 25023656 ps
CPU time 1.47 seconds
Started Jan 07 01:17:25 PM PST 24
Finished Jan 07 01:17:28 PM PST 24
Peak memory 217852 kb
Host smart-076b84c8-6803-402d-bbc7-ded0cca8b478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431401940 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.431401940
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.832356908
Short name T195
Test name
Test status
Simulation time 26634730 ps
CPU time 0.97 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:19 PM PST 24
Peak memory 208944 kb
Host smart-88defa5f-b31c-45af-b958-c2145130343b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832356908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.832356908
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1561311076
Short name T137
Test name
Test status
Simulation time 72966829 ps
CPU time 1.44 seconds
Started Jan 07 01:17:18 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 209288 kb
Host smart-d31eb145-b8b7-463a-880a-50cf28d483f4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561311076 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1561311076
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.434339333
Short name T135
Test name
Test status
Simulation time 434569848 ps
CPU time 4.85 seconds
Started Jan 07 01:17:18 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 209428 kb
Host smart-98995c15-2f3f-487e-a661-e246588e7b4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434339333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.434339333
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.334006489
Short name T190
Test name
Test status
Simulation time 2144755869 ps
CPU time 19.06 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:40 PM PST 24
Peak memory 208392 kb
Host smart-cbd2d3fb-7f5c-4096-acf8-905ece9fc877
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334006489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.334006489
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3993684578
Short name T258
Test name
Test status
Simulation time 232179477 ps
CPU time 1.25 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:17:19 PM PST 24
Peak memory 210692 kb
Host smart-54658769-fe5e-44f6-b45b-f85dfc39ef53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993684578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3993684578
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3670630829
Short name T251
Test name
Test status
Simulation time 59558038 ps
CPU time 1.48 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 218048 kb
Host smart-836c392b-9ce0-415b-893d-4c8ba7c0c812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367063
0829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3670630829
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3859386562
Short name T250
Test name
Test status
Simulation time 185693755 ps
CPU time 1.69 seconds
Started Jan 07 01:17:22 PM PST 24
Finished Jan 07 01:17:26 PM PST 24
Peak memory 209564 kb
Host smart-adb74829-f53e-4cc9-a498-556465abd337
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859386562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3859386562
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4190214274
Short name T211
Test name
Test status
Simulation time 28177108 ps
CPU time 1.37 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 209496 kb
Host smart-3bc4fb20-6a5e-4d9b-8371-ad0c1214594b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190214274 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.4190214274
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1931515861
Short name T255
Test name
Test status
Simulation time 43483995 ps
CPU time 1.62 seconds
Started Jan 07 01:17:25 PM PST 24
Finished Jan 07 01:17:28 PM PST 24
Peak memory 209720 kb
Host smart-29c9abb2-f645-4a8f-bc64-939f3396cd2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931515861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1931515861
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4062404732
Short name T118
Test name
Test status
Simulation time 425722139 ps
CPU time 3.61 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 217732 kb
Host smart-ac003fbe-ed51-49e8-b05c-dce81e1d6be8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062404732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4062404732
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2140848037
Short name T167
Test name
Test status
Simulation time 122713899 ps
CPU time 1.63 seconds
Started Jan 07 01:17:51 PM PST 24
Finished Jan 07 01:17:54 PM PST 24
Peak memory 209524 kb
Host smart-d96e66ca-3e1c-435a-891b-df1a103e89b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140848037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2140848037
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2366777006
Short name T266
Test name
Test status
Simulation time 67738179 ps
CPU time 1.49 seconds
Started Jan 07 01:17:54 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 208488 kb
Host smart-17cd8de3-89ea-4732-986a-aeaae4bf178c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366777006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2366777006
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2393244258
Short name T205
Test name
Test status
Simulation time 24784270 ps
CPU time 1.17 seconds
Started Jan 07 01:18:03 PM PST 24
Finished Jan 07 01:18:05 PM PST 24
Peak memory 211520 kb
Host smart-f48d02bf-7448-4eaf-b52e-d421d1977f65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393244258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2393244258
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2210006931
Short name T209
Test name
Test status
Simulation time 17285205 ps
CPU time 1.24 seconds
Started Jan 07 01:17:39 PM PST 24
Finished Jan 07 01:17:41 PM PST 24
Peak memory 218156 kb
Host smart-a2d9e500-8f59-4a44-b3c7-b5ba4ebbb530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210006931 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2210006931
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2496510380
Short name T225
Test name
Test status
Simulation time 52291650 ps
CPU time 0.89 seconds
Started Jan 07 01:17:56 PM PST 24
Finished Jan 07 01:17:58 PM PST 24
Peak memory 209112 kb
Host smart-cd383815-aa1d-476a-bbd5-ecd1086bde3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496510380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2496510380
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1509050600
Short name T171
Test name
Test status
Simulation time 52419637 ps
CPU time 1.2 seconds
Started Jan 07 01:17:55 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 207760 kb
Host smart-097f963b-6ed1-440b-918a-67ce9bb189c2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509050600 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1509050600
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1183359717
Short name T222
Test name
Test status
Simulation time 221014881 ps
CPU time 5.75 seconds
Started Jan 07 01:17:41 PM PST 24
Finished Jan 07 01:17:47 PM PST 24
Peak memory 209440 kb
Host smart-7f515777-a8b5-49bf-a69a-0f6af5a9a556
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183359717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1183359717
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3593476461
Short name T201
Test name
Test status
Simulation time 5465702882 ps
CPU time 13.95 seconds
Started Jan 07 01:17:19 PM PST 24
Finished Jan 07 01:17:35 PM PST 24
Peak memory 208560 kb
Host smart-8aeaa9d8-460b-4db6-8019-fc11e52a0cab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593476461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3593476461
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2162747213
Short name T235
Test name
Test status
Simulation time 51995729 ps
CPU time 1.39 seconds
Started Jan 07 01:17:49 PM PST 24
Finished Jan 07 01:17:51 PM PST 24
Peak memory 217904 kb
Host smart-f9bd309e-bbc9-4051-b4b3-8e4d893114f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216274
7213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2162747213
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1239572954
Short name T143
Test name
Test status
Simulation time 326514742 ps
CPU time 1.08 seconds
Started Jan 07 01:17:25 PM PST 24
Finished Jan 07 01:17:27 PM PST 24
Peak memory 209468 kb
Host smart-d557cdfc-b2a0-4baf-a14a-8a78188e226e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239572954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1239572954
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.918498347
Short name T285
Test name
Test status
Simulation time 24431871 ps
CPU time 1.04 seconds
Started Jan 07 01:17:40 PM PST 24
Finished Jan 07 01:17:41 PM PST 24
Peak memory 209632 kb
Host smart-65e6c641-c153-494c-aad9-dc373d97321a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918498347 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.918498347
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1031419756
Short name T249
Test name
Test status
Simulation time 62794645 ps
CPU time 1.15 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:54 PM PST 24
Peak memory 209512 kb
Host smart-03284077-636e-4d50-af01-4ba1ec766d7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031419756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1031419756
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1224208230
Short name T215
Test name
Test status
Simulation time 581812962 ps
CPU time 3.68 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 217684 kb
Host smart-cc80f641-9721-491d-a482-c4015e5d21f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224208230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1224208230
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4268252467
Short name T131
Test name
Test status
Simulation time 2658993500 ps
CPU time 3.35 seconds
Started Jan 07 01:17:59 PM PST 24
Finished Jan 07 01:18:03 PM PST 24
Peak memory 222216 kb
Host smart-eaf67772-78b5-48a8-bf62-72b6c65f4950
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268252467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4268252467
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.661069513
Short name T96
Test name
Test status
Simulation time 90931291 ps
CPU time 1.72 seconds
Started Jan 07 01:17:53 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 217664 kb
Host smart-e52dd519-4ed9-4f9f-b536-15a035a20684
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661069513 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.661069513
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.950272114
Short name T242
Test name
Test status
Simulation time 65878087 ps
CPU time 0.88 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:55 PM PST 24
Peak memory 209524 kb
Host smart-1b743fad-b3cd-4e4f-ae60-6dec721822d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950272114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.950272114
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4239221775
Short name T246
Test name
Test status
Simulation time 46056713 ps
CPU time 1.58 seconds
Started Jan 07 01:17:55 PM PST 24
Finished Jan 07 01:17:58 PM PST 24
Peak memory 207840 kb
Host smart-39a598cd-b029-4c28-a222-c0f65f63424c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239221775 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4239221775
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.928734379
Short name T86
Test name
Test status
Simulation time 1139058537 ps
CPU time 23.7 seconds
Started Jan 07 01:17:39 PM PST 24
Finished Jan 07 01:18:04 PM PST 24
Peak memory 209420 kb
Host smart-d10b3e23-8b33-4fab-a7ef-d50374012f76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928734379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.928734379
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.515425868
Short name T194
Test name
Test status
Simulation time 2912977303 ps
CPU time 5.97 seconds
Started Jan 07 01:17:54 PM PST 24
Finished Jan 07 01:18:01 PM PST 24
Peak memory 209472 kb
Host smart-2be624c4-bb59-48a6-8bf0-c518f3f0adca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515425868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.515425868
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3961189353
Short name T281
Test name
Test status
Simulation time 52537175 ps
CPU time 1.29 seconds
Started Jan 07 01:17:55 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 210676 kb
Host smart-e17950a1-2116-45c1-beed-b6233b34ef3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961189353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3961189353
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.429134360
Short name T257
Test name
Test status
Simulation time 91429375 ps
CPU time 1.71 seconds
Started Jan 07 01:17:53 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 217652 kb
Host smart-7ea7ccc6-6387-4a4c-9c21-f59419a6b0b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429134
360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.429134360
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.620282933
Short name T141
Test name
Test status
Simulation time 421897122 ps
CPU time 2.37 seconds
Started Jan 07 01:17:38 PM PST 24
Finished Jan 07 01:17:41 PM PST 24
Peak memory 209428 kb
Host smart-ad69f3b5-ac58-444e-8ad7-6fb3a8316dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620282933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.620282933
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3681651884
Short name T90
Test name
Test status
Simulation time 16576281 ps
CPU time 0.95 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:54 PM PST 24
Peak memory 209556 kb
Host smart-2a5b1490-3720-46c8-8b72-02c39cc5e093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681651884 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3681651884
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.834888227
Short name T144
Test name
Test status
Simulation time 110693718 ps
CPU time 3.01 seconds
Started Jan 07 01:17:39 PM PST 24
Finished Jan 07 01:17:42 PM PST 24
Peak memory 217756 kb
Host smart-546daece-44ea-4d1f-87bf-bdc4c3d403ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834888227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.834888227
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3852339306
Short name T150
Test name
Test status
Simulation time 51037379 ps
CPU time 1.04 seconds
Started Jan 07 01:18:06 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 217888 kb
Host smart-aabca253-9915-44e7-a792-a4474a269ce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852339306 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3852339306
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4106910347
Short name T133
Test name
Test status
Simulation time 22585640 ps
CPU time 0.9 seconds
Started Jan 07 01:17:51 PM PST 24
Finished Jan 07 01:17:52 PM PST 24
Peak memory 209616 kb
Host smart-639268a6-4ee4-4d6e-8f79-cca5a86cc617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106910347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4106910347
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3173424762
Short name T146
Test name
Test status
Simulation time 79919942 ps
CPU time 1.13 seconds
Started Jan 07 01:17:39 PM PST 24
Finished Jan 07 01:17:41 PM PST 24
Peak memory 207844 kb
Host smart-19f480aa-3adc-44c6-a82e-f3b6ebc84bef
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173424762 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3173424762
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.43113549
Short name T134
Test name
Test status
Simulation time 186105381 ps
CPU time 2.74 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 209432 kb
Host smart-1a8b488c-9178-4059-98b4-ba43088a34cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43113549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.lc_ctrl_jtag_csr_aliasing.43113549
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3957064242
Short name T280
Test name
Test status
Simulation time 2131760243 ps
CPU time 23.28 seconds
Started Jan 07 01:17:53 PM PST 24
Finished Jan 07 01:18:17 PM PST 24
Peak memory 209488 kb
Host smart-0f379431-2153-46dd-a23e-5179ab179ed8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957064242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3957064242
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2887738580
Short name T207
Test name
Test status
Simulation time 44280339 ps
CPU time 1.76 seconds
Started Jan 07 01:17:56 PM PST 24
Finished Jan 07 01:17:59 PM PST 24
Peak memory 210552 kb
Host smart-03c6261a-b598-47cb-ad75-39d195522099
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887738580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2887738580
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3592856052
Short name T233
Test name
Test status
Simulation time 47814912 ps
CPU time 1.26 seconds
Started Jan 07 01:17:54 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 217852 kb
Host smart-024eb87c-cb68-4f7d-b2f0-7a884e7455ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359285
6052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3592856052
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.536217825
Short name T200
Test name
Test status
Simulation time 176160006 ps
CPU time 1.1 seconds
Started Jan 07 01:17:53 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 209296 kb
Host smart-aad761df-c37a-42d7-8671-d8b38368b450
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536217825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.536217825
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1231820283
Short name T291
Test name
Test status
Simulation time 52565005 ps
CPU time 1.16 seconds
Started Jan 07 01:17:53 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 209556 kb
Host smart-bc365ec7-bfb2-4160-ab9e-f1fe06527052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231820283 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1231820283
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4222937222
Short name T259
Test name
Test status
Simulation time 123837224 ps
CPU time 1.41 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 211388 kb
Host smart-df25ae4b-f812-4e5b-9c38-2f4684386261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222937222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.4222937222
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1341737101
Short name T154
Test name
Test status
Simulation time 88759956 ps
CPU time 2.82 seconds
Started Jan 07 01:17:41 PM PST 24
Finished Jan 07 01:17:45 PM PST 24
Peak memory 217832 kb
Host smart-c0349275-26c1-46b7-9df1-1fdc68df8757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341737101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1341737101
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1037861190
Short name T239
Test name
Test status
Simulation time 30230786 ps
CPU time 1.76 seconds
Started Jan 07 01:17:53 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 218792 kb
Host smart-afb95c1a-1ff1-4fa2-a386-4f9e2516f81c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037861190 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1037861190
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3521169367
Short name T162
Test name
Test status
Simulation time 28611209 ps
CPU time 0.88 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 208824 kb
Host smart-e1246ba3-0495-41e1-9ac8-a54f5d524087
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521169367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3521169367
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3885802150
Short name T237
Test name
Test status
Simulation time 58252270 ps
CPU time 1.87 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:55 PM PST 24
Peak memory 209432 kb
Host smart-1ee7810c-e732-491f-8cd7-e1b6028b5156
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885802150 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3885802150
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.233896628
Short name T279
Test name
Test status
Simulation time 1555750562 ps
CPU time 8.01 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:15 PM PST 24
Peak memory 208412 kb
Host smart-a3c93af7-7284-4811-926a-3403a84a34eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233896628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.233896628
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3272572279
Short name T202
Test name
Test status
Simulation time 686901089 ps
CPU time 3.85 seconds
Started Jan 07 01:18:06 PM PST 24
Finished Jan 07 01:18:13 PM PST 24
Peak memory 207976 kb
Host smart-ba6b183c-7a0c-4481-81fd-ba98671181d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272572279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3272572279
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.440261567
Short name T139
Test name
Test status
Simulation time 385689693 ps
CPU time 1.63 seconds
Started Jan 07 01:17:51 PM PST 24
Finished Jan 07 01:17:54 PM PST 24
Peak memory 210884 kb
Host smart-3a0322e0-b79b-48a8-8d5f-1577eae761ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440261567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.440261567
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3723768869
Short name T83
Test name
Test status
Simulation time 66046422 ps
CPU time 1.53 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 217908 kb
Host smart-0cf24310-f60c-4a88-8fc6-7d97a9da03f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372376
8869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3723768869
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2191887775
Short name T252
Test name
Test status
Simulation time 44307830 ps
CPU time 1.63 seconds
Started Jan 07 01:18:04 PM PST 24
Finished Jan 07 01:18:07 PM PST 24
Peak memory 209504 kb
Host smart-008dc25b-81a4-4c29-b061-d02cd8c480f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191887775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2191887775
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.108871809
Short name T277
Test name
Test status
Simulation time 223124423 ps
CPU time 1.08 seconds
Started Jan 07 01:17:51 PM PST 24
Finished Jan 07 01:17:53 PM PST 24
Peak memory 209548 kb
Host smart-4b21e4c2-b090-4cf8-856f-067f7cb44798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108871809 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.108871809
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3911397531
Short name T238
Test name
Test status
Simulation time 17134803 ps
CPU time 1.1 seconds
Started Jan 07 01:17:53 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 209600 kb
Host smart-18058b90-8c20-4629-8e61-dd5ffd10224d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911397531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3911397531
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1816113200
Short name T221
Test name
Test status
Simulation time 47334484 ps
CPU time 2.22 seconds
Started Jan 07 01:18:04 PM PST 24
Finished Jan 07 01:18:07 PM PST 24
Peak memory 217700 kb
Host smart-faabf999-bf2a-4736-ab49-abaed1b411da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816113200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1816113200
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.636440104
Short name T97
Test name
Test status
Simulation time 425004241 ps
CPU time 3.95 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 217720 kb
Host smart-81d546ce-58e8-4330-a112-119126fccb88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636440104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.636440104
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1423795777
Short name T284
Test name
Test status
Simulation time 152025449 ps
CPU time 1.71 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:55 PM PST 24
Peak memory 218208 kb
Host smart-25827504-a6c5-49b0-bd7c-bab5c2d747db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423795777 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1423795777
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3895487890
Short name T89
Test name
Test status
Simulation time 53478341 ps
CPU time 0.78 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:53 PM PST 24
Peak memory 209436 kb
Host smart-8f722ae7-8a74-46d0-a5cb-f826b47c8669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895487890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3895487890
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3672460833
Short name T226
Test name
Test status
Simulation time 62077523 ps
CPU time 1.35 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 207812 kb
Host smart-7df209a0-eb97-44bf-9639-791f659e4508
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672460833 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3672460833
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1853788919
Short name T241
Test name
Test status
Simulation time 1059377219 ps
CPU time 5.09 seconds
Started Jan 07 01:18:08 PM PST 24
Finished Jan 07 01:18:15 PM PST 24
Peak memory 209456 kb
Host smart-cde783cb-1842-4378-b51d-9656cb7cca43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853788919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1853788919
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2469655168
Short name T247
Test name
Test status
Simulation time 2599206508 ps
CPU time 15.25 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 209400 kb
Host smart-24bf2a9b-1aa9-444e-933f-059710dfcb70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469655168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2469655168
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1265541565
Short name T261
Test name
Test status
Simulation time 165843807 ps
CPU time 2.53 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 210884 kb
Host smart-c90a9e12-41d5-4b54-9b34-5313cebc6431
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265541565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1265541565
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1412751331
Short name T169
Test name
Test status
Simulation time 98495279 ps
CPU time 1.58 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 209376 kb
Host smart-2da8f6ca-f55e-4abc-9e9e-1b17e98fde88
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412751331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1412751331
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.497199872
Short name T234
Test name
Test status
Simulation time 29741279 ps
CPU time 1.08 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:07 PM PST 24
Peak memory 209516 kb
Host smart-ff9c760d-b2d9-4173-8a29-4397fffea1e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497199872 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.497199872
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1021635125
Short name T273
Test name
Test status
Simulation time 64265139 ps
CPU time 0.97 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 209616 kb
Host smart-7cab7edc-6b87-48ea-b6fc-883b5e8f191f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021635125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1021635125
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.949315648
Short name T196
Test name
Test status
Simulation time 132185102 ps
CPU time 4.95 seconds
Started Jan 07 01:17:51 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 217640 kb
Host smart-61527dc8-a0c6-476c-9c8b-152b88ddde2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949315648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.949315648
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2520429963
Short name T129
Test name
Test status
Simulation time 307384139 ps
CPU time 4.41 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 217724 kb
Host smart-d9a8d5a9-0d74-4fa2-a652-89b73cc2dc56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520429963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2520429963
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2770333932
Short name T187
Test name
Test status
Simulation time 14329166 ps
CPU time 1.15 seconds
Started Jan 07 01:18:06 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 217836 kb
Host smart-0a258939-273c-4578-a525-2c30ab5e1eff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770333932 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2770333932
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3514303478
Short name T149
Test name
Test status
Simulation time 17481602 ps
CPU time 1.09 seconds
Started Jan 07 01:18:06 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 209492 kb
Host smart-5c4b4cfd-5a3a-4884-b0dd-ecceabbe0327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514303478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3514303478
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3155823885
Short name T136
Test name
Test status
Simulation time 197553022 ps
CPU time 1.06 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 207864 kb
Host smart-d800d30b-c0a0-4bf8-94f1-0b9161c24094
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155823885 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3155823885
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2681432182
Short name T256
Test name
Test status
Simulation time 866326217 ps
CPU time 3.07 seconds
Started Jan 07 01:18:04 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 209540 kb
Host smart-87396448-0747-4c56-9978-343345808e88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681432182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2681432182
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.783494690
Short name T142
Test name
Test status
Simulation time 4138830821 ps
CPU time 11.59 seconds
Started Jan 07 01:17:52 PM PST 24
Finished Jan 07 01:18:05 PM PST 24
Peak memory 208452 kb
Host smart-c2e0d2c0-2485-4345-81cc-36b23cdc9466
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783494690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.783494690
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4002776788
Short name T216
Test name
Test status
Simulation time 162149066 ps
CPU time 2.59 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 210924 kb
Host smart-a7fdaa85-47dc-487e-9cf4-1622845d6b48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002776788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.4002776788
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.114431247
Short name T170
Test name
Test status
Simulation time 69023094 ps
CPU time 1.65 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:09 PM PST 24
Peak memory 218068 kb
Host smart-7cb99996-b307-4d7d-9cc5-727a66acf90d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114431
247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.114431247
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4054694687
Short name T227
Test name
Test status
Simulation time 49993572 ps
CPU time 1.05 seconds
Started Jan 07 01:17:53 PM PST 24
Finished Jan 07 01:17:56 PM PST 24
Peak memory 209400 kb
Host smart-25755eca-4719-49f6-a345-9f8730e57361
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054694687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.4054694687
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.58745174
Short name T253
Test name
Test status
Simulation time 52945529 ps
CPU time 1.3 seconds
Started Jan 07 01:18:05 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 209648 kb
Host smart-007c2e31-aea3-4fae-8d12-50be7d80b40e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58745174 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.58745174
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2298665025
Short name T219
Test name
Test status
Simulation time 20167541 ps
CPU time 1.44 seconds
Started Jan 07 01:18:07 PM PST 24
Finished Jan 07 01:18:11 PM PST 24
Peak memory 209468 kb
Host smart-ba5e5dd4-5568-451c-bf22-b5364e436402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298665025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2298665025
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.391432221
Short name T236
Test name
Test status
Simulation time 277454288 ps
CPU time 2.49 seconds
Started Jan 07 01:18:04 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 217652 kb
Host smart-1c2efde9-02dc-469f-b5c5-5321627c15ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391432221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.391432221
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.968989633
Short name T865
Test name
Test status
Simulation time 101146780 ps
CPU time 0.78 seconds
Started Jan 07 01:01:29 PM PST 24
Finished Jan 07 01:01:59 PM PST 24
Peak memory 208088 kb
Host smart-402b5ec2-1b63-4d45-a82f-31d43d90ca04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968989633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.968989633
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2553013252
Short name T528
Test name
Test status
Simulation time 4934814375 ps
CPU time 12.64 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:23 PM PST 24
Peak memory 218236 kb
Host smart-05f9992d-657f-46e8-8656-b8953a1782bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553013252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2553013252
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.515070267
Short name T522
Test name
Test status
Simulation time 548652524 ps
CPU time 1.91 seconds
Started Jan 07 01:01:43 PM PST 24
Finished Jan 07 01:02:09 PM PST 24
Peak memory 209696 kb
Host smart-599c44cd-fbbf-45d4-b5a0-1e3dd6deefa5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515070267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_acc
ess.515070267
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3245649196
Short name T928
Test name
Test status
Simulation time 4164546958 ps
CPU time 58.28 seconds
Started Jan 07 01:01:42 PM PST 24
Finished Jan 07 01:03:05 PM PST 24
Peak memory 219276 kb
Host smart-9e312ec7-046e-40e1-9ec0-8a0adef89b68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245649196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3245649196
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1803610659
Short name T503
Test name
Test status
Simulation time 234499633 ps
CPU time 5.42 seconds
Started Jan 07 01:01:45 PM PST 24
Finished Jan 07 01:02:13 PM PST 24
Peak memory 209756 kb
Host smart-6a80b16f-4220-4f06-a2e5-c1d3afcf1841
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803610659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.1803610659
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.867687081
Short name T346
Test name
Test status
Simulation time 395268463 ps
CPU time 6.88 seconds
Started Jan 07 01:01:42 PM PST 24
Finished Jan 07 01:02:13 PM PST 24
Peak memory 218124 kb
Host smart-ce0f5f9f-1ae4-425c-aa4e-8a7ba6dfe2cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867687081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.867687081
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2483144482
Short name T77
Test name
Test status
Simulation time 16865629987 ps
CPU time 11.93 seconds
Started Jan 07 01:01:35 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 213568 kb
Host smart-9261fd3b-b163-4f8f-9c7f-ac79ebfb5968
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483144482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2483144482
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2381482979
Short name T831
Test name
Test status
Simulation time 118532870 ps
CPU time 2.64 seconds
Started Jan 07 01:01:39 PM PST 24
Finished Jan 07 01:02:07 PM PST 24
Peak memory 213072 kb
Host smart-220692b2-2463-45d4-a318-b161c2e31e18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381482979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2381482979
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2727466965
Short name T384
Test name
Test status
Simulation time 4860485860 ps
CPU time 89.01 seconds
Started Jan 07 01:01:42 PM PST 24
Finished Jan 07 01:03:36 PM PST 24
Peak memory 275716 kb
Host smart-31d79d77-b666-4487-91f5-d1fdf95508ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727466965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2727466965
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1262891484
Short name T832
Test name
Test status
Simulation time 565914586 ps
CPU time 21.34 seconds
Started Jan 07 01:01:43 PM PST 24
Finished Jan 07 01:02:28 PM PST 24
Peak memory 251136 kb
Host smart-f4b05c91-064f-4b63-968d-e79eb87f3a0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262891484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1262891484
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.814580470
Short name T563
Test name
Test status
Simulation time 637763258 ps
CPU time 3.32 seconds
Started Jan 07 01:01:16 PM PST 24
Finished Jan 07 01:01:59 PM PST 24
Peak memory 218232 kb
Host smart-d46246d9-274c-4c27-82b0-15b673111d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814580470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.814580470
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.540727012
Short name T104
Test name
Test status
Simulation time 297596544 ps
CPU time 28.31 seconds
Started Jan 07 01:01:44 PM PST 24
Finished Jan 07 01:02:36 PM PST 24
Peak memory 268504 kb
Host smart-9f46bce6-e16f-44d9-86d3-e767e14eafbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540727012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.540727012
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2896960385
Short name T467
Test name
Test status
Simulation time 668050297 ps
CPU time 9.72 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 218220 kb
Host smart-6fe438e3-bd9b-4570-89f9-0d9ea85d6a00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896960385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2896960385
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4053146156
Short name T594
Test name
Test status
Simulation time 4112177328 ps
CPU time 10.68 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:23 PM PST 24
Peak memory 218156 kb
Host smart-7ba62351-982a-41c1-b482-eb43b9a1d6b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053146156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.4053146156
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.4083667432
Short name T738
Test name
Test status
Simulation time 275612189 ps
CPU time 8.69 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 218052 kb
Host smart-e48eba73-8753-498e-bde5-6ffd9eedcb97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083667432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.4
083667432
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3870764486
Short name T532
Test name
Test status
Simulation time 2909754852 ps
CPU time 6.25 seconds
Started Jan 07 01:01:40 PM PST 24
Finished Jan 07 01:02:11 PM PST 24
Peak memory 218332 kb
Host smart-5c5eb433-bc1c-46e4-98eb-f72af0ae03d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870764486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3870764486
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3982805302
Short name T559
Test name
Test status
Simulation time 20497883 ps
CPU time 1.33 seconds
Started Jan 07 01:01:37 PM PST 24
Finished Jan 07 01:02:09 PM PST 24
Peak memory 212872 kb
Host smart-803bc21e-1321-4027-98ba-c1b0e9eed277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982805302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3982805302
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2077945800
Short name T307
Test name
Test status
Simulation time 366240205 ps
CPU time 28.4 seconds
Started Jan 07 01:01:38 PM PST 24
Finished Jan 07 01:02:32 PM PST 24
Peak memory 251184 kb
Host smart-b91f2882-a6f6-4cde-9717-1f456c826ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077945800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2077945800
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.210832236
Short name T531
Test name
Test status
Simulation time 59693369 ps
CPU time 7.1 seconds
Started Jan 07 01:01:36 PM PST 24
Finished Jan 07 01:02:09 PM PST 24
Peak memory 251176 kb
Host smart-e5866c2c-6bca-4f93-b8e3-6170b77c944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210832236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.210832236
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.55969309
Short name T609
Test name
Test status
Simulation time 18056670 ps
CPU time 0.75 seconds
Started Jan 07 01:01:37 PM PST 24
Finished Jan 07 01:02:09 PM PST 24
Peak memory 206652 kb
Host smart-21756452-4232-4f52-9fcb-e032c5a7fac8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55969309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_volatile_unlock_smoke.55969309
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.396074925
Short name T769
Test name
Test status
Simulation time 21514690 ps
CPU time 0.88 seconds
Started Jan 07 01:01:39 PM PST 24
Finished Jan 07 01:02:05 PM PST 24
Peak memory 208328 kb
Host smart-0d653547-a6ec-43bd-8611-ec671c0774fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396074925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.396074925
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1492571936
Short name T877
Test name
Test status
Simulation time 15264228 ps
CPU time 0.85 seconds
Started Jan 07 01:01:33 PM PST 24
Finished Jan 07 01:02:06 PM PST 24
Peak memory 209456 kb
Host smart-5b01cc2b-c460-4ab8-8ce3-2a0f8d2d893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492571936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1492571936
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.718824351
Short name T948
Test name
Test status
Simulation time 2168701361 ps
CPU time 8.54 seconds
Started Jan 07 01:01:28 PM PST 24
Finished Jan 07 01:02:05 PM PST 24
Peak memory 218176 kb
Host smart-4ac3f919-3e2b-4a9f-8a71-2fddc38ae836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718824351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.718824351
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.681966247
Short name T915
Test name
Test status
Simulation time 2333485031 ps
CPU time 12.75 seconds
Started Jan 07 01:01:06 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 209740 kb
Host smart-f28b73d9-c078-452a-a830-a5923d97c539
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681966247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_acc
ess.681966247
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3296506172
Short name T44
Test name
Test status
Simulation time 1779923392 ps
CPU time 51.77 seconds
Started Jan 07 01:01:36 PM PST 24
Finished Jan 07 01:02:54 PM PST 24
Peak memory 218180 kb
Host smart-27b0830c-a944-4ba0-bb14-62b0c14a29be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296506172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3296506172
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2349913790
Short name T569
Test name
Test status
Simulation time 1793158730 ps
CPU time 16.07 seconds
Started Jan 07 01:01:35 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 217952 kb
Host smart-21bfac3b-699f-47e0-9a05-9ac2f657d7ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349913790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.2349913790
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3328957148
Short name T444
Test name
Test status
Simulation time 299347726 ps
CPU time 8.39 seconds
Started Jan 07 01:01:34 PM PST 24
Finished Jan 07 01:02:11 PM PST 24
Peak memory 218144 kb
Host smart-4a20d08d-3849-447e-9ddd-5c36e0d78d74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328957148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3328957148
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3930927139
Short name T505
Test name
Test status
Simulation time 3785976338 ps
CPU time 13.57 seconds
Started Jan 07 01:01:39 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 213660 kb
Host smart-e4ea190b-28bb-4423-81a2-5e95338cfb38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930927139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3930927139
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3161322386
Short name T78
Test name
Test status
Simulation time 221961166 ps
CPU time 6.51 seconds
Started Jan 07 01:01:06 PM PST 24
Finished Jan 07 01:01:52 PM PST 24
Peak memory 213348 kb
Host smart-93521c55-fd59-455a-84f3-cad8ae7ec1fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161322386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3161322386
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3875670611
Short name T829
Test name
Test status
Simulation time 5706637631 ps
CPU time 42.6 seconds
Started Jan 07 01:01:35 PM PST 24
Finished Jan 07 01:02:44 PM PST 24
Peak memory 276040 kb
Host smart-6cc11771-1e0e-4dad-99d1-a2c79c738601
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875670611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3875670611
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.76669362
Short name T938
Test name
Test status
Simulation time 1530739893 ps
CPU time 11.35 seconds
Started Jan 07 01:01:23 PM PST 24
Finished Jan 07 01:02:01 PM PST 24
Peak memory 250460 kb
Host smart-8a886ac8-79fd-495c-bccb-17e2785d48c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76669362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jt
ag_state_post_trans.76669362
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3384022549
Short name T492
Test name
Test status
Simulation time 77148349 ps
CPU time 3.82 seconds
Started Jan 07 01:01:34 PM PST 24
Finished Jan 07 01:02:06 PM PST 24
Peak memory 218216 kb
Host smart-39363a2d-e77e-4cd4-b3bb-0f9f1eeff1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384022549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3384022549
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.246219680
Short name T322
Test name
Test status
Simulation time 367597781 ps
CPU time 19.37 seconds
Started Jan 07 01:01:27 PM PST 24
Finished Jan 07 01:02:16 PM PST 24
Peak memory 217844 kb
Host smart-8606fc39-99ef-40e2-b014-3cfac4d4ba95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246219680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.246219680
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3769689184
Short name T52
Test name
Test status
Simulation time 776305532 ps
CPU time 37.61 seconds
Started Jan 07 01:01:25 PM PST 24
Finished Jan 07 01:02:30 PM PST 24
Peak memory 273212 kb
Host smart-a2e22593-d121-4b16-97b7-407de81e29ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769689184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3769689184
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1770832913
Short name T385
Test name
Test status
Simulation time 2480939426 ps
CPU time 12.51 seconds
Started Jan 07 01:01:39 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 219472 kb
Host smart-4c8d7ec6-d73c-4d4b-a914-d538d0d084b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770832913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1770832913
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3014209590
Short name T679
Test name
Test status
Simulation time 572960088 ps
CPU time 12.36 seconds
Started Jan 07 01:01:39 PM PST 24
Finished Jan 07 01:02:17 PM PST 24
Peak memory 218148 kb
Host smart-53422e6a-ac40-4bd2-9ea2-7bd70c5a3682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014209590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3014209590
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3817815133
Short name T547
Test name
Test status
Simulation time 310928040 ps
CPU time 10.31 seconds
Started Jan 07 01:01:16 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 218152 kb
Host smart-d871f918-205a-4d68-9cfc-2f5b7aca07b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817815133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
817815133
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1925398498
Short name T729
Test name
Test status
Simulation time 695735226 ps
CPU time 6.89 seconds
Started Jan 07 01:01:36 PM PST 24
Finished Jan 07 01:02:09 PM PST 24
Peak memory 218212 kb
Host smart-cfc53afd-88d5-4cd8-b226-40f39f5c2576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925398498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1925398498
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3413386859
Short name T757
Test name
Test status
Simulation time 53861270 ps
CPU time 1.37 seconds
Started Jan 07 01:01:28 PM PST 24
Finished Jan 07 01:01:59 PM PST 24
Peak memory 213400 kb
Host smart-7abe7091-3666-4c50-bf27-eafb53023c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413386859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3413386859
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1630225681
Short name T670
Test name
Test status
Simulation time 433891500 ps
CPU time 22.11 seconds
Started Jan 07 01:01:27 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 251172 kb
Host smart-9203ed21-7b4d-4b30-bf06-e5a51119ce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630225681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1630225681
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.4155888008
Short name T181
Test name
Test status
Simulation time 158830510 ps
CPU time 6.68 seconds
Started Jan 07 01:01:36 PM PST 24
Finished Jan 07 01:02:09 PM PST 24
Peak memory 250512 kb
Host smart-22558fb3-c79d-45ea-a35e-6fe407abb043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155888008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.4155888008
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1365802029
Short name T669
Test name
Test status
Simulation time 1673453996 ps
CPU time 53.49 seconds
Started Jan 07 01:01:37 PM PST 24
Finished Jan 07 01:02:56 PM PST 24
Peak memory 267072 kb
Host smart-d2d497cb-0572-4502-bb55-0a07cfe7248b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365802029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1365802029
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3054208056
Short name T792
Test name
Test status
Simulation time 11784970 ps
CPU time 0.98 seconds
Started Jan 07 01:01:29 PM PST 24
Finished Jan 07 01:01:58 PM PST 24
Peak memory 208456 kb
Host smart-47e85199-0bfc-4cda-a1bb-17a9b42121fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054208056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3054208056
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1014555227
Short name T541
Test name
Test status
Simulation time 49452494 ps
CPU time 1.27 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 209744 kb
Host smart-f774768b-d7a2-4c38-80f8-4ebf64b050e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014555227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1014555227
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.245854793
Short name T314
Test name
Test status
Simulation time 1028446776 ps
CPU time 8.36 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:26 PM PST 24
Peak memory 218220 kb
Host smart-0ba22aa7-6b7c-4f19-a4e1-cb323ac2bdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245854793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.245854793
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1953874065
Short name T431
Test name
Test status
Simulation time 282247924 ps
CPU time 7.28 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:26 PM PST 24
Peak memory 209660 kb
Host smart-53a1270b-da3b-4611-ac77-4d0e7a897e60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953874065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.1953874065
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3801175486
Short name T301
Test name
Test status
Simulation time 8980472598 ps
CPU time 22.83 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:40 PM PST 24
Peak memory 218292 kb
Host smart-3443d0fb-57ff-4ca2-8402-3be1de360812
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801175486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3801175486
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3734788193
Short name T981
Test name
Test status
Simulation time 1472410421 ps
CPU time 10.56 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 218040 kb
Host smart-c1c92ffc-bf86-46ed-a4c6-7bab7d4e110f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734788193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3734788193
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2304209563
Short name T415
Test name
Test status
Simulation time 617559989 ps
CPU time 8.52 seconds
Started Jan 07 01:02:12 PM PST 24
Finished Jan 07 01:02:26 PM PST 24
Peak memory 213420 kb
Host smart-eeb25754-ce4b-4459-86c6-5bc36ce65a7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304209563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2304209563
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2884996944
Short name T854
Test name
Test status
Simulation time 9842531445 ps
CPU time 39.46 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:56 PM PST 24
Peak memory 283804 kb
Host smart-bb3226d9-a5fc-4241-95ef-ba34424fb5fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884996944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2884996944
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3583207709
Short name T638
Test name
Test status
Simulation time 703641423 ps
CPU time 11.15 seconds
Started Jan 07 01:02:12 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 251160 kb
Host smart-606f38a2-6c0f-451b-9dcd-268efd91dfe5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583207709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3583207709
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1752374764
Short name T58
Test name
Test status
Simulation time 95494302 ps
CPU time 2.05 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 218112 kb
Host smart-3a4db299-0ff8-4fef-9898-211cb3864da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752374764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1752374764
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.4034111277
Short name T561
Test name
Test status
Simulation time 1477881950 ps
CPU time 12.29 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 218124 kb
Host smart-ddc9915a-3ffc-40a5-8ee7-76febbba4f40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034111277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.4034111277
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1594134564
Short name T765
Test name
Test status
Simulation time 219726775 ps
CPU time 8.18 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218164 kb
Host smart-2e1a356f-ef0d-4e05-8c72-8b7b4ea77654
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594134564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1594134564
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2182046335
Short name T623
Test name
Test status
Simulation time 469371074 ps
CPU time 15.57 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:32 PM PST 24
Peak memory 218120 kb
Host smart-ec644753-9cc4-4c9c-98a9-6e32e43ac8a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182046335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2182046335
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1270349730
Short name T848
Test name
Test status
Simulation time 508548999 ps
CPU time 7.35 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:24 PM PST 24
Peak memory 218164 kb
Host smart-104fe67a-ad24-4e2c-b92e-4b8525608876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270349730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1270349730
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.464498343
Short name T382
Test name
Test status
Simulation time 102617932 ps
CPU time 2.23 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 213908 kb
Host smart-ac5cf5be-fcdf-412b-8327-cac59d4098ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464498343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.464498343
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3803824664
Short name T521
Test name
Test status
Simulation time 252986433 ps
CPU time 30.74 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:48 PM PST 24
Peak memory 251064 kb
Host smart-90e6ac5c-11ec-4f18-b563-3fb4f5a578a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803824664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3803824664
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1175020628
Short name T715
Test name
Test status
Simulation time 186423642 ps
CPU time 5.88 seconds
Started Jan 07 01:02:09 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 246516 kb
Host smart-a0ad5f30-657a-4863-9548-061146f05c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175020628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1175020628
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.664616430
Short name T500
Test name
Test status
Simulation time 4997071376 ps
CPU time 108.38 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 273520 kb
Host smart-2bcff753-2817-4a27-8f50-5e67939a103e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664616430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.664616430
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2629553068
Short name T878
Test name
Test status
Simulation time 13030241 ps
CPU time 1.08 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 211500 kb
Host smart-1f0703e7-da8e-4109-a67b-5b2f1f088c89
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629553068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2629553068
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2017879839
Short name T808
Test name
Test status
Simulation time 109190939 ps
CPU time 0.95 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 209724 kb
Host smart-d94f517f-1601-43b2-8db3-5bc067d42b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017879839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2017879839
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2290672813
Short name T493
Test name
Test status
Simulation time 420031015 ps
CPU time 8.35 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 218136 kb
Host smart-55526669-70c1-4fd6-bee1-d41ce38e1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290672813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2290672813
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.785102711
Short name T697
Test name
Test status
Simulation time 163965532 ps
CPU time 2.41 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:21 PM PST 24
Peak memory 209664 kb
Host smart-8bc2b9f4-eb91-4978-965c-09aa1692abf6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785102711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_ac
cess.785102711
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2952919335
Short name T459
Test name
Test status
Simulation time 6864591579 ps
CPU time 39.43 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:58 PM PST 24
Peak memory 219244 kb
Host smart-eb56ee7d-15ff-4195-b55d-b1e26ba5ed09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952919335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2952919335
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2626547119
Short name T184
Test name
Test status
Simulation time 468062631 ps
CPU time 7.16 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218180 kb
Host smart-d077e052-a7b2-4c1a-a0ae-474fca0dd4ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626547119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2626547119
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2351573327
Short name T887
Test name
Test status
Simulation time 728959878 ps
CPU time 3.11 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 212880 kb
Host smart-2acde76d-802a-444c-bed2-3e4279a5def3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351573327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2351573327
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3576631688
Short name T727
Test name
Test status
Simulation time 3092551309 ps
CPU time 32.16 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:50 PM PST 24
Peak memory 251300 kb
Host smart-e2223e52-2fea-4801-b528-3636ee3a7680
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576631688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3576631688
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3547167243
Short name T635
Test name
Test status
Simulation time 776841329 ps
CPU time 15.4 seconds
Started Jan 07 01:02:15 PM PST 24
Finished Jan 07 01:02:36 PM PST 24
Peak memory 251160 kb
Host smart-6696d0c7-dd91-4f94-b340-2bfe9233d61c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547167243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3547167243
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2098644525
Short name T513
Test name
Test status
Simulation time 43638215 ps
CPU time 2.15 seconds
Started Jan 07 01:02:15 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 218288 kb
Host smart-3dba18dd-f6ce-490c-ae94-4448975306fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098644525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2098644525
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.4244923374
Short name T917
Test name
Test status
Simulation time 2150702791 ps
CPU time 31.19 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:48 PM PST 24
Peak memory 219272 kb
Host smart-eceed9a2-dac2-4ac4-b4a0-41c6024ad472
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244923374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4244923374
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3714480116
Short name T857
Test name
Test status
Simulation time 393843793 ps
CPU time 16.35 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:35 PM PST 24
Peak memory 218104 kb
Host smart-e40514f1-25ad-4a75-ae4f-f3e582f35bf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714480116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3714480116
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1781380133
Short name T858
Test name
Test status
Simulation time 323250547 ps
CPU time 12.46 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:31 PM PST 24
Peak memory 218184 kb
Host smart-32aff4fd-b130-4bf8-a803-a171120de54d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781380133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1781380133
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2568363412
Short name T624
Test name
Test status
Simulation time 454930732 ps
CPU time 5.77 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218248 kb
Host smart-0a1263a7-9759-458c-bff8-3d7b9fc9c31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568363412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2568363412
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2140059361
Short name T74
Test name
Test status
Simulation time 23288368 ps
CPU time 1.02 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 212636 kb
Host smart-eee3b2a3-f2d3-4a06-84bf-4e3754e323e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140059361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2140059361
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4267266955
Short name T483
Test name
Test status
Simulation time 365684539 ps
CPU time 20.56 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:39 PM PST 24
Peak memory 251048 kb
Host smart-039bc32b-31d2-4152-8280-9cb945cb170e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267266955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4267266955
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4041530183
Short name T182
Test name
Test status
Simulation time 56762307 ps
CPU time 5.7 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:24 PM PST 24
Peak memory 246296 kb
Host smart-d67789a8-35f1-4f37-9fe4-e096bdb86372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041530183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4041530183
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.995200053
Short name T833
Test name
Test status
Simulation time 9177437913 ps
CPU time 111.07 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:04:10 PM PST 24
Peak memory 270200 kb
Host smart-2689b1a9-4633-4901-9ba6-8e13b66473c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995200053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.995200053
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2188908689
Short name T853
Test name
Test status
Simulation time 23909140 ps
CPU time 0.89 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 208368 kb
Host smart-9b9a565f-e589-4447-a235-c720d7ac4f71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188908689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2188908689
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1323994318
Short name T811
Test name
Test status
Simulation time 30220412 ps
CPU time 0.88 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 209704 kb
Host smart-55d9470d-d02b-44b5-a276-941eeedcd2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323994318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1323994318
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2098347519
Short name T685
Test name
Test status
Simulation time 281074046 ps
CPU time 9.51 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 218228 kb
Host smart-063ef190-8454-4eca-b232-970842911429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098347519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2098347519
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3497548794
Short name T424
Test name
Test status
Simulation time 49397347 ps
CPU time 1.57 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:21 PM PST 24
Peak memory 209608 kb
Host smart-7ca9e108-98a3-4b82-9f5f-44f6c96f2f64
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497548794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_a
ccess.3497548794
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4137752452
Short name T744
Test name
Test status
Simulation time 1575537745 ps
CPU time 33.15 seconds
Started Jan 07 01:02:17 PM PST 24
Finished Jan 07 01:02:55 PM PST 24
Peak memory 218116 kb
Host smart-bb8e7136-2447-4834-af7e-34fa1a8ff9d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137752452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4137752452
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2376034856
Short name T785
Test name
Test status
Simulation time 1286360678 ps
CPU time 7.89 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 218064 kb
Host smart-b7905535-3989-47b7-a05d-3ea34703e029
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376034856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2376034856
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.497016684
Short name T978
Test name
Test status
Simulation time 382742052 ps
CPU time 6.03 seconds
Started Jan 07 01:02:17 PM PST 24
Finished Jan 07 01:02:28 PM PST 24
Peak memory 213436 kb
Host smart-04f0b9f7-e932-4f43-9bda-e65d7ad1e18e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497016684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
497016684
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2661657943
Short name T786
Test name
Test status
Simulation time 4438812317 ps
CPU time 41.04 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:58 PM PST 24
Peak memory 269012 kb
Host smart-30b39a88-1680-4edd-8f7e-cd02b3778043
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661657943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2661657943
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2753269876
Short name T642
Test name
Test status
Simulation time 565564013 ps
CPU time 13.86 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:32 PM PST 24
Peak memory 251112 kb
Host smart-0975ddcb-2bdb-4eb3-af5d-484acd5832a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753269876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2753269876
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2609325159
Short name T341
Test name
Test status
Simulation time 200857566 ps
CPU time 2.78 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:21 PM PST 24
Peak memory 218228 kb
Host smart-81aea31c-3fed-478b-bcd4-44522ab92390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609325159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2609325159
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2070571668
Short name T817
Test name
Test status
Simulation time 1855007213 ps
CPU time 13.6 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:33 PM PST 24
Peak memory 218908 kb
Host smart-070aaa15-2f34-48ce-8720-5a7fea4318d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070571668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2070571668
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3582348346
Short name T603
Test name
Test status
Simulation time 2200271993 ps
CPU time 18.34 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:40 PM PST 24
Peak memory 217824 kb
Host smart-0910f69c-5c8c-4fe5-a4d3-080b8a45e01b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582348346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3582348346
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2045193170
Short name T537
Test name
Test status
Simulation time 406250066 ps
CPU time 6.31 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218096 kb
Host smart-a2ed35a3-599a-471f-9da8-2677f9985499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045193170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2045193170
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1086524457
Short name T440
Test name
Test status
Simulation time 46875201 ps
CPU time 1.98 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:23 PM PST 24
Peak memory 213724 kb
Host smart-bea42189-f6a4-4e2c-b466-0d1a8f8034c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086524457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1086524457
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2532200990
Short name T677
Test name
Test status
Simulation time 291783966 ps
CPU time 24.61 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:46 PM PST 24
Peak memory 251108 kb
Host smart-bf8531c8-8a76-49cf-8151-f8a63daa4db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532200990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2532200990
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1997842078
Short name T498
Test name
Test status
Simulation time 78496834 ps
CPU time 7.93 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:26 PM PST 24
Peak memory 251232 kb
Host smart-24647ee3-4fa7-42cc-b325-64fef8f6fa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997842078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1997842078
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1554733801
Short name T348
Test name
Test status
Simulation time 53232264021 ps
CPU time 121.2 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:04:22 PM PST 24
Peak memory 281308 kb
Host smart-6643fa19-2660-404e-bbb1-eb5932731092
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554733801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1554733801
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1189550290
Short name T610
Test name
Test status
Simulation time 11104716 ps
CPU time 0.76 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 208360 kb
Host smart-5128b7d2-f209-416a-b0fc-55442ffdd96d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189550290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1189550290
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.215407031
Short name T717
Test name
Test status
Simulation time 25291738 ps
CPU time 1.01 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 209500 kb
Host smart-46627d02-1621-4c4f-8226-6f0ec41c39b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215407031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.215407031
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.481387166
Short name T553
Test name
Test status
Simulation time 942419051 ps
CPU time 8.87 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 218148 kb
Host smart-0f692590-9e8f-4c4e-85fe-46764e18bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481387166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.481387166
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3554437501
Short name T900
Test name
Test status
Simulation time 1333483167 ps
CPU time 3.82 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:23 PM PST 24
Peak memory 209792 kb
Host smart-afb30613-9947-407a-9bc4-55b58b313d98
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554437501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_a
ccess.3554437501
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1880309116
Short name T93
Test name
Test status
Simulation time 1321319251 ps
CPU time 37.67 seconds
Started Jan 07 01:02:15 PM PST 24
Finished Jan 07 01:02:58 PM PST 24
Peak memory 218064 kb
Host smart-bde786ef-bd54-403b-bddd-4267a4946732
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880309116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1880309116
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2162266468
Short name T798
Test name
Test status
Simulation time 442515995 ps
CPU time 5.83 seconds
Started Jan 07 01:02:15 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218104 kb
Host smart-62fb797b-47c5-446e-87bc-10836917fb3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162266468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2162266468
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3626944453
Short name T365
Test name
Test status
Simulation time 897616194 ps
CPU time 5.6 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 212920 kb
Host smart-9077f8ef-11d7-47b5-9efa-a6852cb947da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626944453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3626944453
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3611704293
Short name T554
Test name
Test status
Simulation time 1550551645 ps
CPU time 51.49 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:03:10 PM PST 24
Peak memory 267592 kb
Host smart-4c5a1cbb-ed21-4ddb-b8ff-0fa5abb3d19f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611704293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3611704293
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3260306238
Short name T419
Test name
Test status
Simulation time 1108308752 ps
CPU time 15.17 seconds
Started Jan 07 01:02:17 PM PST 24
Finished Jan 07 01:02:37 PM PST 24
Peak memory 251200 kb
Host smart-04dab020-aa26-458e-b44c-a0bf1a0bd10a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260306238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3260306238
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2433979590
Short name T880
Test name
Test status
Simulation time 49032732 ps
CPU time 2.32 seconds
Started Jan 07 01:02:21 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218296 kb
Host smart-35969ed5-1946-47b4-894a-d06ff4c12edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433979590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2433979590
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3070719973
Short name T409
Test name
Test status
Simulation time 392349046 ps
CPU time 16.97 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:35 PM PST 24
Peak memory 218220 kb
Host smart-7a1cfb7c-0818-4fad-9f7c-69a9de532a76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070719973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3070719973
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1509405332
Short name T710
Test name
Test status
Simulation time 1021113112 ps
CPU time 9.23 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 218052 kb
Host smart-67b6fea0-ea9d-49eb-8f1e-7445d6bacfc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509405332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1509405332
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1859803284
Short name T896
Test name
Test status
Simulation time 322479213 ps
CPU time 7.71 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 218164 kb
Host smart-045e050e-db57-4538-867e-ce0f2d877009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859803284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1859803284
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2671051949
Short name T889
Test name
Test status
Simulation time 1606328321 ps
CPU time 13.95 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:33 PM PST 24
Peak memory 218148 kb
Host smart-271b434b-ca0c-4e04-9a48-3b496a38dd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671051949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2671051949
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3248441539
Short name T300
Test name
Test status
Simulation time 282721050 ps
CPU time 1.72 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:23 PM PST 24
Peak memory 213500 kb
Host smart-c8105bbd-a831-4c2d-8154-74053d42b08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248441539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3248441539
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1654916740
Short name T339
Test name
Test status
Simulation time 1156289084 ps
CPU time 24.45 seconds
Started Jan 07 01:02:16 PM PST 24
Finished Jan 07 01:02:46 PM PST 24
Peak memory 251100 kb
Host smart-0ee10be4-10b8-40c4-a896-249f5a723dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654916740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1654916740
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2290360187
Short name T564
Test name
Test status
Simulation time 265972794 ps
CPU time 6.54 seconds
Started Jan 07 01:02:18 PM PST 24
Finished Jan 07 01:02:28 PM PST 24
Peak memory 245924 kb
Host smart-536e5af5-dce4-4976-98e6-afbc7a867ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290360187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2290360187
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3214761254
Short name T568
Test name
Test status
Simulation time 8893654461 ps
CPU time 137.13 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 300284 kb
Host smart-2b6bf890-af27-4251-9f84-256719fda595
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214761254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3214761254
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2019684519
Short name T395
Test name
Test status
Simulation time 251986190 ps
CPU time 1.03 seconds
Started Jan 07 01:02:54 PM PST 24
Finished Jan 07 01:03:26 PM PST 24
Peak memory 209644 kb
Host smart-3b97fdc4-90a7-4442-b779-03ddbda0691d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019684519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2019684519
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1262634271
Short name T407
Test name
Test status
Simulation time 1259129199 ps
CPU time 12.6 seconds
Started Jan 07 01:02:54 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 218148 kb
Host smart-92a25421-3ca2-4656-8f3c-d14b5ea4a8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262634271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1262634271
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.613716012
Short name T953
Test name
Test status
Simulation time 382335288 ps
CPU time 10.67 seconds
Started Jan 07 01:02:54 PM PST 24
Finished Jan 07 01:03:35 PM PST 24
Peak memory 209720 kb
Host smart-b6927967-1ed0-4a61-bdff-78ae6a9444bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613716012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_ac
cess.613716012
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2384045464
Short name T618
Test name
Test status
Simulation time 2837817264 ps
CPU time 78.11 seconds
Started Jan 07 01:03:07 PM PST 24
Finished Jan 07 01:04:50 PM PST 24
Peak memory 219060 kb
Host smart-aeed0aec-c5d4-4288-ae18-2b1896abb6b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384045464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2384045464
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2496793735
Short name T759
Test name
Test status
Simulation time 3990589175 ps
CPU time 13.87 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 219244 kb
Host smart-01717279-9983-4722-b7e4-c2214998d938
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496793735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2496793735
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1257722638
Short name T752
Test name
Test status
Simulation time 275645362 ps
CPU time 2.2 seconds
Started Jan 07 01:02:57 PM PST 24
Finished Jan 07 01:03:30 PM PST 24
Peak memory 212500 kb
Host smart-421bf967-56dd-4080-a6f1-78eb31dddd80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257722638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1257722638
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2150751753
Short name T825
Test name
Test status
Simulation time 5449331799 ps
CPU time 40.17 seconds
Started Jan 07 01:02:51 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 251176 kb
Host smart-1c0c7e2a-d129-4ee3-93c0-c9f3a4686a99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150751753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2150751753
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2653672503
Short name T372
Test name
Test status
Simulation time 1753552963 ps
CPU time 16.75 seconds
Started Jan 07 01:02:52 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 250540 kb
Host smart-8fc95f50-91d8-4e9d-af94-ade2f7c87812
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653672503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2653672503
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2291035732
Short name T496
Test name
Test status
Simulation time 530993766 ps
CPU time 2.33 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 218092 kb
Host smart-4d6e6c39-78ca-4e33-81b4-7cae89d8a3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291035732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2291035732
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.353958869
Short name T777
Test name
Test status
Simulation time 286450371 ps
CPU time 13.39 seconds
Started Jan 07 01:02:51 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 219252 kb
Host smart-aabc7ab3-3a7c-4fd6-8c4c-b4674775682e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353958869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.353958869
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3322712855
Short name T306
Test name
Test status
Simulation time 282868580 ps
CPU time 11.79 seconds
Started Jan 07 01:02:55 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 218232 kb
Host smart-9b7bad3f-7407-4f3b-992a-4b7eb4a82609
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322712855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3322712855
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3926789102
Short name T606
Test name
Test status
Simulation time 476188563 ps
CPU time 16.05 seconds
Started Jan 07 01:02:54 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 218076 kb
Host smart-b7e45356-dd6d-40d0-b0e8-f08bf97db9dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926789102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3926789102
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2156981928
Short name T324
Test name
Test status
Simulation time 230371267 ps
CPU time 8.91 seconds
Started Jan 07 01:03:07 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 218076 kb
Host smart-81a30e46-7d85-41e1-9175-9915200fab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156981928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2156981928
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.442053845
Short name T34
Test name
Test status
Simulation time 140312252 ps
CPU time 2.17 seconds
Started Jan 07 01:02:12 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 213504 kb
Host smart-95bb79e9-41ab-400a-800d-223c57c842e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442053845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.442053845
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3701718212
Short name T678
Test name
Test status
Simulation time 664213696 ps
CPU time 20.71 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:39 PM PST 24
Peak memory 251232 kb
Host smart-e0d11071-d3b1-439d-b956-3ca4d2dca580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701718212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3701718212
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3027081886
Short name T716
Test name
Test status
Simulation time 71857371 ps
CPU time 7.44 seconds
Started Jan 07 01:02:12 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 251156 kb
Host smart-f3f60480-0d10-4356-ba3b-3ac9b429adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027081886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3027081886
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1145948738
Short name T982
Test name
Test status
Simulation time 10719242475 ps
CPU time 186.74 seconds
Started Jan 07 01:02:55 PM PST 24
Finished Jan 07 01:06:33 PM PST 24
Peak memory 283984 kb
Host smart-28fd72b0-e7a0-4d21-b83f-5256b067d0fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145948738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1145948738
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3621930281
Short name T649
Test name
Test status
Simulation time 59088749 ps
CPU time 0.76 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 207980 kb
Host smart-f191d162-08fe-49d2-9960-67f171256add
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621930281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3621930281
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2549428374
Short name T712
Test name
Test status
Simulation time 56289936 ps
CPU time 1.01 seconds
Started Jan 07 01:02:51 PM PST 24
Finished Jan 07 01:03:26 PM PST 24
Peak memory 208496 kb
Host smart-d3ee6fab-6604-428e-9b5c-7c97780eacc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549428374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2549428374
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3263105142
Short name T944
Test name
Test status
Simulation time 2184072725 ps
CPU time 15.34 seconds
Started Jan 07 01:02:56 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 218256 kb
Host smart-0548c132-926c-4771-9f2b-24f240a82d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263105142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3263105142
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1914229114
Short name T533
Test name
Test status
Simulation time 118979626 ps
CPU time 2.05 seconds
Started Jan 07 01:02:52 PM PST 24
Finished Jan 07 01:03:27 PM PST 24
Peak memory 209844 kb
Host smart-e6316515-8caa-4431-8d62-396aa67ec90f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914229114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.1914229114
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1383435607
Short name T408
Test name
Test status
Simulation time 2167532261 ps
CPU time 43.58 seconds
Started Jan 07 01:03:02 PM PST 24
Finished Jan 07 01:04:11 PM PST 24
Peak memory 218124 kb
Host smart-c30e8d19-450c-4fc4-bcc5-b1cbe29e783b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383435607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1383435607
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.158785727
Short name T709
Test name
Test status
Simulation time 766603323 ps
CPU time 5.66 seconds
Started Jan 07 01:02:52 PM PST 24
Finished Jan 07 01:03:30 PM PST 24
Peak memory 218192 kb
Host smart-2d264742-1208-4740-bc79-b311c8be50b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158785727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.158785727
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2495475219
Short name T741
Test name
Test status
Simulation time 378559691 ps
CPU time 4.44 seconds
Started Jan 07 01:02:50 PM PST 24
Finished Jan 07 01:03:29 PM PST 24
Peak memory 213372 kb
Host smart-a0f1b2e5-ebfe-4ad9-b2e5-773a3cfb93d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495475219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2495475219
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.337903774
Short name T824
Test name
Test status
Simulation time 2925866357 ps
CPU time 33.32 seconds
Started Jan 07 01:02:55 PM PST 24
Finished Jan 07 01:03:59 PM PST 24
Peak memory 267424 kb
Host smart-f3233e8b-41c5-484d-99e3-9a28aa52a900
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337903774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.337903774
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2823052097
Short name T600
Test name
Test status
Simulation time 846135388 ps
CPU time 27.82 seconds
Started Jan 07 01:02:53 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 251088 kb
Host smart-2d3dafcb-9616-4f52-91f1-12fa21d9999b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823052097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2823052097
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.4197360587
Short name T674
Test name
Test status
Simulation time 149547794 ps
CPU time 3.81 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:32 PM PST 24
Peak memory 218220 kb
Host smart-00385d0a-10af-4d6b-b993-778f47056c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197360587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.4197360587
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2321410798
Short name T637
Test name
Test status
Simulation time 1002129081 ps
CPU time 10.48 seconds
Started Jan 07 01:03:04 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 218172 kb
Host smart-750eb44b-fcdd-4677-ac84-16333eece9fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321410798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2321410798
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3115105158
Short name T909
Test name
Test status
Simulation time 643806802 ps
CPU time 12.38 seconds
Started Jan 07 01:02:52 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 218096 kb
Host smart-de8a2e8f-333d-4194-b1a5-63ed3cf169e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115105158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3115105158
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.13058495
Short name T551
Test name
Test status
Simulation time 1163696430 ps
CPU time 11.24 seconds
Started Jan 07 01:02:54 PM PST 24
Finished Jan 07 01:03:36 PM PST 24
Peak memory 218156 kb
Host smart-5c4d5c0c-2b24-4038-aecc-b0b49d6d9914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13058495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.13058495
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2483437730
Short name T530
Test name
Test status
Simulation time 37845002 ps
CPU time 1.25 seconds
Started Jan 07 01:02:55 PM PST 24
Finished Jan 07 01:03:27 PM PST 24
Peak memory 213212 kb
Host smart-41e4f3cf-ac6f-45d2-a2f8-eece9b5691a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483437730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2483437730
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1783998261
Short name T375
Test name
Test status
Simulation time 1559759762 ps
CPU time 24.94 seconds
Started Jan 07 01:02:52 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 246240 kb
Host smart-e5c75d67-72f7-4c4d-9940-39481179d97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783998261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1783998261
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2802615661
Short name T658
Test name
Test status
Simulation time 114999431 ps
CPU time 8.22 seconds
Started Jan 07 01:03:08 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 251244 kb
Host smart-8fe87d2e-00bc-4402-9add-e8b3e8ff1313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802615661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2802615661
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4128972398
Short name T930
Test name
Test status
Simulation time 1539653507 ps
CPU time 60.33 seconds
Started Jan 07 01:03:07 PM PST 24
Finished Jan 07 01:04:32 PM PST 24
Peak memory 267432 kb
Host smart-3a796973-5420-4b97-9c27-c63899cff075
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128972398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4128972398
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.491568657
Short name T387
Test name
Test status
Simulation time 44380379 ps
CPU time 0.88 seconds
Started Jan 07 01:02:53 PM PST 24
Finished Jan 07 01:03:26 PM PST 24
Peak memory 208176 kb
Host smart-0b5685c3-c81b-4ea5-ab0d-26f2558cc365
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491568657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.491568657
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2032561309
Short name T567
Test name
Test status
Simulation time 16667804 ps
CPU time 1.08 seconds
Started Jan 07 01:03:06 PM PST 24
Finished Jan 07 01:03:32 PM PST 24
Peak memory 208520 kb
Host smart-0920fefe-cee0-4102-89bd-134840558f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032561309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2032561309
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1524144580
Short name T684
Test name
Test status
Simulation time 266585341 ps
CPU time 11.85 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 218224 kb
Host smart-b9e58dd1-6752-4744-b75e-e32b5e565ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524144580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1524144580
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.843679601
Short name T974
Test name
Test status
Simulation time 145648937 ps
CPU time 4.43 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:32 PM PST 24
Peak memory 209724 kb
Host smart-14fceb96-0cd3-4af1-9697-4e1a5ac6d6b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843679601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_ac
cess.843679601
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2886236522
Short name T499
Test name
Test status
Simulation time 1592775634 ps
CPU time 47.16 seconds
Started Jan 07 01:03:01 PM PST 24
Finished Jan 07 01:04:15 PM PST 24
Peak memory 218100 kb
Host smart-ec42a09d-3612-47cb-a057-1af41622eafd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886236522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2886236522
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1025417159
Short name T760
Test name
Test status
Simulation time 560150568 ps
CPU time 8.04 seconds
Started Jan 07 01:02:53 PM PST 24
Finished Jan 07 01:03:33 PM PST 24
Peak memory 218100 kb
Host smart-bce485b1-5d1b-4021-bf93-75300e47666d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025417159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1025417159
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1793572218
Short name T791
Test name
Test status
Simulation time 1032909986 ps
CPU time 4.64 seconds
Started Jan 07 01:03:07 PM PST 24
Finished Jan 07 01:03:36 PM PST 24
Peak memory 213500 kb
Host smart-7cff8b98-e4bf-404f-89a2-d4180be42e78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793572218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1793572218
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3719887822
Short name T484
Test name
Test status
Simulation time 2283471817 ps
CPU time 70.89 seconds
Started Jan 07 01:02:55 PM PST 24
Finished Jan 07 01:04:36 PM PST 24
Peak memory 267696 kb
Host smart-d5c50248-7bda-4046-929b-9487867c725c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719887822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3719887822
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1225124478
Short name T742
Test name
Test status
Simulation time 957162092 ps
CPU time 19.34 seconds
Started Jan 07 01:03:04 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 251072 kb
Host smart-4d7db57e-c5d3-482d-9a04-2b408295ab13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225124478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1225124478
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3297382520
Short name T358
Test name
Test status
Simulation time 16043592 ps
CPU time 1.66 seconds
Started Jan 07 01:02:48 PM PST 24
Finished Jan 07 01:03:17 PM PST 24
Peak memory 218104 kb
Host smart-8a53cb75-de58-4df4-bca6-f609f2040373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297382520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3297382520
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.521063167
Short name T356
Test name
Test status
Simulation time 751664559 ps
CPU time 10.06 seconds
Started Jan 07 01:02:56 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 218248 kb
Host smart-eecc9437-28e4-4bf7-8754-c396fa99c3a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521063167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.521063167
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1820096858
Short name T449
Test name
Test status
Simulation time 1851603856 ps
CPU time 7.99 seconds
Started Jan 07 01:02:49 PM PST 24
Finished Jan 07 01:03:28 PM PST 24
Peak memory 218168 kb
Host smart-466fd590-99ab-43db-ae1a-1a883a5c8da6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820096858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1820096858
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2273991092
Short name T510
Test name
Test status
Simulation time 356754986 ps
CPU time 14.47 seconds
Started Jan 07 01:02:52 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 218204 kb
Host smart-5133ad65-a61d-4662-b7ec-f284e4b1868e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273991092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2273991092
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3245249160
Short name T912
Test name
Test status
Simulation time 60056047 ps
CPU time 2.32 seconds
Started Jan 07 01:02:53 PM PST 24
Finished Jan 07 01:03:27 PM PST 24
Peak memory 213396 kb
Host smart-1a94fbd6-3e45-4d73-9aeb-9452cc4d0ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245249160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3245249160
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2857409536
Short name T645
Test name
Test status
Simulation time 753433415 ps
CPU time 22.8 seconds
Started Jan 07 01:02:54 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 251064 kb
Host smart-1d1987c8-b6d2-4001-b512-555176400b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857409536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2857409536
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.35229639
Short name T830
Test name
Test status
Simulation time 72530458 ps
CPU time 7.38 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:35 PM PST 24
Peak memory 248160 kb
Host smart-b8e4fa15-794a-4954-8934-fe5ee1780620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35229639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.35229639
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2505218074
Short name T109
Test name
Test status
Simulation time 14826633634 ps
CPU time 224.83 seconds
Started Jan 07 01:03:08 PM PST 24
Finished Jan 07 01:07:17 PM PST 24
Peak memory 277036 kb
Host smart-470a43f3-9965-463d-af73-3e74fe3067b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2505218074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2505218074
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1673263589
Short name T660
Test name
Test status
Simulation time 31485875 ps
CPU time 0.83 seconds
Started Jan 07 01:02:52 PM PST 24
Finished Jan 07 01:03:26 PM PST 24
Peak memory 208168 kb
Host smart-20a9c5a7-1ad6-4279-9f55-aec06d6d0051
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673263589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1673263589
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2636647108
Short name T386
Test name
Test status
Simulation time 19940562 ps
CPU time 0.93 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:36 PM PST 24
Peak memory 209640 kb
Host smart-9916e2af-4512-48fc-9e78-f6c266d463ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636647108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2636647108
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3973330107
Short name T345
Test name
Test status
Simulation time 594709040 ps
CPU time 15.41 seconds
Started Jan 07 01:03:06 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 218180 kb
Host smart-7d8cfbcf-4635-4fa9-9684-8e9c5cd699d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973330107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3973330107
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3135155534
Short name T950
Test name
Test status
Simulation time 2892515376 ps
CPU time 8.98 seconds
Started Jan 07 01:03:04 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 209648 kb
Host smart-7ed35aa3-2c5a-4c2f-b8f6-f70e06a9e344
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135155534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.3135155534
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.767486136
Short name T834
Test name
Test status
Simulation time 8489726821 ps
CPU time 33.21 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:04:10 PM PST 24
Peak memory 218436 kb
Host smart-55c72cfc-36bf-4836-ae96-d9d95953e1a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767486136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.767486136
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2614757358
Short name T927
Test name
Test status
Simulation time 126590836 ps
CPU time 3.17 seconds
Started Jan 07 01:03:10 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 218208 kb
Host smart-44ac10c9-2e79-4350-9db5-3db7c487fe3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614757358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2614757358
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3041825783
Short name T976
Test name
Test status
Simulation time 1963927096 ps
CPU time 11.3 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 213428 kb
Host smart-77a03800-6f3f-44e1-8e36-ae9063fa4568
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041825783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3041825783
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2945678271
Short name T960
Test name
Test status
Simulation time 18352837182 ps
CPU time 72.54 seconds
Started Jan 07 01:03:09 PM PST 24
Finished Jan 07 01:04:46 PM PST 24
Peak memory 283892 kb
Host smart-4498cebc-e62e-4d87-961f-f44d3401ceed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945678271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2945678271
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3301230430
Short name T420
Test name
Test status
Simulation time 3562949104 ps
CPU time 15.78 seconds
Started Jan 07 01:03:11 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 251104 kb
Host smart-fd9df673-354e-4776-8238-6b30cff3568c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301230430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3301230430
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2229599018
Short name T418
Test name
Test status
Simulation time 13967186 ps
CPU time 1.38 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:30 PM PST 24
Peak memory 218108 kb
Host smart-400e3ea6-d614-480f-8e02-390f8c3fe172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229599018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2229599018
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1933724544
Short name T838
Test name
Test status
Simulation time 376998720 ps
CPU time 15.41 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 219224 kb
Host smart-0ccc1ec2-96db-4bfc-8638-e7bfedf0f44d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933724544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1933724544
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.924817050
Short name T580
Test name
Test status
Simulation time 908979931 ps
CPU time 14.99 seconds
Started Jan 07 01:03:12 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 218100 kb
Host smart-d8188d80-07e4-40b4-977e-7ce686afc205
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924817050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.924817050
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1624493572
Short name T470
Test name
Test status
Simulation time 325546044 ps
CPU time 10.48 seconds
Started Jan 07 01:03:06 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 218140 kb
Host smart-72bb8fc0-98ef-4993-bd97-f23ac203b452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624493572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1624493572
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1026983613
Short name T661
Test name
Test status
Simulation time 1772026041 ps
CPU time 8.68 seconds
Started Jan 07 01:03:07 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 218160 kb
Host smart-71d51659-86da-4dd7-8dfc-21000b422e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026983613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1026983613
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1125157621
Short name T773
Test name
Test status
Simulation time 24987160 ps
CPU time 2 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:30 PM PST 24
Peak memory 213808 kb
Host smart-d5d035e0-0b1b-4faf-aa5f-6a52392385e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125157621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1125157621
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3493441250
Short name T694
Test name
Test status
Simulation time 419626727 ps
CPU time 27.31 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 251132 kb
Host smart-22042da7-bae4-4cd0-88af-794681513a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493441250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3493441250
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1259599319
Short name T920
Test name
Test status
Simulation time 120465360 ps
CPU time 7.88 seconds
Started Jan 07 01:03:04 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 251232 kb
Host smart-c29b9169-d8d7-4147-83bf-2da4c9eabe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259599319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1259599319
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.597242874
Short name T776
Test name
Test status
Simulation time 4105698353 ps
CPU time 100.92 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:05:18 PM PST 24
Peak memory 251312 kb
Host smart-3801c25a-ba18-4e30-9884-91d0f233e141
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597242874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.597242874
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3048929637
Short name T374
Test name
Test status
Simulation time 16691227 ps
CPU time 0.96 seconds
Started Jan 07 01:03:05 PM PST 24
Finished Jan 07 01:03:32 PM PST 24
Peak memory 212672 kb
Host smart-5d8103b4-6b2c-4d1f-9aa1-761bacbfd0a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048929637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3048929637
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3254988734
Short name T560
Test name
Test status
Simulation time 1603241323 ps
CPU time 15.56 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 218232 kb
Host smart-6001ce9b-f278-415c-bf94-09510f48677c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254988734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3254988734
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3694583565
Short name T519
Test name
Test status
Simulation time 1369091429 ps
CPU time 3.06 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 209692 kb
Host smart-22168562-7218-495e-b158-d8ab2dac2a73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694583565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.3694583565
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.808049239
Short name T445
Test name
Test status
Simulation time 2743539246 ps
CPU time 30.01 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 218140 kb
Host smart-ff81038d-0a88-4986-9dee-238a3e6da967
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808049239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.808049239
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3012237331
Short name T732
Test name
Test status
Simulation time 1064608957 ps
CPU time 7.76 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 218036 kb
Host smart-4f5db036-ad01-4bcb-979d-b13b43888e87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012237331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3012237331
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1282226914
Short name T604
Test name
Test status
Simulation time 272834605 ps
CPU time 7.73 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 213404 kb
Host smart-cddb9f64-4611-4240-a212-31e3e4a87c35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282226914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1282226914
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3327863522
Short name T780
Test name
Test status
Simulation time 24154950228 ps
CPU time 40.95 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:04:18 PM PST 24
Peak memory 275812 kb
Host smart-e704238e-7f22-4115-b474-09e5e5a7449e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327863522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3327863522
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1815679427
Short name T354
Test name
Test status
Simulation time 674412625 ps
CPU time 23.52 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 251156 kb
Host smart-df1c6029-f914-4a88-8903-61d87eb242a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815679427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1815679427
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.195980860
Short name T675
Test name
Test status
Simulation time 150893050 ps
CPU time 3.78 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 218224 kb
Host smart-ead08673-abca-4e97-acd0-45bcb95a6f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195980860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.195980860
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.4057307955
Short name T586
Test name
Test status
Simulation time 717521881 ps
CPU time 9.71 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 219076 kb
Host smart-5f3a3b9e-f075-4cbc-b8b5-eaef9c58b8c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057307955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.4057307955
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3076671595
Short name T507
Test name
Test status
Simulation time 410956179 ps
CPU time 8.63 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 218148 kb
Host smart-570e0ae4-302b-4dee-88f1-da5ee8ffa5ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076671595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3076671595
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.4141592613
Short name T640
Test name
Test status
Simulation time 685822080 ps
CPU time 13.22 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 217984 kb
Host smart-a3f01042-76d0-4dd4-a5be-c3d22a772d0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141592613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
4141592613
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1247319827
Short name T740
Test name
Test status
Simulation time 1122155105 ps
CPU time 9.06 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218188 kb
Host smart-1b94edf4-dd41-477c-8823-2e17dc4f2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247319827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1247319827
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1050113697
Short name T518
Test name
Test status
Simulation time 195261891 ps
CPU time 2.74 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 214396 kb
Host smart-ec9d8add-a4fb-43df-ae0b-8d79bed9c039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050113697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1050113697
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.680674365
Short name T423
Test name
Test status
Simulation time 294848443 ps
CPU time 21.34 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 251128 kb
Host smart-bcfab465-22c8-4fd5-b292-fafeb5374dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680674365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.680674365
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.164859879
Short name T379
Test name
Test status
Simulation time 109672772 ps
CPU time 7.91 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 251236 kb
Host smart-e310bb16-3fb4-452e-a74b-390cd7835caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164859879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.164859879
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.497144642
Short name T112
Test name
Test status
Simulation time 20091164541 ps
CPU time 103.28 seconds
Started Jan 07 01:03:28 PM PST 24
Finished Jan 07 01:05:25 PM PST 24
Peak memory 270324 kb
Host smart-cdc41bd4-9cdc-472f-bbda-3292c0fee92c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497144642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.497144642
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2383528086
Short name T30
Test name
Test status
Simulation time 32794279 ps
CPU time 0.73 seconds
Started Jan 07 01:03:20 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 207860 kb
Host smart-e8868771-696a-4ad5-b139-944ceb93fdde
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383528086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2383528086
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.916292640
Short name T67
Test name
Test status
Simulation time 167566778 ps
CPU time 1.1 seconds
Started Jan 07 01:03:09 PM PST 24
Finished Jan 07 01:03:34 PM PST 24
Peak memory 209720 kb
Host smart-c0308322-2865-4618-9dc3-78a09a6a1236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916292640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.916292640
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2711415693
Short name T45
Test name
Test status
Simulation time 436427858 ps
CPU time 16.92 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:59 PM PST 24
Peak memory 218080 kb
Host smart-05798402-f820-4711-aad8-33f2a76fa23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711415693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2711415693
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.4235277778
Short name T25
Test name
Test status
Simulation time 726494167 ps
CPU time 2.65 seconds
Started Jan 07 01:03:04 PM PST 24
Finished Jan 07 01:03:31 PM PST 24
Peak memory 209604 kb
Host smart-8322b260-7498-4697-9664-beba77643d03
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235277778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.4235277778
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.582756136
Short name T517
Test name
Test status
Simulation time 1770509366 ps
CPU time 33.29 seconds
Started Jan 07 01:02:51 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 218136 kb
Host smart-a8e6d40a-6f19-435f-9a01-df30a9d6fecb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582756136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.582756136
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.345493504
Short name T545
Test name
Test status
Simulation time 349377533 ps
CPU time 10.85 seconds
Started Jan 07 01:03:14 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 218180 kb
Host smart-3252fa7d-e61f-4006-9034-31af8c5f7fae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345493504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.345493504
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2097991511
Short name T650
Test name
Test status
Simulation time 367667754 ps
CPU time 5.64 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 213768 kb
Host smart-46982b7e-e164-45ce-a6cc-05e432043c3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097991511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2097991511
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2653625910
Short name T904
Test name
Test status
Simulation time 990616053 ps
CPU time 37.36 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:04:09 PM PST 24
Peak memory 251404 kb
Host smart-ee97d505-aa27-464d-a5d2-97cc6d859c63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653625910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2653625910
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1913188097
Short name T711
Test name
Test status
Simulation time 1210576297 ps
CPU time 22.54 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 251160 kb
Host smart-25531b02-9743-4f34-9458-ddb4af0d88af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913188097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1913188097
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2772938660
Short name T388
Test name
Test status
Simulation time 176134887 ps
CPU time 4.22 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 218196 kb
Host smart-41a027b5-5f19-4ca2-ba2a-da1574d8dd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772938660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2772938660
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3405331004
Short name T538
Test name
Test status
Simulation time 249273136 ps
CPU time 9.51 seconds
Started Jan 07 01:03:03 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 218288 kb
Host smart-b61652e2-3ec9-40d3-9bf9-e2ee17ec4a97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405331004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3405331004
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.458829336
Short name T879
Test name
Test status
Simulation time 865118202 ps
CPU time 18.88 seconds
Started Jan 07 01:03:04 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 218264 kb
Host smart-5d5d7dc6-546c-4827-879a-f897e1ff8f03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458829336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.458829336
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2834563030
Short name T400
Test name
Test status
Simulation time 192393852 ps
CPU time 6.11 seconds
Started Jan 07 01:03:05 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 218120 kb
Host smart-60f04c3e-36dc-4885-948e-f532c380c08a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834563030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2834563030
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3426389354
Short name T810
Test name
Test status
Simulation time 6505981335 ps
CPU time 17.55 seconds
Started Jan 07 01:03:20 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 218304 kb
Host smart-d3041741-8592-464d-986e-9261da192465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426389354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3426389354
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1706810333
Short name T972
Test name
Test status
Simulation time 50767528 ps
CPU time 2.05 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 213920 kb
Host smart-d3d15eb1-60af-4c72-8645-902687c22946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706810333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1706810333
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.759186345
Short name T333
Test name
Test status
Simulation time 697537028 ps
CPU time 17.56 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 251152 kb
Host smart-eb0d5722-e205-45b7-89ac-e51f262eb7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759186345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.759186345
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2348349342
Short name T639
Test name
Test status
Simulation time 418226881 ps
CPU time 9.65 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 251068 kb
Host smart-ac495417-cb7d-4153-8627-ec3dcf9ff064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348349342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2348349342
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3798690689
Short name T910
Test name
Test status
Simulation time 36514106299 ps
CPU time 156.56 seconds
Started Jan 07 01:03:04 PM PST 24
Finished Jan 07 01:06:08 PM PST 24
Peak memory 247740 kb
Host smart-c587511a-8f41-4d27-bfaa-f9cecb26fbf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798690689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3798690689
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1481873945
Short name T587
Test name
Test status
Simulation time 18813739 ps
CPU time 0.88 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 208248 kb
Host smart-fc8cb4ee-e899-48b0-bb36-45d9a0e854b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481873945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1481873945
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2611685703
Short name T397
Test name
Test status
Simulation time 55975503 ps
CPU time 1.08 seconds
Started Jan 07 01:01:16 PM PST 24
Finished Jan 07 01:01:47 PM PST 24
Peak memory 209736 kb
Host smart-522d5308-1996-4eb9-a197-a573955da617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611685703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2611685703
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.946142355
Short name T861
Test name
Test status
Simulation time 12505003 ps
CPU time 0.83 seconds
Started Jan 07 01:01:36 PM PST 24
Finished Jan 07 01:02:02 PM PST 24
Peak memory 209420 kb
Host smart-31ed9cf7-e989-4d71-a16f-a72cf0f4edd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946142355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.946142355
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1441001428
Short name T873
Test name
Test status
Simulation time 1308037168 ps
CPU time 11.01 seconds
Started Jan 07 01:01:37 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 218236 kb
Host smart-1ed1e29f-965d-452d-8242-ccd895d4fd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441001428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1441001428
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1845373342
Short name T967
Test name
Test status
Simulation time 2548134687 ps
CPU time 15.6 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:28 PM PST 24
Peak memory 209628 kb
Host smart-a6d66372-54c6-4773-9fd5-6982c25b17e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845373342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ac
cess.1845373342
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2983265016
Short name T724
Test name
Test status
Simulation time 2405189207 ps
CPU time 63.82 seconds
Started Jan 07 01:01:23 PM PST 24
Finished Jan 07 01:02:53 PM PST 24
Peak memory 218240 kb
Host smart-604b37d2-0e54-4f65-99fc-04c7086375af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983265016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2983265016
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3575195129
Short name T801
Test name
Test status
Simulation time 267419447 ps
CPU time 3.76 seconds
Started Jan 07 01:01:44 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 209768 kb
Host smart-8aed9182-45b8-4d0d-993f-d786d8a64472
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575195129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.3575195129
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3674438520
Short name T303
Test name
Test status
Simulation time 2041302510 ps
CPU time 14.48 seconds
Started Jan 07 01:01:16 PM PST 24
Finished Jan 07 01:02:17 PM PST 24
Peak memory 218092 kb
Host smart-c5d9dab0-056e-4232-ae6e-e23f8fc6ee44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674438520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3674438520
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3267190710
Short name T802
Test name
Test status
Simulation time 3974200167 ps
CPU time 20.47 seconds
Started Jan 07 01:01:44 PM PST 24
Finished Jan 07 01:02:28 PM PST 24
Peak memory 213912 kb
Host smart-8ecd3903-ee6a-41ba-a0fc-8c46c8ae98ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267190710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3267190710
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1656433310
Short name T913
Test name
Test status
Simulation time 298710585 ps
CPU time 2.47 seconds
Started Jan 07 01:01:43 PM PST 24
Finished Jan 07 01:02:10 PM PST 24
Peak memory 212836 kb
Host smart-16e8df37-737f-4404-bfae-01e2a41bab44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656433310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1656433310
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2414871495
Short name T672
Test name
Test status
Simulation time 5956928245 ps
CPU time 52.79 seconds
Started Jan 07 01:01:45 PM PST 24
Finished Jan 07 01:03:01 PM PST 24
Peak memory 251068 kb
Host smart-76dff31e-a3ad-4f06-bfa2-bc6e0ade8e04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414871495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2414871495
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2606629250
Short name T5
Test name
Test status
Simulation time 711030828 ps
CPU time 11.96 seconds
Started Jan 07 01:01:40 PM PST 24
Finished Jan 07 01:02:17 PM PST 24
Peak memory 251072 kb
Host smart-cc4fcb34-a59b-4e99-bb60-5461c7e62c07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606629250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2606629250
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3275678039
Short name T687
Test name
Test status
Simulation time 197609547 ps
CPU time 3.53 seconds
Started Jan 07 01:01:40 PM PST 24
Finished Jan 07 01:02:08 PM PST 24
Peak memory 218224 kb
Host smart-7196e50c-80cc-4486-8c9e-5dcc9b885f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275678039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3275678039
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2746771528
Short name T882
Test name
Test status
Simulation time 285411213 ps
CPU time 18.25 seconds
Started Jan 07 01:01:43 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 217972 kb
Host smart-6f0fce2c-098a-4a80-9e68-e8df2a649e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746771528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2746771528
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1897655316
Short name T37
Test name
Test status
Simulation time 1482252150 ps
CPU time 9.25 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 218116 kb
Host smart-21b50966-1906-4d18-ae45-9857dbd65895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897655316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1897655316
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4232493085
Short name T726
Test name
Test status
Simulation time 523607737 ps
CPU time 12.19 seconds
Started Jan 07 01:01:35 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 218180 kb
Host smart-d8e83f65-0656-48a9-8dab-74efbf1f1616
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232493085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4232493085
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2052211364
Short name T693
Test name
Test status
Simulation time 1517085616 ps
CPU time 9.86 seconds
Started Jan 07 01:01:36 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 218124 kb
Host smart-3fe6daa9-2267-4cad-bdf2-46505569053d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052211364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
052211364
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3104521724
Short name T659
Test name
Test status
Simulation time 251853482 ps
CPU time 8.12 seconds
Started Jan 07 01:01:23 PM PST 24
Finished Jan 07 01:01:57 PM PST 24
Peak memory 218076 kb
Host smart-88398f29-527b-4709-b74c-84c8270a23b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104521724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3104521724
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.134348777
Short name T941
Test name
Test status
Simulation time 28464777 ps
CPU time 1.24 seconds
Started Jan 07 01:01:40 PM PST 24
Finished Jan 07 01:02:06 PM PST 24
Peak memory 213276 kb
Host smart-ca90d37f-d420-4067-b518-1c12d153f843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134348777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.134348777
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.177253359
Short name T320
Test name
Test status
Simulation time 461347136 ps
CPU time 21.74 seconds
Started Jan 07 01:01:40 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 251148 kb
Host smart-ac88daa8-8558-4e0a-9cc6-66d8a6d0d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177253359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.177253359
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3588472887
Short name T751
Test name
Test status
Simulation time 187786806 ps
CPU time 3.58 seconds
Started Jan 07 01:01:38 PM PST 24
Finished Jan 07 01:02:07 PM PST 24
Peak memory 220908 kb
Host smart-7dcfa36e-fd45-48b5-92c7-9c60d9e4c543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588472887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3588472887
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2228345747
Short name T438
Test name
Test status
Simulation time 26109184512 ps
CPU time 207.46 seconds
Started Jan 07 01:01:50 PM PST 24
Finished Jan 07 01:05:38 PM PST 24
Peak memory 221008 kb
Host smart-a3806429-bd45-4378-bca3-96131cb594d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228345747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2228345747
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2432837214
Short name T453
Test name
Test status
Simulation time 16422685 ps
CPU time 0.84 seconds
Started Jan 07 01:01:37 PM PST 24
Finished Jan 07 01:02:09 PM PST 24
Peak memory 208152 kb
Host smart-69ad3454-7510-4b85-a04a-5cd22f87bd93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432837214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2432837214
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2630171010
Short name T739
Test name
Test status
Simulation time 63743631 ps
CPU time 0.96 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 208232 kb
Host smart-7dbb1929-3142-4295-8da9-bf2d006bcddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630171010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2630171010
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2682160421
Short name T359
Test name
Test status
Simulation time 325164569 ps
CPU time 14.8 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 218140 kb
Host smart-3e52c7ba-1174-48e1-a98a-a9176de26159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682160421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2682160421
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2301108831
Short name T427
Test name
Test status
Simulation time 39425422 ps
CPU time 1.97 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 218356 kb
Host smart-8937dcd7-ad66-4173-b8ff-36b9c97f4470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301108831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2301108831
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.475713724
Short name T11
Test name
Test status
Simulation time 573567223 ps
CPU time 12.38 seconds
Started Jan 07 01:03:14 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 219172 kb
Host smart-10b75936-d7e0-4d8f-bd40-0ad4efc5a5e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475713724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.475713724
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.207621016
Short name T293
Test name
Test status
Simulation time 316433328 ps
CPU time 13.02 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218164 kb
Host smart-5344388c-b55e-462c-8e0e-9a9d49be3afe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207621016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.207621016
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3655547026
Short name T451
Test name
Test status
Simulation time 377885466 ps
CPU time 6.48 seconds
Started Jan 07 01:03:14 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 218020 kb
Host smart-4d8f21e1-8406-4bca-a6c4-f01c8c359bb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655547026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3655547026
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1702219128
Short name T48
Test name
Test status
Simulation time 878363097 ps
CPU time 13.56 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218140 kb
Host smart-3db61b98-13dc-4de3-8318-04e9b2772e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702219128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1702219128
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1253015509
Short name T630
Test name
Test status
Simulation time 889130121 ps
CPU time 2.81 seconds
Started Jan 07 01:03:02 PM PST 24
Finished Jan 07 01:03:31 PM PST 24
Peak memory 214220 kb
Host smart-aa76b353-9f0b-4af7-b62c-bf98eb95784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253015509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1253015509
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3128365529
Short name T980
Test name
Test status
Simulation time 2497000426 ps
CPU time 23.45 seconds
Started Jan 07 01:03:06 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 251240 kb
Host smart-7a18a3ea-6b4e-4719-89ad-5e46d3980723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128365529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3128365529
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3182814435
Short name T328
Test name
Test status
Simulation time 49675677 ps
CPU time 7.14 seconds
Started Jan 07 01:03:08 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 246812 kb
Host smart-1b6596d1-a0d7-43a1-9f3d-526e5a051c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182814435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3182814435
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3115879062
Short name T80
Test name
Test status
Simulation time 12183212890 ps
CPU time 117.28 seconds
Started Jan 07 01:03:14 PM PST 24
Finished Jan 07 01:05:32 PM PST 24
Peak memory 251156 kb
Host smart-7d7625e1-1a2a-4758-8695-1944ade1034a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115879062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3115879062
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1378200151
Short name T349
Test name
Test status
Simulation time 15669530 ps
CPU time 0.8 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 209460 kb
Host smart-20d2f75e-7e27-4160-8d27-40e42b824a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378200151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1378200151
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3954166066
Short name T540
Test name
Test status
Simulation time 609499564 ps
CPU time 12.75 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218224 kb
Host smart-a8875fd4-410a-4f67-8f35-4fa3cf25e122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954166066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3954166066
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1337682437
Short name T582
Test name
Test status
Simulation time 656960522 ps
CPU time 4.8 seconds
Started Jan 07 01:03:21 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 209380 kb
Host smart-ce994562-1797-4f77-97af-06fd717ab7a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337682437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.1337682437
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1748632523
Short name T414
Test name
Test status
Simulation time 394880891 ps
CPU time 3.41 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 218232 kb
Host smart-e6d71390-4a2b-4290-aa29-943d3cbece28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748632523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1748632523
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1206702346
Short name T894
Test name
Test status
Simulation time 374898986 ps
CPU time 12.11 seconds
Started Jan 07 01:03:27 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 218060 kb
Host smart-fd9f06cb-c8b9-4e70-a040-c0dca56e30c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206702346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1206702346
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2379271893
Short name T593
Test name
Test status
Simulation time 319073738 ps
CPU time 9.85 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 217996 kb
Host smart-9c1557ba-e0b2-4c01-9502-434aad3d4bfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379271893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2379271893
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.451069209
Short name T745
Test name
Test status
Simulation time 360476835 ps
CPU time 8.38 seconds
Started Jan 07 01:03:21 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 217800 kb
Host smart-4e1ce922-ddce-4be4-a868-5d1fc49eb125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451069209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.451069209
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.668709805
Short name T701
Test name
Test status
Simulation time 310715824 ps
CPU time 9.4 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 218084 kb
Host smart-2ffaabfc-7feb-4776-8d8f-056a8dcc5c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668709805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.668709805
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1505053369
Short name T426
Test name
Test status
Simulation time 79936852 ps
CPU time 2.82 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 214116 kb
Host smart-c3a40cad-008b-453e-9f91-a2476eb14471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505053369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1505053369
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3806102278
Short name T566
Test name
Test status
Simulation time 728937014 ps
CPU time 32.57 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:04:11 PM PST 24
Peak memory 251116 kb
Host smart-5722d249-0cc6-460b-ba1e-23980a2724d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806102278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3806102278
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1963490408
Short name T949
Test name
Test status
Simulation time 74544352 ps
CPU time 6.21 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 246152 kb
Host smart-e61fbd78-36ef-4d03-9296-ee5ade576925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963490408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1963490408
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4018946602
Short name T629
Test name
Test status
Simulation time 4685035086 ps
CPU time 125.01 seconds
Started Jan 07 01:03:20 PM PST 24
Finished Jan 07 01:05:44 PM PST 24
Peak memory 251356 kb
Host smart-259dcbd6-7ad9-4546-a3ec-662e9766a60e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018946602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4018946602
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3455091462
Short name T512
Test name
Test status
Simulation time 29762303 ps
CPU time 0.76 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 207888 kb
Host smart-a3c23d22-9a3e-4930-b765-28417225cb95
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455091462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3455091462
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1889814389
Short name T367
Test name
Test status
Simulation time 85179008 ps
CPU time 0.94 seconds
Started Jan 07 01:03:04 PM PST 24
Finished Jan 07 01:03:32 PM PST 24
Peak memory 208348 kb
Host smart-7921d07b-3483-497f-9f90-7100b31dad3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889814389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1889814389
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1102352462
Short name T378
Test name
Test status
Simulation time 421942622 ps
CPU time 17.49 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 218052 kb
Host smart-63c3a8cd-21f9-4265-9a02-66d082b9f180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102352462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1102352462
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2117056548
Short name T17
Test name
Test status
Simulation time 1107410713 ps
CPU time 6.2 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:51 PM PST 24
Peak memory 209708 kb
Host smart-7f4912eb-3931-4e42-835a-5905cf8c49b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117056548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.2117056548
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3263988573
Short name T318
Test name
Test status
Simulation time 343041729 ps
CPU time 3.5 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 218144 kb
Host smart-87045d55-8fe5-4f10-8b77-c7dbe97a6ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263988573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3263988573
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1728055550
Short name T883
Test name
Test status
Simulation time 284216170 ps
CPU time 15.39 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 219100 kb
Host smart-699e0f1d-7ec6-4b25-9c3e-9703e51f763e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728055550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1728055550
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2942935029
Short name T589
Test name
Test status
Simulation time 387510112 ps
CPU time 14.91 seconds
Started Jan 07 01:03:38 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 218168 kb
Host smart-cf385cf4-e6a0-4e8e-8a13-5c9b079fb568
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942935029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2942935029
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1541763850
Short name T951
Test name
Test status
Simulation time 350103310 ps
CPU time 9.27 seconds
Started Jan 07 01:03:20 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218112 kb
Host smart-e47d896b-cb36-4852-b6f2-76cfb3c60b3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541763850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1541763850
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1518427045
Short name T647
Test name
Test status
Simulation time 235992886 ps
CPU time 8.83 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:51 PM PST 24
Peak memory 218092 kb
Host smart-6dd0408a-8a5c-4b43-821f-fc9d4ab39b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518427045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1518427045
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.549402519
Short name T901
Test name
Test status
Simulation time 44232972 ps
CPU time 2.14 seconds
Started Jan 07 01:03:20 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 213976 kb
Host smart-132af2f8-3a38-4ae4-962e-084ca6c20ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549402519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.549402519
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.867112122
Short name T656
Test name
Test status
Simulation time 298482686 ps
CPU time 27.07 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 251072 kb
Host smart-a76cc227-6c09-4e63-8f98-c472118990c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867112122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.867112122
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3247534651
Short name T897
Test name
Test status
Simulation time 160949238 ps
CPU time 6.5 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 246272 kb
Host smart-a833bdd6-34b7-4e02-b028-d32a635cc0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247534651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3247534651
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2183411264
Short name T474
Test name
Test status
Simulation time 11288252 ps
CPU time 0.74 seconds
Started Jan 07 01:03:31 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 208100 kb
Host smart-a50dfa87-8d3b-4846-b534-c37019bb4b42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183411264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2183411264
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2077595579
Short name T842
Test name
Test status
Simulation time 38791574 ps
CPU time 1.03 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 209736 kb
Host smart-6bea0562-085c-4b64-98d8-646ba3251588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077595579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2077595579
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2021977005
Short name T643
Test name
Test status
Simulation time 848803057 ps
CPU time 12.95 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:51 PM PST 24
Peak memory 218240 kb
Host smart-d4ef9b1f-9e67-4c6a-98a6-2a9021665ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021977005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2021977005
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2647577919
Short name T599
Test name
Test status
Simulation time 2863123555 ps
CPU time 6.71 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 209764 kb
Host smart-3c274fac-b58a-474a-8ad3-aad01ba3ea42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647577919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.2647577919
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3252267254
Short name T940
Test name
Test status
Simulation time 126880605 ps
CPU time 3.05 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 218136 kb
Host smart-4d8f0790-7b5f-491a-ad05-d9eb3372ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252267254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3252267254
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.375582123
Short name T789
Test name
Test status
Simulation time 319960638 ps
CPU time 9.97 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 219184 kb
Host smart-cc5fd963-c97b-4ae8-b31f-5dba7ed431ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375582123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.375582123
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.401348412
Short name T605
Test name
Test status
Simulation time 521467352 ps
CPU time 8.71 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 218168 kb
Host smart-73ad479f-a9f3-4dd3-a7a6-8b1e71679d5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401348412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.401348412
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1057806380
Short name T370
Test name
Test status
Simulation time 356395443 ps
CPU time 8.71 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 218184 kb
Host smart-4f9b7db4-8b33-410d-9ac1-4149cc2ecbcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057806380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1057806380
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1667596919
Short name T326
Test name
Test status
Simulation time 913458684 ps
CPU time 9.13 seconds
Started Jan 07 01:03:14 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 218200 kb
Host smart-5c1574ce-7fc6-44f9-9876-a44e8a444fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667596919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1667596919
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.992132281
Short name T465
Test name
Test status
Simulation time 563998087 ps
CPU time 2.9 seconds
Started Jan 07 01:02:55 PM PST 24
Finished Jan 07 01:03:29 PM PST 24
Peak memory 214652 kb
Host smart-49cff424-897a-4179-ae71-b5d273966b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992132281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.992132281
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2997706998
Short name T814
Test name
Test status
Simulation time 3289237507 ps
CPU time 29.78 seconds
Started Jan 07 01:02:52 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 251048 kb
Host smart-ba92f1ab-258f-4bba-a338-5338c81cec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997706998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2997706998
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2201520712
Short name T410
Test name
Test status
Simulation time 57527868 ps
CPU time 7.07 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 250668 kb
Host smart-c9591ee3-674f-4d0a-8528-61471fdf1bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201520712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2201520712
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1700823265
Short name T557
Test name
Test status
Simulation time 30277855577 ps
CPU time 76.73 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:04:55 PM PST 24
Peak memory 251296 kb
Host smart-0003bdd7-afcc-472b-b4f5-69ece3a62a7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700823265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1700823265
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3201021539
Short name T870
Test name
Test status
Simulation time 103240209 ps
CPU time 0.87 seconds
Started Jan 07 01:03:07 PM PST 24
Finished Jan 07 01:03:33 PM PST 24
Peak memory 208328 kb
Host smart-61be63e0-c908-4f20-9511-bdf447130e8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201021539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3201021539
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3085847024
Short name T733
Test name
Test status
Simulation time 149613354 ps
CPU time 1.06 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:36 PM PST 24
Peak memory 209704 kb
Host smart-5dccbb67-34cb-432d-b1f4-c6838e5030e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085847024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3085847024
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.4220388092
Short name T550
Test name
Test status
Simulation time 1245278488 ps
CPU time 10.11 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218200 kb
Host smart-79e44fd2-c6af-4ffe-be9d-df609fde561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220388092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.4220388092
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.648643625
Short name T767
Test name
Test status
Simulation time 294350630 ps
CPU time 2.17 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 209616 kb
Host smart-3b2e0548-9606-4a02-8ac1-fc6850471860
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648643625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_ac
cess.648643625
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.4182946292
Short name T439
Test name
Test status
Simulation time 42245407 ps
CPU time 2.87 seconds
Started Jan 07 01:03:12 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 218140 kb
Host smart-5559528d-d5f6-4f39-81f8-67e97f77d0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182946292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.4182946292
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.341663245
Short name T815
Test name
Test status
Simulation time 1206092078 ps
CPU time 15.7 seconds
Started Jan 07 01:03:14 PM PST 24
Finished Jan 07 01:03:51 PM PST 24
Peak memory 218128 kb
Host smart-c6f9c2cf-2b0a-448d-9392-85a15d6bb3bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341663245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.341663245
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2016110274
Short name T591
Test name
Test status
Simulation time 989447092 ps
CPU time 10.95 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218112 kb
Host smart-de0e3482-2944-4c1c-b1c0-64ab9144a8cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016110274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2016110274
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3365228336
Short name T13
Test name
Test status
Simulation time 244663021 ps
CPU time 6.42 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 218200 kb
Host smart-b08d19ca-a5e5-46db-afc0-388ab926cfdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365228336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3365228336
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.12847325
Short name T812
Test name
Test status
Simulation time 351154583 ps
CPU time 7.87 seconds
Started Jan 07 01:03:11 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 218168 kb
Host smart-fbca4860-db80-4076-91da-97b8b5887e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12847325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.12847325
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1996869763
Short name T309
Test name
Test status
Simulation time 133551304 ps
CPU time 1.93 seconds
Started Jan 07 01:03:12 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 213504 kb
Host smart-de972d16-bd83-4f6d-96cf-c2d04606f72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996869763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1996869763
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.139361784
Short name T297
Test name
Test status
Simulation time 493922989 ps
CPU time 21.01 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 251140 kb
Host smart-c54755fb-843e-4877-995d-1227e6a60e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139361784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.139361784
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.229096939
Short name T330
Test name
Test status
Simulation time 1910888729 ps
CPU time 6.93 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 247100 kb
Host smart-1e69455b-ce61-4e86-a536-394eeff97239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229096939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.229096939
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1627817171
Short name T662
Test name
Test status
Simulation time 11546428933 ps
CPU time 157.22 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:06:14 PM PST 24
Peak memory 243052 kb
Host smart-70af636f-9742-4172-acd2-123b64b6632c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627817171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1627817171
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1556276924
Short name T543
Test name
Test status
Simulation time 13874209 ps
CPU time 1.1 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 211540 kb
Host smart-3c7dabc6-e2ff-4ca0-b8f1-90f22c07edd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556276924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1556276924
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2452898427
Short name T94
Test name
Test status
Simulation time 221498633 ps
CPU time 0.91 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 209728 kb
Host smart-f7f48ba2-7458-4823-a83f-9cfda4834877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452898427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2452898427
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1027435371
Short name T874
Test name
Test status
Simulation time 483480315 ps
CPU time 12.36 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 218140 kb
Host smart-40fa004b-56ce-4efe-bb1a-3c3cefa96cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027435371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1027435371
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3771661952
Short name T22
Test name
Test status
Simulation time 717619049 ps
CPU time 10.55 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 209664 kb
Host smart-33b744c8-869a-4493-9176-113c7808d3af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771661952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_a
ccess.3771661952
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.95558388
Short name T911
Test name
Test status
Simulation time 88886682 ps
CPU time 2.5 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 218240 kb
Host smart-88616598-b27a-40e1-b1a6-39f329d901b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95558388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.95558388
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.390130633
Short name T430
Test name
Test status
Simulation time 790168243 ps
CPU time 17.25 seconds
Started Jan 07 01:03:12 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 219128 kb
Host smart-5a421062-70a5-449a-814b-6b6cfd4f965f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390130633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.390130633
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3599149765
Short name T33
Test name
Test status
Simulation time 798572974 ps
CPU time 17.12 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 218140 kb
Host smart-9f8b08a5-52c9-45bb-a8ae-555dc0be3b58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599149765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3599149765
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2973145998
Short name T371
Test name
Test status
Simulation time 2459132487 ps
CPU time 8.58 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 218236 kb
Host smart-6934862d-5547-4284-8011-81d46a9fb027
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973145998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2973145998
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.535385989
Short name T749
Test name
Test status
Simulation time 1394158425 ps
CPU time 12.73 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218208 kb
Host smart-1010a545-ace8-4c3f-9754-1316d8631733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535385989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.535385989
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2506290231
Short name T644
Test name
Test status
Simulation time 18801142 ps
CPU time 1.45 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 213372 kb
Host smart-14ce368c-e0e2-4533-a328-a7f59090aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506290231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2506290231
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3650187295
Short name T688
Test name
Test status
Simulation time 353436735 ps
CPU time 30.83 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 251176 kb
Host smart-e9fdf5e5-e5c9-4dcd-a827-3bc9be20c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650187295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3650187295
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3966443943
Short name T782
Test name
Test status
Simulation time 210825532 ps
CPU time 7.74 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 251180 kb
Host smart-52d6e05f-95d0-49ed-bdf5-b158f0232483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966443943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3966443943
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2852248841
Short name T15
Test name
Test status
Simulation time 7311710346 ps
CPU time 39.87 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:04:17 PM PST 24
Peak memory 251300 kb
Host smart-23fe4e9e-86b0-4f30-ae4b-ac18deb2691c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852248841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2852248841
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2609884021
Short name T779
Test name
Test status
Simulation time 33901226 ps
CPU time 0.83 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:37 PM PST 24
Peak memory 208400 kb
Host smart-d306c5b3-dfbf-44d4-b787-b6bb6d8370fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609884021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2609884021
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2995390612
Short name T64
Test name
Test status
Simulation time 20492138 ps
CPU time 1.21 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 208440 kb
Host smart-924b2890-e833-4a31-9cda-e074631c4965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995390612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2995390612
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1004289236
Short name T597
Test name
Test status
Simulation time 1970923157 ps
CPU time 13.98 seconds
Started Jan 07 01:03:14 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218180 kb
Host smart-a339a0a3-623d-4d05-9cca-d8d662d7d10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004289236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1004289236
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2198602616
Short name T6
Test name
Test status
Simulation time 6298990300 ps
CPU time 3.89 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 209740 kb
Host smart-595aaebe-9d69-41a3-9f7d-25f07f44671c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198602616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.2198602616
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1718246556
Short name T702
Test name
Test status
Simulation time 129288691 ps
CPU time 2.33 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 218252 kb
Host smart-0e5b9232-c9a8-4e77-b998-1f936d03cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718246556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1718246556
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1195676629
Short name T946
Test name
Test status
Simulation time 1788778279 ps
CPU time 13.15 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 218180 kb
Host smart-c794fc15-526e-4f62-af06-6e5b20028cca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195676629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1195676629
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3765035662
Short name T747
Test name
Test status
Simulation time 1437014326 ps
CPU time 10.69 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218152 kb
Host smart-cbcfdc38-fc8d-420f-95bd-4e18c94ce589
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765035662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3765035662
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.300383347
Short name T631
Test name
Test status
Simulation time 838266309 ps
CPU time 7.81 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 218172 kb
Host smart-2ab9e35d-b085-4bcd-bd75-e2ef00f203ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300383347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.300383347
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.640082662
Short name T849
Test name
Test status
Simulation time 1784112512 ps
CPU time 8.51 seconds
Started Jan 07 01:03:11 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 218072 kb
Host smart-41e0f818-3030-416e-bcb6-9bb0df9c01d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640082662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.640082662
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.4043417368
Short name T69
Test name
Test status
Simulation time 50818806 ps
CPU time 3.09 seconds
Started Jan 07 01:03:12 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 214340 kb
Host smart-d64578fe-4226-4791-a6a7-c40b1242df27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043417368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.4043417368
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1443277877
Short name T321
Test name
Test status
Simulation time 854435496 ps
CPU time 17.99 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 250964 kb
Host smart-23a66a74-1bdb-407d-a9fc-53e0619662ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443277877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1443277877
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1575927209
Short name T778
Test name
Test status
Simulation time 127404400 ps
CPU time 7.04 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 250680 kb
Host smart-efc4aec7-fe71-4884-9633-e612c79a7101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575927209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1575927209
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.210260178
Short name T487
Test name
Test status
Simulation time 6104132447 ps
CPU time 69.49 seconds
Started Jan 07 01:03:11 PM PST 24
Finished Jan 07 01:04:44 PM PST 24
Peak memory 278184 kb
Host smart-4eaa21c6-8784-4241-be5d-0ba4db37a1e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210260178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.210260178
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1971134842
Short name T863
Test name
Test status
Simulation time 41070643 ps
CPU time 0.83 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 208352 kb
Host smart-690dcf51-1b4e-49b5-a370-67b8fe1f9db9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971134842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1971134842
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2068036238
Short name T899
Test name
Test status
Simulation time 17377642 ps
CPU time 0.91 seconds
Started Jan 07 01:03:23 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 208400 kb
Host smart-9a0fcd44-a684-40c3-8af9-616a39c16fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068036238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2068036238
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.4278223506
Short name T846
Test name
Test status
Simulation time 1151454270 ps
CPU time 11.6 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218036 kb
Host smart-e1a68de9-4f3a-4e7d-9d6d-c05b8366d896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278223506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.4278223506
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2135241528
Short name T871
Test name
Test status
Simulation time 441027167 ps
CPU time 5.27 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 209732 kb
Host smart-1b4105a2-8100-4456-a032-840b7caa20ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135241528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.2135241528
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3953763081
Short name T608
Test name
Test status
Simulation time 246932671 ps
CPU time 2.6 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 218192 kb
Host smart-c7f825f7-3547-4ec9-9c42-6af7735577d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953763081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3953763081
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.606810513
Short name T622
Test name
Test status
Simulation time 353893422 ps
CPU time 9.02 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 218212 kb
Host smart-40c73e3a-ff77-469e-a76e-5c91b437eb54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606810513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.606810513
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.903385007
Short name T469
Test name
Test status
Simulation time 1604908563 ps
CPU time 11.67 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218156 kb
Host smart-8ea72a74-9b74-4c38-9072-a77bed391ceb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903385007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.903385007
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3867802723
Short name T399
Test name
Test status
Simulation time 180417314 ps
CPU time 5.8 seconds
Started Jan 07 01:03:24 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 218196 kb
Host smart-34842727-b75c-4bdf-83fa-0a9a61f6bba2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867802723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3867802723
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3990834923
Short name T893
Test name
Test status
Simulation time 886864610 ps
CPU time 6.69 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 218188 kb
Host smart-a20d309c-eb1d-4334-bf83-cd11a09c1eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990834923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3990834923
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3081075102
Short name T63
Test name
Test status
Simulation time 114700646 ps
CPU time 2.6 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 213912 kb
Host smart-b0963734-59d8-4336-86f2-c306a62f9dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081075102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3081075102
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.712615340
Short name T509
Test name
Test status
Simulation time 260788640 ps
CPU time 29.57 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:04:06 PM PST 24
Peak memory 251104 kb
Host smart-fc3e6f40-8ec9-4c69-a548-b83e01898262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712615340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.712615340
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.826422093
Short name T970
Test name
Test status
Simulation time 112489609 ps
CPU time 6.26 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 246768 kb
Host smart-b701adbc-9d80-43f6-b3bd-2f6d998faf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826422093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.826422093
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1564018332
Short name T485
Test name
Test status
Simulation time 1241905520 ps
CPU time 26.93 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 219080 kb
Host smart-76817b61-a811-4c46-a6e8-7da9859b0252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564018332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1564018332
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3653883161
Short name T31
Test name
Test status
Simulation time 12932717 ps
CPU time 0.78 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:36 PM PST 24
Peak memory 208480 kb
Host smart-31346bd7-9b11-453d-acf8-0c8ff8f84f7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653883161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3653883161
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2138503187
Short name T686
Test name
Test status
Simulation time 18562443 ps
CPU time 0.85 seconds
Started Jan 07 01:03:27 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 209480 kb
Host smart-fb49674e-c1cb-420c-9efe-6d7654653b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138503187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2138503187
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2720814457
Short name T41
Test name
Test status
Simulation time 1355849435 ps
CPU time 13.67 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 218196 kb
Host smart-31613183-b704-411a-ad93-e48c33436fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720814457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2720814457
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.518050770
Short name T575
Test name
Test status
Simulation time 560331299 ps
CPU time 5.93 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:51 PM PST 24
Peak memory 209560 kb
Host smart-1f587f4b-4e0f-4046-a5ec-5d0cb4b7440b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518050770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_ac
cess.518050770
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2515511700
Short name T718
Test name
Test status
Simulation time 63607518 ps
CPU time 2.17 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 218196 kb
Host smart-68264c64-647f-4263-8e77-a1eddf750eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515511700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2515511700
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2436717079
Short name T450
Test name
Test status
Simulation time 1329453023 ps
CPU time 13.33 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 219148 kb
Host smart-eb37b93f-a655-4dc5-aae9-c38378793a00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436717079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2436717079
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3162932554
Short name T619
Test name
Test status
Simulation time 245885656 ps
CPU time 8.62 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 218040 kb
Host smart-57cdfc2a-5712-4d63-be65-ba227ed886be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162932554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3162932554
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2095501292
Short name T476
Test name
Test status
Simulation time 221732668 ps
CPU time 6.82 seconds
Started Jan 07 01:03:31 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 218168 kb
Host smart-890a74ba-1ea6-4e15-bb27-67f6ea9cf690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095501292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2095501292
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3964695922
Short name T632
Test name
Test status
Simulation time 312202057 ps
CPU time 8.68 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 218184 kb
Host smart-9faee710-9eda-471c-88fa-dce140cbfc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964695922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3964695922
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.828946084
Short name T66
Test name
Test status
Simulation time 61183521 ps
CPU time 1.78 seconds
Started Jan 07 01:03:15 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 213096 kb
Host smart-c0bdc57c-dd07-40f6-8e6f-f9b1656ecb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828946084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.828946084
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2620620170
Short name T82
Test name
Test status
Simulation time 1463539839 ps
CPU time 31.21 seconds
Started Jan 07 01:03:20 PM PST 24
Finished Jan 07 01:04:10 PM PST 24
Peak memory 250832 kb
Host smart-88799064-ba3f-4491-bedd-493bd69d0e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620620170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2620620170
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2772422856
Short name T821
Test name
Test status
Simulation time 89528138 ps
CPU time 9.9 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 246720 kb
Host smart-179b726c-1fa5-4c1a-988e-905e9e32a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772422856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2772422856
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1395374934
Short name T441
Test name
Test status
Simulation time 16294642349 ps
CPU time 133.29 seconds
Started Jan 07 01:03:24 PM PST 24
Finished Jan 07 01:05:53 PM PST 24
Peak memory 272072 kb
Host smart-d5323edb-8c41-44f1-8e56-029bfa416ae2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395374934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1395374934
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1704403537
Short name T108
Test name
Test status
Simulation time 31488492986 ps
CPU time 144.88 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:06:03 PM PST 24
Peak memory 281348 kb
Host smart-169a7f9c-f2be-46e2-b4d9-3489f857692d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1704403537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1704403537
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1844835806
Short name T26
Test name
Test status
Simulation time 11747502 ps
CPU time 0.9 seconds
Started Jan 07 01:03:25 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 208116 kb
Host smart-eb927b78-dccc-487b-8765-9b13a060e6ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844835806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1844835806
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3609844363
Short name T571
Test name
Test status
Simulation time 68308071 ps
CPU time 0.91 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 209752 kb
Host smart-e6535aad-29e8-4702-9c8d-b6478b0209f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609844363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3609844363
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.810401882
Short name T636
Test name
Test status
Simulation time 5098403138 ps
CPU time 11.76 seconds
Started Jan 07 01:03:25 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 218260 kb
Host smart-77a172df-4ece-4254-a85d-9ff0e7faf192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810401882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.810401882
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2532121080
Short name T353
Test name
Test status
Simulation time 82445495 ps
CPU time 1.62 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 209692 kb
Host smart-18ecaa0a-1e38-4ba8-a252-4d029bf7bd9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532121080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.2532121080
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.740436889
Short name T837
Test name
Test status
Simulation time 88863322 ps
CPU time 2.15 seconds
Started Jan 07 01:03:35 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218236 kb
Host smart-11564c51-8842-495d-992f-16dc80a2ac81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740436889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.740436889
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.879345218
Short name T590
Test name
Test status
Simulation time 1881030982 ps
CPU time 21.37 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 218212 kb
Host smart-56b25663-3284-441c-b4bf-5f505ff99836
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879345218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.879345218
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.738407407
Short name T292
Test name
Test status
Simulation time 1966227662 ps
CPU time 16.05 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:04:01 PM PST 24
Peak memory 218144 kb
Host smart-e5d6d9cc-d03c-4aa4-a76e-883cc11933f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738407407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.738407407
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3198980016
Short name T954
Test name
Test status
Simulation time 1425071386 ps
CPU time 9.55 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 218176 kb
Host smart-ae307f72-38c1-49d1-8c27-c830857ec3aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198980016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3198980016
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.285229396
Short name T335
Test name
Test status
Simulation time 2230135804 ps
CPU time 14.08 seconds
Started Jan 07 01:03:31 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 218300 kb
Host smart-884553b7-5345-463a-98bf-fddb5d80e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285229396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.285229396
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3390449834
Short name T977
Test name
Test status
Simulation time 38874166 ps
CPU time 1.59 seconds
Started Jan 07 01:03:27 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 213692 kb
Host smart-5c74c5b7-5c63-4b9e-a15d-95a665994ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390449834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3390449834
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2144993074
Short name T458
Test name
Test status
Simulation time 400866028 ps
CPU time 33.14 seconds
Started Jan 07 01:03:25 PM PST 24
Finished Jan 07 01:04:13 PM PST 24
Peak memory 251132 kb
Host smart-a029df34-6b43-4b94-9255-c6205ccf0cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144993074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2144993074
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2539758969
Short name T417
Test name
Test status
Simulation time 111347468 ps
CPU time 6.88 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 249924 kb
Host smart-d1743098-e63d-48ba-b4b6-bae110333b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539758969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2539758969
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3379314930
Short name T784
Test name
Test status
Simulation time 9645974798 ps
CPU time 51.5 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:04:36 PM PST 24
Peak memory 226372 kb
Host smart-eb8c439f-142a-40ed-9383-298eb6fd0de0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379314930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3379314930
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4147889579
Short name T311
Test name
Test status
Simulation time 37711004 ps
CPU time 0.84 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 208112 kb
Host smart-36a778f9-75e7-43f2-8ae9-88185bb9fcd5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147889579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4147889579
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1687510030
Short name T394
Test name
Test status
Simulation time 14621201 ps
CPU time 0.99 seconds
Started Jan 07 01:01:29 PM PST 24
Finished Jan 07 01:01:58 PM PST 24
Peak memory 209684 kb
Host smart-15708787-88f9-4d0a-b609-309dee46b564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687510030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1687510030
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1046104461
Short name T177
Test name
Test status
Simulation time 118165013 ps
CPU time 0.8 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 209360 kb
Host smart-9d4b1e78-2292-4c13-ad98-c5b9f5be914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046104461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1046104461
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3721527766
Short name T746
Test name
Test status
Simulation time 1324154898 ps
CPU time 15.49 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:28 PM PST 24
Peak memory 218176 kb
Host smart-dbf55a4f-b4b9-4a17-8460-b314a3c09b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721527766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3721527766
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1294188599
Short name T641
Test name
Test status
Simulation time 350016674 ps
CPU time 6.16 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 209628 kb
Host smart-ace0dd53-eac6-403b-bab5-0b72f4e84722
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294188599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.1294188599
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.322483816
Short name T92
Test name
Test status
Simulation time 25434699957 ps
CPU time 47.9 seconds
Started Jan 07 01:01:32 PM PST 24
Finished Jan 07 01:02:47 PM PST 24
Peak memory 219252 kb
Host smart-75b1f287-fee7-41ab-8589-d3517f719edd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322483816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.322483816
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1521489011
Short name T735
Test name
Test status
Simulation time 614812652 ps
CPU time 16.22 seconds
Started Jan 07 01:01:56 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 217940 kb
Host smart-77351a19-2a91-4f3a-858c-a6a7ae291783
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521489011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.1521489011
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1850781403
Short name T406
Test name
Test status
Simulation time 160863137 ps
CPU time 3.13 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:16 PM PST 24
Peak memory 218192 kb
Host smart-0e228f84-d367-4750-9e6e-685121e96fc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850781403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1850781403
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2933453292
Short name T592
Test name
Test status
Simulation time 5447671870 ps
CPU time 32.96 seconds
Started Jan 07 01:01:34 PM PST 24
Finished Jan 07 01:02:33 PM PST 24
Peak memory 214040 kb
Host smart-836c1aeb-aead-464e-9725-9066e42781e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933453292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2933453292
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2161528950
Short name T525
Test name
Test status
Simulation time 259970102 ps
CPU time 4.41 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:16 PM PST 24
Peak memory 213376 kb
Host smart-4b052937-3887-409d-8ee3-21f8b4e71275
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161528950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2161528950
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.577947822
Short name T573
Test name
Test status
Simulation time 9918929565 ps
CPU time 55.33 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:03:08 PM PST 24
Peak memory 279764 kb
Host smart-a25f023d-0cab-4eab-a1b1-c7eea85348a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577947822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.577947822
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.300129606
Short name T843
Test name
Test status
Simulation time 655317571 ps
CPU time 13.26 seconds
Started Jan 07 01:01:41 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 251132 kb
Host smart-554e342e-759a-43d1-bbd8-fae2a46b51d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300129606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.300129606
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3555383790
Short name T494
Test name
Test status
Simulation time 94910537 ps
CPU time 2.06 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 218224 kb
Host smart-c829f95c-3b40-4f83-a4ee-3b6b5059e392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555383790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3555383790
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1798594192
Short name T447
Test name
Test status
Simulation time 854381413 ps
CPU time 5.75 seconds
Started Jan 07 01:01:32 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 214032 kb
Host smart-b63aa1aa-5291-48d4-ba77-9fee80ea5fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798594192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1798594192
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.4269194301
Short name T59
Test name
Test status
Simulation time 297107223 ps
CPU time 35.26 seconds
Started Jan 07 01:01:56 PM PST 24
Finished Jan 07 01:02:48 PM PST 24
Peak memory 268448 kb
Host smart-88598268-4359-4885-b275-067edabf03f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269194301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.4269194301
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.813761556
Short name T489
Test name
Test status
Simulation time 596858731 ps
CPU time 16.12 seconds
Started Jan 07 01:01:32 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 219264 kb
Host smart-19a74fe1-322e-47c2-841c-49e760b9c086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813761556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.813761556
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.378290179
Short name T850
Test name
Test status
Simulation time 570137221 ps
CPU time 7.7 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 218076 kb
Host smart-df7ae51a-c613-43ec-9b10-6ad561cb1a7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378290179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.378290179
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4139806497
Short name T881
Test name
Test status
Simulation time 345486414 ps
CPU time 8.65 seconds
Started Jan 07 01:01:26 PM PST 24
Finished Jan 07 01:02:10 PM PST 24
Peak memory 218240 kb
Host smart-c0106303-c076-4a25-9b69-6406f5f41da2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139806497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
139806497
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4145541811
Short name T473
Test name
Test status
Simulation time 744409676 ps
CPU time 9.74 seconds
Started Jan 07 01:01:32 PM PST 24
Finished Jan 07 01:02:08 PM PST 24
Peak memory 218236 kb
Host smart-b8ea4e37-b2dc-4486-b07b-3e858a66d46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145541811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4145541811
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1578348032
Short name T657
Test name
Test status
Simulation time 43780412 ps
CPU time 1.65 seconds
Started Jan 07 01:01:22 PM PST 24
Finished Jan 07 01:01:51 PM PST 24
Peak memory 213464 kb
Host smart-d07a7596-c88a-4a6f-8b26-90ecf3763525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578348032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1578348032
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1566709881
Short name T304
Test name
Test status
Simulation time 254518013 ps
CPU time 17.16 seconds
Started Jan 07 01:01:37 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 250828 kb
Host smart-217a2311-8ca4-4eff-a1ff-fa3c796f7c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566709881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1566709881
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.959631272
Short name T696
Test name
Test status
Simulation time 88252720 ps
CPU time 7.39 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 246304 kb
Host smart-91b477b8-785e-4d3a-9d73-f3b8f651ada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959631272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.959631272
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1832667923
Short name T721
Test name
Test status
Simulation time 29072969197 ps
CPU time 207.58 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:05:40 PM PST 24
Peak memory 283916 kb
Host smart-fb610306-d28b-48d8-b537-af5c3aea7056
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832667923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1832667923
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1506593978
Short name T478
Test name
Test status
Simulation time 36706590 ps
CPU time 0.72 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 207948 kb
Host smart-b7c792f9-c964-4ccd-a734-a56a273d2559
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506593978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1506593978
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3326194858
Short name T581
Test name
Test status
Simulation time 47146607 ps
CPU time 1.03 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 209808 kb
Host smart-c1c58751-ac00-4cbd-86b1-15779d47e55a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326194858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3326194858
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2920664395
Short name T10
Test name
Test status
Simulation time 1997180111 ps
CPU time 7.16 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 218228 kb
Host smart-b4c511e3-0ae4-49e3-a6fe-e774587288f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920664395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2920664395
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.107366091
Short name T482
Test name
Test status
Simulation time 1267479941 ps
CPU time 15.27 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 209704 kb
Host smart-cd8e63ff-f356-4636-b949-e226cf5bbf34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107366091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_ac
cess.107366091
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2912383757
Short name T851
Test name
Test status
Simulation time 77208354 ps
CPU time 3.26 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 218148 kb
Host smart-8175136f-38da-4c77-b530-606fd46eea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912383757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2912383757
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3001804478
Short name T319
Test name
Test status
Simulation time 709252199 ps
CPU time 19.37 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 218052 kb
Host smart-45869550-1240-4450-943f-3cd1930e55de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001804478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3001804478
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.630917382
Short name T294
Test name
Test status
Simulation time 1180394358 ps
CPU time 10.05 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218052 kb
Host smart-d29485dd-d338-453d-9599-02e9c7ea1339
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630917382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.630917382
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.199821375
Short name T750
Test name
Test status
Simulation time 489023876 ps
CPU time 11.61 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218176 kb
Host smart-6be52361-7da9-4fe1-b051-20e40123dc9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199821375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.199821375
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1559791218
Short name T49
Test name
Test status
Simulation time 719610291 ps
CPU time 12.97 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 218204 kb
Host smart-9ebff15a-4f2e-469c-a6ce-582bdcef031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559791218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1559791218
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2101345269
Short name T835
Test name
Test status
Simulation time 588656044 ps
CPU time 2.51 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 214060 kb
Host smart-75d0662e-b274-48b0-8ea4-2bec3f05b548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101345269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2101345269
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1064408539
Short name T588
Test name
Test status
Simulation time 352286877 ps
CPU time 24.28 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 250984 kb
Host smart-0f4aa43a-715b-4e7f-9e44-0936cb6c3bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064408539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1064408539
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3019137739
Short name T317
Test name
Test status
Simulation time 146583309 ps
CPU time 6.47 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 249932 kb
Host smart-59f8fed0-7685-44bf-a8c7-aa66f5afb369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019137739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3019137739
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1091304957
Short name T984
Test name
Test status
Simulation time 9596791121 ps
CPU time 141.93 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:05:59 PM PST 24
Peak memory 252784 kb
Host smart-85676753-3aad-4bf4-bda0-90e67f1c4fe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091304957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1091304957
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3262536155
Short name T29
Test name
Test status
Simulation time 37023023 ps
CPU time 0.96 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 211460 kb
Host smart-b1c783be-e56f-4c8d-92be-338024874f23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262536155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3262536155
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.414995216
Short name T504
Test name
Test status
Simulation time 109998412 ps
CPU time 0.82 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 209452 kb
Host smart-954befa8-f7e6-410a-9545-5f9eab978ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414995216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.414995216
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1658802127
Short name T555
Test name
Test status
Simulation time 409602980 ps
CPU time 10.75 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 218180 kb
Host smart-6a3ec785-5073-4489-bc1a-ae523e455f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658802127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1658802127
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1219330656
Short name T23
Test name
Test status
Simulation time 972298155 ps
CPU time 5.12 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 209600 kb
Host smart-82866afc-8fa6-4bc8-a982-3f7829307940
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219330656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.1219330656
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.743101846
Short name T105
Test name
Test status
Simulation time 50998696 ps
CPU time 2.47 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 218084 kb
Host smart-cd0c579c-551d-435d-a98b-1822dabe535b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743101846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.743101846
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2886754265
Short name T392
Test name
Test status
Simulation time 2542537657 ps
CPU time 25.59 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:04:04 PM PST 24
Peak memory 219292 kb
Host smart-957bfa15-f711-411b-ad5c-408fb9d7269e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886754265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2886754265
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.961240405
Short name T54
Test name
Test status
Simulation time 170707574 ps
CPU time 8.65 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 218068 kb
Host smart-f069101c-901f-46c5-b2b2-a3a464b245f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961240405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.961240405
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4102057188
Short name T923
Test name
Test status
Simulation time 374605284 ps
CPU time 7.77 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 218184 kb
Host smart-73dce8dc-03c2-4f60-aa71-f4ad981b8a10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102057188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
4102057188
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3719223143
Short name T731
Test name
Test status
Simulation time 735353645 ps
CPU time 6.31 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218076 kb
Host smart-511e4963-2f15-4be1-8bbb-e3c2b6be94b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719223143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3719223143
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4036332799
Short name T813
Test name
Test status
Simulation time 42937091 ps
CPU time 2.4 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 213924 kb
Host smart-0f59fbfe-3db6-4c4d-aff1-774a898b0e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036332799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4036332799
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3261947937
Short name T891
Test name
Test status
Simulation time 272423068 ps
CPU time 22.43 seconds
Started Jan 07 01:03:24 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 251052 kb
Host smart-0a51cc19-d07e-4ca6-9ca7-7808a8963a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261947937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3261947937
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1229776705
Short name T516
Test name
Test status
Simulation time 272337130 ps
CPU time 7.09 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 251120 kb
Host smart-df3018c5-ef2f-4a6e-8daf-003a24733722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229776705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1229776705
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3916635052
Short name T666
Test name
Test status
Simulation time 167523604249 ps
CPU time 253.53 seconds
Started Jan 07 01:03:20 PM PST 24
Finished Jan 07 01:07:53 PM PST 24
Peak memory 316876 kb
Host smart-7e56b884-3539-4aef-83e3-efd6ed2157f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916635052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3916635052
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.208308452
Short name T480
Test name
Test status
Simulation time 44702193 ps
CPU time 0.75 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 208144 kb
Host smart-23b88ceb-c232-4620-9362-d7e5f7d21785
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208308452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.208308452
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.994834874
Short name T936
Test name
Test status
Simulation time 50352163 ps
CPU time 0.83 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 208324 kb
Host smart-c4f5e912-af60-49d7-a30f-20251e7e8b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994834874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.994834874
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.224684423
Short name T790
Test name
Test status
Simulation time 1820266562 ps
CPU time 15.16 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 218180 kb
Host smart-afaa53c3-3a3d-454d-b775-d9bae1883edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224684423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.224684423
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2084269549
Short name T21
Test name
Test status
Simulation time 499525810 ps
CPU time 2.02 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 209604 kb
Host smart-0430abf9-3bc7-4f88-a749-c857573db58c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084269549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.2084269549
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.36303035
Short name T338
Test name
Test status
Simulation time 56511530 ps
CPU time 1.6 seconds
Started Jan 07 01:03:38 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218184 kb
Host smart-d6354aeb-3f59-415c-818c-b3263de58d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36303035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.36303035
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4224563962
Short name T754
Test name
Test status
Simulation time 434552135 ps
CPU time 20.01 seconds
Started Jan 07 01:03:31 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 218224 kb
Host smart-0356b696-f0d6-46dc-8545-27b56ecc0d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224563962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4224563962
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.386605148
Short name T329
Test name
Test status
Simulation time 616707372 ps
CPU time 9.96 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 218072 kb
Host smart-784a20c1-551a-4241-9c02-cffa2e22ddfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386605148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.386605148
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2723635965
Short name T107
Test name
Test status
Simulation time 821227277 ps
CPU time 7.6 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 218116 kb
Host smart-6333515f-4288-480b-857f-e4f0a401b914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723635965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2723635965
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.422853396
Short name T689
Test name
Test status
Simulation time 312279734 ps
CPU time 7.81 seconds
Started Jan 07 01:03:28 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218136 kb
Host smart-1dbeaf3b-f84b-4d62-85ab-91916984b3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422853396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.422853396
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3086903403
Short name T902
Test name
Test status
Simulation time 137784947 ps
CPU time 3.47 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 214516 kb
Host smart-0d2eaee9-a4b1-4a06-ab7f-f9f0805b7555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086903403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3086903403
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2602109286
Short name T935
Test name
Test status
Simulation time 3035016771 ps
CPU time 32.59 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 251208 kb
Host smart-ec1671f2-d72f-489a-863e-f56c8a880971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602109286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2602109286
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.724892245
Short name T822
Test name
Test status
Simulation time 698606948 ps
CPU time 4.79 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 222084 kb
Host smart-d1d2ef2c-ff07-4369-88f5-32bdfda9ebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724892245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.724892245
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.963146414
Short name T313
Test name
Test status
Simulation time 5320441263 ps
CPU time 140.59 seconds
Started Jan 07 01:03:35 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 251112 kb
Host smart-ea98a94a-8ff0-4557-af23-1cac7f88d74b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963146414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.963146414
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4192725450
Short name T448
Test name
Test status
Simulation time 16523881 ps
CPU time 0.81 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 208176 kb
Host smart-bdce8f58-f34b-461e-8f5e-2b5984eaa70e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192725450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.4192725450
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1151082461
Short name T614
Test name
Test status
Simulation time 40799127 ps
CPU time 0.96 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 208492 kb
Host smart-83f6aaf1-38f5-4bfa-99dc-36ff7ff33b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151082461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1151082461
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.438800448
Short name T943
Test name
Test status
Simulation time 541957988 ps
CPU time 16.64 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 218268 kb
Host smart-d109971a-46d1-4f00-a2e5-559a7839129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438800448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.438800448
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2995254777
Short name T676
Test name
Test status
Simulation time 2024375454 ps
CPU time 11.89 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 209732 kb
Host smart-5a059a2a-0c5a-42f0-a8e8-202f29314a23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995254777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.2995254777
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2333967545
Short name T437
Test name
Test status
Simulation time 31073621 ps
CPU time 1.8 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 218132 kb
Host smart-c86bdde0-3d86-4d34-bac0-70f7b1c72f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333967545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2333967545
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3053636556
Short name T602
Test name
Test status
Simulation time 673974839 ps
CPU time 10.33 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 219148 kb
Host smart-19a5503d-32f6-4d74-a814-f56407bcd5a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053636556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3053636556
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3076037979
Short name T852
Test name
Test status
Simulation time 2299960302 ps
CPU time 12.33 seconds
Started Jan 07 01:03:13 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 218244 kb
Host smart-a5e86309-a4d2-4032-a68e-7082863dda1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076037979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3076037979
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3082399953
Short name T584
Test name
Test status
Simulation time 244733153 ps
CPU time 6.74 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 218184 kb
Host smart-da534b93-a061-4d38-9f9b-46cfc52b28f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082399953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3082399953
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2458934361
Short name T583
Test name
Test status
Simulation time 546293305 ps
CPU time 6.2 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:03:51 PM PST 24
Peak memory 218264 kb
Host smart-886765e1-121c-4742-b159-9a87ae16f4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458934361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2458934361
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2638476129
Short name T57
Test name
Test status
Simulation time 479352116 ps
CPU time 2.69 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 214412 kb
Host smart-6f08ce56-cf86-4b3f-ad10-7b54110563ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638476129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2638476129
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.948596080
Short name T433
Test name
Test status
Simulation time 1105386777 ps
CPU time 24.67 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 250844 kb
Host smart-e8942f1e-38b7-4ab2-8cf3-90b7398f66e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948596080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.948596080
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1538617347
Short name T460
Test name
Test status
Simulation time 258353798 ps
CPU time 6.21 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 250632 kb
Host smart-80df73db-6a6c-4aea-8bc4-63e9611f8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538617347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1538617347
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2133409623
Short name T403
Test name
Test status
Simulation time 1949273805 ps
CPU time 72.05 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:04:49 PM PST 24
Peak memory 251488 kb
Host smart-92e70422-c139-4938-8cd6-09a9a50ee51f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133409623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2133409623
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2313787319
Short name T391
Test name
Test status
Simulation time 11933063 ps
CPU time 0.89 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 208404 kb
Host smart-7ae173b8-f5ef-484a-9232-add9aae8c80b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313787319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2313787319
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3316719270
Short name T962
Test name
Test status
Simulation time 23419043 ps
CPU time 0.88 seconds
Started Jan 07 01:03:25 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 209708 kb
Host smart-9c560097-feec-43ba-9c6b-ad0812e957f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316719270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3316719270
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.4213252270
Short name T40
Test name
Test status
Simulation time 269097939 ps
CPU time 11.9 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218112 kb
Host smart-dfb1b5e2-6660-4b04-b4ef-f69d5dd63809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213252270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.4213252270
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3667469791
Short name T19
Test name
Test status
Simulation time 214703040 ps
CPU time 1.41 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 209604 kb
Host smart-7c90f073-75b2-4606-9f77-6301ec658703
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667469791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.3667469791
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.151230641
Short name T334
Test name
Test status
Simulation time 61772999 ps
CPU time 1.8 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:39 PM PST 24
Peak memory 218168 kb
Host smart-133c2661-6edb-4e19-99aa-7a46642ed4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151230641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.151230641
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.134914508
Short name T764
Test name
Test status
Simulation time 886045726 ps
CPU time 14.72 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 218728 kb
Host smart-b514b4c0-5376-4e3c-8ddd-444319b76db1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134914508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.134914508
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2225934911
Short name T840
Test name
Test status
Simulation time 307423222 ps
CPU time 13.39 seconds
Started Jan 07 01:03:23 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 218124 kb
Host smart-7c01ac6e-f63e-41d7-957b-a4b52587bf09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225934911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2225934911
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.916289395
Short name T667
Test name
Test status
Simulation time 186416329 ps
CPU time 7.04 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 218120 kb
Host smart-a47f7ca8-206d-4292-a51b-851c5f28f9b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916289395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.916289395
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3813914469
Short name T616
Test name
Test status
Simulation time 1192551934 ps
CPU time 10.32 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 218216 kb
Host smart-fe86b79d-798b-4e99-9094-ba83e2098df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813914469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3813914469
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.928663799
Short name T361
Test name
Test status
Simulation time 29193199 ps
CPU time 1.06 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 212960 kb
Host smart-fdf16a3f-e856-42e2-8a17-b3cd10578e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928663799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.928663799
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1776224205
Short name T734
Test name
Test status
Simulation time 237143222 ps
CPU time 15.93 seconds
Started Jan 07 01:03:16 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 251144 kb
Host smart-d342057f-f373-4a24-9ac8-4a3f3fb34e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776224205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1776224205
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2458462448
Short name T867
Test name
Test status
Simulation time 79294264 ps
CPU time 3.34 seconds
Started Jan 07 01:03:20 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 218196 kb
Host smart-183ce5f3-bef9-4803-8dbb-fccd594a6e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458462448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2458462448
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3834300535
Short name T809
Test name
Test status
Simulation time 3236319490 ps
CPU time 65.91 seconds
Started Jan 07 01:03:23 PM PST 24
Finished Jan 07 01:04:46 PM PST 24
Peak memory 226364 kb
Host smart-014ae4dd-738d-4dd5-8ba4-d8ded6b131cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834300535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3834300535
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2820942152
Short name T32
Test name
Test status
Simulation time 23124936 ps
CPU time 0.79 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:38 PM PST 24
Peak memory 208472 kb
Host smart-ab4c00f1-3630-44da-80c8-4c8a75e5a975
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820942152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2820942152
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3414156147
Short name T461
Test name
Test status
Simulation time 63118769 ps
CPU time 0.87 seconds
Started Jan 07 01:03:29 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 209684 kb
Host smart-d2ff3162-360b-4dfa-b75a-c0bb32eca01e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414156147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3414156147
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1172462901
Short name T380
Test name
Test status
Simulation time 3009284202 ps
CPU time 9.09 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 218216 kb
Host smart-3cbe77c3-44b1-4c0b-83a8-2d21866033c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172462901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1172462901
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2992803194
Short name T18
Test name
Test status
Simulation time 30848914 ps
CPU time 1.14 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 209648 kb
Host smart-ab335b67-3fb7-4518-a46f-66af24647a37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992803194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.2992803194
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3132039508
Short name T826
Test name
Test status
Simulation time 316593041 ps
CPU time 3.08 seconds
Started Jan 07 01:03:18 PM PST 24
Finished Jan 07 01:03:41 PM PST 24
Peak memory 218220 kb
Host smart-aa5682ca-b064-4853-9925-482814a6015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132039508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3132039508
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2764213442
Short name T794
Test name
Test status
Simulation time 317175565 ps
CPU time 11.5 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:04:01 PM PST 24
Peak memory 219092 kb
Host smart-7ff1efa2-fda1-4365-866d-8f24bf3028f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764213442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2764213442
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.899961291
Short name T2
Test name
Test status
Simulation time 358016999 ps
CPU time 13.85 seconds
Started Jan 07 01:03:26 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 218160 kb
Host smart-73162180-0906-4b72-ba89-ddbfa5adb34b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899961291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.899961291
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1876997853
Short name T895
Test name
Test status
Simulation time 940295751 ps
CPU time 8.64 seconds
Started Jan 07 01:03:28 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 218136 kb
Host smart-0733b586-0990-4896-a29f-7fa4396459e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876997853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1876997853
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3750009417
Short name T973
Test name
Test status
Simulation time 370379300 ps
CPU time 8.22 seconds
Started Jan 07 01:03:19 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 218168 kb
Host smart-b2bb4013-1d23-4765-a3c9-a5c80877a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750009417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3750009417
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1580907329
Short name T340
Test name
Test status
Simulation time 24236560 ps
CPU time 1.68 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 213408 kb
Host smart-9fdae83c-cc69-45e4-9ca4-8640915be54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580907329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1580907329
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2624193800
Short name T490
Test name
Test status
Simulation time 205516275 ps
CPU time 21.4 seconds
Started Jan 07 01:03:17 PM PST 24
Finished Jan 07 01:03:59 PM PST 24
Peak memory 250884 kb
Host smart-0caef70e-79cf-4c7c-b735-9312d3fd49ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624193800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2624193800
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.366653461
Short name T761
Test name
Test status
Simulation time 162749042 ps
CPU time 7.34 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 251092 kb
Host smart-04e57582-f21b-421d-8f69-9b50c910b6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366653461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.366653461
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.463579655
Short name T422
Test name
Test status
Simulation time 56107978406 ps
CPU time 472.22 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:11:38 PM PST 24
Peak memory 279776 kb
Host smart-dc1f68bb-727d-42a8-9c01-902116ec8152
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463579655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.463579655
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2471390907
Short name T885
Test name
Test status
Simulation time 13370046 ps
CPU time 0.8 seconds
Started Jan 07 01:03:31 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 208392 kb
Host smart-0fce4fb4-4355-4935-97ea-6956247de7b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471390907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2471390907
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.4099654527
Short name T327
Test name
Test status
Simulation time 16823894 ps
CPU time 1.07 seconds
Started Jan 07 01:03:35 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 209720 kb
Host smart-bcee90c3-848e-481f-aa3b-c5683065510b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099654527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.4099654527
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2268642899
Short name T673
Test name
Test status
Simulation time 288068138 ps
CPU time 12.17 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 218168 kb
Host smart-44af2882-e962-4f61-ac1a-69f002d82aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268642899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2268642899
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1908624570
Short name T457
Test name
Test status
Simulation time 119565320 ps
CPU time 2.97 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 209728 kb
Host smart-0d04f0a1-0bec-4812-87a4-eb6f37863539
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908624570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.1908624570
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.963256231
Short name T800
Test name
Test status
Simulation time 136784565 ps
CPU time 2.84 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 218264 kb
Host smart-489f89cb-2172-4da1-9fc4-1583ffc0a3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963256231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.963256231
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1296475741
Short name T404
Test name
Test status
Simulation time 392185860 ps
CPU time 17.3 seconds
Started Jan 07 01:03:33 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 218468 kb
Host smart-2c10a497-6a74-42d2-8e5c-d8985c5330a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296475741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1296475741
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2469030215
Short name T692
Test name
Test status
Simulation time 205103764 ps
CPU time 9.36 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 218052 kb
Host smart-e83dbf39-2cd9-4df3-8d93-bf766adfb7ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469030215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2469030215
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3420553322
Short name T368
Test name
Test status
Simulation time 1270653993 ps
CPU time 9.5 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 218152 kb
Host smart-6efbe04c-3fba-49a8-827f-129a7ebad8fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420553322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3420553322
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2095111371
Short name T975
Test name
Test status
Simulation time 965217838 ps
CPU time 7.49 seconds
Started Jan 07 01:03:41 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 218260 kb
Host smart-3203e645-8715-4e0b-b9b5-fa56d92493fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095111371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2095111371
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1485322920
Short name T939
Test name
Test status
Simulation time 216393406 ps
CPU time 3.02 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 214108 kb
Host smart-4495f084-2ec1-4595-a132-5909a8758b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485322920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1485322920
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.804079057
Short name T366
Test name
Test status
Simulation time 522416035 ps
CPU time 25.87 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 251120 kb
Host smart-6db6795c-1e74-4a9b-8e51-38b8165265da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804079057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.804079057
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2237388618
Short name T908
Test name
Test status
Simulation time 99128598 ps
CPU time 9.33 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 251240 kb
Host smart-02ced6f3-dbc7-467f-a94d-94a0c7e84572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237388618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2237388618
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3739733437
Short name T925
Test name
Test status
Simulation time 563254148 ps
CPU time 37.5 seconds
Started Jan 07 01:03:31 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 244448 kb
Host smart-43f357b6-1a72-47c1-9ed9-856e515d34d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739733437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3739733437
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1435143123
Short name T607
Test name
Test status
Simulation time 100548307 ps
CPU time 0.95 seconds
Started Jan 07 01:03:30 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 211488 kb
Host smart-a1b9e391-8634-40bd-ac01-ce512286f028
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435143123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1435143123
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3274948602
Short name T68
Test name
Test status
Simulation time 18164195 ps
CPU time 0.88 seconds
Started Jan 07 01:03:43 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 209720 kb
Host smart-443d7d2f-0d1f-4ac9-89ce-29956827cd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274948602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3274948602
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1109487980
Short name T771
Test name
Test status
Simulation time 363262016 ps
CPU time 10.89 seconds
Started Jan 07 01:03:52 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 218348 kb
Host smart-983b9b8f-4624-4193-88a9-caf79396e05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109487980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1109487980
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1629448653
Short name T916
Test name
Test status
Simulation time 2460320192 ps
CPU time 14.91 seconds
Started Jan 07 01:03:58 PM PST 24
Finished Jan 07 01:04:16 PM PST 24
Peak memory 209792 kb
Host smart-6566c72b-7f81-4ede-80bd-a0964bf0e735
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629448653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.1629448653
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2057653365
Short name T859
Test name
Test status
Simulation time 26591966 ps
CPU time 1.63 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 218248 kb
Host smart-3da0cb14-4e03-4564-bf8c-52fe79ef5bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057653365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2057653365
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.934811805
Short name T186
Test name
Test status
Simulation time 381091339 ps
CPU time 15.71 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 219252 kb
Host smart-30532aff-5bc1-4d0d-a295-292c28b57300
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934811805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.934811805
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2775551615
Short name T787
Test name
Test status
Simulation time 499130085 ps
CPU time 10.15 seconds
Started Jan 07 01:03:42 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 218120 kb
Host smart-b2c79ba7-6600-4a3e-9215-48b644dbf9e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775551615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2775551615
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.587799272
Short name T847
Test name
Test status
Simulation time 827294637 ps
CPU time 6.47 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 218140 kb
Host smart-b1494883-1d2f-4465-8960-95f9d5a56d7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587799272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.587799272
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1424740636
Short name T526
Test name
Test status
Simulation time 1423047690 ps
CPU time 13.78 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 218224 kb
Host smart-dc803cd0-0bcb-432d-80fb-c6e523c508e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424740636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1424740636
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2493366748
Short name T793
Test name
Test status
Simulation time 39245387 ps
CPU time 1.7 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 213456 kb
Host smart-53d8b858-4b2e-4d51-a029-1f19a1930ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493366748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2493366748
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.554068035
Short name T725
Test name
Test status
Simulation time 182426954 ps
CPU time 16.45 seconds
Started Jan 07 01:03:52 PM PST 24
Finished Jan 07 01:04:13 PM PST 24
Peak memory 251064 kb
Host smart-1efe5674-8b55-45bc-a62a-a1d854b091da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554068035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.554068035
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.816777882
Short name T389
Test name
Test status
Simulation time 344007434 ps
CPU time 6.72 seconds
Started Jan 07 01:03:42 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 249000 kb
Host smart-3df19e89-f81b-4ae5-9bdc-b959348d59ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816777882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.816777882
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3577368525
Short name T488
Test name
Test status
Simulation time 30089009415 ps
CPU time 97.98 seconds
Started Jan 07 01:03:59 PM PST 24
Finished Jan 07 01:05:41 PM PST 24
Peak memory 268444 kb
Host smart-78410b5b-ad7e-4f4e-ab30-79773e60d7f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577368525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3577368525
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1690553687
Short name T804
Test name
Test status
Simulation time 33810396 ps
CPU time 0.96 seconds
Started Jan 07 01:03:34 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 211408 kb
Host smart-9275dacc-ce26-4ad0-acd1-1ce3c843a538
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690553687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1690553687
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1083303161
Short name T680
Test name
Test status
Simulation time 122845972 ps
CPU time 0.86 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 209740 kb
Host smart-f60b30a1-665a-4eb7-b37a-d1b3362324c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083303161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1083303161
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3624476360
Short name T443
Test name
Test status
Simulation time 1321142322 ps
CPU time 13.7 seconds
Started Jan 07 01:03:32 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 218232 kb
Host smart-3922ed3b-79d8-4ead-94b9-e927d5753c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624476360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3624476360
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1617976199
Short name T924
Test name
Test status
Simulation time 442554759 ps
CPU time 6.3 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 209680 kb
Host smart-c1a43ec9-5e1a-4928-8dd1-d9c211cc0af5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617976199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.1617976199
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3384764138
Short name T106
Test name
Test status
Simulation time 53558930 ps
CPU time 3.05 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 218220 kb
Host smart-ff29dcfe-a069-4da1-a8aa-11b9ed42805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384764138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3384764138
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4137596465
Short name T315
Test name
Test status
Simulation time 884302208 ps
CPU time 13.52 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 219224 kb
Host smart-4d16c671-75ca-4af9-bc0d-65774686074f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137596465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4137596465
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1325141214
Short name T704
Test name
Test status
Simulation time 720410534 ps
CPU time 12.16 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:03:59 PM PST 24
Peak memory 218144 kb
Host smart-f6c407b7-c420-4d06-af35-877ec3f4c03d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325141214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1325141214
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.473880354
Short name T529
Test name
Test status
Simulation time 201688287 ps
CPU time 7.96 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:03:55 PM PST 24
Peak memory 218148 kb
Host smart-20e89f6b-648d-41c7-b43d-936d402df33b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473880354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.473880354
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.263485521
Short name T876
Test name
Test status
Simulation time 498857582 ps
CPU time 6.98 seconds
Started Jan 07 01:03:42 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 218132 kb
Host smart-83fb040e-9903-478b-a540-9e92c1656bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263485521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.263485521
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1969930675
Short name T65
Test name
Test status
Simulation time 69451946 ps
CPU time 2.37 seconds
Started Jan 07 01:03:44 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 213712 kb
Host smart-f9634979-9712-4f37-9d85-938e60ef2793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969930675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1969930675
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3698045442
Short name T100
Test name
Test status
Simulation time 225722455 ps
CPU time 20.08 seconds
Started Jan 07 01:03:38 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 245048 kb
Host smart-2da8b982-23de-4b7f-b8cf-9bbbb95b82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698045442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3698045442
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1710323015
Short name T452
Test name
Test status
Simulation time 525065821 ps
CPU time 2.77 seconds
Started Jan 07 01:03:35 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 218188 kb
Host smart-6160f0f4-a745-4b1d-aab2-71bb7e3b192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710323015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1710323015
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2492986008
Short name T937
Test name
Test status
Simulation time 10898313419 ps
CPU time 87.52 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:05:14 PM PST 24
Peak memory 275884 kb
Host smart-23c042ed-a86c-4f87-8cee-2a002836e566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492986008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2492986008
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2567822797
Short name T872
Test name
Test status
Simulation time 12348273 ps
CPU time 0.77 seconds
Started Jan 07 01:03:35 PM PST 24
Finished Jan 07 01:03:47 PM PST 24
Peak memory 208372 kb
Host smart-dd9a68ea-4d45-4ffe-a392-8c8b974618fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567822797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2567822797
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.569944931
Short name T730
Test name
Test status
Simulation time 50168054 ps
CPU time 0.96 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 209744 kb
Host smart-e4d14455-e3f8-4798-ab1f-6b7ac3a32dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569944931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.569944931
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.596144447
Short name T442
Test name
Test status
Simulation time 417687812 ps
CPU time 9.58 seconds
Started Jan 07 01:03:43 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 218220 kb
Host smart-db4d7ee5-e76a-487d-9b68-79c42202d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596144447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.596144447
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3628949618
Short name T699
Test name
Test status
Simulation time 1500476924 ps
CPU time 3.69 seconds
Started Jan 07 01:03:41 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 209732 kb
Host smart-1dfea224-9519-4880-a2b9-af46ab75e16c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628949618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.3628949618
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1562367704
Short name T862
Test name
Test status
Simulation time 58104924 ps
CPU time 2.87 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 218228 kb
Host smart-151fe85e-9181-4510-aaff-b2528bfe5498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562367704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1562367704
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.4126279293
Short name T753
Test name
Test status
Simulation time 1248659588 ps
CPU time 9.23 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 219220 kb
Host smart-a3ac5a07-760f-4868-b739-3de4fe26cb1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126279293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.4126279293
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.656329562
Short name T627
Test name
Test status
Simulation time 2236068617 ps
CPU time 19.22 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:04:12 PM PST 24
Peak memory 218264 kb
Host smart-ccb7b880-70c8-4ba1-a232-9648a8ae0cd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656329562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.656329562
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.380959081
Short name T497
Test name
Test status
Simulation time 1068535844 ps
CPU time 7.13 seconds
Started Jan 07 01:03:44 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 218176 kb
Host smart-4d629905-f476-415a-854e-d6ba8d9e568d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380959081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.380959081
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.608858720
Short name T820
Test name
Test status
Simulation time 409665814 ps
CPU time 10.87 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 218224 kb
Host smart-9f88df04-3920-46c5-b75f-1353019714f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608858720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.608858720
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.164960686
Short name T691
Test name
Test status
Simulation time 162154178 ps
CPU time 3.43 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 213572 kb
Host smart-d9db2fb3-c2a9-4c0c-87c0-839f28f5343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164960686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.164960686
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3348032691
Short name T383
Test name
Test status
Simulation time 167766881 ps
CPU time 16.79 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 251128 kb
Host smart-748d74e1-acf7-483b-86a8-cf674ddfebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348032691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3348032691
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.473688459
Short name T401
Test name
Test status
Simulation time 435547857 ps
CPU time 2.87 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 226744 kb
Host smart-772dcd7d-c1f3-4e5d-8ebe-518e94e991cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473688459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.473688459
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1024967138
Short name T308
Test name
Test status
Simulation time 97033502977 ps
CPU time 268.63 seconds
Started Jan 07 01:03:57 PM PST 24
Finished Jan 07 01:08:30 PM PST 24
Peak memory 270980 kb
Host smart-4698f5b4-923a-476a-88be-87a63fd66458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024967138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1024967138
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.783685474
Short name T648
Test name
Test status
Simulation time 19553040 ps
CPU time 1.01 seconds
Started Jan 07 01:03:36 PM PST 24
Finished Jan 07 01:03:48 PM PST 24
Peak memory 211576 kb
Host smart-f5d1831a-f6eb-4126-9ae3-e9fbd03cf8fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783685474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.783685474
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1163754136
Short name T574
Test name
Test status
Simulation time 18982996 ps
CPU time 1.04 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 209636 kb
Host smart-60a57aee-4b33-4e83-849f-09acc2431f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163754136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1163754136
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2565538335
Short name T845
Test name
Test status
Simulation time 41116270 ps
CPU time 0.8 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:11 PM PST 24
Peak memory 209444 kb
Host smart-c702b76f-4681-4162-90d8-2084d82c9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565538335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2565538335
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2016638360
Short name T479
Test name
Test status
Simulation time 1237666993 ps
CPU time 11.67 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:21 PM PST 24
Peak memory 218240 kb
Host smart-971c6c9c-e02e-4c2c-9ecd-ee48552dcda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016638360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2016638360
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2251158381
Short name T477
Test name
Test status
Simulation time 4842953467 ps
CPU time 3.33 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 209640 kb
Host smart-65fc4388-c81d-4bc1-aa9c-ad8a075565e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251158381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ac
cess.2251158381
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3694224493
Short name T983
Test name
Test status
Simulation time 22486281999 ps
CPU time 36.99 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:46 PM PST 24
Peak memory 218516 kb
Host smart-3d0c8f25-6483-4464-803b-616b9c400c8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694224493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3694224493
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2210841576
Short name T633
Test name
Test status
Simulation time 814929919 ps
CPU time 3.38 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 217800 kb
Host smart-45452413-1fe5-4315-8509-0f8e3be4b4d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210841576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.2210841576
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3478560683
Short name T405
Test name
Test status
Simulation time 1379356186 ps
CPU time 6.2 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:17 PM PST 24
Peak memory 218152 kb
Host smart-ce267470-d308-4681-9ede-5f3b46a38af9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478560683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3478560683
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1161731023
Short name T654
Test name
Test status
Simulation time 2214622933 ps
CPU time 30.88 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:44 PM PST 24
Peak memory 213412 kb
Host smart-72a298b1-5113-4635-85ef-07dfb1e99b8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161731023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1161731023
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1245932775
Short name T713
Test name
Test status
Simulation time 632908830 ps
CPU time 3.51 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 213244 kb
Host smart-16047be7-e66d-4872-b63d-02461d45afa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245932775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1245932775
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.803867825
Short name T922
Test name
Test status
Simulation time 1437386594 ps
CPU time 45.04 seconds
Started Jan 07 01:01:50 PM PST 24
Finished Jan 07 01:02:56 PM PST 24
Peak memory 267496 kb
Host smart-fed65676-c170-4a32-b57d-72592acf5391
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803867825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.803867825
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1156806737
Short name T495
Test name
Test status
Simulation time 3309418117 ps
CPU time 16.57 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 251068 kb
Host smart-44a10870-e1c5-46a2-a847-d629d73ecc52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156806737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1156806737
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3008104879
Short name T956
Test name
Test status
Simulation time 72812839 ps
CPU time 2.87 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:16 PM PST 24
Peak memory 218188 kb
Host smart-8d5f7f81-d983-4b37-abed-c6c4a2cea8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008104879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3008104879
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3528212311
Short name T36
Test name
Test status
Simulation time 360423919 ps
CPU time 25.52 seconds
Started Jan 07 01:01:45 PM PST 24
Finished Jan 07 01:02:34 PM PST 24
Peak memory 214480 kb
Host smart-54dc7d08-0f0d-494a-909a-e5514df1f5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528212311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3528212311
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2159171833
Short name T50
Test name
Test status
Simulation time 174447079 ps
CPU time 22.94 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:34 PM PST 24
Peak memory 272680 kb
Host smart-24138735-43b4-49b4-8800-3fa686a9fd4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159171833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2159171833
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1602408864
Short name T869
Test name
Test status
Simulation time 419978888 ps
CPU time 16.31 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 219220 kb
Host smart-3e5541de-ff12-444b-a629-c509652ec32b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602408864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1602408864
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.136661322
Short name T502
Test name
Test status
Simulation time 1370600484 ps
CPU time 10.89 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:21 PM PST 24
Peak memory 218140 kb
Host smart-2b3db254-33c8-4ad7-bca7-80ea0c75beb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136661322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.136661322
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.4173388228
Short name T434
Test name
Test status
Simulation time 291061910 ps
CPU time 8.07 seconds
Started Jan 07 01:01:47 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 218236 kb
Host smart-ef889ae5-cfb6-4727-b202-c82496165a61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173388228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.4
173388228
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4021089531
Short name T332
Test name
Test status
Simulation time 556582855 ps
CPU time 10.08 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 218092 kb
Host smart-c443c2ae-1a54-4a23-a624-106faae8a3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021089531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4021089531
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1571069337
Short name T929
Test name
Test status
Simulation time 119852798 ps
CPU time 1.02 seconds
Started Jan 07 01:01:32 PM PST 24
Finished Jan 07 01:01:59 PM PST 24
Peak memory 212936 kb
Host smart-c7a1bb3b-c8f6-4ebf-9dc3-6d61b8bcc4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571069337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1571069337
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4086155185
Short name T511
Test name
Test status
Simulation time 810650646 ps
CPU time 16.47 seconds
Started Jan 07 01:01:36 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 251092 kb
Host smart-876b6fe2-45ab-4fd0-945c-55b2e2c5868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086155185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4086155185
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2367659303
Short name T183
Test name
Test status
Simulation time 224139327 ps
CPU time 3.36 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:16 PM PST 24
Peak memory 222164 kb
Host smart-9b54d131-093c-4b85-a9e6-0c46f262bd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367659303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2367659303
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2456999139
Short name T552
Test name
Test status
Simulation time 11327023148 ps
CPU time 52.11 seconds
Started Jan 07 01:01:47 PM PST 24
Finished Jan 07 01:03:02 PM PST 24
Peak memory 267564 kb
Host smart-385a37e5-3ac3-4055-aa1f-1362b5e36953
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456999139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2456999139
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3539828651
Short name T110
Test name
Test status
Simulation time 104014071779 ps
CPU time 1158.86 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:21:28 PM PST 24
Peak memory 365364 kb
Host smart-821baebc-ba52-476f-a92a-10d578d99d90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3539828651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3539828651
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2559607181
Short name T772
Test name
Test status
Simulation time 21755410 ps
CPU time 0.73 seconds
Started Jan 07 01:01:57 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 208380 kb
Host smart-fb83f6a9-441d-4bad-b89f-daca2d1ba515
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559607181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2559607181
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.595036947
Short name T344
Test name
Test status
Simulation time 62351742 ps
CPU time 1.07 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 208568 kb
Host smart-2c6d09b4-992e-4105-9d1a-f3d1c3e4ae35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595036947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.595036947
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1850789031
Short name T429
Test name
Test status
Simulation time 1502723497 ps
CPU time 10.8 seconds
Started Jan 07 01:03:51 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 218224 kb
Host smart-45681894-7845-4a9a-97bb-b99168993aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850789031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1850789031
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3631051584
Short name T556
Test name
Test status
Simulation time 411542958 ps
CPU time 4.44 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 209540 kb
Host smart-c4c199c1-92d9-4c7a-9849-e8971ad18876
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631051584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.3631051584
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2760420499
Short name T347
Test name
Test status
Simulation time 59978011 ps
CPU time 2.73 seconds
Started Jan 07 01:03:54 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 218212 kb
Host smart-5f404695-7729-4de3-87e5-e3c23fe8de6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760420499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2760420499
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1180483006
Short name T906
Test name
Test status
Simulation time 1631976557 ps
CPU time 8.75 seconds
Started Jan 07 01:03:41 PM PST 24
Finished Jan 07 01:03:59 PM PST 24
Peak memory 218488 kb
Host smart-22ab5ad6-a939-4f42-8f64-b86baed9a882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180483006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1180483006
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3876570693
Short name T855
Test name
Test status
Simulation time 463336320 ps
CPU time 8.44 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 218164 kb
Host smart-78914d31-928d-48b9-a3c1-1f7704183335
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876570693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3876570693
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3579847731
Short name T914
Test name
Test status
Simulation time 961031937 ps
CPU time 8.98 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 218184 kb
Host smart-59c0fb8a-5024-467f-ac73-2dbf84dee213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579847731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3579847731
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3741989709
Short name T535
Test name
Test status
Simulation time 248692071 ps
CPU time 7.83 seconds
Started Jan 07 01:03:55 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 218208 kb
Host smart-c8d1c5d2-e138-490a-a2d9-c3ff9215956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741989709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3741989709
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3374380080
Short name T818
Test name
Test status
Simulation time 37878571 ps
CPU time 1.84 seconds
Started Jan 07 01:03:44 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 213608 kb
Host smart-669ac3fe-5485-4aab-b8d8-785ea96ecd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374380080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3374380080
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.643567494
Short name T323
Test name
Test status
Simulation time 363341238 ps
CPU time 17.68 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 251064 kb
Host smart-c04a0589-b241-4eba-b70b-3a31bc606a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643567494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.643567494
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3288273780
Short name T926
Test name
Test status
Simulation time 88421915 ps
CPU time 3.17 seconds
Started Jan 07 01:03:58 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 218260 kb
Host smart-bd5df825-ea58-4de6-95a7-696471b04589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288273780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3288273780
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1550133221
Short name T337
Test name
Test status
Simulation time 2153485314 ps
CPU time 58.42 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:04:52 PM PST 24
Peak memory 251184 kb
Host smart-4c054a5f-33bc-4a57-b309-63df1537a17d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550133221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1550133221
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.620970528
Short name T888
Test name
Test status
Simulation time 195519579 ps
CPU time 0.97 seconds
Started Jan 07 01:03:38 PM PST 24
Finished Jan 07 01:03:49 PM PST 24
Peak memory 211496 kb
Host smart-a33a1b29-1d70-4e5f-bb5b-dd9477577194
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620970528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.620970528
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2651444559
Short name T95
Test name
Test status
Simulation time 59528283 ps
CPU time 1.07 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:04:16 PM PST 24
Peak memory 209648 kb
Host smart-a42360f8-382a-4560-bb05-446f7a7dc94d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651444559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2651444559
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.385314610
Short name T364
Test name
Test status
Simulation time 957182134 ps
CPU time 10.78 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 218232 kb
Host smart-c8cb9b3e-b05a-4be6-8644-e4b7d2ee5d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385314610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.385314610
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2451912195
Short name T803
Test name
Test status
Simulation time 999024780 ps
CPU time 3.61 seconds
Started Jan 07 01:04:02 PM PST 24
Finished Jan 07 01:04:10 PM PST 24
Peak memory 209684 kb
Host smart-e52bf277-946e-4719-aef1-b392f3b572a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451912195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.2451912195
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3887091639
Short name T376
Test name
Test status
Simulation time 55198781 ps
CPU time 3.27 seconds
Started Jan 07 01:04:04 PM PST 24
Finished Jan 07 01:04:11 PM PST 24
Peak memory 218200 kb
Host smart-a5c4b823-2ecd-4d43-a936-66c0c10577af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887091639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3887091639
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3648881073
Short name T663
Test name
Test status
Simulation time 222671494 ps
CPU time 10.84 seconds
Started Jan 07 01:04:11 PM PST 24
Finished Jan 07 01:04:24 PM PST 24
Peak memory 218088 kb
Host smart-8ba4ee19-65fd-415c-8ff8-8d8c3d0048b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648881073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3648881073
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3120448508
Short name T432
Test name
Test status
Simulation time 431479978 ps
CPU time 12.41 seconds
Started Jan 07 01:04:28 PM PST 24
Finished Jan 07 01:04:43 PM PST 24
Peak memory 218176 kb
Host smart-4cbc6ba9-b009-4608-8610-9b336c6700b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120448508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3120448508
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2179701744
Short name T466
Test name
Test status
Simulation time 279570930 ps
CPU time 11.31 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:04:21 PM PST 24
Peak memory 218116 kb
Host smart-3daeac7b-1acc-4dac-b7f0-ebb98a661bf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179701744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2179701744
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2862263310
Short name T921
Test name
Test status
Simulation time 595375472 ps
CPU time 10.39 seconds
Started Jan 07 01:04:01 PM PST 24
Finished Jan 07 01:04:16 PM PST 24
Peak memory 217940 kb
Host smart-22c8add5-6546-47e5-b6e6-eb72d7d05e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862263310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2862263310
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.941583959
Short name T856
Test name
Test status
Simulation time 16388011 ps
CPU time 1.19 seconds
Started Jan 07 01:04:00 PM PST 24
Finished Jan 07 01:04:06 PM PST 24
Peak memory 213340 kb
Host smart-fef93c64-1863-4e0b-a7c2-8b4cb4a6c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941583959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.941583959
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.988667628
Short name T714
Test name
Test status
Simulation time 525936985 ps
CPU time 29.96 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:04:30 PM PST 24
Peak memory 247436 kb
Host smart-d4afa2b4-a1fb-4bbb-868a-e0baff31cb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988667628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.988667628
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2204475567
Short name T816
Test name
Test status
Simulation time 74126355 ps
CPU time 6.98 seconds
Started Jan 07 01:04:11 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 246376 kb
Host smart-ac5650a6-c531-4075-9038-26658b0d2844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204475567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2204475567
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1269405244
Short name T390
Test name
Test status
Simulation time 22113141784 ps
CPU time 118.46 seconds
Started Jan 07 01:04:16 PM PST 24
Finished Jan 07 01:06:18 PM PST 24
Peak memory 267688 kb
Host smart-8f253ae9-9bd0-436b-87ab-a1caeb9eb251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269405244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1269405244
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1843147895
Short name T806
Test name
Test status
Simulation time 30984970 ps
CPU time 1.04 seconds
Started Jan 07 01:04:27 PM PST 24
Finished Jan 07 01:04:31 PM PST 24
Peak memory 209712 kb
Host smart-c87e4f84-5d70-4c81-a3f9-42ddb005f73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843147895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1843147895
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.4185241956
Short name T774
Test name
Test status
Simulation time 437333182 ps
CPU time 12.44 seconds
Started Jan 07 01:04:14 PM PST 24
Finished Jan 07 01:04:29 PM PST 24
Peak memory 218160 kb
Host smart-0c2f98a7-a805-4130-ae5a-653eb802acab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185241956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4185241956
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.4208441430
Short name T491
Test name
Test status
Simulation time 1928352877 ps
CPU time 12.12 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:04:27 PM PST 24
Peak memory 209676 kb
Host smart-602ab75a-df82-44b8-9d47-aea227f8438d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208441430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.4208441430
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.771138321
Short name T296
Test name
Test status
Simulation time 581411076 ps
CPU time 2.45 seconds
Started Jan 07 01:04:46 PM PST 24
Finished Jan 07 01:04:50 PM PST 24
Peak memory 218160 kb
Host smart-e9199c1d-16bb-443c-a189-8633d6d9ca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771138321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.771138321
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4197382740
Short name T620
Test name
Test status
Simulation time 640040771 ps
CPU time 18.96 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:04:58 PM PST 24
Peak memory 219240 kb
Host smart-766fa232-474f-4d8c-860e-0ef767d5e5fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197382740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4197382740
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3006815886
Short name T615
Test name
Test status
Simulation time 4476041672 ps
CPU time 11.99 seconds
Started Jan 07 01:04:22 PM PST 24
Finished Jan 07 01:04:37 PM PST 24
Peak memory 218160 kb
Host smart-d84811bb-4c5f-448f-aea0-7f305af35665
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006815886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3006815886
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.901175670
Short name T56
Test name
Test status
Simulation time 205337874 ps
CPU time 5.97 seconds
Started Jan 07 01:04:41 PM PST 24
Finished Jan 07 01:04:49 PM PST 24
Peak memory 218168 kb
Host smart-ef73aa08-ef35-42c1-ab90-50253658f6a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901175670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.901175670
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2725216300
Short name T698
Test name
Test status
Simulation time 597704169 ps
CPU time 9.39 seconds
Started Jan 07 01:04:08 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 218240 kb
Host smart-76fddff4-e160-4594-b020-83740e6e033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725216300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2725216300
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1074514227
Short name T961
Test name
Test status
Simulation time 51513422 ps
CPU time 1.21 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:04:23 PM PST 24
Peak memory 213176 kb
Host smart-75aca84a-9e73-41b2-94ba-32f7a4dd51a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074514227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1074514227
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1290994920
Short name T807
Test name
Test status
Simulation time 199099675 ps
CPU time 23.64 seconds
Started Jan 07 01:04:10 PM PST 24
Finished Jan 07 01:04:36 PM PST 24
Peak memory 250372 kb
Host smart-91c7b39e-a676-4c8c-8cab-0c84dc157e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290994920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1290994920
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.4016233311
Short name T585
Test name
Test status
Simulation time 183435185 ps
CPU time 10.78 seconds
Started Jan 07 01:04:20 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 251140 kb
Host smart-64d86070-a29a-421f-b2c8-769020518a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016233311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.4016233311
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2510143990
Short name T396
Test name
Test status
Simulation time 3617513389 ps
CPU time 51.15 seconds
Started Jan 07 01:04:08 PM PST 24
Finished Jan 07 01:05:02 PM PST 24
Peak memory 226612 kb
Host smart-306fe8ae-2d1d-4a7a-b606-0ccb18d99f34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510143990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2510143990
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2208971211
Short name T886
Test name
Test status
Simulation time 15677461 ps
CPU time 0.96 seconds
Started Jan 07 01:04:16 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 211344 kb
Host smart-6a059a46-c456-4e36-87b1-8e6704e91799
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208971211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2208971211
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.21409770
Short name T71
Test name
Test status
Simulation time 18659859 ps
CPU time 1.17 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 208488 kb
Host smart-1568169c-fc0e-40c4-ab37-d8b8ae901d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21409770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.21409770
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.618647771
Short name T828
Test name
Test status
Simulation time 1644457825 ps
CPU time 13.5 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 218216 kb
Host smart-06df352d-bcfd-4232-bc07-bbcbaee190bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618647771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.618647771
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3074031071
Short name T979
Test name
Test status
Simulation time 319370702 ps
CPU time 4.68 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 209668 kb
Host smart-70215ff4-8d65-43b6-90e1-5c02f3795ff6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074031071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.3074031071
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.685005913
Short name T965
Test name
Test status
Simulation time 189929933 ps
CPU time 2.53 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:03:52 PM PST 24
Peak memory 218204 kb
Host smart-d05d60ad-83b2-41ac-b0e9-9de128f899d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685005913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.685005913
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1588387865
Short name T393
Test name
Test status
Simulation time 984751273 ps
CPU time 12.39 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:04:09 PM PST 24
Peak memory 218204 kb
Host smart-3ab7215f-5117-4302-af3e-4d9f821d23b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588387865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1588387865
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2182758980
Short name T596
Test name
Test status
Simulation time 895201491 ps
CPU time 14.34 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:04:24 PM PST 24
Peak memory 218140 kb
Host smart-2b48a502-8cbc-4c41-b96d-cb69d4eb003e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182758980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2182758980
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3656160592
Short name T8
Test name
Test status
Simulation time 1145919891 ps
CPU time 9.03 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 218084 kb
Host smart-cfb923de-64ae-427c-85ea-127d138d2c3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656160592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3656160592
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3037624882
Short name T546
Test name
Test status
Simulation time 231138271 ps
CPU time 10.8 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:04:05 PM PST 24
Peak memory 218268 kb
Host smart-b4894fd7-16af-4e61-b3f7-216a580515b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037624882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3037624882
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.261766662
Short name T934
Test name
Test status
Simulation time 19724658 ps
CPU time 1.11 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:04:28 PM PST 24
Peak memory 213116 kb
Host smart-2a1dd7e8-8eb3-4aba-9f5f-1690a7d63af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261766662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.261766662
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2940523829
Short name T38
Test name
Test status
Simulation time 396577970 ps
CPU time 28.75 seconds
Started Jan 07 01:03:37 PM PST 24
Finished Jan 07 01:04:16 PM PST 24
Peak memory 251060 kb
Host smart-5f76fd6e-aade-41c3-8297-e813f6543333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940523829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2940523829
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.371706583
Short name T413
Test name
Test status
Simulation time 45878320 ps
CPU time 6.79 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:04:01 PM PST 24
Peak memory 251140 kb
Host smart-1f463a9a-58e3-47d1-ba42-b4ebcd86d87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371706583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.371706583
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2873405962
Short name T520
Test name
Test status
Simulation time 6252441336 ps
CPU time 50.85 seconds
Started Jan 07 01:03:50 PM PST 24
Finished Jan 07 01:04:45 PM PST 24
Peak memory 267620 kb
Host smart-d1e8b349-4dc6-4e4f-b2b9-7bc7464c8ef0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873405962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2873405962
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1307792538
Short name T81
Test name
Test status
Simulation time 26131295 ps
CPU time 1.09 seconds
Started Jan 07 01:04:34 PM PST 24
Finished Jan 07 01:04:39 PM PST 24
Peak memory 211508 kb
Host smart-266ce688-bac4-42bc-bb83-e3edd54a63f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307792538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1307792538
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2102457398
Short name T534
Test name
Test status
Simulation time 54225061 ps
CPU time 0.85 seconds
Started Jan 07 01:04:02 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 209716 kb
Host smart-90ace286-3c13-46cd-9e9a-1b78575c6b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102457398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2102457398
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2088615033
Short name T455
Test name
Test status
Simulation time 441008820 ps
CPU time 9.84 seconds
Started Jan 07 01:03:52 PM PST 24
Finished Jan 07 01:04:06 PM PST 24
Peak memory 218228 kb
Host smart-e7e790b6-a5c6-4da1-9527-6d8efc88c841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088615033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2088615033
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3760116974
Short name T16
Test name
Test status
Simulation time 4870958524 ps
CPU time 11.59 seconds
Started Jan 07 01:03:54 PM PST 24
Finished Jan 07 01:04:09 PM PST 24
Peak memory 209764 kb
Host smart-104b358c-81e8-4537-9b93-b61cb86401ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760116974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.3760116974
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.793443514
Short name T875
Test name
Test status
Simulation time 181923216 ps
CPU time 7.29 seconds
Started Jan 07 01:03:48 PM PST 24
Finished Jan 07 01:04:01 PM PST 24
Peak memory 218200 kb
Host smart-4c6ff253-cf19-4bc1-84e7-ee77b9f7303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793443514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.793443514
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.4083533216
Short name T539
Test name
Test status
Simulation time 524489002 ps
CPU time 14.97 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:04:15 PM PST 24
Peak memory 218132 kb
Host smart-75764335-20fe-417b-9c84-2a4ae39b649e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083533216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4083533216
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.532356812
Short name T884
Test name
Test status
Simulation time 1002392329 ps
CPU time 10.03 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:04:19 PM PST 24
Peak memory 218180 kb
Host smart-ce575fda-decd-457a-b95b-e6383ef6f51a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532356812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.532356812
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3507257979
Short name T625
Test name
Test status
Simulation time 287459600 ps
CPU time 6.88 seconds
Started Jan 07 01:03:57 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 218112 kb
Host smart-eb740291-68ee-44a3-8dde-54b31604d775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507257979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3507257979
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2501284257
Short name T47
Test name
Test status
Simulation time 266369508 ps
CPU time 8.65 seconds
Started Jan 07 01:03:54 PM PST 24
Finished Jan 07 01:04:06 PM PST 24
Peak memory 218152 kb
Host smart-500f1d6c-1f2f-466d-b58b-de5eedf67c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501284257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2501284257
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3636145013
Short name T836
Test name
Test status
Simulation time 45560955 ps
CPU time 2.7 seconds
Started Jan 07 01:03:49 PM PST 24
Finished Jan 07 01:03:56 PM PST 24
Peak memory 213928 kb
Host smart-8b101b7e-1699-43b8-9de6-614c8164e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636145013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3636145013
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2243242559
Short name T611
Test name
Test status
Simulation time 227625256 ps
CPU time 29.55 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:04:23 PM PST 24
Peak memory 251040 kb
Host smart-704cab9b-4a73-4363-91d4-0a14c92648a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243242559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2243242559
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1894152116
Short name T664
Test name
Test status
Simulation time 286492380 ps
CPU time 7.14 seconds
Started Jan 07 01:03:48 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 246304 kb
Host smart-b35b2a1d-2e5b-4bf4-83a7-197df4b96df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894152116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1894152116
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2878376052
Short name T955
Test name
Test status
Simulation time 10660568649 ps
CPU time 84.48 seconds
Started Jan 07 01:04:15 PM PST 24
Finished Jan 07 01:05:42 PM PST 24
Peak memory 268288 kb
Host smart-96cf0b4f-86fa-4e38-b21a-93269d66dc02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878376052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2878376052
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3128882115
Short name T20
Test name
Test status
Simulation time 23866834 ps
CPU time 0.95 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:03:54 PM PST 24
Peak memory 208112 kb
Host smart-3303ca92-b2ae-466a-a511-473e85f4f024
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128882115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3128882115
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2638971347
Short name T766
Test name
Test status
Simulation time 29084141 ps
CPU time 1.01 seconds
Started Jan 07 01:04:33 PM PST 24
Finished Jan 07 01:04:38 PM PST 24
Peak memory 209724 kb
Host smart-5a712857-6fd1-44a4-ad6c-cbe98ad8f9da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638971347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2638971347
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1743405319
Short name T572
Test name
Test status
Simulation time 513151476 ps
CPU time 12.17 seconds
Started Jan 07 01:04:03 PM PST 24
Finished Jan 07 01:04:20 PM PST 24
Peak memory 218176 kb
Host smart-13f5af88-afcd-45b8-88a0-af6032ec7b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743405319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1743405319
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1455311103
Short name T486
Test name
Test status
Simulation time 50329955 ps
CPU time 2 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 209716 kb
Host smart-fc421b2b-4c82-4ccc-88bd-c468606d0cb3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455311103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.1455311103
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1670353571
Short name T456
Test name
Test status
Simulation time 92018498 ps
CPU time 3.44 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:04:19 PM PST 24
Peak memory 218256 kb
Host smart-ba85f178-d5c3-4d6a-9cd3-2a531dc96327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670353571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1670353571
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.4034470921
Short name T558
Test name
Test status
Simulation time 552278668 ps
CPU time 10.42 seconds
Started Jan 07 01:04:31 PM PST 24
Finished Jan 07 01:04:44 PM PST 24
Peak memory 219260 kb
Host smart-11981294-031d-4c97-a263-c6c6fd8cd341
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034470921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.4034470921
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1337090687
Short name T971
Test name
Test status
Simulation time 441216742 ps
CPU time 11.05 seconds
Started Jan 07 01:04:13 PM PST 24
Finished Jan 07 01:04:27 PM PST 24
Peak memory 218048 kb
Host smart-ca4c9756-624d-47ca-83aa-85b6ece2dc8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337090687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1337090687
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.521066914
Short name T919
Test name
Test status
Simulation time 478157283 ps
CPU time 11.91 seconds
Started Jan 07 01:04:25 PM PST 24
Finished Jan 07 01:04:40 PM PST 24
Peak memory 218064 kb
Host smart-a41f53a6-9daf-41cb-908a-32dfb1fe70f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521066914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.521066914
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.45359698
Short name T363
Test name
Test status
Simulation time 2403067703 ps
CPU time 12 seconds
Started Jan 07 01:04:02 PM PST 24
Finished Jan 07 01:04:18 PM PST 24
Peak memory 218296 kb
Host smart-d4a5d64d-52d5-4b2a-9a9f-541bc437cb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45359698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.45359698
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3899191118
Short name T524
Test name
Test status
Simulation time 56442313 ps
CPU time 3.26 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 01:04:31 PM PST 24
Peak memory 214276 kb
Host smart-d92d3ab8-c6fb-4fef-9ef1-004a81030bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899191118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3899191118
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.180974715
Short name T381
Test name
Test status
Simulation time 711272543 ps
CPU time 24.9 seconds
Started Jan 07 01:04:07 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 251120 kb
Host smart-a4993340-b592-4130-8b50-888974c45796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180974715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.180974715
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.328890095
Short name T707
Test name
Test status
Simulation time 63659049 ps
CPU time 3.69 seconds
Started Jan 07 01:03:56 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 218224 kb
Host smart-978ef986-7ce3-47cf-834e-6e4abd18c83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328890095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.328890095
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.4169296325
Short name T75
Test name
Test status
Simulation time 26760386329 ps
CPU time 319.02 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:09:42 PM PST 24
Peak memory 227268 kb
Host smart-a0a1fa5f-d159-407a-97c4-fe0deaee3359
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169296325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.4169296325
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.777481451
Short name T703
Test name
Test status
Simulation time 35679171 ps
CPU time 0.89 seconds
Started Jan 07 01:04:09 PM PST 24
Finished Jan 07 01:04:12 PM PST 24
Peak memory 208604 kb
Host smart-d69943a3-cfe8-4810-8c93-7a748d4e4fde
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777481451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.777481451
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3163039425
Short name T799
Test name
Test status
Simulation time 69966241 ps
CPU time 1.1 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:03:50 PM PST 24
Peak memory 209692 kb
Host smart-216d924a-f3e9-4dac-89b5-125f38d8ca0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163039425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3163039425
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.4274885423
Short name T299
Test name
Test status
Simulation time 320462159 ps
CPU time 14.52 seconds
Started Jan 07 01:04:20 PM PST 24
Finished Jan 07 01:04:37 PM PST 24
Peak memory 218076 kb
Host smart-55391ea2-2bdd-48b2-b9cd-27907cd5192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274885423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.4274885423
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.342328671
Short name T844
Test name
Test status
Simulation time 228315608 ps
CPU time 2.54 seconds
Started Jan 07 01:04:30 PM PST 24
Finished Jan 07 01:04:35 PM PST 24
Peak memory 209700 kb
Host smart-94f07341-a169-4c46-aaf6-cfe013950de5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342328671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_ac
cess.342328671
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.193679425
Short name T839
Test name
Test status
Simulation time 91181451 ps
CPU time 2.15 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:04:29 PM PST 24
Peak memory 218092 kb
Host smart-61343fb9-6274-45aa-99b4-35d9390a7eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193679425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.193679425
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3552759193
Short name T868
Test name
Test status
Simulation time 189309030 ps
CPU time 8.22 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 01:04:51 PM PST 24
Peak memory 218116 kb
Host smart-ae611d62-2b60-45e2-95db-1ba02ed7e7dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552759193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3552759193
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.877530044
Short name T905
Test name
Test status
Simulation time 5738265953 ps
CPU time 14.58 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 218160 kb
Host smart-b547ef91-1f90-4142-bf69-1354109bc50d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877530044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.877530044
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1812030271
Short name T646
Test name
Test status
Simulation time 3718944104 ps
CPU time 12.61 seconds
Started Jan 07 01:04:40 PM PST 24
Finished Jan 07 01:04:55 PM PST 24
Peak memory 218152 kb
Host smart-274ce6b0-841d-4325-a6d7-0fa7e5e8dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812030271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1812030271
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1310691032
Short name T544
Test name
Test status
Simulation time 52805838 ps
CPU time 3.26 seconds
Started Jan 07 01:04:36 PM PST 24
Finished Jan 07 01:04:47 PM PST 24
Peak memory 217952 kb
Host smart-86fdbb1a-7f3a-4e0d-94b7-3cffeb6f52e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310691032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1310691032
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2309966928
Short name T464
Test name
Test status
Simulation time 1101342630 ps
CPU time 25.69 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:05:05 PM PST 24
Peak memory 251032 kb
Host smart-23b73e54-6e52-4a3c-b100-3621aeb15089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309966928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2309966928
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2620666415
Short name T756
Test name
Test status
Simulation time 186983184 ps
CPU time 7.63 seconds
Started Jan 07 01:04:32 PM PST 24
Finished Jan 07 01:04:44 PM PST 24
Peak memory 251168 kb
Host smart-39011750-b159-4229-bbaf-cb7203268759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620666415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2620666415
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.4294289203
Short name T748
Test name
Test status
Simulation time 2499659820 ps
CPU time 99.74 seconds
Started Jan 07 01:03:39 PM PST 24
Finished Jan 07 01:05:28 PM PST 24
Peak memory 275752 kb
Host smart-97c318ea-4b29-43e2-8720-b60c9ddd3ce7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294289203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.4294289203
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2692011964
Short name T472
Test name
Test status
Simulation time 54925833 ps
CPU time 0.73 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:04:23 PM PST 24
Peak memory 208232 kb
Host smart-391662bd-246c-4baa-b9a9-e9a3dfdb9391
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692011964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2692011964
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1506869367
Short name T628
Test name
Test status
Simulation time 24733039 ps
CPU time 0.91 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:03:57 PM PST 24
Peak memory 209724 kb
Host smart-171a9fca-0c09-4c89-a421-c1aaba99becc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506869367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1506869367
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1769510580
Short name T933
Test name
Test status
Simulation time 276132378 ps
CPU time 10.78 seconds
Started Jan 07 01:03:54 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 218124 kb
Host smart-6d90ee7c-0eb5-472d-9e2c-eb1bdffd6e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769510580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1769510580
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2664340214
Short name T864
Test name
Test status
Simulation time 297791583 ps
CPU time 1.57 seconds
Started Jan 07 01:03:46 PM PST 24
Finished Jan 07 01:03:53 PM PST 24
Peak memory 209608 kb
Host smart-2696bd25-3373-4e1b-b371-734f614e824e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664340214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_a
ccess.2664340214
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.564207535
Short name T706
Test name
Test status
Simulation time 132936112 ps
CPU time 3.53 seconds
Started Jan 07 01:03:38 PM PST 24
Finished Jan 07 01:03:51 PM PST 24
Peak memory 218200 kb
Host smart-ece4680a-0a73-4af7-8f17-8411a8de77cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564207535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.564207535
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3313463308
Short name T890
Test name
Test status
Simulation time 293408715 ps
CPU time 13.04 seconds
Started Jan 07 01:03:49 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 219228 kb
Host smart-2587f8e4-11f0-41e5-ba18-c8e4ffe167c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313463308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3313463308
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1357963238
Short name T475
Test name
Test status
Simulation time 656676736 ps
CPU time 13.6 seconds
Started Jan 07 01:03:54 PM PST 24
Finished Jan 07 01:04:11 PM PST 24
Peak memory 218048 kb
Host smart-72950263-bbdd-4efd-b802-69a31f8fc182
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357963238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1357963238
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2887145615
Short name T598
Test name
Test status
Simulation time 679193449 ps
CPU time 11.05 seconds
Started Jan 07 01:03:47 PM PST 24
Finished Jan 07 01:04:04 PM PST 24
Peak memory 218064 kb
Host smart-6a844651-aa71-4500-bcf5-f9f0fb396f5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887145615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2887145615
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1738848581
Short name T942
Test name
Test status
Simulation time 799868013 ps
CPU time 9.36 seconds
Started Jan 07 01:03:40 PM PST 24
Finished Jan 07 01:03:59 PM PST 24
Peak memory 218200 kb
Host smart-9b1a43f0-f20b-4b4f-baa4-dc5ce2d0e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738848581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1738848581
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.292078110
Short name T720
Test name
Test status
Simulation time 146455767 ps
CPU time 2.28 seconds
Started Jan 07 01:04:25 PM PST 24
Finished Jan 07 01:04:31 PM PST 24
Peak memory 213244 kb
Host smart-e0e12369-2d82-4608-ba81-a04da4e5773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292078110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.292078110
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3318958777
Short name T463
Test name
Test status
Simulation time 293978152 ps
CPU time 27.45 seconds
Started Jan 07 01:03:48 PM PST 24
Finished Jan 07 01:04:21 PM PST 24
Peak memory 250952 kb
Host smart-72fc98eb-2060-4ed9-aa59-76d581d8ca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318958777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3318958777
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1413538788
Short name T958
Test name
Test status
Simulation time 229943024 ps
CPU time 6.74 seconds
Started Jan 07 01:03:48 PM PST 24
Finished Jan 07 01:04:00 PM PST 24
Peak memory 246456 kb
Host smart-7b4faf4a-d3c0-4ea5-be09-ab547cd4e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413538788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1413538788
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1020152092
Short name T683
Test name
Test status
Simulation time 8319659462 ps
CPU time 66.52 seconds
Started Jan 07 01:03:49 PM PST 24
Finished Jan 07 01:05:00 PM PST 24
Peak memory 267608 kb
Host smart-4fb80aca-d9d1-4267-ac7b-1f2e13f84556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020152092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1020152092
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.913683988
Short name T27
Test name
Test status
Simulation time 43201531 ps
CPU time 0.92 seconds
Started Jan 07 01:03:55 PM PST 24
Finished Jan 07 01:03:59 PM PST 24
Peak memory 212572 kb
Host smart-a47ae6ad-49b1-4d3d-9c5d-5c57055629ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913683988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.913683988
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1672961605
Short name T969
Test name
Test status
Simulation time 77682408 ps
CPU time 1.01 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 209708 kb
Host smart-927aa626-4d14-47b8-bed9-d6d3bbe6a3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672961605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1672961605
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3628950506
Short name T471
Test name
Test status
Simulation time 975290280 ps
CPU time 16.63 seconds
Started Jan 07 01:03:44 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 218168 kb
Host smart-72e67da7-75e6-4415-92cc-1342271c326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628950506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3628950506
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3705873263
Short name T515
Test name
Test status
Simulation time 1061755786 ps
CPU time 3.67 seconds
Started Jan 07 01:03:55 PM PST 24
Finished Jan 07 01:04:02 PM PST 24
Peak memory 209696 kb
Host smart-06600979-c60a-4c2c-bed7-e5f7f55537b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705873263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.3705873263
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2593323594
Short name T907
Test name
Test status
Simulation time 19855434 ps
CPU time 1.77 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 218232 kb
Host smart-ba3438ad-36ba-4246-a1b7-bfeb30605b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593323594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2593323594
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.774236397
Short name T819
Test name
Test status
Simulation time 1364553692 ps
CPU time 10.83 seconds
Started Jan 07 01:03:53 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 218744 kb
Host smart-457b4d49-90a5-480c-b52b-1639b3b4719b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774236397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.774236397
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.269303923
Short name T723
Test name
Test status
Simulation time 1630610085 ps
CPU time 11 seconds
Started Jan 07 01:03:52 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 218012 kb
Host smart-fd38f765-01f6-471e-bec6-79f1acff5a06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269303923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.269303923
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.624649919
Short name T343
Test name
Test status
Simulation time 1050930511 ps
CPU time 9.76 seconds
Started Jan 07 01:04:05 PM PST 24
Finished Jan 07 01:04:18 PM PST 24
Peak memory 218172 kb
Host smart-88624d3a-7ea0-4736-a1a4-5ba0ca53037d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624649919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.624649919
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3091291073
Short name T35
Test name
Test status
Simulation time 1574691054 ps
CPU time 13.48 seconds
Started Jan 07 01:03:58 PM PST 24
Finished Jan 07 01:04:15 PM PST 24
Peak memory 218224 kb
Host smart-a5e12f72-9576-4130-8bed-7177d9f62a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091291073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3091291073
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3265410054
Short name T805
Test name
Test status
Simulation time 770937977 ps
CPU time 9.64 seconds
Started Jan 07 01:03:57 PM PST 24
Finished Jan 07 01:04:11 PM PST 24
Peak memory 214656 kb
Host smart-c9ad9967-6581-4d4c-9866-e7bdb55f37b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265410054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3265410054
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2189031103
Short name T425
Test name
Test status
Simulation time 565217967 ps
CPU time 25.95 seconds
Started Jan 07 01:03:55 PM PST 24
Finished Jan 07 01:04:24 PM PST 24
Peak memory 251012 kb
Host smart-c794d9d3-0808-4b37-8cc6-c7cdfb231492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189031103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2189031103
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2957143240
Short name T523
Test name
Test status
Simulation time 155478308 ps
CPU time 6.84 seconds
Started Jan 07 01:03:58 PM PST 24
Finished Jan 07 01:04:09 PM PST 24
Peak memory 250632 kb
Host smart-ca249af0-0fea-4028-98f5-76b4c6d94496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957143240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2957143240
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2295165674
Short name T963
Test name
Test status
Simulation time 65430010092 ps
CPU time 140.31 seconds
Started Jan 07 01:04:07 PM PST 24
Finished Jan 07 01:06:30 PM PST 24
Peak memory 220908 kb
Host smart-51d1e841-f4b4-4a7b-88b7-b8a844b68fbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295165674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2295165674
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3996139258
Short name T621
Test name
Test status
Simulation time 27439999 ps
CPU time 0.87 seconds
Started Jan 07 01:04:03 PM PST 24
Finished Jan 07 01:04:08 PM PST 24
Peak memory 208176 kb
Host smart-57b244b5-2233-4254-8228-69f38cbe1906
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996139258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3996139258
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1502271474
Short name T768
Test name
Test status
Simulation time 158503486 ps
CPU time 0.98 seconds
Started Jan 07 01:04:18 PM PST 24
Finished Jan 07 01:04:23 PM PST 24
Peak memory 208372 kb
Host smart-1b324d78-f9cb-4b80-b286-09c5d01015d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502271474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1502271474
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.841263876
Short name T770
Test name
Test status
Simulation time 1373367043 ps
CPU time 12.05 seconds
Started Jan 07 01:04:19 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 218144 kb
Host smart-fa864f93-9840-49e1-8125-ed096ac1faca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841263876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.841263876
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2472866982
Short name T722
Test name
Test status
Simulation time 2249851447 ps
CPU time 4.2 seconds
Started Jan 07 01:04:04 PM PST 24
Finished Jan 07 01:04:12 PM PST 24
Peak memory 209708 kb
Host smart-9a25eecf-e877-4368-8020-77e6a3624c76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472866982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_a
ccess.2472866982
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2924009253
Short name T634
Test name
Test status
Simulation time 48310089 ps
CPU time 2.08 seconds
Started Jan 07 01:04:05 PM PST 24
Finished Jan 07 01:04:11 PM PST 24
Peak memory 218232 kb
Host smart-b92d47b8-3225-403b-8361-08e2c3a5831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924009253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2924009253
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2218690359
Short name T43
Test name
Test status
Simulation time 435991674 ps
CPU time 9.82 seconds
Started Jan 07 01:04:23 PM PST 24
Finished Jan 07 01:04:36 PM PST 24
Peak memory 218124 kb
Host smart-28f7c0de-38de-4961-8890-17dc8382e81d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218690359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2218690359
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.649248560
Short name T681
Test name
Test status
Simulation time 1339351248 ps
CPU time 11.73 seconds
Started Jan 07 01:04:06 PM PST 24
Finished Jan 07 01:04:23 PM PST 24
Peak memory 217992 kb
Host smart-eef911c6-65ae-4e81-ac90-077717bcbed7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649248560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.649248560
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1400416897
Short name T613
Test name
Test status
Simulation time 660148923 ps
CPU time 14.84 seconds
Started Jan 07 01:04:24 PM PST 24
Finished Jan 07 01:04:42 PM PST 24
Peak memory 218084 kb
Host smart-40eee535-15d5-4fd4-90ca-9611a0a30542
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400416897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1400416897
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1522105173
Short name T595
Test name
Test status
Simulation time 616387957 ps
CPU time 12.86 seconds
Started Jan 07 01:04:35 PM PST 24
Finished Jan 07 01:04:52 PM PST 24
Peak memory 218176 kb
Host smart-2d096fc9-3d3d-42ab-9102-0a87208b04c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522105173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1522105173
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3436271493
Short name T527
Test name
Test status
Simulation time 137466977 ps
CPU time 1.5 seconds
Started Jan 07 01:04:01 PM PST 24
Finished Jan 07 01:04:07 PM PST 24
Peak memory 213196 kb
Host smart-0aa517be-33d3-455b-9f06-37dd802e04bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436271493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3436271493
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1159885312
Short name T968
Test name
Test status
Simulation time 548607596 ps
CPU time 25.2 seconds
Started Jan 07 01:04:11 PM PST 24
Finished Jan 07 01:04:38 PM PST 24
Peak memory 251112 kb
Host smart-db655ad2-afcd-4771-a1a7-b76cf338e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159885312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1159885312
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3566677262
Short name T416
Test name
Test status
Simulation time 115622932 ps
CPU time 9.05 seconds
Started Jan 07 01:04:00 PM PST 24
Finished Jan 07 01:04:13 PM PST 24
Peak memory 251108 kb
Host smart-9719a003-0c80-432f-a9a7-c1639d57b001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566677262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3566677262
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3386531421
Short name T342
Test name
Test status
Simulation time 35938649460 ps
CPU time 268.65 seconds
Started Jan 07 01:04:03 PM PST 24
Finished Jan 07 01:08:37 PM PST 24
Peak memory 250216 kb
Host smart-52879af6-3895-4e5a-a458-c292d3ff6e35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386531421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3386531421
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.645298912
Short name T755
Test name
Test status
Simulation time 144962692 ps
CPU time 0.95 seconds
Started Jan 07 01:03:58 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 211492 kb
Host smart-3cd767f3-3368-4370-baf4-ce10de543a62
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645298912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.645298912
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3575220683
Short name T355
Test name
Test status
Simulation time 16940914 ps
CPU time 0.86 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:02:13 PM PST 24
Peak memory 209620 kb
Host smart-02148598-93b9-4352-9c2f-0e4063e451b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575220683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3575220683
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1939117114
Short name T454
Test name
Test status
Simulation time 29347377 ps
CPU time 0.85 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 209648 kb
Host smart-0e20f7e8-f951-4959-aaa2-f2b46a56fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939117114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1939117114
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4109564373
Short name T823
Test name
Test status
Simulation time 697839372 ps
CPU time 13.36 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218132 kb
Host smart-e2cc63a2-33c2-43e0-925f-b9615ec36827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109564373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4109564373
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.258543089
Short name T728
Test name
Test status
Simulation time 3126566723 ps
CPU time 13.52 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:26 PM PST 24
Peak memory 209720 kb
Host smart-32b9db69-be13-44af-810d-d616e6d0ddc3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258543089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_acc
ess.258543089
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2299955906
Short name T671
Test name
Test status
Simulation time 3568611422 ps
CPU time 66.17 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:03:18 PM PST 24
Peak memory 220624 kb
Host smart-d4de7501-0fc9-4ed3-9245-08ed6c2fa030
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299955906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2299955906
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3284239630
Short name T966
Test name
Test status
Simulation time 703717120 ps
CPU time 5.39 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 209664 kb
Host smart-035f618f-1c32-4530-9c42-97e9ab224335
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284239630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.3284239630
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1990388621
Short name T653
Test name
Test status
Simulation time 1899840766 ps
CPU time 13 seconds
Started Jan 07 01:01:50 PM PST 24
Finished Jan 07 01:02:24 PM PST 24
Peak memory 218060 kb
Host smart-845bb5db-fc1f-4989-9a09-b0ed86477ced
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990388621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1990388621
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.391218297
Short name T612
Test name
Test status
Simulation time 3266057618 ps
CPU time 22.59 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:35 PM PST 24
Peak memory 213416 kb
Host smart-8469955c-790c-4008-95f8-1c705c99dc0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391218297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.391218297
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2716802115
Short name T690
Test name
Test status
Simulation time 160150031 ps
CPU time 5.1 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 213056 kb
Host smart-aace740d-dbc5-4ac7-b49c-ea97f95dd710
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716802115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2716802115
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1697933075
Short name T462
Test name
Test status
Simulation time 3020000661 ps
CPU time 63.07 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:03:15 PM PST 24
Peak memory 268676 kb
Host smart-996cc42c-3b8f-4af6-9913-ba761b0cc482
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697933075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1697933075
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1703121532
Short name T548
Test name
Test status
Simulation time 391218133 ps
CPU time 13.19 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:24 PM PST 24
Peak memory 251048 kb
Host smart-defe49d8-55fb-402d-aa7b-bd711cfd2ea4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703121532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1703121532
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.4053538701
Short name T351
Test name
Test status
Simulation time 204845099 ps
CPU time 4.02 seconds
Started Jan 07 01:01:50 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 218212 kb
Host smart-3d6d26e6-3862-43f0-9001-7308cc3ad77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053538701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4053538701
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4218383781
Short name T61
Test name
Test status
Simulation time 238917851 ps
CPU time 8.69 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 218092 kb
Host smart-c7fc02df-46fa-4f9b-96e8-1b89e27be556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218383781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4218383781
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3917977505
Short name T918
Test name
Test status
Simulation time 1369255366 ps
CPU time 9.11 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 219244 kb
Host smart-3ac5b042-772c-41d4-9e51-1fd6aaac5933
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917977505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3917977505
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2216787052
Short name T682
Test name
Test status
Simulation time 2443993087 ps
CPU time 8.05 seconds
Started Jan 07 01:01:50 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 218120 kb
Host smart-69c4d174-1a86-4adb-8142-1c403686cf7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216787052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2216787052
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3391895493
Short name T719
Test name
Test status
Simulation time 861980450 ps
CPU time 14.41 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 218072 kb
Host smart-af8c8d1a-e16b-432e-bd22-efcba41ecb11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391895493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
391895493
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1726121497
Short name T783
Test name
Test status
Simulation time 338984572 ps
CPU time 10.51 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 218208 kb
Host smart-6ca643a3-d781-4894-abb8-d5dba5c75c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726121497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1726121497
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3420061229
Short name T70
Test name
Test status
Simulation time 182365997 ps
CPU time 1.91 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 213460 kb
Host smart-1cafafc0-7189-40bd-9170-a527bbd038e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420061229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3420061229
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2634009261
Short name T298
Test name
Test status
Simulation time 453985785 ps
CPU time 27.23 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:36 PM PST 24
Peak memory 251268 kb
Host smart-d2848e38-0660-42f2-9be2-c6159d0ab036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634009261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2634009261
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2799581435
Short name T708
Test name
Test status
Simulation time 67959189 ps
CPU time 6.49 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 250496 kb
Host smart-2c3d7b51-1e82-4ad4-883e-d687bc7aab4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799581435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2799581435
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.950908393
Short name T565
Test name
Test status
Simulation time 9884740823 ps
CPU time 185.7 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:05:18 PM PST 24
Peak memory 246308 kb
Host smart-8bfb4bf0-44f0-4d6c-8a25-e39245746208
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950908393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.950908393
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3775399765
Short name T795
Test name
Test status
Simulation time 38371749 ps
CPU time 0.89 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:11 PM PST 24
Peak memory 208388 kb
Host smart-abe1c81a-9fee-474d-a4a4-b4efe55d05b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775399765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3775399765
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.87719745
Short name T369
Test name
Test status
Simulation time 33189313 ps
CPU time 1.15 seconds
Started Jan 07 01:01:47 PM PST 24
Finished Jan 07 01:02:10 PM PST 24
Peak memory 209776 kb
Host smart-fd727535-1f38-4be2-915b-35ba741c82d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87719745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.87719745
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2526855477
Short name T860
Test name
Test status
Simulation time 568924391 ps
CPU time 12.44 seconds
Started Jan 07 01:01:57 PM PST 24
Finished Jan 07 01:02:26 PM PST 24
Peak memory 218148 kb
Host smart-61bd8022-5199-4dc7-afd1-8c3c4521fd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526855477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2526855477
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.4035702107
Short name T841
Test name
Test status
Simulation time 1315431519 ps
CPU time 3.47 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:16 PM PST 24
Peak memory 209724 kb
Host smart-b58bc962-634b-4b4b-b0ee-cdc453850cfc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035702107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.4035702107
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1394378579
Short name T514
Test name
Test status
Simulation time 4867665092 ps
CPU time 34.29 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:43 PM PST 24
Peak memory 218228 kb
Host smart-9ab25924-2d47-4a14-89dc-2e0fc467826b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394378579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1394378579
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.162336696
Short name T570
Test name
Test status
Simulation time 306607644 ps
CPU time 4.41 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 209748 kb
Host smart-26ad93a6-196f-4f55-adee-c8941f5e0afc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162336696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_p
riority.162336696
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1287117485
Short name T762
Test name
Test status
Simulation time 768265451 ps
CPU time 7.27 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:16 PM PST 24
Peak memory 218120 kb
Host smart-28e811ee-6648-446b-9a14-cc16e0f58cbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287117485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1287117485
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3749778292
Short name T788
Test name
Test status
Simulation time 2956992618 ps
CPU time 22.08 seconds
Started Jan 07 01:01:47 PM PST 24
Finished Jan 07 01:02:31 PM PST 24
Peak memory 213320 kb
Host smart-ff7814f7-34f3-4956-86a8-d8781f4769c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749778292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3749778292
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1233477115
Short name T79
Test name
Test status
Simulation time 509928986 ps
CPU time 2.35 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 212896 kb
Host smart-53ac98ed-e090-4e94-b8c8-9a290b1e2ba9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233477115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1233477115
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1458091135
Short name T421
Test name
Test status
Simulation time 1141014418 ps
CPU time 34.85 seconds
Started Jan 07 01:01:47 PM PST 24
Finished Jan 07 01:02:45 PM PST 24
Peak memory 251100 kb
Host smart-2a38037f-a60f-4055-a436-7b832987707b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458091135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1458091135
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3697328148
Short name T775
Test name
Test status
Simulation time 3837890277 ps
CPU time 21.75 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:34 PM PST 24
Peak memory 251224 kb
Host smart-b9cc55c2-80db-4189-916e-6ab54bc658c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697328148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3697328148
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1361367515
Short name T892
Test name
Test status
Simulation time 93858271 ps
CPU time 1.65 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:02:13 PM PST 24
Peak memory 218224 kb
Host smart-069fee3b-7451-443e-94a2-da7cc10d5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361367515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1361367515
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1321143981
Short name T411
Test name
Test status
Simulation time 876128909 ps
CPU time 8.03 seconds
Started Jan 07 01:01:59 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 214084 kb
Host smart-320b962b-b322-43ea-8e3f-9d451a78c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321143981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1321143981
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.206003434
Short name T655
Test name
Test status
Simulation time 887159686 ps
CPU time 11.56 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 218220 kb
Host smart-bcce2879-6f39-44e1-8c46-8e2cff6ad094
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206003434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.206003434
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.503724781
Short name T373
Test name
Test status
Simulation time 954465955 ps
CPU time 18.7 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 218140 kb
Host smart-f38110e5-9db1-49d6-8323-1c4b34f2dbc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503724781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.503724781
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3407776800
Short name T601
Test name
Test status
Simulation time 943615175 ps
CPU time 7.77 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 218172 kb
Host smart-f7730143-2b46-4e45-8d92-9b06540ba4f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407776800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
407776800
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2209036783
Short name T947
Test name
Test status
Simulation time 244631308 ps
CPU time 9.49 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 218192 kb
Host smart-668bbbb5-51ed-4725-b433-eb7391d5a7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209036783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2209036783
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1593223664
Short name T398
Test name
Test status
Simulation time 52511903 ps
CPU time 2.87 seconds
Started Jan 07 01:02:00 PM PST 24
Finished Jan 07 01:02:17 PM PST 24
Peak memory 214232 kb
Host smart-d3c90674-b991-428d-8aba-3d161d771b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593223664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1593223664
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3938956732
Short name T903
Test name
Test status
Simulation time 5204996908 ps
CPU time 24.08 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:02:36 PM PST 24
Peak memory 250876 kb
Host smart-6106d689-3093-437e-bead-f288986f7a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938956732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3938956732
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2449632547
Short name T468
Test name
Test status
Simulation time 168363528 ps
CPU time 7.2 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 251208 kb
Host smart-2ee39c99-9c7c-40a7-8da9-9612cbac1a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449632547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2449632547
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.782398849
Short name T111
Test name
Test status
Simulation time 35308530024 ps
CPU time 222.08 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:05:55 PM PST 24
Peak memory 405052 kb
Host smart-081ef2a5-eb82-4094-b449-565fdfac48db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782398849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.782398849
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4251318673
Short name T325
Test name
Test status
Simulation time 153497901 ps
CPU time 0.73 seconds
Started Jan 07 01:02:01 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 208180 kb
Host smart-5bf9f2c4-4462-4dca-ba75-7abdd7f18958
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251318673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4251318673
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3118991192
Short name T945
Test name
Test status
Simulation time 17338414 ps
CPU time 1.04 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 209752 kb
Host smart-feb26a10-9f9d-42a2-9e3b-c8d8f18addd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118991192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3118991192
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4275446919
Short name T763
Test name
Test status
Simulation time 13233959 ps
CPU time 1.02 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:13 PM PST 24
Peak memory 209680 kb
Host smart-92b8f406-21a5-4d7e-a04f-4eef107457fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275446919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4275446919
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1477585111
Short name T781
Test name
Test status
Simulation time 993971336 ps
CPU time 9.6 seconds
Started Jan 07 01:01:57 PM PST 24
Finished Jan 07 01:02:23 PM PST 24
Peak memory 218136 kb
Host smart-61355044-0c6c-42e6-9759-acb2bff73cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477585111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1477585111
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2376297321
Short name T7
Test name
Test status
Simulation time 746051416 ps
CPU time 7.46 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 209668 kb
Host smart-a3fa669f-3f12-4cd5-8384-6206d71f4811
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376297321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.2376297321
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4130034041
Short name T959
Test name
Test status
Simulation time 6680560791 ps
CPU time 41.68 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:53 PM PST 24
Peak memory 219372 kb
Host smart-8f633100-0d87-4bb5-9c6d-6ebf81449e41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130034041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4130034041
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2578241142
Short name T481
Test name
Test status
Simulation time 1254091086 ps
CPU time 14.78 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:27 PM PST 24
Peak memory 217980 kb
Host smart-5e7df106-e3cb-403d-b6a2-e92e39f370d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578241142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.2578241142
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1645195885
Short name T362
Test name
Test status
Simulation time 65332828 ps
CPU time 2.96 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 218224 kb
Host smart-59e7ac43-4913-4f10-b449-e254a612e831
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645195885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1645195885
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1528182043
Short name T76
Test name
Test status
Simulation time 1254754836 ps
CPU time 16.7 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:28 PM PST 24
Peak memory 213096 kb
Host smart-43eb7f53-9403-4ff0-8fc9-177763a0b81a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528182043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1528182043
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2509765243
Short name T72
Test name
Test status
Simulation time 371662663 ps
CPU time 3.17 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 213048 kb
Host smart-30a17dd3-901e-47df-8482-da168389a3ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509765243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2509765243
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.544833690
Short name T542
Test name
Test status
Simulation time 1918022680 ps
CPU time 27.72 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:39 PM PST 24
Peak memory 251076 kb
Host smart-30bbc75a-0cd3-4ff0-a9f8-9e2cb04155ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544833690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.544833690
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3501089799
Short name T506
Test name
Test status
Simulation time 1389869645 ps
CPU time 17.84 seconds
Started Jan 07 01:01:50 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 251124 kb
Host smart-ebf0fdb8-d434-46bb-9aad-bfb9e1415872
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501089799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3501089799
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.475317691
Short name T898
Test name
Test status
Simulation time 14675140 ps
CPU time 1.52 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 218192 kb
Host smart-4c237193-2a93-4ba6-aa9d-e44e870e3a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475317691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.475317691
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1374802783
Short name T932
Test name
Test status
Simulation time 1786785603 ps
CPU time 12.86 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:26 PM PST 24
Peak memory 214436 kb
Host smart-1b1be94c-6825-4eb6-bd2e-9d96c80cfeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374802783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1374802783
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1873900838
Short name T562
Test name
Test status
Simulation time 602587837 ps
CPU time 15.15 seconds
Started Jan 07 01:01:57 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 218132 kb
Host smart-f8e1abc5-585e-4805-9d38-510f24e70b86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873900838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1873900838
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2110190476
Short name T695
Test name
Test status
Simulation time 701616784 ps
CPU time 17.24 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:29 PM PST 24
Peak memory 218092 kb
Host smart-f41a9af8-cc72-44bf-83ef-f2c9b87b612f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110190476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2110190476
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1990550373
Short name T312
Test name
Test status
Simulation time 292764738 ps
CPU time 10.88 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:02:23 PM PST 24
Peak memory 218176 kb
Host smart-5d20b85a-76e7-4428-b340-dfa029934351
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990550373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
990550373
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.952899454
Short name T501
Test name
Test status
Simulation time 515278165 ps
CPU time 16.64 seconds
Started Jan 07 01:01:56 PM PST 24
Finished Jan 07 01:02:30 PM PST 24
Peak memory 218200 kb
Host smart-fc9a2e66-c570-4a1a-a0f7-76c062aa9a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952899454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.952899454
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1445558097
Short name T578
Test name
Test status
Simulation time 201390717 ps
CPU time 2.85 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:13 PM PST 24
Peak memory 214228 kb
Host smart-bbb2aee1-c1bb-400b-9716-3f9434c43f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445558097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1445558097
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2905355514
Short name T743
Test name
Test status
Simulation time 225855129 ps
CPU time 24.84 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:34 PM PST 24
Peak memory 251124 kb
Host smart-ef35ebb0-dc85-473a-a1e7-2a07fbe3d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905355514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2905355514
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1941002430
Short name T737
Test name
Test status
Simulation time 54864776 ps
CPU time 3.29 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:13 PM PST 24
Peak memory 222008 kb
Host smart-5b081d67-da36-4ed6-a3e8-d26624b7d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941002430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1941002430
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2688998887
Short name T435
Test name
Test status
Simulation time 932630434 ps
CPU time 13.57 seconds
Started Jan 07 01:01:51 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 251108 kb
Host smart-ed3a728c-b2fb-4d97-b03b-a41cbbbf33fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688998887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2688998887
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3742578157
Short name T508
Test name
Test status
Simulation time 14345185 ps
CPU time 0.94 seconds
Started Jan 07 01:01:49 PM PST 24
Finished Jan 07 01:02:11 PM PST 24
Peak memory 208448 kb
Host smart-8e2c9395-75e3-4245-a522-e0ae62691617
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742578157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3742578157
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.566464621
Short name T436
Test name
Test status
Simulation time 21232817 ps
CPU time 0.91 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 209672 kb
Host smart-a9cd9357-fca1-410d-8ab2-23e8b1996db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566464621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.566464621
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3185848395
Short name T931
Test name
Test status
Simulation time 18786023 ps
CPU time 0.75 seconds
Started Jan 07 01:01:50 PM PST 24
Finished Jan 07 01:02:12 PM PST 24
Peak memory 208052 kb
Host smart-52acd5ef-4e30-4fc8-a03d-a0f0ca30b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185848395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3185848395
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.4052343286
Short name T700
Test name
Test status
Simulation time 488005119 ps
CPU time 12.23 seconds
Started Jan 07 01:01:57 PM PST 24
Finished Jan 07 01:02:26 PM PST 24
Peak memory 218172 kb
Host smart-d717cf70-3fca-49c7-a7e1-5e9437bc1d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052343286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.4052343286
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2836665144
Short name T24
Test name
Test status
Simulation time 3974124804 ps
CPU time 9.05 seconds
Started Jan 07 01:01:47 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 209756 kb
Host smart-f10e7e0f-ff62-4a08-bbee-4b612677938d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836665144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.2836665144
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2045357848
Short name T42
Test name
Test status
Simulation time 1450203585 ps
CPU time 44.47 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:54 PM PST 24
Peak memory 218132 kb
Host smart-29019cb8-8232-4989-b3c8-ab5cf164c8ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045357848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2045357848
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2017170078
Short name T295
Test name
Test status
Simulation time 7797828282 ps
CPU time 21.63 seconds
Started Jan 07 01:01:46 PM PST 24
Finished Jan 07 01:02:30 PM PST 24
Peak memory 217892 kb
Host smart-fab72114-37a2-41b8-90c0-1499bd3d6d3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017170078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.2017170078
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1802380924
Short name T797
Test name
Test status
Simulation time 343878065 ps
CPU time 11.09 seconds
Started Jan 07 01:01:54 PM PST 24
Finished Jan 07 01:02:24 PM PST 24
Peak memory 218172 kb
Host smart-5d4af5d8-2423-4397-8b1d-9b901263c85d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802380924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1802380924
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1828155397
Short name T651
Test name
Test status
Simulation time 5983508979 ps
CPU time 18.25 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:31 PM PST 24
Peak memory 213932 kb
Host smart-82bc7f6d-c218-4eb5-825e-38a3b3a2b6a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828155397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1828155397
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2740055091
Short name T331
Test name
Test status
Simulation time 292512118 ps
CPU time 5.86 seconds
Started Jan 07 01:01:55 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 213488 kb
Host smart-d4769980-ed55-40bc-b5c7-2e5007e07911
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740055091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2740055091
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2070465859
Short name T360
Test name
Test status
Simulation time 3359401141 ps
CPU time 64.71 seconds
Started Jan 07 01:02:01 PM PST 24
Finished Jan 07 01:03:19 PM PST 24
Peak memory 251108 kb
Host smart-1c3a2ba1-95a8-4e9a-ac78-512ade32e39d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070465859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2070465859
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.4163048457
Short name T446
Test name
Test status
Simulation time 649931857 ps
CPU time 10.42 seconds
Started Jan 07 01:01:58 PM PST 24
Finished Jan 07 01:02:24 PM PST 24
Peak memory 251084 kb
Host smart-e43b805a-1368-4e09-a817-1b70d09aafdd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163048457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.4163048457
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1806260099
Short name T357
Test name
Test status
Simulation time 139112833 ps
CPU time 2.75 seconds
Started Jan 07 01:01:57 PM PST 24
Finished Jan 07 01:02:16 PM PST 24
Peak memory 218112 kb
Host smart-8043b2eb-5617-444a-8ffd-6df7c17a65ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806260099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1806260099
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3091175818
Short name T302
Test name
Test status
Simulation time 2648639967 ps
CPU time 10.09 seconds
Started Jan 07 01:01:59 PM PST 24
Finished Jan 07 01:02:24 PM PST 24
Peak memory 214204 kb
Host smart-141a28e0-2fbb-4eaa-930a-758e242e22c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091175818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3091175818
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2192221011
Short name T536
Test name
Test status
Simulation time 967553442 ps
CPU time 19.34 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:30 PM PST 24
Peak memory 218364 kb
Host smart-660eaa73-f7ac-4c4a-a890-21fa4c603b3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192221011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2192221011
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.477905628
Short name T412
Test name
Test status
Simulation time 362141791 ps
CPU time 14.02 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:24 PM PST 24
Peak memory 218116 kb
Host smart-3272a948-581d-458c-ad6d-98bde31f2807
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477905628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.477905628
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1597217943
Short name T866
Test name
Test status
Simulation time 1978570532 ps
CPU time 9.63 seconds
Started Jan 07 01:01:48 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 218100 kb
Host smart-19145f1f-0525-4f59-a0be-444a07697d65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597217943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
597217943
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1158534263
Short name T626
Test name
Test status
Simulation time 1126588563 ps
CPU time 7.52 seconds
Started Jan 07 01:01:59 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 218132 kb
Host smart-59dd9fc8-ee55-417b-a056-507f59d30b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158534263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1158534263
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2834991523
Short name T652
Test name
Test status
Simulation time 83379089 ps
CPU time 1.8 seconds
Started Jan 07 01:01:53 PM PST 24
Finished Jan 07 01:02:14 PM PST 24
Peak memory 213452 kb
Host smart-969ea386-59d1-4753-a482-2df5a845ac3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834991523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2834991523
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1360055015
Short name T758
Test name
Test status
Simulation time 1520486772 ps
CPU time 22.27 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:02:34 PM PST 24
Peak memory 251144 kb
Host smart-8ca98623-b326-4076-9743-87b7b0643299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360055015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1360055015
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.253559682
Short name T310
Test name
Test status
Simulation time 49532542 ps
CPU time 6.43 seconds
Started Jan 07 01:01:52 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 250676 kb
Host smart-f4d2acae-1afe-4dbe-84b7-b9d742708c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253559682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.253559682
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.738687831
Short name T576
Test name
Test status
Simulation time 4262089516 ps
CPU time 92.39 seconds
Started Jan 07 01:01:56 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 277236 kb
Host smart-0f97f9b6-8497-4bd9-b906-4703b15cf522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738687831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.738687831
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.447040408
Short name T377
Test name
Test status
Simulation time 41327885 ps
CPU time 0.9 seconds
Started Jan 07 01:01:59 PM PST 24
Finished Jan 07 01:02:15 PM PST 24
Peak memory 208192 kb
Host smart-3ca10e06-59d3-4150-aab4-418445918ab5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447040408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.447040408
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2525368470
Short name T827
Test name
Test status
Simulation time 116089691 ps
CPU time 1.1 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:19 PM PST 24
Peak memory 209644 kb
Host smart-33fddaed-b390-4042-88d9-40fcae5d9721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525368470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2525368470
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1351868871
Short name T352
Test name
Test status
Simulation time 1915295646 ps
CPU time 14.57 seconds
Started Jan 07 01:02:12 PM PST 24
Finished Jan 07 01:02:32 PM PST 24
Peak memory 218204 kb
Host smart-5b13bc53-5646-4dc2-9239-61351d163111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351868871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1351868871
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1883213064
Short name T549
Test name
Test status
Simulation time 580850895 ps
CPU time 2.49 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:21 PM PST 24
Peak memory 209696 kb
Host smart-d71d889a-df03-4f0f-b4be-a0b2aac4fff6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883213064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.1883213064
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2566576232
Short name T796
Test name
Test status
Simulation time 1640863138 ps
CPU time 29.04 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:48 PM PST 24
Peak memory 218108 kb
Host smart-f7fca60b-ddca-437b-a6ca-2411976fb16b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566576232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2566576232
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1071428122
Short name T60
Test name
Test status
Simulation time 499233376 ps
CPU time 2.99 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 209664 kb
Host smart-f9ae72c2-b4af-4089-ae42-80255f7e332e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071428122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
priority.1071428122
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.4001053893
Short name T668
Test name
Test status
Simulation time 227289864 ps
CPU time 7.15 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218176 kb
Host smart-234fbb0b-a6eb-40c5-b569-aa923f52aa1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001053893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.4001053893
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2434536388
Short name T736
Test name
Test status
Simulation time 3325916019 ps
CPU time 31.75 seconds
Started Jan 07 01:02:12 PM PST 24
Finished Jan 07 01:02:49 PM PST 24
Peak memory 213864 kb
Host smart-3035bfda-4c8b-488d-9a4a-cb041ff9b156
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434536388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2434536388
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1292924029
Short name T579
Test name
Test status
Simulation time 1016632940 ps
CPU time 8.08 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 213816 kb
Host smart-17753fb9-344d-49ae-b6dc-4ce4fcaa9e18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292924029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1292924029
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1453908461
Short name T185
Test name
Test status
Simulation time 1296638295 ps
CPU time 54.37 seconds
Started Jan 07 01:02:12 PM PST 24
Finished Jan 07 01:03:12 PM PST 24
Peak memory 252148 kb
Host smart-bb6f8cb6-d618-4282-9832-cf1efe5f7d90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453908461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1453908461
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.428933425
Short name T428
Test name
Test status
Simulation time 1778006233 ps
CPU time 7.74 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 223752 kb
Host smart-049892f9-7bc3-4dc3-9ed0-979bad645ea5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428933425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.428933425
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2993206874
Short name T964
Test name
Test status
Simulation time 65125127 ps
CPU time 2.77 seconds
Started Jan 07 01:02:14 PM PST 24
Finished Jan 07 01:02:22 PM PST 24
Peak memory 218268 kb
Host smart-e39de16b-708f-4483-9e62-8719c913e7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993206874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2993206874
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.628136697
Short name T73
Test name
Test status
Simulation time 812441907 ps
CPU time 7.91 seconds
Started Jan 07 01:02:12 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 214068 kb
Host smart-fa532131-3547-4bea-8219-71f24efb0ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628136697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.628136697
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1483754058
Short name T952
Test name
Test status
Simulation time 1277376558 ps
CPU time 16.49 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:33 PM PST 24
Peak memory 218144 kb
Host smart-7303fe69-8c4e-4703-ad39-b73121e49cc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483754058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1483754058
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2693113511
Short name T665
Test name
Test status
Simulation time 2221731090 ps
CPU time 11.75 seconds
Started Jan 07 01:02:09 PM PST 24
Finished Jan 07 01:02:28 PM PST 24
Peak memory 218236 kb
Host smart-aa18e5cc-04eb-4c8a-a69d-391777d06670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693113511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
693113511
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2927788635
Short name T53
Test name
Test status
Simulation time 243128843 ps
CPU time 7.96 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 218068 kb
Host smart-3f81db8b-a4b1-4d61-852a-ba46776332fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927788635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2927788635
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2437340854
Short name T305
Test name
Test status
Simulation time 130440370 ps
CPU time 3.69 seconds
Started Jan 07 01:02:11 PM PST 24
Finished Jan 07 01:02:21 PM PST 24
Peak memory 214132 kb
Host smart-4d617568-dad5-4b91-982e-b4a011947748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437340854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2437340854
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3475454507
Short name T957
Test name
Test status
Simulation time 1445603146 ps
CPU time 37.69 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:02:56 PM PST 24
Peak memory 250916 kb
Host smart-ee20a9b9-a564-478c-b98a-6a4eff2a38de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475454507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3475454507
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2752062119
Short name T617
Test name
Test status
Simulation time 75611216 ps
CPU time 3.34 seconds
Started Jan 07 01:02:09 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 222208 kb
Host smart-7343554c-e116-4763-a09c-4174377f6382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752062119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2752062119
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.454605343
Short name T577
Test name
Test status
Simulation time 1767924906 ps
CPU time 67.96 seconds
Started Jan 07 01:02:13 PM PST 24
Finished Jan 07 01:03:26 PM PST 24
Peak memory 251204 kb
Host smart-0eb7bb00-01e9-4b42-ad67-69d86cf4e131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454605343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.454605343
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3134299397
Short name T705
Test name
Test status
Simulation time 29727599 ps
CPU time 0.7 seconds
Started Jan 07 01:02:10 PM PST 24
Finished Jan 07 01:02:17 PM PST 24
Peak memory 206660 kb
Host smart-051ba690-b317-4341-a01b-69b228c9df56
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134299397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3134299397
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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