LC_CTRL Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: `042415198f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.640s	770.938us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.220s	19.496us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	17.482us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.490s	246.633us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.700s	129.391us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.040s	92.048us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	17.482us	20	20	100.00
		lc_ctrl_csr_aliasing	1.700s	129.391us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.780s	183.435us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.520s	360.424us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	13.234us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.290s	181.923us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	17.490s	421.943us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_prog_failure	7.290s	181.923us	50	50	100.00
		lc_ctrl_errors	17.490s	421.943us	50	50	100.00
		lc_ctrl_security_escalation	17.550s	6.506ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.484m	4.860ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.480s	2.041ms	20	20	100.00
		lc_ctrl_jtag_errors	1.302m	2.838ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.300s	1.964ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.820s	846.135us	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.480s	2.041ms	20	20	100.00
		lc_ctrl_jtag_errors	1.302m	2.838ms	20	20	100.00
		lc_ctrl_jtag_access	15.600s	2.548ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.960s	5.448ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.590s	162.149us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.370s	421.897us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.280s	2.132ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.700s	1.139ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.690s	68.729us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.340s	34.660us	8	10	80.00
		lc_ctrl_jtag_alert_test	1.870s	58.252us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	21.630s	7.798ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.100s	13.874us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.870m	56.108ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.270s	49.452us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.950s	132.185us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.950s	132.185us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.220s	19.496us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	17.482us	20	20	100.00
		lc_ctrl_csr_aliasing	1.700s	129.391us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.820s	38.307us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.220s	19.496us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	17.482us	20	20	100.00
		lc_ctrl_csr_aliasing	1.700s	129.391us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.820s	38.307us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
		lc_ctrl_tl_intg_err	4.410s	307.384us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.410s	307.384us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.520s	360.424us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.690s	1.446ms	50	50	100.00
		lc_ctrl_sec_cm	37.610s	776.306us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.550s	6.506ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.780s	183.435us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.820s	846.135us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	31.190s	2.151ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	31.190s	2.151ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.220s	2.236ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.050s	476.189us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.050s	476.189us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.106h	454.615ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			984	1030	95.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.38	97.29	95.97	91.98	100.00	96.13	98.48	94.82

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 28 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 28 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.36435286846933347627592707976809716603038233603969642674154744816891886037874
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:176d0506-ccc3-4f68-b793-969aeca8cb9f
```
  - 5.lc_ctrl_stress_all_with_rand_reset.85399706422237236295345213171752434889202645168272529444215700735533669759833
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:236b62d4-d062-4c81-a81a-7ddf750a9272
```
  - ... and 26 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 6 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.13600396553157625181897100768808252678213099048227771989921678329375323913109
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:448b0958-ff0d-4233-8f27-64ba6d71a94a
```
  - 2.lc_ctrl_stress_all_with_rand_reset.91695891399772693588443405926543060570558491946273572879676735702716701502619
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:33880d7e-a2b9-44a9-9be4-3fb9d78e525a
```
  - ... and 4 more failures.
UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 5 failures:
- Test lc_ctrl_jtag_csr_mem_rw_with_rand_reset has 2 failures.
  - 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.68667133330163612452784051159624143356221965429813757883578033478949079331730
    Line 332, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34659847 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @  34659847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.50782505843953010532390031962563312125728094317656748371282303962541612331905
    Line 334, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  57797018 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @  57797018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 14.lc_ctrl_stress_all_with_rand_reset.106433159476078333622101282307014864852608985425065562702942430078818185085053
    Line 15759, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6739205125 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 6739205125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.lc_ctrl_stress_all_with_rand_reset.112438822662346810546113042189355581855447565814711298909027799766671276850166
    Line 4474, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16319451194 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 16319451194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.58652051822969668462376614459965936829990764936305710797957322739209319480623
    Line 19554, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16336917012 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 16336917012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_stress_all has 1 failures.
  - 16.lc_ctrl_stress_all.107371468917671801066161807566141118443082723140634475497899623071425764023066
    Line 11759, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 11857883001 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 11857883001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 36.lc_ctrl_stress_all_with_rand_reset.102155843650200938605407217223494920163139967800362036426828735774649104218612
    Line 13810, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9928607339 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xe1b247a0
  UVM_INFO @ 9928607339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.lc_ctrl_stress_all_with_rand_reset.78320434580841248500142822201482348506487174299678282392895805883749774910281
    Line 11866, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 7455117952 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x13385200
  UVM_INFO @ 7455117952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.lc_ctrl_stress_all_with_rand_reset.45930138556242437188580834838840074765888976425556057036682717124825431154328
    Line 3965, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3860221769 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0
  UVM_INFO @ 3860221769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.lc_ctrl_stress_all_with_rand_reset.28547232641535567476504020811225381162737199546391727950963743342446027465402
    Line 26270, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10419041696 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
  UVM_INFO @ 10419041696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.lc_ctrl_stress_all_with_rand_reset.18905145558016025007572252090033666206819817376994281096766838516003798421763
    Line 17951, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56475709845 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked6
  UVM_INFO @ 56475709845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: 042415198f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `042415198f`