Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70283019

1

T66

12151

T90

6569

T91

7395

auto[1]

1282199

1

T1

1485

T2

99

T3

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70273323

1

T66

12151

T90

6569

T91

7395

auto[1]

1291895

1

T1

396

T2

594

T3

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5628902	1			T66	80		T90	110		T91	107
auto[IdleSt]	17068073	1			T66	12071		T90	6459		T91	7288
auto[ClkMuxSt]	30013	1			T1	19		T2	3		T3	5
auto[CntIncrSt]	29874	1			T1	19		T2	3		T3	5
auto[CntProgSt]	1389691	1			T1	140		T2	26		T3	51
auto[TransCheckSt]	23458	1			T2	3		T3	5		T10	51
auto[TokenHashSt]	23362250	1			T2	148		T3	109		T10	3005
auto[FlashRmaSt]	24111	1			T2	3		T3	49		T10	57
auto[TokenCheck0St]	10370	1			T2	3		T3	5		T10	38
auto[TokenCheck1St]	7450	1			T2	3		T3	5		T10	21
auto[TransProgSt]	300832	1			T2	11		T3	59		T10	401
auto[PostTransSt]	9981127	1			T1	1397		T2	476		T3	948
auto[ScrapSt]	67405	1			T106	631		T119	531		T116	214
auto[EscalateSt]	5572229	1			T1	2493		T2	1127		T3	1189
auto[InvalidSt]	8067944	1			T2	488		T3	508		T10	3662

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1489	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	8067944	1			T2	488		T3	508		T10	3662
EscalateSt	5572229	1			T1	2493		T2	1127		T3	1189
ScrapSt	67405	1			T106	631		T119	531		T116	214
PostTransSt	9981127	1			T1	1397		T2	476		T3	948
TransProgSt	300832	1			T2	11		T3	59		T10	401
TokenCheck1St	7450	1			T2	3		T3	5		T10	21
TokenCheck0St	10370	1			T2	3		T3	5		T10	38
FlashRmaSt	24111	1			T2	3		T3	49		T10	57
TokenHashSt	23362250	1			T2	148		T3	109		T10	3005
TransCheckSt	23458	1			T2	3		T3	5		T10	51
CntProgSt	1389691	1			T1	140		T2	26		T3	51
CntIncrSt	29874	1			T1	19		T2	3		T3	5
ClkMuxSt	30013	1			T1	19		T2	3		T3	5
IdleSt	17068073	1			T66	12071		T90	6459		T91	7288
ResetSt	5628902	1			T66	80		T90	110		T91	107
arcs[ResetSt=>IdleSt]	44462	1			T66	1		T90	1		T91	1
arcs[IdleSt=>ScrapSt]	228	1			T106	1		T119	2		T116	1
arcs[IdleSt=>ClkMuxSt]	29920	1			T1	19		T2	3		T3	5
arcs[ClkMuxSt=>CntIncrSt]	29874	1			T1	19		T2	3		T3	5
arcs[CntIncrSt=>PostTransSt]	1374	1			T5	8		T51	14		T6	11
arcs[CntIncrSt=>CntProgSt]	28441	1			T1	19		T2	3		T3	5
arcs[CntProgSt=>PostTransSt]	3859	1			T1	19		T10	18		T16	15
arcs[CntProgSt=>TransCheckSt]	23458	1			T2	3		T3	5		T10	51
arcs[TransCheckSt=>PostTransSt]	3314	1			T13	27		T5	7		T51	8
arcs[TransCheckSt=>TokenHashSt]	20024	1			T2	3		T3	5		T10	51
arcs[TokenHashSt=>PostTransSt]	8764	1			T10	13		T13	13		T16	8
arcs[TokenHashSt=>FlashRmaSt]	10476	1			T2	3		T3	5		T10	38
arcs[FlashRmaSt=>TokenCheck0St]	10370	1			T2	3		T3	5		T10	38
arcs[TokenCheck0St=>PostTransSt]	2882	1			T10	17		T13	14		T16	14
arcs[TokenCheck0St=>TokenCheck1St]	7450	1			T2	3		T3	5		T10	21
arcs[TokenCheck1St=>PostTransSt]	606	1			T10	1		T13	8		T16	2
arcs[TransProgSt=>PostTransSt]	5925	1			T2	3		T3	5		T10	20
arcs[IdleSt=>EscalateSt]	194	1			T17	4		T27	6		T53	10
arcs[ClkMuxSt=>EscalateSt]	46	1			T12	3		T17	1		T53	1
arcs[CntIncrSt=>EscalateSt]	59	1			T12	2		T17	1		T88	1
arcs[CntProgSt=>EscalateSt]	1124	1			T12	32		T17	31		T27	13
arcs[TransCheckSt=>EscalateSt]	120	1			T12	1		T17	1		T27	5
arcs[TokenHashSt=>EscalateSt]	768	1			T12	10		T17	11		T27	28
arcs[FlashRmaSt=>EscalateSt]	106	1			T12	6		T17	3		T27	1
arcs[TokenCheck0St=>EscalateSt]	38	1			T17	2		T87	2		T88	2
arcs[TokenCheck1St=>EscalateSt]	137	1			T12	2		T17	1		T27	2
arcs[TransProgSt=>EscalateSt]	782	1			T12	24		T17	17		T27	13
arcs[PostTransSt=>EscalateSt]	4099	1			T1	19		T10	18		T12	1
arcs[InvalidSt=>EscalateSt]	11981	1			T2	7		T3	7		T10	21

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5628719	1			T66	80		T90	110		T91	107
auto[0]	auto[IdleSt]	17067951	1			T66	12071		T90	6459		T91	7288
auto[0]	auto[ClkMuxSt]	29978	1			T1	19		T2	3		T3	5
auto[0]	auto[CntIncrSt]	29831	1			T1	19		T2	3		T3	5
auto[0]	auto[CntProgSt]	1388945	1			T1	140		T2	26		T3	51
auto[0]	auto[TransCheckSt]	23380	1			T2	3		T3	5		T10	51
auto[0]	auto[TokenHashSt]	23361735	1			T2	148		T3	109		T10	3005
auto[0]	auto[FlashRmaSt]	24037	1			T2	3		T3	49		T10	57
auto[0]	auto[TokenCheck0St]	10343	1			T2	3		T3	5		T10	38
auto[0]	auto[TokenCheck1St]	7357	1			T2	3		T3	5		T10	21
auto[0]	auto[TransProgSt]	300312	1			T2	11		T3	59		T10	401
auto[0]	auto[PostTransSt]	9979038	1			T1	1382		T2	476		T3	948
auto[0]	auto[ScrapSt]	67360	1			T106	631		T119	531		T116	214
auto[0]	auto[EscalateSt]	4300562	1			T1	1023		T2	1029		T3	699
auto[0]	auto[InvalidSt]	8061982	1			T2	487		T3	503		T10	3651
auto[1]	auto[ResetSt]	183	1			T12	9		T17	3		T27	5
auto[1]	auto[IdleSt]	122	1			T17	4		T27	5		T53	7
auto[1]	auto[ClkMuxSt]	35	1			T12	3		T17	1		T53	1
auto[1]	auto[CntIncrSt]	43	1			T17	1		T88	1		T192	2
auto[1]	auto[CntProgSt]	746	1			T12	21		T17	15		T27	8
auto[1]	auto[TransCheckSt]	78	1			T12	1		T17	1		T27	3
auto[1]	auto[TokenHashSt]	515	1			T12	9		T17	8		T27	19
auto[1]	auto[FlashRmaSt]	74	1			T12	2		T17	3		T53	2
auto[1]	auto[TokenCheck0St]	27	1			T17	2		T87	2		T88	2
auto[1]	auto[TokenCheck1St]	93	1			T27	2		T87	2		T88	2
auto[1]	auto[TransProgSt]	520	1			T12	16		T17	8		T27	7
auto[1]	auto[PostTransSt]	2089	1			T1	15		T10	10		T16	6
auto[1]	auto[ScrapSt]	45	1			T12	1		T27	1		T87	1
auto[1]	auto[EscalateSt]	1271667	1			T1	1470		T2	98		T3	490
auto[1]	auto[InvalidSt]	5962	1			T2	1		T3	5		T10	11

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5628699	1			T66	80		T90	110		T91	107
auto[0]	auto[IdleSt]	17067938	1			T66	12071		T90	6459		T91	7288
auto[0]	auto[ClkMuxSt]	29984	1			T1	19		T2	3		T3	5
auto[0]	auto[CntIncrSt]	29836	1			T1	19		T2	3		T3	5
auto[0]	auto[CntProgSt]	1388946	1			T1	140		T2	26		T3	51
auto[0]	auto[TransCheckSt]	23377	1			T2	3		T3	5		T10	51
auto[0]	auto[TokenHashSt]	23361738	1			T2	148		T3	109		T10	3005
auto[0]	auto[FlashRmaSt]	24046	1			T2	3		T3	49		T10	57
auto[0]	auto[TokenCheck0St]	10340	1			T2	3		T3	5		T10	38
auto[0]	auto[TokenCheck1St]	7360	1			T2	3		T3	5		T10	21
auto[0]	auto[TransProgSt]	300310	1			T2	11		T3	59		T10	401
auto[0]	auto[PostTransSt]	9979058	1			T1	1393		T2	476		T3	948
auto[0]	auto[ScrapSt]	67351	1			T106	631		T119	531		T116	214
auto[0]	auto[EscalateSt]	4290926	1			T1	2101		T2	539		T3	993
auto[0]	auto[InvalidSt]	8061925	1			T2	482		T3	506		T10	3652
auto[1]	auto[ResetSt]	203	1			T12	6		T17	1		T27	7
auto[1]	auto[IdleSt]	135	1			T17	2		T27	4		T53	5
auto[1]	auto[ClkMuxSt]	29	1			T12	1		T53	1		T87	1
auto[1]	auto[CntIncrSt]	38	1			T12	2		T17	1		T192	1
auto[1]	auto[CntProgSt]	745	1			T12	22		T17	24		T27	9
auto[1]	auto[TransCheckSt]	81	1			T12	1		T27	5		T53	1
auto[1]	auto[TokenHashSt]	512	1			T12	5		T17	5		T27	19
auto[1]	auto[FlashRmaSt]	65	1			T12	6		T17	1		T27	1
auto[1]	auto[TokenCheck0St]	30	1			T17	2		T87	1		T88	2
auto[1]	auto[TokenCheck1St]	90	1			T12	2		T17	1		T27	1
auto[1]	auto[TransProgSt]	522	1			T12	18		T17	15		T27	10
auto[1]	auto[PostTransSt]	2069	1			T1	4		T10	8		T12	1
auto[1]	auto[ScrapSt]	54	1			T12	1		T17	1		T27	1
auto[1]	auto[EscalateSt]	1281303	1			T1	392		T2	588		T3	196
auto[1]	auto[InvalidSt]	6019	1			T2	6		T3	2		T10	10