Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	792498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

980628

1

T66

506

T90

368

T91

222

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1481103	1			T66	131		T90	384		T91	55
values[0x0]	145425	1			T66	207		T90	181		T91	74
values[0x1]	146598	1			T66	245		T90	203		T91	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	626875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1146251

1

T66

562

T90

428

T91

254

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7236	1			T66	4		T90	2		T171	3
valid_sources[0x01]	7675	1			T66	2		T90	3		T171	4
valid_sources[0x02]	9009	1			T66	2		T90	2		T94	1
valid_sources[0x03]	5512	1			T66	2		T90	3		T96	1
valid_sources[0x04]	6804	1			T66	1		T92	10		T96	3
valid_sources[0x05]	6741	1			T66	2		T90	4		T94	3
valid_sources[0x06]	19507	1			T90	6		T94	6		T171	3
valid_sources[0x07]	8981	1			T90	2		T96	1		T171	4
valid_sources[0x08]	5296	1			T66	2		T90	3		T96	3
valid_sources[0x09]	5886	1			T66	1		T111	1		T135	8
valid_sources[0x0a]	6720	1			T66	3		T90	5		T171	2
valid_sources[0x0b]	5560	1			T66	2		T90	4		T94	3
valid_sources[0x0c]	6189	1			T66	1		T90	3		T96	2
valid_sources[0x0d]	6817	1			T66	2		T90	3		T171	3
valid_sources[0x0e]	5740	1			T66	4		T90	3		T135	3
valid_sources[0x0f]	5904	1			T66	1		T90	4		T98	2
valid_sources[0x10]	7505	1			T66	6		T90	4		T135	5
valid_sources[0x11]	5974	1			T90	1		T96	1		T171	4
valid_sources[0x12]	5543	1			T66	3		T90	6		T98	7
valid_sources[0x13]	7832	1			T66	3		T90	4		T94	2
valid_sources[0x14]	5450	1			T66	3		T90	3		T96	1
valid_sources[0x15]	6269	1			T66	1		T90	1		T96	1
valid_sources[0x16]	5388	1			T66	1		T90	3		T94	1
valid_sources[0x17]	7044	1			T66	4		T90	2		T171	4
valid_sources[0x18]	5940	1			T66	1		T90	3		T135	6
valid_sources[0x19]	6019	1			T66	2		T90	1		T96	1
valid_sources[0x1a]	5938	1			T66	3		T90	3		T94	1
valid_sources[0x1b]	5877	1			T66	2		T90	7		T94	13
valid_sources[0x1c]	6789	1			T66	3		T90	4		T96	2
valid_sources[0x1d]	7044	1			T66	4		T90	6		T94	3
valid_sources[0x1e]	5575	1			T66	3		T90	2		T171	3
valid_sources[0x1f]	5674	1			T66	1		T90	2		T96	2
valid_sources[0x20]	5470	1			T66	2		T90	4		T96	2
valid_sources[0x21]	5733	1			T66	4		T96	3		T171	4
valid_sources[0x22]	5602	1			T90	1		T94	6		T96	1
valid_sources[0x23]	5762	1			T66	6		T90	6		T94	3
valid_sources[0x24]	5554	1			T66	1		T90	3		T94	6
valid_sources[0x25]	9050	1			T94	6		T171	5		T103	1
valid_sources[0x26]	12301	1			T66	2		T90	3		T95	1
valid_sources[0x27]	5660	1			T66	3		T90	6		T171	4
valid_sources[0x28]	5815	1			T66	2		T90	6		T95	1
valid_sources[0x29]	5492	1			T66	3		T90	3		T171	4
valid_sources[0x2a]	5343	1			T90	4		T171	4		T173	2
valid_sources[0x2b]	5737	1			T66	1		T90	3		T94	2
valid_sources[0x2c]	6928	1			T66	5		T94	1		T96	2
valid_sources[0x2d]	5275	1			T90	4		T94	9		T96	1
valid_sources[0x2e]	7465	1			T66	1		T90	1		T95	1
valid_sources[0x2f]	9772	1			T66	1		T90	4		T94	2
valid_sources[0x30]	5691	1			T66	3		T90	5		T94	1
valid_sources[0x31]	5452	1			T66	2		T90	4		T94	1
valid_sources[0x32]	7056	1			T90	3		T171	4		T168	18
valid_sources[0x33]	12861	1			T66	3		T90	1		T94	7
valid_sources[0x34]	5916	1			T66	1		T90	5		T95	5
valid_sources[0x35]	6597	1			T66	3		T90	1		T96	1
valid_sources[0x36]	5926	1			T66	1		T90	2		T96	1
valid_sources[0x37]	5751	1			T66	2		T90	3		T96	1
valid_sources[0x38]	5697	1			T66	1		T90	2		T96	1
valid_sources[0x39]	5652	1			T66	1		T90	4		T94	1
valid_sources[0x3a]	5589	1			T66	3		T90	3		T94	6
valid_sources[0x3b]	6052	1			T90	4		T92	6		T94	1
valid_sources[0x3c]	5606	1			T66	3		T90	3		T94	6
valid_sources[0x3d]	5752	1			T66	2		T90	6		T95	2
valid_sources[0x3e]	5567	1			T66	1		T90	1		T94	8
valid_sources[0x3f]	5882	1			T66	2		T90	4		T98	3
valid_sources[0x40]	6845	1			T66	2		T94	2		T135	1
valid_sources[0x41]	5703	1			T66	6		T90	2		T135	7
valid_sources[0x42]	9973	1			T66	4		T90	3		T96	1
valid_sources[0x43]	6867	1			T66	3		T90	1		T171	3
valid_sources[0x44]	6018	1			T66	2		T96	1		T98	1
valid_sources[0x45]	5468	1			T66	1		T90	1		T94	3
valid_sources[0x46]	5915	1			T66	3		T90	3		T96	3
valid_sources[0x47]	5632	1			T66	2		T90	1		T95	1
valid_sources[0x48]	8699	1			T66	3		T90	3		T171	4
valid_sources[0x49]	5661	1			T66	3		T90	2		T92	26
valid_sources[0x4a]	5802	1			T66	3		T90	1		T96	1
valid_sources[0x4b]	5847	1			T66	1		T90	1		T94	11
valid_sources[0x4c]	5486	1			T66	2		T90	1		T111	2
valid_sources[0x4d]	5702	1			T66	1		T90	2		T94	6
valid_sources[0x4e]	5578	1			T66	1		T90	3		T96	1
valid_sources[0x4f]	5862	1			T66	1		T171	2		T173	2
valid_sources[0x50]	5612	1			T66	5		T90	1		T94	2
valid_sources[0x51]	6086	1			T90	4		T91	128		T171	2
valid_sources[0x52]	5789	1			T90	1		T96	1		T111	1
valid_sources[0x53]	5766	1			T66	5		T90	2		T94	2
valid_sources[0x54]	5427	1			T66	1		T90	4		T92	6
valid_sources[0x55]	5615	1			T66	1		T90	6		T94	5
valid_sources[0x56]	6307	1			T66	2		T90	6		T96	2
valid_sources[0x57]	5615	1			T66	2		T98	1		T135	1
valid_sources[0x58]	7222	1			T90	3		T95	2		T171	3
valid_sources[0x59]	5967	1			T66	6		T90	4		T171	4
valid_sources[0x5a]	5419	1			T66	2		T90	2		T94	1
valid_sources[0x5b]	39587	1			T66	1		T90	3		T94	4
valid_sources[0x5c]	8480	1			T66	3		T90	3		T94	1
valid_sources[0x5d]	5534	1			T66	4		T90	5		T96	1
valid_sources[0x5e]	5521	1			T66	2		T90	1		T94	4
valid_sources[0x5f]	5961	1			T66	1		T90	1		T94	2
valid_sources[0x60]	5671	1			T66	3		T90	2		T96	1
valid_sources[0x61]	6073	1			T90	5		T135	39		T171	1
valid_sources[0x62]	7644	1			T66	5		T90	2		T96	1
valid_sources[0x63]	5606	1			T66	2		T90	3		T96	1
valid_sources[0x64]	5601	1			T66	2		T90	2		T171	2
valid_sources[0x65]	8910	1			T66	2		T90	2		T96	1
valid_sources[0x66]	7509	1			T66	3		T90	7		T96	1
valid_sources[0x67]	5834	1			T66	2		T90	5		T171	2
valid_sources[0x68]	8628	1			T90	1		T94	6		T98	2
valid_sources[0x69]	5780	1			T66	2		T90	4		T98	4
valid_sources[0x6a]	5552	1			T90	4		T171	3		T146	1
valid_sources[0x6b]	5469	1			T66	2		T90	5		T94	6
valid_sources[0x6c]	5901	1			T66	2		T90	3		T96	2
valid_sources[0x6d]	5869	1			T66	6		T90	3		T94	4
valid_sources[0x6e]	6788	1			T66	4		T90	2		T96	1
valid_sources[0x6f]	5877	1			T66	4		T90	3		T171	2
valid_sources[0x70]	5742	1			T66	3		T90	8		T135	4
valid_sources[0x71]	5750	1			T66	2		T90	3		T94	1
valid_sources[0x72]	5772	1			T66	3		T90	5		T96	1
valid_sources[0x73]	7162	1			T90	2		T171	1		T109	1
valid_sources[0x74]	8509	1			T66	2		T90	1		T171	2
valid_sources[0x75]	5577	1			T90	1		T96	1		T171	4
valid_sources[0x76]	5868	1			T66	3		T90	2		T98	8
valid_sources[0x77]	5400	1			T66	5		T90	3		T96	1
valid_sources[0x78]	6925	1			T66	2		T90	5		T94	13
valid_sources[0x79]	7589	1			T66	2		T90	1		T94	6
valid_sources[0x7a]	5769	1			T66	8		T90	5		T98	4
valid_sources[0x7b]	7013	1			T66	5		T90	8		T135	34
valid_sources[0x7c]	27086	1			T66	3		T90	1		T94	1
valid_sources[0x7d]	5210	1			T90	5		T171	5		T173	2
valid_sources[0x7e]	7171	1			T66	3		T90	3		T94	1
valid_sources[0x7f]	8204	1			T66	1		T90	2		T94	6
valid_sources[0x80]	7628	1			T90	5		T98	3		T172	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

729165

1

T66

123

T90

175

T91

46

values[0x0]

all_enables

biggest_size

125977

1

T66

202

T90

97

T91

73

values[0x1]

all_enables

biggest_size

125486

1

T66

181

T90

96

T91

103