Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	71564929	14443	0	0
claim_transition_if_regwen_rd_A	71564929	1462	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71564929	14443	0	0
T66	12151	585	0	0
T90	6569	0	0	0
T91	7394	540	0	0
T92	2262	10	0	0
T93	78372	0	0	0
T94	4524	0	0	0
T95	1591	0	0	0
T96	1612	105	0	0
T97	970	0	0	0
T98	1361	0	0	0
T103	0	194	0	0
T106	0	4	0	0
T110	0	69	0	0
T135	0	838	0	0
T146	0	1083	0	0
T167	0	59	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71564929	1462	0	0
T66	12151	13	0	0
T90	6569	0	0	0
T91	7394	0	0	0
T92	2262	13	0	0
T93	78372	0	0	0
T94	4524	56	0	0
T95	1591	0	0	0
T96	1612	0	0	0
T97	970	0	0	0
T98	1361	0	0	0
T106	0	85	0	0
T115	0	61	0	0
T135	0	12	0	0
T146	0	14	0	0
T168	0	1	0	0
T169	0	8	0	0
T170	0	5	0	0