Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.37 97.29 95.88 91.98 100.00 96.13 98.48 94.82


Total test records in report: 979
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T762 /workspace/coverage/default/17.lc_ctrl_state_post_trans.183032052 Jan 10 12:40:55 PM PST 24 Jan 10 12:41:57 PM PST 24 217683967 ps
T763 /workspace/coverage/default/22.lc_ctrl_state_post_trans.749171359 Jan 10 12:34:19 PM PST 24 Jan 10 12:34:59 PM PST 24 97618512 ps
T764 /workspace/coverage/default/10.lc_ctrl_state_failure.729599231 Jan 10 12:40:06 PM PST 24 Jan 10 12:41:26 PM PST 24 741771839 ps
T765 /workspace/coverage/default/3.lc_ctrl_state_failure.4270860545 Jan 10 12:54:13 PM PST 24 Jan 10 12:55:47 PM PST 24 928788921 ps
T766 /workspace/coverage/default/8.lc_ctrl_prog_failure.2117816699 Jan 10 12:40:57 PM PST 24 Jan 10 12:41:54 PM PST 24 20844847 ps
T767 /workspace/coverage/default/46.lc_ctrl_state_post_trans.3234446960 Jan 10 12:36:08 PM PST 24 Jan 10 12:36:40 PM PST 24 83350140 ps
T768 /workspace/coverage/default/21.lc_ctrl_smoke.3317185870 Jan 10 12:34:23 PM PST 24 Jan 10 12:34:58 PM PST 24 22249933 ps
T769 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2859254783 Jan 10 12:34:21 PM PST 24 Jan 10 12:34:57 PM PST 24 133488963 ps
T770 /workspace/coverage/default/32.lc_ctrl_alert_test.3875092362 Jan 10 12:34:24 PM PST 24 Jan 10 12:34:59 PM PST 24 58592816 ps
T771 /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3484019260 Jan 10 12:39:40 PM PST 24 Jan 10 12:40:17 PM PST 24 2246099765 ps
T772 /workspace/coverage/default/14.lc_ctrl_state_failure.436551524 Jan 10 12:34:31 PM PST 24 Jan 10 12:35:37 PM PST 24 1888014793 ps
T773 /workspace/coverage/default/8.lc_ctrl_jtag_priority.2936780827 Jan 10 12:34:06 PM PST 24 Jan 10 12:34:39 PM PST 24 523964987 ps
T774 /workspace/coverage/default/0.lc_ctrl_stress_all.2054457711 Jan 10 12:46:21 PM PST 24 Jan 10 12:48:47 PM PST 24 3459881538 ps
T775 /workspace/coverage/default/22.lc_ctrl_alert_test.3424796121 Jan 10 12:34:25 PM PST 24 Jan 10 12:35:02 PM PST 24 19686764 ps
T776 /workspace/coverage/default/9.lc_ctrl_errors.899180249 Jan 10 12:34:28 PM PST 24 Jan 10 12:35:16 PM PST 24 315487878 ps
T777 /workspace/coverage/default/41.lc_ctrl_state_post_trans.4034961963 Jan 10 12:35:43 PM PST 24 Jan 10 12:36:11 PM PST 24 326797970 ps
T778 /workspace/coverage/default/49.lc_ctrl_jtag_access.2421387357 Jan 10 12:36:10 PM PST 24 Jan 10 12:36:50 PM PST 24 271178983 ps
T779 /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.74880380 Jan 10 12:34:33 PM PST 24 Jan 10 12:35:19 PM PST 24 369225669 ps
T780 /workspace/coverage/default/5.lc_ctrl_sec_mubi.3801277761 Jan 10 12:35:26 PM PST 24 Jan 10 12:36:07 PM PST 24 277319053 ps
T781 /workspace/coverage/default/42.lc_ctrl_prog_failure.853030649 Jan 10 12:35:42 PM PST 24 Jan 10 12:36:10 PM PST 24 101004712 ps
T782 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1162723185 Jan 10 12:52:25 PM PST 24 Jan 10 12:53:40 PM PST 24 11543604 ps
T783 /workspace/coverage/default/27.lc_ctrl_security_escalation.2373144937 Jan 10 12:34:04 PM PST 24 Jan 10 12:34:46 PM PST 24 431061624 ps
T784 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2049277487 Jan 10 12:42:58 PM PST 24 Jan 10 12:44:29 PM PST 24 779972623 ps
T785 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1602033747 Jan 10 12:35:59 PM PST 24 Jan 10 12:36:22 PM PST 24 11812565 ps
T786 /workspace/coverage/default/32.lc_ctrl_security_escalation.3618437293 Jan 10 12:34:28 PM PST 24 Jan 10 12:35:13 PM PST 24 320423463 ps
T787 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1744544042 Jan 10 12:50:14 PM PST 24 Jan 10 12:51:46 PM PST 24 851990312 ps
T788 /workspace/coverage/default/9.lc_ctrl_jtag_errors.3832047729 Jan 10 12:34:30 PM PST 24 Jan 10 12:35:40 PM PST 24 1101230913 ps
T789 /workspace/coverage/default/46.lc_ctrl_prog_failure.1857273624 Jan 10 12:36:05 PM PST 24 Jan 10 12:36:33 PM PST 24 97334245 ps
T790 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2914930515 Jan 10 12:39:05 PM PST 24 Jan 10 12:39:45 PM PST 24 501379299 ps
T791 /workspace/coverage/default/28.lc_ctrl_stress_all.104622247 Jan 10 12:34:04 PM PST 24 Jan 10 12:37:38 PM PST 24 9260264162 ps
T792 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3901186146 Jan 10 12:34:34 PM PST 24 Jan 10 12:35:23 PM PST 24 172546763 ps
T101 /workspace/coverage/default/1.lc_ctrl_sec_cm.2837198787 Jan 10 12:44:38 PM PST 24 Jan 10 12:46:16 PM PST 24 467935464 ps
T793 /workspace/coverage/default/31.lc_ctrl_state_failure.2010216986 Jan 10 12:34:28 PM PST 24 Jan 10 12:35:30 PM PST 24 177099350 ps
T794 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.323099542 Jan 10 12:34:21 PM PST 24 Jan 10 12:35:03 PM PST 24 667400427 ps
T795 /workspace/coverage/default/5.lc_ctrl_smoke.3882873930 Jan 10 01:13:06 PM PST 24 Jan 10 01:14:35 PM PST 24 64668291 ps
T796 /workspace/coverage/default/21.lc_ctrl_errors.3298183176 Jan 10 12:34:03 PM PST 24 Jan 10 12:34:39 PM PST 24 858966589 ps
T797 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2538324102 Jan 10 12:35:55 PM PST 24 Jan 10 12:36:27 PM PST 24 242430530 ps
T798 /workspace/coverage/default/33.lc_ctrl_alert_test.863093037 Jan 10 12:34:34 PM PST 24 Jan 10 12:35:15 PM PST 24 39260570 ps
T799 /workspace/coverage/default/49.lc_ctrl_prog_failure.3042779439 Jan 10 12:36:04 PM PST 24 Jan 10 12:36:31 PM PST 24 298203865 ps
T800 /workspace/coverage/default/19.lc_ctrl_security_escalation.4200767019 Jan 10 12:44:05 PM PST 24 Jan 10 12:45:28 PM PST 24 206539367 ps
T801 /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.876832918 Jan 10 12:38:41 PM PST 24 Jan 10 12:39:14 PM PST 24 14214948 ps
T802 /workspace/coverage/default/45.lc_ctrl_sec_mubi.753373022 Jan 10 12:36:07 PM PST 24 Jan 10 12:36:46 PM PST 24 268189151 ps
T803 /workspace/coverage/default/37.lc_ctrl_state_post_trans.3912994599 Jan 10 12:35:37 PM PST 24 Jan 10 12:36:09 PM PST 24 48449360 ps
T804 /workspace/coverage/default/20.lc_ctrl_prog_failure.2764408167 Jan 10 01:22:58 PM PST 24 Jan 10 01:23:18 PM PST 24 147210544 ps
T78 /workspace/coverage/default/36.lc_ctrl_alert_test.3391992015 Jan 10 12:35:27 PM PST 24 Jan 10 12:35:55 PM PST 24 145914334 ps
T805 /workspace/coverage/default/6.lc_ctrl_stress_all.2476559490 Jan 10 12:39:40 PM PST 24 Jan 10 12:44:53 PM PST 24 41357478111 ps
T806 /workspace/coverage/default/1.lc_ctrl_jtag_access.2915607088 Jan 10 12:40:07 PM PST 24 Jan 10 12:41:05 PM PST 24 7643257810 ps
T807 /workspace/coverage/default/2.lc_ctrl_state_failure.71298181 Jan 10 01:02:01 PM PST 24 Jan 10 01:04:07 PM PST 24 403360936 ps
T808 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1124720320 Jan 10 12:53:23 PM PST 24 Jan 10 12:54:43 PM PST 24 640299942 ps
T809 /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.188902227 Jan 10 12:45:47 PM PST 24 Jan 10 12:51:29 PM PST 24 83568523449 ps
T810 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.313646226 Jan 10 12:35:53 PM PST 24 Jan 10 12:36:33 PM PST 24 4359573137 ps
T811 /workspace/coverage/default/7.lc_ctrl_errors.1206043544 Jan 10 12:44:06 PM PST 24 Jan 10 12:45:38 PM PST 24 522887463 ps
T85 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.415453488 Jan 10 12:49:59 PM PST 24 Jan 10 12:51:50 PM PST 24 493035197 ps
T812 /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.610569343 Jan 10 12:34:12 PM PST 24 Jan 10 12:39:17 PM PST 24 51082198390 ps
T813 /workspace/coverage/default/30.lc_ctrl_prog_failure.1571797097 Jan 10 12:34:15 PM PST 24 Jan 10 12:34:49 PM PST 24 18390928 ps
T814 /workspace/coverage/default/5.lc_ctrl_prog_failure.3126671476 Jan 10 12:44:33 PM PST 24 Jan 10 12:45:54 PM PST 24 69860596 ps
T815 /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1358672489 Jan 10 12:36:06 PM PST 24 Jan 10 12:36:33 PM PST 24 15817361 ps
T816 /workspace/coverage/default/10.lc_ctrl_jtag_errors.927653001 Jan 10 12:37:35 PM PST 24 Jan 10 12:38:31 PM PST 24 4349521274 ps
T817 /workspace/coverage/default/46.lc_ctrl_jtag_access.1800051271 Jan 10 12:36:01 PM PST 24 Jan 10 12:36:28 PM PST 24 664223396 ps
T818 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3328675071 Jan 10 12:35:30 PM PST 24 Jan 10 12:36:09 PM PST 24 680525347 ps
T819 /workspace/coverage/default/8.lc_ctrl_sec_mubi.3090503081 Jan 10 12:34:22 PM PST 24 Jan 10 12:35:11 PM PST 24 1091389305 ps
T820 /workspace/coverage/default/49.lc_ctrl_security_escalation.865546473 Jan 10 12:36:10 PM PST 24 Jan 10 12:36:52 PM PST 24 1375174670 ps
T821 /workspace/coverage/default/41.lc_ctrl_security_escalation.546639818 Jan 10 12:35:54 PM PST 24 Jan 10 12:36:25 PM PST 24 1494527413 ps
T822 /workspace/coverage/default/6.lc_ctrl_security_escalation.3421421731 Jan 10 12:44:21 PM PST 24 Jan 10 12:45:47 PM PST 24 831426885 ps
T823 /workspace/coverage/default/5.lc_ctrl_errors.664194952 Jan 10 12:50:06 PM PST 24 Jan 10 12:51:54 PM PST 24 578196600 ps
T824 /workspace/coverage/default/48.lc_ctrl_smoke.2117705001 Jan 10 12:36:00 PM PST 24 Jan 10 12:36:25 PM PST 24 37035058 ps
T825 /workspace/coverage/default/14.lc_ctrl_jtag_errors.4217315050 Jan 10 12:34:38 PM PST 24 Jan 10 12:35:59 PM PST 24 5838402573 ps
T826 /workspace/coverage/default/37.lc_ctrl_security_escalation.4194725794 Jan 10 12:35:34 PM PST 24 Jan 10 12:36:14 PM PST 24 1216900345 ps
T827 /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1361719464 Jan 10 12:34:15 PM PST 24 Jan 10 12:34:48 PM PST 24 15085419 ps
T828 /workspace/coverage/default/14.lc_ctrl_errors.3276608773 Jan 10 12:34:27 PM PST 24 Jan 10 12:35:15 PM PST 24 479622520 ps
T121 /workspace/coverage/default/0.lc_ctrl_sec_cm.1842768974 Jan 10 12:41:07 PM PST 24 Jan 10 12:42:27 PM PST 24 449171867 ps
T829 /workspace/coverage/default/34.lc_ctrl_prog_failure.1956268430 Jan 10 12:34:52 PM PST 24 Jan 10 12:35:35 PM PST 24 37530055 ps
T830 /workspace/coverage/default/6.lc_ctrl_errors.323910632 Jan 10 01:33:21 PM PST 24 Jan 10 01:33:44 PM PST 24 248677990 ps
T831 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.146822215 Jan 10 12:34:22 PM PST 24 Jan 10 12:35:10 PM PST 24 3025481738 ps
T832 /workspace/coverage/default/40.lc_ctrl_errors.1363257248 Jan 10 12:35:53 PM PST 24 Jan 10 12:36:26 PM PST 24 362062485 ps
T833 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2550842781 Jan 10 12:40:21 PM PST 24 Jan 10 12:43:02 PM PST 24 14675923471 ps
T834 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4292863820 Jan 10 12:50:42 PM PST 24 Jan 10 12:52:27 PM PST 24 4908675107 ps
T79 /workspace/coverage/default/9.lc_ctrl_alert_test.2700142653 Jan 10 12:34:27 PM PST 24 Jan 10 12:35:04 PM PST 24 17404705 ps
T835 /workspace/coverage/default/26.lc_ctrl_errors.3566062729 Jan 10 12:34:13 PM PST 24 Jan 10 12:34:56 PM PST 24 342642538 ps
T836 /workspace/coverage/default/39.lc_ctrl_alert_test.528762610 Jan 10 12:35:43 PM PST 24 Jan 10 12:36:08 PM PST 24 69588366 ps
T837 /workspace/coverage/default/24.lc_ctrl_smoke.2807274536 Jan 10 12:40:45 PM PST 24 Jan 10 12:41:33 PM PST 24 39782391 ps
T838 /workspace/coverage/default/47.lc_ctrl_stress_all.1629443299 Jan 10 12:36:01 PM PST 24 Jan 10 12:37:04 PM PST 24 1022344386 ps
T839 /workspace/coverage/default/29.lc_ctrl_alert_test.4289556366 Jan 10 12:34:19 PM PST 24 Jan 10 12:34:53 PM PST 24 16413996 ps
T840 /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2055969557 Jan 10 12:36:01 PM PST 24 Jan 10 12:36:26 PM PST 24 22673163 ps
T841 /workspace/coverage/default/7.lc_ctrl_state_post_trans.93639949 Jan 10 12:45:22 PM PST 24 Jan 10 12:46:55 PM PST 24 157794891 ps
T842 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.677211864 Jan 10 12:57:16 PM PST 24 Jan 10 12:59:12 PM PST 24 3305708286 ps
T843 /workspace/coverage/default/17.lc_ctrl_smoke.3807818914 Jan 10 12:44:35 PM PST 24 Jan 10 12:45:54 PM PST 24 57135742 ps
T844 /workspace/coverage/default/16.lc_ctrl_jtag_access.709626207 Jan 10 12:34:35 PM PST 24 Jan 10 12:35:21 PM PST 24 391735140 ps
T845 /workspace/coverage/default/15.lc_ctrl_jtag_access.2154558962 Jan 10 12:34:22 PM PST 24 Jan 10 12:35:08 PM PST 24 1899050011 ps
T846 /workspace/coverage/default/21.lc_ctrl_jtag_access.1096399274 Jan 10 12:40:10 PM PST 24 Jan 10 12:41:02 PM PST 24 704609669 ps
T847 /workspace/coverage/default/47.lc_ctrl_jtag_access.1233734576 Jan 10 12:35:55 PM PST 24 Jan 10 12:36:21 PM PST 24 172540802 ps
T848 /workspace/coverage/default/33.lc_ctrl_sec_mubi.145648138 Jan 10 12:34:35 PM PST 24 Jan 10 12:35:29 PM PST 24 714024724 ps
T849 /workspace/coverage/default/42.lc_ctrl_smoke.655174134 Jan 10 12:35:58 PM PST 24 Jan 10 12:36:24 PM PST 24 277741750 ps
T850 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2644037282 Jan 10 12:34:15 PM PST 24 Jan 10 12:35:43 PM PST 24 1585473994 ps
T851 /workspace/coverage/default/19.lc_ctrl_errors.1764304313 Jan 10 12:47:47 PM PST 24 Jan 10 12:49:29 PM PST 24 1462683153 ps
T852 /workspace/coverage/default/44.lc_ctrl_alert_test.1216212980 Jan 10 12:35:56 PM PST 24 Jan 10 12:36:20 PM PST 24 40544501 ps
T853 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3226272253 Jan 10 12:34:30 PM PST 24 Jan 10 12:36:11 PM PST 24 2849677153 ps
T122 /workspace/coverage/default/2.lc_ctrl_sec_cm.1757677139 Jan 10 12:36:02 PM PST 24 Jan 10 12:37:01 PM PST 24 417506647 ps
T854 /workspace/coverage/default/20.lc_ctrl_stress_all.2912441914 Jan 10 12:40:17 PM PST 24 Jan 10 12:43:08 PM PST 24 29005996328 ps
T855 /workspace/coverage/default/0.lc_ctrl_jtag_access.441807095 Jan 10 12:46:59 PM PST 24 Jan 10 12:48:23 PM PST 24 1008797613 ps
T856 /workspace/coverage/default/33.lc_ctrl_prog_failure.1862231343 Jan 10 12:34:34 PM PST 24 Jan 10 12:35:18 PM PST 24 325781007 ps
T857 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1598551806 Jan 10 12:35:30 PM PST 24 Jan 10 12:35:58 PM PST 24 32341823 ps
T858 /workspace/coverage/default/25.lc_ctrl_sec_mubi.522467304 Jan 10 12:42:34 PM PST 24 Jan 10 12:44:02 PM PST 24 368026005 ps
T859 /workspace/coverage/default/15.lc_ctrl_state_post_trans.2543962982 Jan 10 12:34:11 PM PST 24 Jan 10 12:34:49 PM PST 24 99854450 ps
T860 /workspace/coverage/default/30.lc_ctrl_alert_test.2657745848 Jan 10 12:34:17 PM PST 24 Jan 10 12:34:50 PM PST 24 43889312 ps
T861 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3949146665 Jan 10 12:34:34 PM PST 24 Jan 10 12:35:26 PM PST 24 317765048 ps
T862 /workspace/coverage/default/45.lc_ctrl_security_escalation.4202406519 Jan 10 12:35:52 PM PST 24 Jan 10 12:36:28 PM PST 24 1375172288 ps
T863 /workspace/coverage/default/5.lc_ctrl_jtag_access.1647160091 Jan 10 12:46:02 PM PST 24 Jan 10 12:47:25 PM PST 24 1130977860 ps
T864 /workspace/coverage/default/40.lc_ctrl_state_post_trans.60467219 Jan 10 12:35:46 PM PST 24 Jan 10 12:36:14 PM PST 24 90590590 ps
T865 /workspace/coverage/default/45.lc_ctrl_errors.3070475374 Jan 10 12:35:58 PM PST 24 Jan 10 12:36:34 PM PST 24 2145478326 ps
T866 /workspace/coverage/default/44.lc_ctrl_state_failure.4205553059 Jan 10 12:35:55 PM PST 24 Jan 10 12:36:45 PM PST 24 1438064634 ps
T867 /workspace/coverage/default/47.lc_ctrl_prog_failure.1058159596 Jan 10 12:35:58 PM PST 24 Jan 10 12:36:24 PM PST 24 126229811 ps
T868 /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3834758597 Jan 10 12:34:28 PM PST 24 Jan 10 12:36:06 PM PST 24 7326925949 ps
T869 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3550774281 Jan 10 01:07:47 PM PST 24 Jan 10 01:09:09 PM PST 24 47097581 ps
T870 /workspace/coverage/default/12.lc_ctrl_state_post_trans.920892515 Jan 10 12:34:21 PM PST 24 Jan 10 12:34:57 PM PST 24 116698133 ps
T871 /workspace/coverage/default/46.lc_ctrl_security_escalation.3790029495 Jan 10 12:36:05 PM PST 24 Jan 10 12:36:39 PM PST 24 699759400 ps
T872 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3089249795 Jan 10 12:48:36 PM PST 24 Jan 10 12:50:15 PM PST 24 2284700827 ps
T873 /workspace/coverage/default/28.lc_ctrl_state_failure.2486562605 Jan 10 12:34:11 PM PST 24 Jan 10 12:35:10 PM PST 24 312084208 ps
T874 /workspace/coverage/default/35.lc_ctrl_alert_test.2492655877 Jan 10 12:35:04 PM PST 24 Jan 10 12:35:42 PM PST 24 21128978 ps
T875 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.4196966526 Jan 10 01:17:22 PM PST 24 Jan 10 01:18:13 PM PST 24 1725961419 ps
T876 /workspace/coverage/default/34.lc_ctrl_sec_mubi.1323511450 Jan 10 12:34:43 PM PST 24 Jan 10 12:35:39 PM PST 24 4074854206 ps
T55 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2431903082 Jan 10 12:35:58 PM PST 24 Jan 10 12:36:22 PM PST 24 64489360 ps
T877 /workspace/coverage/default/1.lc_ctrl_jtag_errors.3397848136 Jan 10 12:40:09 PM PST 24 Jan 10 12:41:34 PM PST 24 5665296200 ps
T878 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1230507247 Jan 10 12:39:32 PM PST 24 Jan 10 12:40:13 PM PST 24 846854243 ps
T879 /workspace/coverage/default/17.lc_ctrl_stress_all.4126693637 Jan 10 12:34:23 PM PST 24 Jan 10 12:36:54 PM PST 24 6262143395 ps
T880 /workspace/coverage/default/6.lc_ctrl_alert_test.312540631 Jan 10 12:39:28 PM PST 24 Jan 10 12:39:59 PM PST 24 112313210 ps
T881 /workspace/coverage/default/3.lc_ctrl_sec_mubi.2568090679 Jan 10 12:46:00 PM PST 24 Jan 10 12:47:32 PM PST 24 1332940981 ps
T882 /workspace/coverage/default/40.lc_ctrl_smoke.773483708 Jan 10 12:35:44 PM PST 24 Jan 10 12:36:10 PM PST 24 23328248 ps
T883 /workspace/coverage/default/15.lc_ctrl_alert_test.232529717 Jan 10 12:34:31 PM PST 24 Jan 10 12:35:13 PM PST 24 60881358 ps
T884 /workspace/coverage/default/17.lc_ctrl_sec_mubi.3096122919 Jan 10 12:34:22 PM PST 24 Jan 10 12:35:05 PM PST 24 305720164 ps
T885 /workspace/coverage/default/33.lc_ctrl_stress_all.2453729873 Jan 10 12:34:35 PM PST 24 Jan 10 12:37:16 PM PST 24 25444820579 ps
T886 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.901026752 Jan 10 12:48:45 PM PST 24 Jan 10 12:50:22 PM PST 24 1624716024 ps
T887 /workspace/coverage/default/40.lc_ctrl_jtag_access.2135709783 Jan 10 12:35:58 PM PST 24 Jan 10 12:36:31 PM PST 24 356316439 ps
T888 /workspace/coverage/default/39.lc_ctrl_errors.2053209560 Jan 10 12:35:58 PM PST 24 Jan 10 12:36:39 PM PST 24 1241581529 ps
T889 /workspace/coverage/default/13.lc_ctrl_errors.1863582380 Jan 10 01:00:20 PM PST 24 Jan 10 01:02:24 PM PST 24 1436201088 ps
T890 /workspace/coverage/default/22.lc_ctrl_state_failure.2022960719 Jan 10 12:34:07 PM PST 24 Jan 10 12:34:55 PM PST 24 381951035 ps
T62 /workspace/coverage/default/36.lc_ctrl_stress_all.4063071993 Jan 10 12:35:29 PM PST 24 Jan 10 12:46:39 PM PST 24 46318519840 ps
T891 /workspace/coverage/default/22.lc_ctrl_sec_mubi.2561340516 Jan 10 12:34:16 PM PST 24 Jan 10 12:35:08 PM PST 24 2149821798 ps
T892 /workspace/coverage/default/5.lc_ctrl_security_escalation.1661205218 Jan 10 12:46:26 PM PST 24 Jan 10 12:48:01 PM PST 24 1335291433 ps
T893 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3687714616 Jan 10 12:34:10 PM PST 24 Jan 10 12:34:41 PM PST 24 41306976 ps
T894 /workspace/coverage/default/4.lc_ctrl_jtag_errors.2434643103 Jan 10 01:02:03 PM PST 24 Jan 10 01:05:15 PM PST 24 9471339156 ps
T895 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.195380605 Jan 10 12:39:33 PM PST 24 Jan 10 12:40:26 PM PST 24 1623393492 ps
T896 /workspace/coverage/default/1.lc_ctrl_stress_all.2428678585 Jan 10 01:23:04 PM PST 24 Jan 10 01:24:31 PM PST 24 10784697103 ps
T897 /workspace/coverage/default/15.lc_ctrl_sec_mubi.3684284203 Jan 10 12:34:17 PM PST 24 Jan 10 12:35:00 PM PST 24 1097247478 ps
T80 /workspace/coverage/default/9.lc_ctrl_smoke.2771985309 Jan 10 12:34:21 PM PST 24 Jan 10 12:34:55 PM PST 24 138559514 ps
T898 /workspace/coverage/default/34.lc_ctrl_stress_all.3315875720 Jan 10 12:34:53 PM PST 24 Jan 10 12:37:57 PM PST 24 7277322744 ps
T899 /workspace/coverage/default/32.lc_ctrl_sec_mubi.3963759756 Jan 10 12:34:26 PM PST 24 Jan 10 12:35:17 PM PST 24 1503758258 ps
T900 /workspace/coverage/default/36.lc_ctrl_state_failure.3750766820 Jan 10 12:35:03 PM PST 24 Jan 10 12:36:13 PM PST 24 926655315 ps
T901 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2934217787 Jan 10 12:53:50 PM PST 24 Jan 10 12:55:09 PM PST 24 393470223 ps
T902 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1193286555 Jan 10 12:34:26 PM PST 24 Jan 10 12:35:07 PM PST 24 532312669 ps
T903 /workspace/coverage/default/31.lc_ctrl_stress_all.1655333797 Jan 10 12:34:31 PM PST 24 Jan 10 12:39:41 PM PST 24 35280129591 ps
T904 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2557505487 Jan 10 12:35:53 PM PST 24 Jan 10 12:36:17 PM PST 24 13357851 ps
T86 /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.719776659 Jan 10 12:46:59 PM PST 24 Jan 10 12:48:18 PM PST 24 36460470 ps
T905 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1771604698 Jan 10 12:34:29 PM PST 24 Jan 10 12:35:15 PM PST 24 476267756 ps
T906 /workspace/coverage/default/37.lc_ctrl_state_failure.3583023454 Jan 10 12:35:39 PM PST 24 Jan 10 12:36:44 PM PST 24 1477944756 ps
T907 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3969639057 Jan 10 12:37:49 PM PST 24 Jan 10 12:38:34 PM PST 24 404734976 ps
T908 /workspace/coverage/default/14.lc_ctrl_prog_failure.2071925533 Jan 10 12:34:17 PM PST 24 Jan 10 12:34:53 PM PST 24 85637751 ps
T909 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2043053185 Jan 10 12:36:00 PM PST 24 Jan 10 12:36:32 PM PST 24 397363051 ps
T910 /workspace/coverage/default/20.lc_ctrl_state_post_trans.4251343887 Jan 10 12:41:33 PM PST 24 Jan 10 12:42:42 PM PST 24 439447271 ps
T911 /workspace/coverage/default/4.lc_ctrl_jtag_priority.528469024 Jan 10 12:37:54 PM PST 24 Jan 10 12:38:39 PM PST 24 1173872496 ps
T912 /workspace/coverage/default/16.lc_ctrl_jtag_errors.3739147012 Jan 10 12:34:34 PM PST 24 Jan 10 12:36:07 PM PST 24 7533878753 ps
T913 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.134412174 Jan 10 12:35:09 PM PST 24 Jan 10 12:35:52 PM PST 24 1470564103 ps
T914 /workspace/coverage/default/21.lc_ctrl_alert_test.1739432904 Jan 10 12:34:12 PM PST 24 Jan 10 12:34:43 PM PST 24 91791741 ps
T915 /workspace/coverage/default/2.lc_ctrl_smoke.648813049 Jan 10 12:49:09 PM PST 24 Jan 10 12:50:43 PM PST 24 98894906 ps
T916 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2616648790 Jan 10 01:21:02 PM PST 24 Jan 10 01:21:21 PM PST 24 1779819921 ps
T917 /workspace/coverage/default/26.lc_ctrl_alert_test.1058286678 Jan 10 12:34:18 PM PST 24 Jan 10 12:34:52 PM PST 24 110981769 ps
T918 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2961707810 Jan 10 12:34:28 PM PST 24 Jan 10 12:35:14 PM PST 24 1413398103 ps
T919 /workspace/coverage/default/3.lc_ctrl_jtag_priority.2077034488 Jan 10 12:50:14 PM PST 24 Jan 10 12:51:55 PM PST 24 383723565 ps
T920 /workspace/coverage/default/16.lc_ctrl_stress_all.683540894 Jan 10 12:42:19 PM PST 24 Jan 10 12:45:05 PM PST 24 2425617358 ps
T921 /workspace/coverage/default/11.lc_ctrl_errors.3361234694 Jan 10 12:34:19 PM PST 24 Jan 10 12:35:08 PM PST 24 369655432 ps
T922 /workspace/coverage/default/21.lc_ctrl_stress_all.3585538585 Jan 10 12:33:57 PM PST 24 Jan 10 12:34:52 PM PST 24 2207942667 ps
T923 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2859408186 Jan 10 12:34:25 PM PST 24 Jan 10 12:35:06 PM PST 24 1828232151 ps
T924 /workspace/coverage/default/10.lc_ctrl_prog_failure.385840544 Jan 10 01:09:33 PM PST 24 Jan 10 01:10:41 PM PST 24 99564007 ps
T925 /workspace/coverage/default/7.lc_ctrl_jtag_errors.2277096223 Jan 10 01:16:08 PM PST 24 Jan 10 01:17:16 PM PST 24 1336165347 ps
T926 /workspace/coverage/default/2.lc_ctrl_jtag_errors.3507530090 Jan 10 12:54:17 PM PST 24 Jan 10 12:56:05 PM PST 24 3499298527 ps
T927 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1653629644 Jan 10 12:34:23 PM PST 24 Jan 10 12:35:08 PM PST 24 2256984012 ps
T928 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3778937426 Jan 10 12:34:05 PM PST 24 Jan 10 12:34:47 PM PST 24 2273180664 ps
T929 /workspace/coverage/default/9.lc_ctrl_prog_failure.2025906992 Jan 10 12:34:22 PM PST 24 Jan 10 12:34:59 PM PST 24 188591862 ps
T930 /workspace/coverage/default/36.lc_ctrl_jtag_access.697804632 Jan 10 12:35:08 PM PST 24 Jan 10 12:35:46 PM PST 24 434385173 ps
T931 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3258908692 Jan 10 12:34:24 PM PST 24 Jan 10 12:35:08 PM PST 24 335695183 ps
T932 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3929302085 Jan 10 12:34:26 PM PST 24 Jan 10 12:35:24 PM PST 24 2158675666 ps
T933 /workspace/coverage/default/49.lc_ctrl_sec_mubi.1209241791 Jan 10 12:36:02 PM PST 24 Jan 10 12:36:38 PM PST 24 1234206139 ps
T934 /workspace/coverage/default/23.lc_ctrl_prog_failure.2135064912 Jan 10 12:34:27 PM PST 24 Jan 10 12:35:09 PM PST 24 1001633031 ps
T935 /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3577601893 Jan 10 12:50:40 PM PST 24 Jan 10 12:52:06 PM PST 24 15500619 ps
T936 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3190264087 Jan 10 12:34:01 PM PST 24 Jan 10 12:34:54 PM PST 24 508740120 ps
T937 /workspace/coverage/default/11.lc_ctrl_alert_test.3001686362 Jan 10 12:34:14 PM PST 24 Jan 10 12:34:46 PM PST 24 73877154 ps
T938 /workspace/coverage/default/17.lc_ctrl_jtag_access.1872158697 Jan 10 12:34:22 PM PST 24 Jan 10 12:35:05 PM PST 24 1563845950 ps
T939 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2682534724 Jan 10 12:35:52 PM PST 24 Jan 10 12:36:24 PM PST 24 238137596 ps
T940 /workspace/coverage/default/34.lc_ctrl_jtag_access.4258414914 Jan 10 12:34:54 PM PST 24 Jan 10 12:35:39 PM PST 24 706026379 ps
T941 /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.170759702 Jan 10 12:34:21 PM PST 24 Jan 10 12:35:08 PM PST 24 475144439 ps
T942 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3457349445 Jan 10 12:34:30 PM PST 24 Jan 10 12:35:13 PM PST 24 646782493 ps
T943 /workspace/coverage/default/12.lc_ctrl_stress_all.1274955927 Jan 10 12:46:58 PM PST 24 Jan 10 12:49:10 PM PST 24 2831363128 ps
T944 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1255522260 Jan 10 12:36:01 PM PST 24 Jan 10 12:36:39 PM PST 24 3358161831 ps
T945 /workspace/coverage/default/34.lc_ctrl_alert_test.2169308999 Jan 10 12:34:51 PM PST 24 Jan 10 12:35:33 PM PST 24 67713340 ps
T946 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3807607862 Jan 10 12:35:58 PM PST 24 Jan 10 12:36:22 PM PST 24 15743654 ps
T947 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.180900609 Jan 10 01:03:51 PM PST 24 Jan 10 01:05:12 PM PST 24 459432014 ps
T948 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2808693937 Jan 10 12:34:23 PM PST 24 Jan 10 12:35:30 PM PST 24 4278887676 ps
T949 /workspace/coverage/default/49.lc_ctrl_stress_all.2793936069 Jan 10 12:36:01 PM PST 24 Jan 10 12:38:25 PM PST 24 8202789175 ps
T950 /workspace/coverage/default/47.lc_ctrl_alert_test.1100746511 Jan 10 12:36:05 PM PST 24 Jan 10 12:36:33 PM PST 24 24038380 ps
T951 /workspace/coverage/default/11.lc_ctrl_stress_all.3687890013 Jan 10 12:34:24 PM PST 24 Jan 10 12:35:52 PM PST 24 1925712181 ps
T952 /workspace/coverage/default/41.lc_ctrl_stress_all.4192469653 Jan 10 12:35:43 PM PST 24 Jan 10 12:36:27 PM PST 24 940100190 ps
T953 /workspace/coverage/default/42.lc_ctrl_alert_test.201256514 Jan 10 12:35:55 PM PST 24 Jan 10 12:36:19 PM PST 24 100319306 ps
T954 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2875732644 Jan 10 12:34:19 PM PST 24 Jan 10 12:35:00 PM PST 24 4095986853 ps
T955 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3778288935 Jan 10 12:34:19 PM PST 24 Jan 10 12:34:53 PM PST 24 40579663 ps
T956 /workspace/coverage/default/23.lc_ctrl_state_post_trans.458133406 Jan 10 12:34:22 PM PST 24 Jan 10 12:35:02 PM PST 24 308530034 ps
T957 /workspace/coverage/default/29.lc_ctrl_security_escalation.1442199567 Jan 10 12:34:08 PM PST 24 Jan 10 12:34:48 PM PST 24 1640100404 ps
T958 /workspace/coverage/default/12.lc_ctrl_sec_mubi.1680624599 Jan 10 12:40:42 PM PST 24 Jan 10 12:41:37 PM PST 24 327073874 ps
T959 /workspace/coverage/default/13.lc_ctrl_state_failure.3204752412 Jan 10 12:45:47 PM PST 24 Jan 10 12:47:27 PM PST 24 321264221 ps
T960 /workspace/coverage/default/15.lc_ctrl_security_escalation.3330027317 Jan 10 12:34:15 PM PST 24 Jan 10 12:34:56 PM PST 24 500409634 ps
T961 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2645598073 Jan 10 12:42:29 PM PST 24 Jan 10 12:43:57 PM PST 24 1045129959 ps
T962 /workspace/coverage/default/4.lc_ctrl_errors.4172736781 Jan 10 12:41:13 PM PST 24 Jan 10 12:42:25 PM PST 24 642084095 ps
T963 /workspace/coverage/default/8.lc_ctrl_stress_all.2043069069 Jan 10 12:34:12 PM PST 24 Jan 10 12:36:32 PM PST 24 12260537611 ps
T964 /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3241590756 Jan 10 12:34:04 PM PST 24 Jan 10 12:34:34 PM PST 24 20088742 ps
T965 /workspace/coverage/default/43.lc_ctrl_security_escalation.1218653145 Jan 10 12:36:03 PM PST 24 Jan 10 12:36:40 PM PST 24 364315534 ps
T966 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.634164383 Jan 10 12:44:48 PM PST 24 Jan 10 12:46:13 PM PST 24 307724374 ps
T967 /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3839674019 Jan 10 12:36:01 PM PST 24 Jan 10 12:36:25 PM PST 24 216959295 ps
T968 /workspace/coverage/default/26.lc_ctrl_prog_failure.251080369 Jan 10 12:34:08 PM PST 24 Jan 10 12:34:40 PM PST 24 42884728 ps
T969 /workspace/coverage/default/0.lc_ctrl_state_failure.172398132 Jan 10 12:44:38 PM PST 24 Jan 10 12:46:13 PM PST 24 2029672583 ps
T970 /workspace/coverage/default/23.lc_ctrl_smoke.3498476824 Jan 10 12:34:21 PM PST 24 Jan 10 12:34:56 PM PST 24 163421849 ps
T971 /workspace/coverage/default/12.lc_ctrl_smoke.1479047286 Jan 10 12:34:27 PM PST 24 Jan 10 12:35:06 PM PST 24 288056439 ps
T972 /workspace/coverage/default/34.lc_ctrl_state_failure.4132801786 Jan 10 12:34:52 PM PST 24 Jan 10 12:36:05 PM PST 24 608903764 ps
T973 /workspace/coverage/default/21.lc_ctrl_prog_failure.475273078 Jan 10 12:49:43 PM PST 24 Jan 10 12:51:21 PM PST 24 234300884 ps
T974 /workspace/coverage/default/1.lc_ctrl_errors.4112518507 Jan 10 01:44:18 PM PST 24 Jan 10 01:44:36 PM PST 24 448407381 ps
T975 /workspace/coverage/default/31.lc_ctrl_jtag_access.2466962127 Jan 10 12:34:27 PM PST 24 Jan 10 12:35:12 PM PST 24 324146535 ps
T976 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3045937192 Jan 10 12:58:54 PM PST 24 Jan 10 01:00:23 PM PST 24 40192018 ps
T977 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3032246047 Jan 10 12:58:55 PM PST 24 Jan 10 01:00:24 PM PST 24 17160296 ps
T978 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2076776599 Jan 10 12:58:28 PM PST 24 Jan 10 12:59:53 PM PST 24 411912645 ps
T184 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.459602847 Jan 10 12:58:36 PM PST 24 Jan 10 01:00:00 PM PST 24 19195630 ps
T979 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3109403730 Jan 10 12:58:36 PM PST 24 Jan 10 01:00:02 PM PST 24 261954525 ps

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1262861270
Short name T66
Test name
Test status
Simulation time 130685441 ps
CPU time 4.49 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:16 PM PST 24
Peak memory 217668 kb
Host smart-45f3c2b9-e248-446e-a667-c6fa97e75bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262861270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1262861270
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1156316307
Short name T10
Test name
Test status
Simulation time 421269256 ps
CPU time 13.36 seconds
Started Jan 10 12:37:50 PM PST 24
Finished Jan 10 12:38:37 PM PST 24
Peak memory 219184 kb
Host smart-a572e4a5-3939-4c56-90ea-5f221780b11e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156316307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1156316307
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2296555254
Short name T22
Test name
Test status
Simulation time 61012535055 ps
CPU time 382.7 seconds
Started Jan 10 12:36:09 PM PST 24
Finished Jan 10 12:43:01 PM PST 24
Peak memory 283900 kb
Host smart-9d924133-34eb-45b9-88a3-d12c4bc911b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296555254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2296555254
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.195088940
Short name T158
Test name
Test status
Simulation time 70060595 ps
CPU time 1.38 seconds
Started Jan 10 12:58:54 PM PST 24
Finished Jan 10 01:00:24 PM PST 24
Peak memory 210664 kb
Host smart-9b993d69-6a8f-470a-83db-bc367521d0f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195088940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.195088940
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.446013610
Short name T106
Test name
Test status
Simulation time 239172682 ps
CPU time 2.83 seconds
Started Jan 10 12:58:55 PM PST 24
Finished Jan 10 01:00:26 PM PST 24
Peak memory 221656 kb
Host smart-b3826346-068c-4a5b-bc89-c8c6a01d022a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446013610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.446013610
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1763230284
Short name T97
Test name
Test status
Simulation time 121462499 ps
CPU time 0.96 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:09 PM PST 24
Peak memory 209620 kb
Host smart-93f5e7d8-d754-4d7c-b9a4-9ddf9589dabd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763230284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1763230284
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4041597640
Short name T12
Test name
Test status
Simulation time 304852111 ps
CPU time 12.41 seconds
Started Jan 10 12:56:11 PM PST 24
Finished Jan 10 12:57:34 PM PST 24
Peak memory 218124 kb
Host smart-954dba1e-8f60-4e91-ad3d-92c0e640591c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041597640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4041597640
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3354696230
Short name T5
Test name
Test status
Simulation time 109180229594 ps
CPU time 158.32 seconds
Started Jan 10 12:44:45 PM PST 24
Finished Jan 10 12:48:40 PM PST 24
Peak memory 270724 kb
Host smart-dc52da88-a611-4731-bbf9-4b8bc66afd46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354696230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3354696230
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3766232739
Short name T90
Test name
Test status
Simulation time 101104103 ps
CPU time 1.78 seconds
Started Jan 10 12:58:30 PM PST 24
Finished Jan 10 12:59:51 PM PST 24
Peak memory 207984 kb
Host smart-6351d006-b1d4-4137-8f29-a1f2f236f7dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766232739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3766232739
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3167539865
Short name T45
Test name
Test status
Simulation time 12687553 ps
CPU time 0.93 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:19 PM PST 24
Peak memory 208388 kb
Host smart-44b53494-fba1-41c4-9c5f-0e030397fdb3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167539865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3167539865
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3543837255
Short name T13
Test name
Test status
Simulation time 3331306588 ps
CPU time 11.38 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:35:10 PM PST 24
Peak memory 218180 kb
Host smart-831ba403-46d6-4a86-9841-6f4bbf91ef74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543837255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
543837255
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1842768974
Short name T121
Test name
Test status
Simulation time 449171867 ps
CPU time 20.12 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 278620 kb
Host smart-1461935f-b3b0-4cf0-bf97-2501879c3d28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842768974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1842768974
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3308607198
Short name T108
Test name
Test status
Simulation time 13384088626 ps
CPU time 230.81 seconds
Started Jan 10 12:34:25 PM PST 24
Finished Jan 10 12:38:51 PM PST 24
Peak memory 284288 kb
Host smart-7c926b1e-9636-4bd5-9fb0-ea8ee9a1d712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3308607198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3308607198
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1224306369
Short name T304
Test name
Test status
Simulation time 1334586394 ps
CPU time 10.84 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:46 PM PST 24
Peak memory 218024 kb
Host smart-11cc7b75-407f-4a7b-be0a-74707d67a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224306369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1224306369
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.527161610
Short name T115
Test name
Test status
Simulation time 462647088 ps
CPU time 4.41 seconds
Started Jan 10 12:58:51 PM PST 24
Finished Jan 10 01:00:22 PM PST 24
Peak memory 213084 kb
Host smart-b36b964a-96f7-479f-a8a0-da45ab0329b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527161610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.527161610
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3276662094
Short name T59
Test name
Test status
Simulation time 9927411424 ps
CPU time 74.29 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:36:01 PM PST 24
Peak memory 268228 kb
Host smart-fea25ffa-e12b-4fbd-8a0e-913bb10b25a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276662094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3276662094
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2421711259
Short name T302
Test name
Test status
Simulation time 117490063 ps
CPU time 0.87 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:34:54 PM PST 24
Peak memory 209740 kb
Host smart-ea4e4698-3e1c-43b6-a594-2d985b9ad554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421711259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2421711259
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1342432274
Short name T92
Test name
Test status
Simulation time 47140753 ps
CPU time 1.15 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:16 PM PST 24
Peak memory 217964 kb
Host smart-edf795b8-047c-437d-bd7c-fe6a50e705a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342432274 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1342432274
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3995767988
Short name T148
Test name
Test status
Simulation time 111320409 ps
CPU time 3.24 seconds
Started Jan 10 12:58:44 PM PST 24
Finished Jan 10 01:00:08 PM PST 24
Peak memory 221964 kb
Host smart-c51a046b-56b5-40e2-9456-abb64d60077d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995767988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3995767988
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1356515074
Short name T176
Test name
Test status
Simulation time 41098041 ps
CPU time 0.98 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:15 PM PST 24
Peak memory 209560 kb
Host smart-b6824526-4f08-48b7-8758-3b2b56e95979
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356515074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1356515074
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4209124224
Short name T145
Test name
Test status
Simulation time 456036472 ps
CPU time 2.78 seconds
Started Jan 10 12:58:52 PM PST 24
Finished Jan 10 01:00:21 PM PST 24
Peak memory 221480 kb
Host smart-dc9605f8-edbf-4045-ac88-1f43fdb1c156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209124224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.4209124224
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1472049138
Short name T31
Test name
Test status
Simulation time 379813077 ps
CPU time 4.47 seconds
Started Jan 10 12:46:49 PM PST 24
Finished Jan 10 12:48:11 PM PST 24
Peak memory 209684 kb
Host smart-7a6e6531-76b9-4926-96f2-c24e152de5b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472049138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.1472049138
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3989642916
Short name T63
Test name
Test status
Simulation time 510678344 ps
CPU time 29.38 seconds
Started Jan 10 12:35:56 PM PST 24
Finished Jan 10 12:36:48 PM PST 24
Peak memory 251024 kb
Host smart-e71a7b04-dc57-474f-a664-018a7fe88d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989642916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3989642916
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4013056175
Short name T136
Test name
Test status
Simulation time 1261811525 ps
CPU time 6.14 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:20 PM PST 24
Peak memory 209076 kb
Host smart-bfa3a4f7-fc3e-4142-9263-a1a3a21a4c02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013056175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4013056175
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2649047030
Short name T54
Test name
Test status
Simulation time 18316605 ps
CPU time 0.73 seconds
Started Jan 10 12:34:17 PM PST 24
Finished Jan 10 12:34:51 PM PST 24
Peak memory 208024 kb
Host smart-1d60a47e-1e5c-4c5d-833a-5ed6a30c7767
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649047030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2649047030
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.313256679
Short name T140
Test name
Test status
Simulation time 279029986 ps
CPU time 3.42 seconds
Started Jan 10 12:58:35 PM PST 24
Finished Jan 10 12:59:59 PM PST 24
Peak memory 221892 kb
Host smart-59a8c22f-7e3c-468e-9bb7-61d729e1f14d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313256679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.313256679
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1373391009
Short name T142
Test name
Test status
Simulation time 112841313 ps
CPU time 4.44 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 217744 kb
Host smart-e96b96d7-935c-4ab3-a9b4-19803c1131bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373391009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1373391009
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3050951484
Short name T388
Test name
Test status
Simulation time 284239440 ps
CPU time 13.22 seconds
Started Jan 10 12:47:10 PM PST 24
Finished Jan 10 12:48:41 PM PST 24
Peak memory 218076 kb
Host smart-11c91fbd-0ae8-45be-baa4-e49e054a8193
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050951484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3050951484
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3324369878
Short name T483
Test name
Test status
Simulation time 30683623 ps
CPU time 0.71 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:34:57 PM PST 24
Peak memory 207916 kb
Host smart-68888eb7-ddc8-4cb3-844d-f285baee67f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324369878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3324369878
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3985416135
Short name T135
Test name
Test status
Simulation time 126078973 ps
CPU time 4.91 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 217684 kb
Host smart-21632966-aac9-44bc-8c96-b62d57b6f597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985416135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3985416135
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2006919712
Short name T119
Test name
Test status
Simulation time 287965544 ps
CPU time 2.77 seconds
Started Jan 10 12:58:42 PM PST 24
Finished Jan 10 01:00:05 PM PST 24
Peak memory 221784 kb
Host smart-81ba13da-9da5-4a50-97f8-6d05fed5fdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006919712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2006919712
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1480115881
Short name T527
Test name
Test status
Simulation time 187524397 ps
CPU time 5.2 seconds
Started Jan 10 01:05:53 PM PST 24
Finished Jan 10 01:07:31 PM PST 24
Peak memory 214624 kb
Host smart-4d1e61f6-b8fc-4f72-970e-9c798e536361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480115881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1480115881
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1256637544
Short name T153
Test name
Test status
Simulation time 233339390 ps
CPU time 2.55 seconds
Started Jan 10 12:58:54 PM PST 24
Finished Jan 10 01:00:23 PM PST 24
Peak memory 217800 kb
Host smart-a8bfa25b-17e0-4430-893e-5f29e00488b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256637544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1256637544
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.247832002
Short name T397
Test name
Test status
Simulation time 606367040 ps
CPU time 11.23 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:35:10 PM PST 24
Peak memory 218184 kb
Host smart-fcc84a5c-bd70-4820-b1dd-74effc565b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247832002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.247832002
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2470066320
Short name T190
Test name
Test status
Simulation time 16245024 ps
CPU time 0.89 seconds
Started Jan 10 12:43:55 PM PST 24
Finished Jan 10 12:45:10 PM PST 24
Peak memory 209644 kb
Host smart-bc73854d-e9ab-4213-bf9a-ff3020cfbbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470066320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2470066320
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1102416246
Short name T25
Test name
Test status
Simulation time 11229709 ps
CPU time 0.76 seconds
Started Jan 10 01:17:35 PM PST 24
Finished Jan 10 01:18:07 PM PST 24
Peak memory 209468 kb
Host smart-1fc781e1-d278-4237-b8e3-ba1dfe232a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102416246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1102416246
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1244796499
Short name T191
Test name
Test status
Simulation time 12161874 ps
CPU time 0.79 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:17 PM PST 24
Peak memory 209416 kb
Host smart-c2dde7bb-16f2-4b2d-956c-3c6330715787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244796499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1244796499
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2568650722
Short name T231
Test name
Test status
Simulation time 302745360 ps
CPU time 2.29 seconds
Started Jan 10 12:58:28 PM PST 24
Finished Jan 10 12:59:51 PM PST 24
Peak memory 211144 kb
Host smart-61719f46-6a62-4396-b2f4-56690adc99d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568650722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2568650722
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3644633385
Short name T155
Test name
Test status
Simulation time 174846948 ps
CPU time 2.32 seconds
Started Jan 10 12:58:30 PM PST 24
Finished Jan 10 12:59:53 PM PST 24
Peak memory 217800 kb
Host smart-0ffd3135-9cb8-40bd-b352-8ad0483061c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644633385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3644633385
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3670159790
Short name T146
Test name
Test status
Simulation time 170049403 ps
CPU time 4.18 seconds
Started Jan 10 12:58:26 PM PST 24
Finished Jan 10 12:59:54 PM PST 24
Peak memory 217632 kb
Host smart-5adb6efd-828b-4407-8651-3183f8edffa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670159790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3670159790
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.4063071993
Short name T62
Test name
Test status
Simulation time 46318519840 ps
CPU time 643.61 seconds
Started Jan 10 12:35:29 PM PST 24
Finished Jan 10 12:46:39 PM PST 24
Peak memory 283908 kb
Host smart-443205b0-9f43-4bf0-b35d-7bd4a8248b2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063071993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.4063071993
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1462036588
Short name T96
Test name
Test status
Simulation time 32918102 ps
CPU time 1.28 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:14 PM PST 24
Peak memory 219668 kb
Host smart-c28b1bee-c601-4f87-bec7-a491d3c6bd6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462036588 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1462036588
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2637497190
Short name T95
Test name
Test status
Simulation time 16606953 ps
CPU time 0.85 seconds
Started Jan 10 12:58:33 PM PST 24
Finished Jan 10 12:59:54 PM PST 24
Peak memory 209576 kb
Host smart-525b9d05-2731-4b7c-a5db-5be8cf035f2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637497190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2637497190
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1554723683
Short name T112
Test name
Test status
Simulation time 19461116 ps
CPU time 1.44 seconds
Started Jan 10 12:58:43 PM PST 24
Finished Jan 10 01:00:06 PM PST 24
Peak memory 211284 kb
Host smart-66473a03-b9a4-4f70-b195-e525c1a02a78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554723683 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1554723683
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.835883607
Short name T173
Test name
Test status
Simulation time 27679200 ps
CPU time 1.3 seconds
Started Jan 10 12:58:30 PM PST 24
Finished Jan 10 12:59:51 PM PST 24
Peak memory 209488 kb
Host smart-dec882a0-9cad-4134-aac5-eacb785b9ed7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835883607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.835883607
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.596299242
Short name T282
Test name
Test status
Simulation time 72097668 ps
CPU time 1.67 seconds
Started Jan 10 12:58:42 PM PST 24
Finished Jan 10 01:00:05 PM PST 24
Peak memory 209428 kb
Host smart-c64ba5d2-77b4-41d1-9c5c-a677fe65720b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596299242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.596299242
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.658689707
Short name T197
Test name
Test status
Simulation time 155962400 ps
CPU time 0.91 seconds
Started Jan 10 12:58:32 PM PST 24
Finished Jan 10 12:59:52 PM PST 24
Peak memory 209672 kb
Host smart-1814323f-f885-46b8-99b0-ec5bc28a3b60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658689707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.658689707
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.803580075
Short name T251
Test name
Test status
Simulation time 19289533 ps
CPU time 1.16 seconds
Started Jan 10 12:58:55 PM PST 24
Finished Jan 10 01:00:24 PM PST 24
Peak memory 220848 kb
Host smart-28c8356c-8873-431a-a2b5-d6efe056380b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803580075 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.803580075
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.35147004
Short name T233
Test name
Test status
Simulation time 12913946 ps
CPU time 0.85 seconds
Started Jan 10 12:58:26 PM PST 24
Finished Jan 10 12:59:47 PM PST 24
Peak memory 209324 kb
Host smart-3fa029d6-94e7-4dff-b129-c5aadf974769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35147004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.35147004
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1993089897
Short name T160
Test name
Test status
Simulation time 89711912 ps
CPU time 1.25 seconds
Started Jan 10 12:58:42 PM PST 24
Finished Jan 10 01:00:03 PM PST 24
Peak memory 209372 kb
Host smart-898a3894-e768-40c0-8337-922ce9ad0a5b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993089897 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1993089897
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3124578859
Short name T196
Test name
Test status
Simulation time 1705388803 ps
CPU time 15.34 seconds
Started Jan 10 12:58:30 PM PST 24
Finished Jan 10 01:00:05 PM PST 24
Peak memory 208464 kb
Host smart-2175b300-52c1-4835-858c-8db6e216b895
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124578859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3124578859
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1677117787
Short name T105
Test name
Test status
Simulation time 405892596 ps
CPU time 4.24 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:23 PM PST 24
Peak memory 209476 kb
Host smart-dc1b0bfe-e9f1-49ba-b4f1-42c8b50e6912
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677117787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1677117787
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2479400477
Short name T269
Test name
Test status
Simulation time 60781837 ps
CPU time 1.5 seconds
Started Jan 10 12:58:28 PM PST 24
Finished Jan 10 12:59:50 PM PST 24
Peak memory 217836 kb
Host smart-bdb0a191-3c25-4e26-90c9-eb92deace09e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247940
0477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2479400477
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4130862672
Short name T165
Test name
Test status
Simulation time 67714759 ps
CPU time 2.2 seconds
Started Jan 10 12:58:25 PM PST 24
Finished Jan 10 12:59:47 PM PST 24
Peak memory 209348 kb
Host smart-5d8afd06-2e38-4b30-8773-8a805cc84420
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130862672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.4130862672
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3690305830
Short name T212
Test name
Test status
Simulation time 118070737 ps
CPU time 1.43 seconds
Started Jan 10 12:58:46 PM PST 24
Finished Jan 10 01:00:11 PM PST 24
Peak memory 209540 kb
Host smart-58c32fd2-5719-4ca3-b8b0-9f946f90c3f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690305830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3690305830
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3941693036
Short name T180
Test name
Test status
Simulation time 35517150 ps
CPU time 1.26 seconds
Started Jan 10 12:58:28 PM PST 24
Finished Jan 10 12:59:50 PM PST 24
Peak memory 208628 kb
Host smart-86b6e4ef-85e0-4e59-ac6e-e1d7959ecec0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941693036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3941693036
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2942866272
Short name T171
Test name
Test status
Simulation time 67558576 ps
CPU time 1.85 seconds
Started Jan 10 12:58:26 PM PST 24
Finished Jan 10 12:59:48 PM PST 24
Peak memory 209532 kb
Host smart-af954fed-60b0-4260-a3e5-0379db730a74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942866272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2942866272
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1675317359
Short name T271
Test name
Test status
Simulation time 18042138 ps
CPU time 1.04 seconds
Started Jan 10 12:58:58 PM PST 24
Finished Jan 10 01:00:28 PM PST 24
Peak memory 210248 kb
Host smart-d71c6cbc-456a-4ed1-8b6d-f55d749ca7d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675317359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1675317359
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2347708584
Short name T261
Test name
Test status
Simulation time 43605789 ps
CPU time 0.98 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:51 PM PST 24
Peak memory 209528 kb
Host smart-95cb6d94-e53d-4892-811e-a44e285398ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347708584 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2347708584
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.290757025
Short name T183
Test name
Test status
Simulation time 31633309 ps
CPU time 0.87 seconds
Started Jan 10 12:58:30 PM PST 24
Finished Jan 10 12:59:51 PM PST 24
Peak memory 209268 kb
Host smart-f5c0c626-8587-43cf-9b05-2ed836488dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290757025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.290757025
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3892971240
Short name T157
Test name
Test status
Simulation time 225353829 ps
CPU time 1.3 seconds
Started Jan 10 12:58:28 PM PST 24
Finished Jan 10 12:59:49 PM PST 24
Peak memory 209328 kb
Host smart-b5cfbd92-5f83-47ce-8d57-39f92e89a2c0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892971240 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3892971240
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2134004803
Short name T216
Test name
Test status
Simulation time 1002535997 ps
CPU time 5.95 seconds
Started Jan 10 12:58:27 PM PST 24
Finished Jan 10 12:59:53 PM PST 24
Peak memory 209384 kb
Host smart-334ca53d-0651-4248-a399-39edabd87570
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134004803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2134004803
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2869205894
Short name T93
Test name
Test status
Simulation time 807957558 ps
CPU time 18 seconds
Started Jan 10 12:58:28 PM PST 24
Finished Jan 10 01:00:07 PM PST 24
Peak memory 209476 kb
Host smart-58526394-10c7-467f-af88-f3570b3b15e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869205894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2869205894
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2076776599
Short name T978
Test name
Test status
Simulation time 411912645 ps
CPU time 4.83 seconds
Started Jan 10 12:58:28 PM PST 24
Finished Jan 10 12:59:53 PM PST 24
Peak memory 210928 kb
Host smart-bed0b527-7254-446c-8bb1-c59db1a13340
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076776599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2076776599
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629621565
Short name T259
Test name
Test status
Simulation time 127782080 ps
CPU time 1.54 seconds
Started Jan 10 12:59:06 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 219888 kb
Host smart-e79e52ce-10d8-4b1c-b1d9-31a30b415c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262962
1565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629621565
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.100755974
Short name T164
Test name
Test status
Simulation time 441616931 ps
CPU time 2.04 seconds
Started Jan 10 12:58:28 PM PST 24
Finished Jan 10 12:59:51 PM PST 24
Peak memory 209404 kb
Host smart-2e4e7d64-f841-4a80-9ee8-a7b85bd6a6ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100755974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.100755974
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1576385596
Short name T250
Test name
Test status
Simulation time 37030062 ps
CPU time 1.3 seconds
Started Jan 10 12:58:30 PM PST 24
Finished Jan 10 12:59:51 PM PST 24
Peak memory 209448 kb
Host smart-a5a25e8a-318d-47f5-af33-228532251cfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576385596 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1576385596
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3133662230
Short name T239
Test name
Test status
Simulation time 29439311 ps
CPU time 1.09 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:16 PM PST 24
Peak memory 209528 kb
Host smart-18849b4a-bd13-4ea2-8a27-b26c25ddd90f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133662230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3133662230
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3429021968
Short name T137
Test name
Test status
Simulation time 75900111 ps
CPU time 2.86 seconds
Started Jan 10 12:58:27 PM PST 24
Finished Jan 10 12:59:50 PM PST 24
Peak memory 222024 kb
Host smart-ecc14b35-c647-4626-bfc3-9ae1465c1d10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429021968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3429021968
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2696744059
Short name T254
Test name
Test status
Simulation time 35296292 ps
CPU time 1.08 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 217760 kb
Host smart-085b33ac-654b-473f-bdbe-fa99ee3865ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696744059 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2696744059
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2003363119
Short name T117
Test name
Test status
Simulation time 25328270 ps
CPU time 0.98 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:10 PM PST 24
Peak memory 209416 kb
Host smart-a535dc06-ef62-494e-afd6-d4123fe17058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003363119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2003363119
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3776945178
Short name T218
Test name
Test status
Simulation time 185611228 ps
CPU time 1.55 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:11 PM PST 24
Peak memory 209608 kb
Host smart-dcbf5b86-c93b-427a-82af-27f5b0a5a925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776945178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3776945178
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.503571232
Short name T241
Test name
Test status
Simulation time 234327532 ps
CPU time 3.16 seconds
Started Jan 10 12:58:54 PM PST 24
Finished Jan 10 01:00:23 PM PST 24
Peak memory 217668 kb
Host smart-2581a170-311f-4137-948a-2e07fa41c265
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503571232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.503571232
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3206084460
Short name T141
Test name
Test status
Simulation time 226328956 ps
CPU time 2.92 seconds
Started Jan 10 12:58:44 PM PST 24
Finished Jan 10 01:00:09 PM PST 24
Peak memory 221544 kb
Host smart-02f4cdc2-4c2e-4144-b743-937027ee2356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206084460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3206084460
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2909577078
Short name T202
Test name
Test status
Simulation time 43413703 ps
CPU time 1.15 seconds
Started Jan 10 12:58:51 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 219488 kb
Host smart-231831ec-3d7d-4e09-ad47-d5c0ed77aee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909577078 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2909577078
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2826408328
Short name T179
Test name
Test status
Simulation time 87763665 ps
CPU time 0.86 seconds
Started Jan 10 12:58:52 PM PST 24
Finished Jan 10 01:00:25 PM PST 24
Peak memory 209552 kb
Host smart-ba2cae00-2f95-4769-8ac3-1d2709d471aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826408328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2826408328
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.458880594
Short name T222
Test name
Test status
Simulation time 94504545 ps
CPU time 1.45 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:20 PM PST 24
Peak memory 209488 kb
Host smart-315c6000-9f41-46fa-96ad-931e33558a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458880594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.458880594
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.114027280
Short name T149
Test name
Test status
Simulation time 61193479 ps
CPU time 2.11 seconds
Started Jan 10 12:58:46 PM PST 24
Finished Jan 10 01:00:12 PM PST 24
Peak memory 217584 kb
Host smart-5ad89eb4-1b4e-4166-b3d4-fa2ca605e7f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114027280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.114027280
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.921830247
Short name T139
Test name
Test status
Simulation time 288184169 ps
CPU time 2.68 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:15 PM PST 24
Peak memory 222376 kb
Host smart-352529ce-b2be-4b22-96ca-42dc731dd22b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921830247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.921830247
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.574606656
Short name T150
Test name
Test status
Simulation time 71107791 ps
CPU time 1.42 seconds
Started Jan 10 12:58:54 PM PST 24
Finished Jan 10 01:00:22 PM PST 24
Peak memory 219464 kb
Host smart-d9ff8c74-7e34-41de-acdb-84d80dbb4e00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574606656 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.574606656
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.146395670
Short name T228
Test name
Test status
Simulation time 15861836 ps
CPU time 0.83 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:18 PM PST 24
Peak memory 209504 kb
Host smart-9ceb8ab7-43b7-4a30-a67c-252b039249a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146395670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.146395670
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.538531903
Short name T280
Test name
Test status
Simulation time 145310563 ps
CPU time 1.28 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 211252 kb
Host smart-a7d710ee-b2e8-4e46-9688-816c8bc2f216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538531903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.538531903
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.323650242
Short name T240
Test name
Test status
Simulation time 146082320 ps
CPU time 2.75 seconds
Started Jan 10 12:58:52 PM PST 24
Finished Jan 10 01:00:27 PM PST 24
Peak memory 217692 kb
Host smart-5efebac6-5818-47c1-b83b-5702eaede84b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323650242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.323650242
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1359022817
Short name T258
Test name
Test status
Simulation time 124373791 ps
CPU time 2.62 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 220976 kb
Host smart-76d8a5ef-8239-43f4-a611-875a49bdf678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359022817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1359022817
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2916361827
Short name T283
Test name
Test status
Simulation time 14694082 ps
CPU time 0.88 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 208944 kb
Host smart-ebb81793-18ab-4681-b47f-200fb502c084
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916361827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2916361827
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1841550443
Short name T138
Test name
Test status
Simulation time 17674165 ps
CPU time 1.17 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 208932 kb
Host smart-2cf83614-9f5b-40d8-a4c6-41526ccdbd38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841550443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1841550443
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2424295760
Short name T273
Test name
Test status
Simulation time 631688372 ps
CPU time 5.44 seconds
Started Jan 10 12:58:53 PM PST 24
Finished Jan 10 01:00:27 PM PST 24
Peak memory 217684 kb
Host smart-ee93e580-9d46-413b-8d05-7755698cfa28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424295760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2424295760
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2170282587
Short name T257
Test name
Test status
Simulation time 43589782 ps
CPU time 1.2 seconds
Started Jan 10 12:58:53 PM PST 24
Finished Jan 10 01:00:22 PM PST 24
Peak memory 217724 kb
Host smart-6468424b-e1cf-4e6a-abc7-b45590b37f00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170282587 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2170282587
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.96440610
Short name T237
Test name
Test status
Simulation time 15933853 ps
CPU time 0.87 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:18 PM PST 24
Peak memory 209488 kb
Host smart-0c31c92f-367e-40f4-b50d-0e08ad28bb4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96440610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.96440610
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.655444466
Short name T234
Test name
Test status
Simulation time 39042284 ps
CPU time 1.3 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:18 PM PST 24
Peak memory 211384 kb
Host smart-2a749925-e47f-4458-954d-8e07a6d1b571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655444466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.655444466
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2125244747
Short name T245
Test name
Test status
Simulation time 106209652 ps
CPU time 2 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 217676 kb
Host smart-9e426bb2-54ba-4adf-b817-1e7a204c4a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125244747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2125244747
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2352127627
Short name T143
Test name
Test status
Simulation time 63490782 ps
CPU time 2.59 seconds
Started Jan 10 12:58:52 PM PST 24
Finished Jan 10 01:00:21 PM PST 24
Peak memory 217736 kb
Host smart-5ebb6fcb-2045-46e6-894f-3ea715800e46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352127627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2352127627
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3032246047
Short name T977
Test name
Test status
Simulation time 17160296 ps
CPU time 1.09 seconds
Started Jan 10 12:58:55 PM PST 24
Finished Jan 10 01:00:24 PM PST 24
Peak memory 208912 kb
Host smart-d43ac1d6-c763-430e-892f-a17757481206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032246047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3032246047
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4162103865
Short name T277
Test name
Test status
Simulation time 32886325 ps
CPU time 1.02 seconds
Started Jan 10 12:59:05 PM PST 24
Finished Jan 10 01:00:39 PM PST 24
Peak memory 209544 kb
Host smart-6b2e9c1b-63b4-4c83-8f1f-7f66e2501447
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162103865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.4162103865
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3045937192
Short name T976
Test name
Test status
Simulation time 40192018 ps
CPU time 2.85 seconds
Started Jan 10 12:58:54 PM PST 24
Finished Jan 10 01:00:23 PM PST 24
Peak memory 217764 kb
Host smart-1c2096d6-1863-48d8-9164-f04129838579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045937192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3045937192
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2763108029
Short name T116
Test name
Test status
Simulation time 556478260 ps
CPU time 1.9 seconds
Started Jan 10 12:58:57 PM PST 24
Finished Jan 10 01:00:27 PM PST 24
Peak memory 221364 kb
Host smart-f2221cc3-8f33-4879-89bd-0abc8517f556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763108029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2763108029
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1888142948
Short name T253
Test name
Test status
Simulation time 22397222 ps
CPU time 1.46 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 217852 kb
Host smart-485892bb-8dc5-4017-b4c4-efb204ba61ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888142948 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1888142948
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.701906249
Short name T203
Test name
Test status
Simulation time 17871805 ps
CPU time 0.9 seconds
Started Jan 10 12:58:53 PM PST 24
Finished Jan 10 01:00:20 PM PST 24
Peak memory 209544 kb
Host smart-54bf06f7-3e4b-4ce0-9d05-1cff2d72a06e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701906249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.701906249
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3703326725
Short name T221
Test name
Test status
Simulation time 101474948 ps
CPU time 1.31 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 209388 kb
Host smart-0a2784c2-cbac-4a88-a506-c0a951a65992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703326725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3703326725
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1006975718
Short name T274
Test name
Test status
Simulation time 33175501 ps
CPU time 1.86 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 217764 kb
Host smart-ac748812-c66f-4fbc-9bb0-9641d9a138d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006975718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1006975718
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2871191233
Short name T209
Test name
Test status
Simulation time 55158346 ps
CPU time 1.17 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 217788 kb
Host smart-e50a50e3-c462-4379-b95c-373d8be3ea72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871191233 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2871191233
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3675567710
Short name T172
Test name
Test status
Simulation time 13877852 ps
CPU time 0.82 seconds
Started Jan 10 12:58:51 PM PST 24
Finished Jan 10 01:00:18 PM PST 24
Peak memory 209392 kb
Host smart-c23c7985-e0f2-4c40-ae30-d980a38adc67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675567710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3675567710
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1189388684
Short name T185
Test name
Test status
Simulation time 77501072 ps
CPU time 1.02 seconds
Started Jan 10 12:58:55 PM PST 24
Finished Jan 10 01:00:24 PM PST 24
Peak memory 209468 kb
Host smart-e6e7bef0-2f35-4df0-875c-c1849ebcbfc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189388684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1189388684
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.770982547
Short name T246
Test name
Test status
Simulation time 976028700 ps
CPU time 3.57 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:21 PM PST 24
Peak memory 217612 kb
Host smart-eecf1e0f-2440-4d21-be5d-2b5989016615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770982547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.770982547
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1546278511
Short name T144
Test name
Test status
Simulation time 177627012 ps
CPU time 3.03 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:34 PM PST 24
Peak memory 217668 kb
Host smart-e187bebf-b340-4f68-bf5f-78c5e54775c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546278511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1546278511
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1356183574
Short name T170
Test name
Test status
Simulation time 20457662 ps
CPU time 0.95 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 217872 kb
Host smart-d360a4c8-49c7-49dc-8949-661d4bb7b356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356183574 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1356183574
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3022710886
Short name T175
Test name
Test status
Simulation time 14223482 ps
CPU time 1.02 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 208932 kb
Host smart-e45eec44-556d-4b4b-af65-41669ffe739c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022710886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3022710886
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1713370909
Short name T220
Test name
Test status
Simulation time 156762486 ps
CPU time 1.77 seconds
Started Jan 10 12:59:02 PM PST 24
Finished Jan 10 01:00:40 PM PST 24
Peak memory 209544 kb
Host smart-fa5b7b76-9713-4f6a-b0b5-3f0a33749075
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713370909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1713370909
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1977812931
Short name T252
Test name
Test status
Simulation time 76690529 ps
CPU time 2.86 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:18 PM PST 24
Peak memory 217848 kb
Host smart-200d654c-c181-4945-8916-09939c005a16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977812931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1977812931
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3934554283
Short name T120
Test name
Test status
Simulation time 58832851 ps
CPU time 1.19 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 217800 kb
Host smart-3b006ac2-e2dd-42db-adde-4b14a460011b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934554283 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3934554283
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2246905824
Short name T177
Test name
Test status
Simulation time 34953705 ps
CPU time 0.82 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:18 PM PST 24
Peak memory 209396 kb
Host smart-99d9c6de-827a-4040-a00a-d46aab7540f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246905824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2246905824
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.741159470
Short name T243
Test name
Test status
Simulation time 31039221 ps
CPU time 1.18 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 209476 kb
Host smart-92f7143c-d49c-4adc-afd5-e92656dd7806
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741159470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.741159470
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3121005808
Short name T256
Test name
Test status
Simulation time 130069444 ps
CPU time 4.65 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 217596 kb
Host smart-d62a767c-f65f-41dc-8cb9-658e468f68ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121005808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3121005808
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3595399667
Short name T178
Test name
Test status
Simulation time 60399358 ps
CPU time 1.13 seconds
Started Jan 10 12:58:29 PM PST 24
Finished Jan 10 12:59:50 PM PST 24
Peak memory 209560 kb
Host smart-fc48b622-c741-4637-b4f7-da46e4e3c312
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595399667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3595399667
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2695589415
Short name T109
Test name
Test status
Simulation time 29763676 ps
CPU time 0.97 seconds
Started Jan 10 12:58:32 PM PST 24
Finished Jan 10 12:59:52 PM PST 24
Peak memory 218092 kb
Host smart-31cac09c-e70c-4990-9fd0-c97e33601a3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695589415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2695589415
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3147045473
Short name T217
Test name
Test status
Simulation time 139868545 ps
CPU time 1.17 seconds
Started Jan 10 12:58:33 PM PST 24
Finished Jan 10 12:59:54 PM PST 24
Peak memory 219144 kb
Host smart-e9e6b829-7783-4da5-880a-3fd568a0dc24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147045473 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3147045473
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3212375003
Short name T169
Test name
Test status
Simulation time 33201453 ps
CPU time 1.03 seconds
Started Jan 10 12:58:26 PM PST 24
Finished Jan 10 12:59:47 PM PST 24
Peak memory 209456 kb
Host smart-d20656f5-22a9-48ec-975b-f0abbbeae7a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212375003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3212375003
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1993266505
Short name T161
Test name
Test status
Simulation time 36704246 ps
CPU time 1.07 seconds
Started Jan 10 12:58:27 PM PST 24
Finished Jan 10 12:59:51 PM PST 24
Peak memory 207940 kb
Host smart-303db7dd-a139-4b77-b1d0-e36853d9ecaa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993266505 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1993266505
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3443007179
Short name T206
Test name
Test status
Simulation time 546230356 ps
CPU time 12.76 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:25 PM PST 24
Peak memory 209444 kb
Host smart-d31a9ec4-20cf-47fe-82cc-922d75971005
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443007179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3443007179
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3065683920
Short name T107
Test name
Test status
Simulation time 161796851 ps
CPU time 2.5 seconds
Started Jan 10 12:58:43 PM PST 24
Finished Jan 10 01:00:07 PM PST 24
Peak memory 210684 kb
Host smart-1e85a84e-5a13-48e0-9cc7-ca291e973af3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065683920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3065683920
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2205057767
Short name T279
Test name
Test status
Simulation time 68951125 ps
CPU time 1.1 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:09 PM PST 24
Peak memory 209556 kb
Host smart-37aaf9d3-86e4-4a46-bb3a-95459d30e616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220505
7767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2205057767
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1579472824
Short name T166
Test name
Test status
Simulation time 146239441 ps
CPU time 1.58 seconds
Started Jan 10 12:58:24 PM PST 24
Finished Jan 10 12:59:45 PM PST 24
Peak memory 209348 kb
Host smart-a0849707-c5f5-4523-bd94-f0fd42b3f601
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579472824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1579472824
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1371832682
Short name T260
Test name
Test status
Simulation time 22184063 ps
CPU time 1.48 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 211556 kb
Host smart-de8eccf4-a566-4157-a42c-90e490e502a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371832682 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1371832682
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3758534111
Short name T265
Test name
Test status
Simulation time 27369476 ps
CPU time 1.39 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:56 PM PST 24
Peak memory 209492 kb
Host smart-772bad4b-d034-4790-a4e5-cbb88d130573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758534111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3758534111
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1048744695
Short name T267
Test name
Test status
Simulation time 126228145 ps
CPU time 4.39 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:22 PM PST 24
Peak memory 217672 kb
Host smart-d57e0d61-08b5-4f07-b358-f885a34851e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048744695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1048744695
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4187856274
Short name T147
Test name
Test status
Simulation time 185785658 ps
CPU time 1.83 seconds
Started Jan 10 12:58:28 PM PST 24
Finished Jan 10 12:59:50 PM PST 24
Peak memory 221088 kb
Host smart-fa81a352-b17d-4610-8bc6-f0b9f070fd78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187856274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.4187856274
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1005927213
Short name T181
Test name
Test status
Simulation time 114699241 ps
CPU time 1.23 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:55 PM PST 24
Peak memory 209516 kb
Host smart-c67c1d99-f697-4be1-90b9-4ddb31f14496
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005927213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1005927213
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.627504805
Short name T227
Test name
Test status
Simulation time 54014196 ps
CPU time 1.97 seconds
Started Jan 10 12:58:33 PM PST 24
Finished Jan 10 12:59:55 PM PST 24
Peak memory 209432 kb
Host smart-6c4cf8c6-5426-4c8c-8a10-e735d46e1bf7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627504805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.627504805
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3474754356
Short name T111
Test name
Test status
Simulation time 20192966 ps
CPU time 0.84 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:54 PM PST 24
Peak memory 209592 kb
Host smart-a823725e-d7b5-46f4-9d01-29c8ca7e2fdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474754356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3474754356
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2772265181
Short name T270
Test name
Test status
Simulation time 59104611 ps
CPU time 1.25 seconds
Started Jan 10 12:58:37 PM PST 24
Finished Jan 10 12:59:57 PM PST 24
Peak memory 218576 kb
Host smart-48dabe43-c952-4e25-8502-bf6f78e539f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772265181 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2772265181
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2224702724
Short name T168
Test name
Test status
Simulation time 33930015 ps
CPU time 0.79 seconds
Started Jan 10 12:58:41 PM PST 24
Finished Jan 10 01:00:03 PM PST 24
Peak memory 208552 kb
Host smart-60e2f09d-b2c0-449d-89e7-d699145713e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224702724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2224702724
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.271146310
Short name T276
Test name
Test status
Simulation time 264819666 ps
CPU time 1.35 seconds
Started Jan 10 12:58:35 PM PST 24
Finished Jan 10 12:59:56 PM PST 24
Peak memory 207848 kb
Host smart-54000846-6e27-4ba6-987c-b04fa140bcd7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271146310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.271146310
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1665760457
Short name T255
Test name
Test status
Simulation time 700674589 ps
CPU time 15.61 seconds
Started Jan 10 12:58:46 PM PST 24
Finished Jan 10 01:00:24 PM PST 24
Peak memory 208460 kb
Host smart-373205b4-cd6a-4dc4-ae91-87e15052aec9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665760457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1665760457
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.960379172
Short name T235
Test name
Test status
Simulation time 4140472636 ps
CPU time 44.11 seconds
Started Jan 10 12:58:43 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 209556 kb
Host smart-c0e5f444-30fc-41c6-b6a4-5d3cacc4a53b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960379172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.960379172
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2482898011
Short name T225
Test name
Test status
Simulation time 885967013 ps
CPU time 2.91 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:57 PM PST 24
Peak memory 210896 kb
Host smart-ebf224de-ce9a-476c-b13f-fcf518e73a82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482898011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2482898011
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.105427440
Short name T248
Test name
Test status
Simulation time 87762552 ps
CPU time 1.94 seconds
Started Jan 10 12:58:32 PM PST 24
Finished Jan 10 12:59:53 PM PST 24
Peak memory 222632 kb
Host smart-3d780abf-fd05-4349-9ae0-b23fd130b026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105427
440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.105427440
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.300272909
Short name T290
Test name
Test status
Simulation time 209843518 ps
CPU time 2.07 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:57 PM PST 24
Peak memory 209392 kb
Host smart-cabe1f4a-5355-4f25-a1b4-fb2ddaf8b11d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300272909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.300272909
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.884702442
Short name T213
Test name
Test status
Simulation time 20734871 ps
CPU time 1.5 seconds
Started Jan 10 12:58:37 PM PST 24
Finished Jan 10 12:59:58 PM PST 24
Peak memory 211388 kb
Host smart-c04a7f37-6444-4d1f-a8a9-42d4a4c6f509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884702442 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.884702442
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1053125226
Short name T187
Test name
Test status
Simulation time 73485759 ps
CPU time 1.35 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:09 PM PST 24
Peak memory 211112 kb
Host smart-9bd35d06-86ec-458d-a93b-fa44c744204d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053125226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1053125226
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2327018568
Short name T288
Test name
Test status
Simulation time 70032408 ps
CPU time 1.97 seconds
Started Jan 10 12:58:33 PM PST 24
Finished Jan 10 12:59:55 PM PST 24
Peak memory 217692 kb
Host smart-f5de97ca-ce09-44b6-b788-02ecabf7d12d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327018568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2327018568
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.65800904
Short name T156
Test name
Test status
Simulation time 380240257 ps
CPU time 3.15 seconds
Started Jan 10 12:58:39 PM PST 24
Finished Jan 10 01:00:02 PM PST 24
Peak memory 213144 kb
Host smart-bdaa87ae-da04-41da-a546-76d31c79689a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65800904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_er
r.65800904
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.459602847
Short name T184
Test name
Test status
Simulation time 19195630 ps
CPU time 1.13 seconds
Started Jan 10 12:58:36 PM PST 24
Finished Jan 10 01:00:00 PM PST 24
Peak memory 209592 kb
Host smart-8e22ee94-0e17-4e07-bee3-80db66774010
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459602847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.459602847
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.917669646
Short name T230
Test name
Test status
Simulation time 26391973 ps
CPU time 1.43 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:55 PM PST 24
Peak memory 208240 kb
Host smart-3e36a1e7-4411-41a6-a788-210f696c324b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917669646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.917669646
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3160678245
Short name T286
Test name
Test status
Simulation time 24264375 ps
CPU time 1.31 seconds
Started Jan 10 12:58:36 PM PST 24
Finished Jan 10 12:59:59 PM PST 24
Peak memory 219608 kb
Host smart-41e82390-9c68-402f-98a4-da7ad489a6bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160678245 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3160678245
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1430868411
Short name T224
Test name
Test status
Simulation time 24951731 ps
CPU time 0.82 seconds
Started Jan 10 12:58:35 PM PST 24
Finished Jan 10 12:59:56 PM PST 24
Peak memory 209416 kb
Host smart-f3da7529-5dc8-431e-a8eb-d294387f1038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430868411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1430868411
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.884052291
Short name T264
Test name
Test status
Simulation time 103446046 ps
CPU time 1.6 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:56 PM PST 24
Peak memory 207812 kb
Host smart-92f166b5-973d-48ad-819e-1727acdfe0c0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884052291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.884052291
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.189123220
Short name T278
Test name
Test status
Simulation time 436293591 ps
CPU time 2.83 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:57 PM PST 24
Peak memory 208456 kb
Host smart-1bfb83cc-e13d-4b46-b02d-5fb5757d7ce2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189123220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.189123220
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1242828334
Short name T198
Test name
Test status
Simulation time 2688891790 ps
CPU time 17.36 seconds
Started Jan 10 12:58:35 PM PST 24
Finished Jan 10 01:00:12 PM PST 24
Peak memory 209456 kb
Host smart-99391da2-3737-4b24-a454-5277f6370ed9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242828334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1242828334
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.252910093
Short name T223
Test name
Test status
Simulation time 154829804 ps
CPU time 1.48 seconds
Started Jan 10 12:58:36 PM PST 24
Finished Jan 10 01:00:00 PM PST 24
Peak memory 210572 kb
Host smart-0cc9df83-57a1-4fa4-8e00-c6e2b443e66a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252910093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.252910093
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2315714111
Short name T167
Test name
Test status
Simulation time 51772880 ps
CPU time 1.55 seconds
Started Jan 10 12:58:33 PM PST 24
Finished Jan 10 12:59:54 PM PST 24
Peak memory 218588 kb
Host smart-f46074fa-fa25-4cd0-b310-bbb6490bfc6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231571
4111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2315714111
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.882011417
Short name T205
Test name
Test status
Simulation time 54785597 ps
CPU time 1.66 seconds
Started Jan 10 12:58:33 PM PST 24
Finished Jan 10 12:59:54 PM PST 24
Peak memory 209376 kb
Host smart-ed15c88d-56b8-4267-b5ea-30fb7f23204f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882011417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.882011417
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2810437780
Short name T188
Test name
Test status
Simulation time 122306560 ps
CPU time 1.07 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:55 PM PST 24
Peak memory 209548 kb
Host smart-c1a0d0a2-3ae4-407e-a3b0-3c8a012d7bb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810437780 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2810437780
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3066511082
Short name T200
Test name
Test status
Simulation time 162148434 ps
CPU time 1.35 seconds
Started Jan 10 12:58:32 PM PST 24
Finished Jan 10 12:59:53 PM PST 24
Peak memory 209380 kb
Host smart-4a34b09a-c5cb-4592-8f23-f3c42e12d516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066511082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3066511082
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2876079764
Short name T151
Test name
Test status
Simulation time 27181489 ps
CPU time 2.08 seconds
Started Jan 10 12:58:40 PM PST 24
Finished Jan 10 01:00:02 PM PST 24
Peak memory 217668 kb
Host smart-edcde21b-f786-46af-8544-056dfb79866d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876079764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2876079764
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3242327762
Short name T201
Test name
Test status
Simulation time 91653281 ps
CPU time 1.22 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:55 PM PST 24
Peak memory 218168 kb
Host smart-22a1ab1e-55f9-40e2-a47d-1f5fc7421519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242327762 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3242327762
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4053324594
Short name T104
Test name
Test status
Simulation time 275649778 ps
CPU time 1.11 seconds
Started Jan 10 12:58:33 PM PST 24
Finished Jan 10 12:59:54 PM PST 24
Peak memory 209372 kb
Host smart-fc46ba74-6f1b-4e2f-ba2f-bbae050a71fb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053324594 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4053324594
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.916932620
Short name T292
Test name
Test status
Simulation time 995191409 ps
CPU time 4.69 seconds
Started Jan 10 12:58:39 PM PST 24
Finished Jan 10 01:00:03 PM PST 24
Peak memory 208392 kb
Host smart-288e1183-8207-4904-a673-26700e352c59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916932620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.916932620
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2627096443
Short name T229
Test name
Test status
Simulation time 2221558604 ps
CPU time 8.9 seconds
Started Jan 10 12:58:44 PM PST 24
Finished Jan 10 01:00:15 PM PST 24
Peak memory 209508 kb
Host smart-72041574-214c-4d82-aade-05b1c4faedf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627096443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2627096443
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1695674466
Short name T287
Test name
Test status
Simulation time 83807390 ps
CPU time 1.13 seconds
Started Jan 10 12:58:32 PM PST 24
Finished Jan 10 12:59:53 PM PST 24
Peak memory 210712 kb
Host smart-fb93b703-14c5-400b-980b-5fc900bcdfef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695674466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1695674466
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.961650517
Short name T110
Test name
Test status
Simulation time 242769556 ps
CPU time 1.84 seconds
Started Jan 10 12:58:43 PM PST 24
Finished Jan 10 01:00:06 PM PST 24
Peak memory 218092 kb
Host smart-55313d43-0355-4895-8c36-bed5d490b03a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961650
517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.961650517
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.816660376
Short name T163
Test name
Test status
Simulation time 42302471 ps
CPU time 1.61 seconds
Started Jan 10 12:58:34 PM PST 24
Finished Jan 10 12:59:56 PM PST 24
Peak memory 209448 kb
Host smart-96b518a7-2e6a-42d8-9c2e-28a7d66d276c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816660376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.816660376
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2876168470
Short name T214
Test name
Test status
Simulation time 20264977 ps
CPU time 1.2 seconds
Started Jan 10 12:58:35 PM PST 24
Finished Jan 10 12:59:56 PM PST 24
Peak memory 217748 kb
Host smart-7e5079e1-181c-4152-8ea1-6d5db10a5a51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876168470 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2876168470
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.840445329
Short name T199
Test name
Test status
Simulation time 152939736 ps
CPU time 1.4 seconds
Started Jan 10 12:58:35 PM PST 24
Finished Jan 10 12:59:57 PM PST 24
Peak memory 209484 kb
Host smart-bd61b927-65e5-49e7-ba76-88781ac78133
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840445329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.840445329
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.668023049
Short name T91
Test name
Test status
Simulation time 295872501 ps
CPU time 2.36 seconds
Started Jan 10 12:58:41 PM PST 24
Finished Jan 10 01:00:04 PM PST 24
Peak memory 217672 kb
Host smart-c52f4133-0128-47f8-bc2a-9fc642a45cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668023049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.668023049
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.849744013
Short name T232
Test name
Test status
Simulation time 33700987 ps
CPU time 0.99 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:15 PM PST 24
Peak memory 217824 kb
Host smart-f7ab08a4-9ab3-4c03-b4b7-0d1be1bee237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849744013 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.849744013
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4018966818
Short name T113
Test name
Test status
Simulation time 15211059 ps
CPU time 0.84 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:20 PM PST 24
Peak memory 208760 kb
Host smart-49b3046c-c846-4fc1-adfa-b7b2000c3b5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018966818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4018966818
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1868921830
Short name T268
Test name
Test status
Simulation time 457997170 ps
CPU time 1.15 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:15 PM PST 24
Peak memory 209380 kb
Host smart-688a0feb-3255-407d-bcf5-c61aef8f5362
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868921830 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1868921830
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1064380514
Short name T226
Test name
Test status
Simulation time 187410709 ps
CPU time 4.79 seconds
Started Jan 10 12:58:36 PM PST 24
Finished Jan 10 01:00:04 PM PST 24
Peak memory 208460 kb
Host smart-4a73eb77-f160-44de-bcd2-ba5797b86f98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064380514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1064380514
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1083032057
Short name T249
Test name
Test status
Simulation time 2015175496 ps
CPU time 16.28 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:24 PM PST 24
Peak memory 209488 kb
Host smart-16e05062-a681-4fc8-b4e1-07ae9c069bfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083032057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1083032057
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3109403730
Short name T979
Test name
Test status
Simulation time 261954525 ps
CPU time 3.43 seconds
Started Jan 10 12:58:36 PM PST 24
Finished Jan 10 01:00:02 PM PST 24
Peak memory 210672 kb
Host smart-70f4dfad-6320-48ed-a547-eed07977bb55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109403730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3109403730
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1240906655
Short name T159
Test name
Test status
Simulation time 66753918 ps
CPU time 2.11 seconds
Started Jan 10 12:58:36 PM PST 24
Finished Jan 10 12:59:58 PM PST 24
Peak memory 209480 kb
Host smart-3b650632-729e-4792-b26f-5806f7132dcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240906655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1240906655
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4151592294
Short name T266
Test name
Test status
Simulation time 46338754 ps
CPU time 1.92 seconds
Started Jan 10 12:58:39 PM PST 24
Finished Jan 10 01:00:00 PM PST 24
Peak memory 209564 kb
Host smart-284b8ef3-29d3-45d5-9e04-9441d0d7f580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151592294 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4151592294
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3666445553
Short name T272
Test name
Test status
Simulation time 252227424 ps
CPU time 1.52 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:14 PM PST 24
Peak memory 211664 kb
Host smart-c4a322ae-278d-432c-bee0-f2607a26453b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666445553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3666445553
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.984522998
Short name T289
Test name
Test status
Simulation time 135783883 ps
CPU time 1.67 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:13 PM PST 24
Peak memory 219420 kb
Host smart-4e6b451a-6149-403e-b9b8-3d05e990dfeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984522998 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.984522998
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3264723514
Short name T210
Test name
Test status
Simulation time 262714093 ps
CPU time 1.86 seconds
Started Jan 10 12:58:44 PM PST 24
Finished Jan 10 01:00:08 PM PST 24
Peak memory 209288 kb
Host smart-b0de6d2c-682c-4705-8444-43c10caec78a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264723514 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3264723514
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1399856200
Short name T263
Test name
Test status
Simulation time 1017118056 ps
CPU time 6.02 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 209396 kb
Host smart-c8312836-101c-4527-8ff7-2b9f4d481e23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399856200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1399856200
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1430230327
Short name T118
Test name
Test status
Simulation time 3894654666 ps
CPU time 25.23 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:39 PM PST 24
Peak memory 209508 kb
Host smart-a31a518f-f347-4038-8092-969870cea38b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430230327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1430230327
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1426131960
Short name T211
Test name
Test status
Simulation time 947759402 ps
CPU time 2.98 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 210948 kb
Host smart-377ee026-1f41-4ff2-829d-7883f2336959
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426131960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1426131960
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1708361404
Short name T204
Test name
Test status
Simulation time 50709439 ps
CPU time 1.93 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:14 PM PST 24
Peak memory 217868 kb
Host smart-a87200bd-1663-4d5c-bae5-892a0813d385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170836
1404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1708361404
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4284499007
Short name T244
Test name
Test status
Simulation time 326509776 ps
CPU time 1.17 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 209392 kb
Host smart-5ecf5241-d54e-4341-aa43-b29b1de6f903
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284499007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.4284499007
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2465295500
Short name T94
Test name
Test status
Simulation time 323319809 ps
CPU time 1.31 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:10 PM PST 24
Peak memory 209548 kb
Host smart-917044ea-2a4d-4075-a4cf-458b799c12a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465295500 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2465295500
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1393094801
Short name T293
Test name
Test status
Simulation time 15881358 ps
CPU time 1.2 seconds
Started Jan 10 12:58:46 PM PST 24
Finished Jan 10 01:00:12 PM PST 24
Peak memory 209500 kb
Host smart-922d8623-ac2c-48c3-b2b9-e4fb35c3e7e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393094801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1393094801
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3153430158
Short name T236
Test name
Test status
Simulation time 139487342 ps
CPU time 2.25 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:16 PM PST 24
Peak memory 217908 kb
Host smart-acb2653b-99d9-45c2-b424-9368c86ac201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153430158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3153430158
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.718710737
Short name T152
Test name
Test status
Simulation time 113927347 ps
CPU time 3.01 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:21 PM PST 24
Peak memory 221900 kb
Host smart-475aa395-bc03-44c5-a3ea-be4f3ca0ea59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718710737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.718710737
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3962897918
Short name T103
Test name
Test status
Simulation time 87120190 ps
CPU time 1.47 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:16 PM PST 24
Peak memory 219500 kb
Host smart-450edddb-c2e4-480c-a992-f8cb7fed2850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962897918 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3962897918
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2300754015
Short name T174
Test name
Test status
Simulation time 11543571 ps
CPU time 0.91 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:11 PM PST 24
Peak memory 208912 kb
Host smart-d2917732-a35f-4934-b98e-3a9d6bb66519
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300754015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2300754015
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2820848451
Short name T281
Test name
Test status
Simulation time 55279806 ps
CPU time 1.81 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 209340 kb
Host smart-545d60dd-8be2-4f9a-bd51-6d14d5220f94
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820848451 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2820848451
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2647734368
Short name T247
Test name
Test status
Simulation time 618864506 ps
CPU time 7.13 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:38 PM PST 24
Peak memory 207716 kb
Host smart-05e13edb-cbd7-44e5-929c-79390a4423bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647734368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2647734368
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2705254263
Short name T238
Test name
Test status
Simulation time 945562305 ps
CPU time 20.61 seconds
Started Jan 10 12:58:44 PM PST 24
Finished Jan 10 01:00:31 PM PST 24
Peak memory 209384 kb
Host smart-df0f6bcf-8505-42e3-8809-83206a4e1d26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705254263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2705254263
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2387443329
Short name T162
Test name
Test status
Simulation time 70693370 ps
CPU time 1.44 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:09 PM PST 24
Peak memory 210716 kb
Host smart-156c714a-2356-4213-b4f4-a1444bcbf26c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387443329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2387443329
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.162292871
Short name T215
Test name
Test status
Simulation time 31870337 ps
CPU time 1.19 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 217648 kb
Host smart-8c76f230-c09d-47fc-be3e-0cd7e9f299d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162292
871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.162292871
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2960433554
Short name T219
Test name
Test status
Simulation time 153361956 ps
CPU time 1.59 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:13 PM PST 24
Peak memory 208400 kb
Host smart-99b17e29-8372-42bf-91c0-624ef1855be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960433554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2960433554
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2666444507
Short name T186
Test name
Test status
Simulation time 34314633 ps
CPU time 1.32 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:09 PM PST 24
Peak memory 209576 kb
Host smart-91a5638a-d498-4a56-9b9e-e9e75aa8fe71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666444507 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2666444507
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3880773859
Short name T208
Test name
Test status
Simulation time 15085842 ps
CPU time 1.04 seconds
Started Jan 10 12:58:50 PM PST 24
Finished Jan 10 01:00:18 PM PST 24
Peak memory 208984 kb
Host smart-880d896c-dcdb-47b8-946f-58219249a6c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880773859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3880773859
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2754971644
Short name T275
Test name
Test status
Simulation time 286451600 ps
CPU time 3.92 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:17 PM PST 24
Peak memory 217592 kb
Host smart-bed0389c-5fdf-47d9-965f-dcacfc5444ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754971644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2754971644
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2787743007
Short name T114
Test name
Test status
Simulation time 80679710 ps
CPU time 1.97 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:16 PM PST 24
Peak memory 219164 kb
Host smart-d88eb833-b7be-448b-b58e-c5debec28d9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787743007 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2787743007
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2671544591
Short name T182
Test name
Test status
Simulation time 11370087 ps
CPU time 0.9 seconds
Started Jan 10 12:58:46 PM PST 24
Finished Jan 10 01:00:10 PM PST 24
Peak memory 209500 kb
Host smart-8cc736a2-6d08-4b63-99a2-d4a44e0d5426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671544591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2671544591
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1362223862
Short name T291
Test name
Test status
Simulation time 60785488 ps
CPU time 1.06 seconds
Started Jan 10 12:58:46 PM PST 24
Finished Jan 10 01:00:11 PM PST 24
Peak memory 209396 kb
Host smart-766100c9-5c21-468e-b2bc-4acc15175e45
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362223862 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1362223862
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3393367794
Short name T207
Test name
Test status
Simulation time 675294868 ps
CPU time 13.31 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 208364 kb
Host smart-4fe9b88e-f8ec-490e-b42d-65a52bd9f366
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393367794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3393367794
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2379051931
Short name T284
Test name
Test status
Simulation time 2956286218 ps
CPU time 8.22 seconds
Started Jan 10 12:58:49 PM PST 24
Finished Jan 10 01:00:27 PM PST 24
Peak memory 209532 kb
Host smart-de4c4c34-6138-4434-8e73-7ff40684770a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379051931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2379051931
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1018168064
Short name T285
Test name
Test status
Simulation time 45161206 ps
CPU time 1.9 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:16 PM PST 24
Peak memory 217728 kb
Host smart-bf77aa0f-68b8-480d-b3b4-9874a530528b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101816
8064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1018168064
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1399656058
Short name T294
Test name
Test status
Simulation time 298570814 ps
CPU time 2.24 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:32 PM PST 24
Peak memory 209380 kb
Host smart-b532e0e7-7559-4c4c-a5b0-54848dea38a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399656058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1399656058
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2266300202
Short name T98
Test name
Test status
Simulation time 56765723 ps
CPU time 0.94 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:14 PM PST 24
Peak memory 209624 kb
Host smart-9561eed3-a286-4db2-b6b3-32128eeca84f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266300202 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2266300202
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.46417080
Short name T242
Test name
Test status
Simulation time 83554605 ps
CPU time 1.24 seconds
Started Jan 10 12:58:48 PM PST 24
Finished Jan 10 01:00:14 PM PST 24
Peak memory 208940 kb
Host smart-d3d7fb6b-cbcb-46af-9679-8ba6123c1570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46417080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_s
ame_csr_outstanding.46417080
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.288501162
Short name T262
Test name
Test status
Simulation time 90040183 ps
CPU time 1.4 seconds
Started Jan 10 12:58:47 PM PST 24
Finished Jan 10 01:00:13 PM PST 24
Peak memory 218604 kb
Host smart-c22cf470-bb15-45ec-aa47-b65e615c4ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288501162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.288501162
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.470242919
Short name T154
Test name
Test status
Simulation time 108654306 ps
CPU time 2.2 seconds
Started Jan 10 12:58:46 PM PST 24
Finished Jan 10 01:00:11 PM PST 24
Peak memory 221808 kb
Host smart-5d5ddeaf-63eb-4642-8f18-772d703cdd2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470242919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.470242919
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.667556067
Short name T673
Test name
Test status
Simulation time 101700532 ps
CPU time 1.25 seconds
Started Jan 10 12:39:38 PM PST 24
Finished Jan 10 12:40:08 PM PST 24
Peak memory 209704 kb
Host smart-3de9a6bc-5645-425b-89a4-67d2e6dc2001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667556067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.667556067
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.406640051
Short name T26
Test name
Test status
Simulation time 10239107 ps
CPU time 0.87 seconds
Started Jan 10 12:49:12 PM PST 24
Finished Jan 10 12:50:44 PM PST 24
Peak memory 209520 kb
Host smart-35f175e2-829c-4d4a-9782-e5346d1e26f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406640051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.406640051
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.948697771
Short name T413
Test name
Test status
Simulation time 477199357 ps
CPU time 13.95 seconds
Started Jan 10 12:52:03 PM PST 24
Finished Jan 10 12:53:36 PM PST 24
Peak memory 218116 kb
Host smart-3f941686-851b-4c2e-8c4c-8e96968f583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948697771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.948697771
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.441807095
Short name T855
Test name
Test status
Simulation time 1008797613 ps
CPU time 5.81 seconds
Started Jan 10 12:46:59 PM PST 24
Finished Jan 10 12:48:23 PM PST 24
Peak memory 209532 kb
Host smart-185bd5d3-c16d-4b2e-9eec-b06ef42ba46e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441807095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_acc
ess.441807095
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3589935642
Short name T512
Test name
Test status
Simulation time 1548856081 ps
CPU time 29.25 seconds
Started Jan 10 01:01:14 PM PST 24
Finished Jan 10 01:03:09 PM PST 24
Peak memory 218192 kb
Host smart-7ab981a0-230c-4607-a09d-9da8c20336ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589935642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3589935642
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1329294878
Short name T561
Test name
Test status
Simulation time 2009682129 ps
CPU time 17.46 seconds
Started Jan 10 01:10:11 PM PST 24
Finished Jan 10 01:11:40 PM PST 24
Peak memory 217916 kb
Host smart-de144310-23a0-40f1-b950-d9537015c301
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329294878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.1329294878
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.385562579
Short name T502
Test name
Test status
Simulation time 1556300930 ps
CPU time 5.21 seconds
Started Jan 10 12:50:06 PM PST 24
Finished Jan 10 12:51:34 PM PST 24
Peak memory 218036 kb
Host smart-75b86466-6469-42ee-95b9-31dac01ffa35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385562579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.385562579
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1653394426
Short name T548
Test name
Test status
Simulation time 1684901510 ps
CPU time 12.92 seconds
Started Jan 10 12:37:34 PM PST 24
Finished Jan 10 12:38:21 PM PST 24
Peak memory 212896 kb
Host smart-641da081-f54b-4f5a-b7f9-92f3cad9cb2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653394426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1653394426
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1341073254
Short name T583
Test name
Test status
Simulation time 4964523385 ps
CPU time 5.73 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:49 PM PST 24
Peak memory 213980 kb
Host smart-dbbe0cc8-1fe7-408a-af02-a24ab45091b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341073254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1341073254
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4190493786
Short name T575
Test name
Test status
Simulation time 6362556885 ps
CPU time 87.84 seconds
Started Jan 10 12:37:24 PM PST 24
Finished Jan 10 12:39:27 PM PST 24
Peak memory 267776 kb
Host smart-069272d8-3c91-4e78-a417-63353cabc4f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190493786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4190493786
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3356811884
Short name T391
Test name
Test status
Simulation time 958432466 ps
CPU time 19.18 seconds
Started Jan 10 12:49:09 PM PST 24
Finished Jan 10 12:50:59 PM PST 24
Peak memory 250980 kb
Host smart-207e15c6-df55-47c2-a208-c832cfc52c5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356811884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3356811884
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.607384743
Short name T125
Test name
Test status
Simulation time 24428011 ps
CPU time 1.69 seconds
Started Jan 10 12:51:09 PM PST 24
Finished Jan 10 12:52:41 PM PST 24
Peak memory 218084 kb
Host smart-d9b0b85c-3efa-4917-80de-54eff04b6f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607384743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.607384743
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2855965159
Short name T515
Test name
Test status
Simulation time 434142488 ps
CPU time 16.06 seconds
Started Jan 10 12:38:36 PM PST 24
Finished Jan 10 12:39:23 PM PST 24
Peak memory 214176 kb
Host smart-a0435081-f6eb-4626-81d0-650085171a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855965159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2855965159
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2370623589
Short name T472
Test name
Test status
Simulation time 911761066 ps
CPU time 12.81 seconds
Started Jan 10 12:40:43 PM PST 24
Finished Jan 10 12:41:42 PM PST 24
Peak memory 218084 kb
Host smart-6fc65935-41ad-4482-9335-bd5c8fa0a32a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370623589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2370623589
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4292863820
Short name T834
Test name
Test status
Simulation time 4908675107 ps
CPU time 23.29 seconds
Started Jan 10 12:50:42 PM PST 24
Finished Jan 10 12:52:27 PM PST 24
Peak memory 218400 kb
Host smart-41aba046-7725-4345-987d-1134f12affae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292863820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.4292863820
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2267502405
Short name T70
Test name
Test status
Simulation time 1180945874 ps
CPU time 7.17 seconds
Started Jan 10 12:40:53 PM PST 24
Finished Jan 10 12:41:51 PM PST 24
Peak memory 218028 kb
Host smart-b4c49710-e7ef-42a2-bb38-1f5ecbd5b52e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267502405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
267502405
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2265506408
Short name T514
Test name
Test status
Simulation time 315956760 ps
CPU time 11.26 seconds
Started Jan 10 12:42:53 PM PST 24
Finished Jan 10 12:44:18 PM PST 24
Peak memory 218084 kb
Host smart-a7ecb775-5d55-4eda-98ee-1a1207ce0590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265506408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2265506408
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.172398132
Short name T969
Test name
Test status
Simulation time 2029672583 ps
CPU time 17.09 seconds
Started Jan 10 12:44:38 PM PST 24
Finished Jan 10 12:46:13 PM PST 24
Peak memory 251160 kb
Host smart-015783a0-0810-4081-b05b-b7358c684fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172398132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.172398132
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2023970682
Short name T305
Test name
Test status
Simulation time 61947401 ps
CPU time 7.19 seconds
Started Jan 10 12:39:47 PM PST 24
Finished Jan 10 12:40:25 PM PST 24
Peak memory 250360 kb
Host smart-b69014f4-f603-4342-bba0-f8cd21459f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023970682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2023970682
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2054457711
Short name T774
Test name
Test status
Simulation time 3459881538 ps
CPU time 69.12 seconds
Started Jan 10 12:46:21 PM PST 24
Finished Jan 10 12:48:47 PM PST 24
Peak memory 249352 kb
Host smart-05bd750f-926a-47c3-9d12-2da0f8610aa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054457711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2054457711
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2055969557
Short name T840
Test name
Test status
Simulation time 22673163 ps
CPU time 0.76 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:26 PM PST 24
Peak memory 208000 kb
Host smart-c2479941-b8b7-40f9-848e-232ef8a4c274
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055969557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2055969557
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4221828036
Short name T662
Test name
Test status
Simulation time 18817538 ps
CPU time 0.81 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 209428 kb
Host smart-1a748fee-e664-4dca-a8b9-10d4a57b98b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221828036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4221828036
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3550774281
Short name T869
Test name
Test status
Simulation time 47097581 ps
CPU time 0.78 seconds
Started Jan 10 01:07:47 PM PST 24
Finished Jan 10 01:09:09 PM PST 24
Peak memory 209192 kb
Host smart-c2c9fae5-f239-4d54-94a9-6a532fa7cbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550774281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3550774281
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4112518507
Short name T974
Test name
Test status
Simulation time 448407381 ps
CPU time 15.81 seconds
Started Jan 10 01:44:18 PM PST 24
Finished Jan 10 01:44:36 PM PST 24
Peak memory 218224 kb
Host smart-bc6193c9-53e8-4450-9ee9-7862d5ffff53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112518507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4112518507
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2915607088
Short name T806
Test name
Test status
Simulation time 7643257810 ps
CPU time 11.79 seconds
Started Jan 10 12:40:07 PM PST 24
Finished Jan 10 12:41:05 PM PST 24
Peak memory 209588 kb
Host smart-14ffc8ef-0c8d-4d31-a940-85be29e06d36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915607088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.2915607088
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3397848136
Short name T877
Test name
Test status
Simulation time 5665296200 ps
CPU time 39.23 seconds
Started Jan 10 12:40:09 PM PST 24
Finished Jan 10 12:41:34 PM PST 24
Peak memory 218460 kb
Host smart-61f2fa4c-37ba-4150-a7da-db9248146325
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397848136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3397848136
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2271768264
Short name T595
Test name
Test status
Simulation time 2318527061 ps
CPU time 6.55 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:40:52 PM PST 24
Peak memory 209676 kb
Host smart-23b01388-12c3-4d2a-853c-e77112966829
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271768264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.2271768264
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1696792035
Short name T759
Test name
Test status
Simulation time 3605097526 ps
CPU time 9.03 seconds
Started Jan 10 12:44:15 PM PST 24
Finished Jan 10 12:45:41 PM PST 24
Peak memory 218016 kb
Host smart-ada87732-e801-4d7e-bbe9-3c2770ada3e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696792035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1696792035
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2683919799
Short name T518
Test name
Test status
Simulation time 8122668757 ps
CPU time 15.68 seconds
Started Jan 10 12:44:08 PM PST 24
Finished Jan 10 12:45:41 PM PST 24
Peak memory 213708 kb
Host smart-24f2ddbb-c321-4d7a-af11-1b8900a8a81f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683919799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2683919799
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1133095150
Short name T19
Test name
Test status
Simulation time 1352274215 ps
CPU time 2.92 seconds
Started Jan 10 12:43:43 PM PST 24
Finished Jan 10 12:45:01 PM PST 24
Peak memory 212528 kb
Host smart-07b07cd7-6aae-49bf-8f4f-7054b9c8a15d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133095150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1133095150
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.677211864
Short name T842
Test name
Test status
Simulation time 3305708286 ps
CPU time 43.45 seconds
Started Jan 10 12:57:16 PM PST 24
Finished Jan 10 12:59:12 PM PST 24
Peak memory 251008 kb
Host smart-86a21586-b711-43cd-9986-5677430e3629
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677211864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.677211864
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.822083549
Short name T751
Test name
Test status
Simulation time 1512296795 ps
CPU time 6.94 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:13 PM PST 24
Peak memory 222384 kb
Host smart-d52433b1-dbfb-46c4-bd8b-e2ee6b943752
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822083549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.822083549
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1570045445
Short name T485
Test name
Test status
Simulation time 86321313 ps
CPU time 2.58 seconds
Started Jan 10 12:57:49 PM PST 24
Finished Jan 10 12:59:10 PM PST 24
Peak memory 218228 kb
Host smart-31846b22-113f-497c-8ef6-48ae1450bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570045445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1570045445
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.4128154694
Short name T676
Test name
Test status
Simulation time 212254344 ps
CPU time 14.33 seconds
Started Jan 10 01:05:53 PM PST 24
Finished Jan 10 01:07:40 PM PST 24
Peak memory 213480 kb
Host smart-3a7ae41b-830f-4b52-a56a-72944cb33bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128154694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.4128154694
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2837198787
Short name T101
Test name
Test status
Simulation time 467935464 ps
CPU time 20.13 seconds
Started Jan 10 12:44:38 PM PST 24
Finished Jan 10 12:46:16 PM PST 24
Peak memory 281176 kb
Host smart-5f14120f-8585-4092-90c5-35034cd4acfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837198787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2837198787
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.4196966526
Short name T875
Test name
Test status
Simulation time 1725961419 ps
CPU time 14.04 seconds
Started Jan 10 01:17:22 PM PST 24
Finished Jan 10 01:18:13 PM PST 24
Peak memory 218100 kb
Host smart-c8e3184e-c353-42f3-849b-529264716db8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196966526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.4196966526
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2665745150
Short name T369
Test name
Test status
Simulation time 1191641794 ps
CPU time 10.83 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:54:27 PM PST 24
Peak memory 218032 kb
Host smart-a0a62c54-dee0-4751-ba05-4e4d97686547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665745150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
665745150
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1634851107
Short name T734
Test name
Test status
Simulation time 316028432 ps
CPU time 10.6 seconds
Started Jan 10 12:39:55 PM PST 24
Finished Jan 10 12:40:44 PM PST 24
Peak memory 218204 kb
Host smart-a598e540-2ffe-4915-b888-92cb6ca57d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634851107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1634851107
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.938804189
Short name T600
Test name
Test status
Simulation time 35510178 ps
CPU time 2.52 seconds
Started Jan 10 12:45:10 PM PST 24
Finished Jan 10 12:46:45 PM PST 24
Peak memory 213740 kb
Host smart-a6964381-667d-4445-9757-470a1c775910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938804189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.938804189
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2681490789
Short name T318
Test name
Test status
Simulation time 1075459051 ps
CPU time 27.9 seconds
Started Jan 10 12:43:55 PM PST 24
Finished Jan 10 12:45:37 PM PST 24
Peak memory 250968 kb
Host smart-e43889ad-551b-4a12-b000-37a17f311dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681490789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2681490789
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3435850821
Short name T507
Test name
Test status
Simulation time 93387252 ps
CPU time 2.94 seconds
Started Jan 10 12:46:13 PM PST 24
Finished Jan 10 12:47:37 PM PST 24
Peak memory 226604 kb
Host smart-e2638ef6-63b9-49be-9476-1ef18e4ef2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435850821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3435850821
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2428678585
Short name T896
Test name
Test status
Simulation time 10784697103 ps
CPU time 69.43 seconds
Started Jan 10 01:23:04 PM PST 24
Finished Jan 10 01:24:31 PM PST 24
Peak memory 284048 kb
Host smart-96ed16c0-f989-46bf-8a8d-e6d3d1ee92d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428678585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2428678585
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.164612587
Short name T496
Test name
Test status
Simulation time 15452692 ps
CPU time 1.15 seconds
Started Jan 10 01:33:58 PM PST 24
Finished Jan 10 01:34:02 PM PST 24
Peak memory 211456 kb
Host smart-acb4eb1b-0749-4076-abf6-0877fecd523c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164612587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.164612587
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1079365920
Short name T682
Test name
Test status
Simulation time 411571817 ps
CPU time 11.99 seconds
Started Jan 10 12:44:37 PM PST 24
Finished Jan 10 12:46:07 PM PST 24
Peak memory 218192 kb
Host smart-d64e4168-a657-4364-a502-d149895ba368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079365920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1079365920
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.927653001
Short name T816
Test name
Test status
Simulation time 4349521274 ps
CPU time 21.42 seconds
Started Jan 10 12:37:35 PM PST 24
Finished Jan 10 12:38:31 PM PST 24
Peak memory 218080 kb
Host smart-f5f7dc9d-d233-44cc-ae07-5f7fd060bfb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927653001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.927653001
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3025529374
Short name T557
Test name
Test status
Simulation time 714628445 ps
CPU time 19.03 seconds
Started Jan 10 12:44:59 PM PST 24
Finished Jan 10 12:46:40 PM PST 24
Peak memory 218172 kb
Host smart-e59dbf87-0206-41e7-97b8-3c821d3978bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025529374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3025529374
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.767127656
Short name T484
Test name
Test status
Simulation time 250441783 ps
CPU time 6.48 seconds
Started Jan 10 12:51:16 PM PST 24
Finished Jan 10 12:52:38 PM PST 24
Peak memory 213112 kb
Host smart-913b571d-2e79-43b3-8f3a-ea94c4c0e3d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767127656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
767127656
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1528522763
Short name T358
Test name
Test status
Simulation time 4972256749 ps
CPU time 66.73 seconds
Started Jan 10 12:48:58 PM PST 24
Finished Jan 10 12:51:35 PM PST 24
Peak memory 267512 kb
Host smart-2826e9e6-dda1-47bf-9a96-c81559944720
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528522763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1528522763
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1495522814
Short name T126
Test name
Test status
Simulation time 2532773331 ps
CPU time 12.86 seconds
Started Jan 10 12:42:19 PM PST 24
Finished Jan 10 12:43:45 PM PST 24
Peak memory 250708 kb
Host smart-981198f3-a40e-4e10-8805-d875689d7ee0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495522814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1495522814
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.385840544
Short name T924
Test name
Test status
Simulation time 99564007 ps
CPU time 4.34 seconds
Started Jan 10 01:09:33 PM PST 24
Finished Jan 10 01:10:41 PM PST 24
Peak memory 218184 kb
Host smart-22c714c5-ab3c-47b6-b566-ea43f19569b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385840544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.385840544
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.616550320
Short name T328
Test name
Test status
Simulation time 375621498 ps
CPU time 8.88 seconds
Started Jan 10 12:34:07 PM PST 24
Finished Jan 10 12:34:47 PM PST 24
Peak memory 217988 kb
Host smart-ab9efa54-5735-4bf2-a6dd-b2d66a923023
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616550320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.616550320
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3957757126
Short name T633
Test name
Test status
Simulation time 223171648 ps
CPU time 9.28 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:57 PM PST 24
Peak memory 218236 kb
Host smart-b3dee815-6866-4ed0-ae8a-215c994d71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957757126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3957757126
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.4247044211
Short name T339
Test name
Test status
Simulation time 349132841 ps
CPU time 2.99 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 221984 kb
Host smart-7649a194-65c3-4609-8cad-ed2a9bf38db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247044211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.4247044211
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.729599231
Short name T764
Test name
Test status
Simulation time 741771839 ps
CPU time 35.36 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:41:26 PM PST 24
Peak memory 251128 kb
Host smart-52f08585-2310-4f45-8a7a-563470175635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729599231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.729599231
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2614438169
Short name T461
Test name
Test status
Simulation time 460851198 ps
CPU time 5.87 seconds
Started Jan 10 12:48:31 PM PST 24
Finished Jan 10 12:49:58 PM PST 24
Peak memory 222808 kb
Host smart-c13750fa-7fc3-4c67-8db0-b29dd112fd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614438169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2614438169
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2235042591
Short name T611
Test name
Test status
Simulation time 4737688098 ps
CPU time 70.79 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:36:07 PM PST 24
Peak memory 251212 kb
Host smart-9603b136-afc7-414b-bcc5-1990663ee118
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235042591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2235042591
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.188902227
Short name T809
Test name
Test status
Simulation time 83568523449 ps
CPU time 262.21 seconds
Started Jan 10 12:45:47 PM PST 24
Finished Jan 10 12:51:29 PM PST 24
Peak memory 422356 kb
Host smart-a9a80d2b-9d2b-45ef-aa4b-c3beb23a113c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=188902227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.188902227
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3577601893
Short name T935
Test name
Test status
Simulation time 15500619 ps
CPU time 0.85 seconds
Started Jan 10 12:50:40 PM PST 24
Finished Jan 10 12:52:06 PM PST 24
Peak memory 208344 kb
Host smart-c1e4084e-f379-45cf-8779-56203f5d0712
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577601893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3577601893
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3001686362
Short name T937
Test name
Test status
Simulation time 73877154 ps
CPU time 0.96 seconds
Started Jan 10 12:34:14 PM PST 24
Finished Jan 10 12:34:46 PM PST 24
Peak memory 208320 kb
Host smart-5b1630ed-2c83-458b-9f01-3e6bbfd7e36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001686362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3001686362
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3361234694
Short name T921
Test name
Test status
Simulation time 369655432 ps
CPU time 15.82 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:08 PM PST 24
Peak memory 218188 kb
Host smart-e6d6ee21-e76c-463c-a1ae-a4f04bda7622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361234694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3361234694
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3460007281
Short name T478
Test name
Test status
Simulation time 1077665843 ps
CPU time 5.45 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:34:48 PM PST 24
Peak memory 209588 kb
Host smart-894217d8-1aff-4059-ad99-84d952e908c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460007281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.3460007281
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1354831055
Short name T447
Test name
Test status
Simulation time 7041792001 ps
CPU time 28.51 seconds
Started Jan 10 12:34:20 PM PST 24
Finished Jan 10 12:35:20 PM PST 24
Peak memory 218048 kb
Host smart-901f6d19-3fa9-4e39-a0e6-3d7088ad8f7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354831055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1354831055
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4191986865
Short name T23
Test name
Test status
Simulation time 287747090 ps
CPU time 8.16 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:19 PM PST 24
Peak memory 218016 kb
Host smart-9e0d80d7-540e-43a4-a5f9-ee7e0e32dcfd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191986865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4191986865
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1890199007
Short name T306
Test name
Test status
Simulation time 1019929571 ps
CPU time 7 seconds
Started Jan 10 12:34:10 PM PST 24
Finished Jan 10 12:34:48 PM PST 24
Peak memory 213560 kb
Host smart-f82fa1b8-3d36-442f-b045-a5472748c808
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890199007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1890199007
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2732387970
Short name T436
Test name
Test status
Simulation time 1114224054 ps
CPU time 35.26 seconds
Started Jan 10 12:34:16 PM PST 24
Finished Jan 10 12:35:22 PM PST 24
Peak memory 250968 kb
Host smart-ec3c0ece-3cae-4ece-96c0-d21f5d1448b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732387970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2732387970
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4069878327
Short name T409
Test name
Test status
Simulation time 772483395 ps
CPU time 24.98 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:28 PM PST 24
Peak memory 250696 kb
Host smart-b1469146-e7c9-4d54-9cfe-eae5f7cc88a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069878327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4069878327
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1878853355
Short name T694
Test name
Test status
Simulation time 56837419 ps
CPU time 2.54 seconds
Started Jan 10 12:34:04 PM PST 24
Finished Jan 10 12:34:37 PM PST 24
Peak memory 218064 kb
Host smart-23ac36e4-29e1-455f-8a48-16f305343edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878853355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1878853355
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3195217703
Short name T555
Test name
Test status
Simulation time 189106988 ps
CPU time 9.2 seconds
Started Jan 10 12:34:17 PM PST 24
Finished Jan 10 12:34:58 PM PST 24
Peak memory 218048 kb
Host smart-e8f122e6-9248-4647-bfa0-76038ecb764d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195217703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3195217703
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3929302085
Short name T932
Test name
Test status
Simulation time 2158675666 ps
CPU time 21.62 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:24 PM PST 24
Peak memory 218028 kb
Host smart-dfc658c2-d75e-4fff-ab66-e97075606ee7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929302085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3929302085
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1758344483
Short name T457
Test name
Test status
Simulation time 602091549 ps
CPU time 8.37 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:00 PM PST 24
Peak memory 217964 kb
Host smart-16f93c0b-8cd7-49a0-b26c-65257f0506e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758344483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1758344483
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2977006594
Short name T75
Test name
Test status
Simulation time 75488718 ps
CPU time 1.56 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:35:00 PM PST 24
Peak memory 213548 kb
Host smart-54e151f0-9991-4821-80cb-21a2d091bbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977006594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2977006594
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1971024686
Short name T559
Test name
Test status
Simulation time 256091197 ps
CPU time 21.63 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:57 PM PST 24
Peak memory 250808 kb
Host smart-c7db2880-36ec-4762-a588-e65cb903abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971024686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1971024686
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3405838613
Short name T620
Test name
Test status
Simulation time 129784098 ps
CPU time 9.02 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:44 PM PST 24
Peak memory 251076 kb
Host smart-3615e815-c5af-46d1-863f-627002da2f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405838613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3405838613
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3687890013
Short name T951
Test name
Test status
Simulation time 1925712181 ps
CPU time 52.44 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:35:52 PM PST 24
Peak memory 250408 kb
Host smart-b4599899-3ce6-4027-8ae9-e9f99a1754e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687890013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3687890013
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2920928693
Short name T727
Test name
Test status
Simulation time 39775529 ps
CPU time 0.77 seconds
Started Jan 10 12:38:04 PM PST 24
Finished Jan 10 12:38:38 PM PST 24
Peak memory 207852 kb
Host smart-ab2d0334-2354-4070-ad7a-2e1d1a80ce70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920928693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2920928693
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2936145813
Short name T487
Test name
Test status
Simulation time 57369193 ps
CPU time 0.97 seconds
Started Jan 10 12:48:26 PM PST 24
Finished Jan 10 12:50:02 PM PST 24
Peak memory 209608 kb
Host smart-a434c684-712c-4567-bd90-44f5e14204df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936145813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2936145813
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1911330481
Short name T670
Test name
Test status
Simulation time 2005957975 ps
CPU time 11.53 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:17 PM PST 24
Peak memory 218048 kb
Host smart-04a996cb-9010-4423-a681-f5ae1a0ac9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911330481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1911330481
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.370126317
Short name T35
Test name
Test status
Simulation time 277853272 ps
CPU time 3.7 seconds
Started Jan 10 12:34:25 PM PST 24
Finished Jan 10 12:35:05 PM PST 24
Peak memory 209740 kb
Host smart-87fc389b-e616-46bf-b306-ca72d41b42d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370126317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_ac
cess.370126317
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.108068893
Short name T473
Test name
Test status
Simulation time 3601583685 ps
CPU time 30.63 seconds
Started Jan 10 12:34:29 PM PST 24
Finished Jan 10 12:35:38 PM PST 24
Peak memory 219076 kb
Host smart-20686645-3cce-4e2e-a443-bf4142102e8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108068893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.108068893
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.711799894
Short name T430
Test name
Test status
Simulation time 1630960772 ps
CPU time 11.7 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:20 PM PST 24
Peak memory 217976 kb
Host smart-49c41bc4-554f-431f-a2ad-e4522fb1061b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711799894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.711799894
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1153697198
Short name T668
Test name
Test status
Simulation time 933631632 ps
CPU time 4.31 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:35:01 PM PST 24
Peak memory 213112 kb
Host smart-9154f57f-4271-437b-b4b5-b05ec5ba5597
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153697198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1153697198
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3661755119
Short name T317
Test name
Test status
Simulation time 1134459475 ps
CPU time 47.15 seconds
Started Jan 10 12:34:29 PM PST 24
Finished Jan 10 12:35:55 PM PST 24
Peak memory 250904 kb
Host smart-5fd30da9-f5b6-471f-b2aa-58807c2ab673
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661755119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3661755119
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2961707810
Short name T918
Test name
Test status
Simulation time 1413398103 ps
CPU time 8.33 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 218024 kb
Host smart-a8bbf268-ea48-40eb-be19-935ad2e068ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961707810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2961707810
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3134274489
Short name T396
Test name
Test status
Simulation time 84812253 ps
CPU time 1.88 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:04 PM PST 24
Peak memory 218024 kb
Host smart-e274ada2-1fb4-49b1-a77b-92a83d473fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134274489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3134274489
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1680624599
Short name T958
Test name
Test status
Simulation time 327073874 ps
CPU time 9.44 seconds
Started Jan 10 12:40:42 PM PST 24
Finished Jan 10 12:41:37 PM PST 24
Peak memory 218008 kb
Host smart-4d16f8be-7265-4149-9e8c-7b89a85fcf77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680624599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1680624599
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1230507247
Short name T878
Test name
Test status
Simulation time 846854243 ps
CPU time 11.51 seconds
Started Jan 10 12:39:32 PM PST 24
Finished Jan 10 12:40:13 PM PST 24
Peak memory 218092 kb
Host smart-07412178-7146-476b-8b51-cc4cbdda17ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230507247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1230507247
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3568847041
Short name T746
Test name
Test status
Simulation time 388569272 ps
CPU time 10.13 seconds
Started Jan 10 12:46:24 PM PST 24
Finished Jan 10 12:48:14 PM PST 24
Peak memory 218060 kb
Host smart-a3f3853a-b091-453d-b9ed-72e3400b0464
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568847041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3568847041
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2192366281
Short name T579
Test name
Test status
Simulation time 872578415 ps
CPU time 8.91 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 218072 kb
Host smart-d08a8e47-bfd4-4d84-8b70-7ff2df3a12b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192366281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2192366281
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1479047286
Short name T971
Test name
Test status
Simulation time 288056439 ps
CPU time 1.25 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 213316 kb
Host smart-75daca8e-2eb6-45ba-977a-e6dffc0cb524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479047286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1479047286
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.223554848
Short name T451
Test name
Test status
Simulation time 462904130 ps
CPU time 19.5 seconds
Started Jan 10 12:34:35 PM PST 24
Finished Jan 10 12:35:34 PM PST 24
Peak memory 251120 kb
Host smart-aa13a3d3-503e-48ee-9a2f-11b37bbbd968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223554848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.223554848
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.920892515
Short name T870
Test name
Test status
Simulation time 116698133 ps
CPU time 3.29 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:34:57 PM PST 24
Peak memory 221828 kb
Host smart-bebbf1f0-acd1-4633-b55d-f439302c4bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920892515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.920892515
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1274955927
Short name T943
Test name
Test status
Simulation time 2831363128 ps
CPU time 54.48 seconds
Started Jan 10 12:46:58 PM PST 24
Finished Jan 10 12:49:10 PM PST 24
Peak memory 251148 kb
Host smart-0ecf8cd4-8659-4aed-a256-fd572eb5a623
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274955927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1274955927
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3829220472
Short name T650
Test name
Test status
Simulation time 21270666 ps
CPU time 0.78 seconds
Started Jan 10 12:34:33 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 207836 kb
Host smart-1a1bbcd5-d33c-4c56-b334-f51c1cda9892
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829220472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3829220472
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2692361659
Short name T76
Test name
Test status
Simulation time 50112516 ps
CPU time 1.27 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:04 PM PST 24
Peak memory 208304 kb
Host smart-6d63be4c-254c-416d-bdbf-cbcaaf1b5f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692361659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2692361659
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1863582380
Short name T889
Test name
Test status
Simulation time 1436201088 ps
CPU time 10.79 seconds
Started Jan 10 01:00:20 PM PST 24
Finished Jan 10 01:02:24 PM PST 24
Peak memory 218192 kb
Host smart-93a41539-46d6-458d-ad6d-11a4eee9f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863582380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1863582380
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3351222017
Short name T36
Test name
Test status
Simulation time 1105743025 ps
CPU time 7.51 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:34 PM PST 24
Peak memory 209588 kb
Host smart-128c4ec8-f35a-4df4-aef6-e554d200a13a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351222017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_a
ccess.3351222017
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2545591637
Short name T718
Test name
Test status
Simulation time 2759628114 ps
CPU time 39.61 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:42 PM PST 24
Peak memory 218024 kb
Host smart-0c4789ab-703d-4779-b95b-65cf884c30ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545591637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2545591637
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3611349317
Short name T194
Test name
Test status
Simulation time 1534099397 ps
CPU time 7.16 seconds
Started Jan 10 12:54:40 PM PST 24
Finished Jan 10 12:55:53 PM PST 24
Peak memory 218096 kb
Host smart-707b5379-0afa-4e20-a441-6005eead6067
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611349317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3611349317
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2655476724
Short name T74
Test name
Test status
Simulation time 638915715 ps
CPU time 5.21 seconds
Started Jan 10 12:34:07 PM PST 24
Finished Jan 10 12:34:42 PM PST 24
Peak memory 213284 kb
Host smart-025142fe-42c0-4df5-bc25-4a520b0d3623
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655476724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2655476724
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2754644497
Short name T443
Test name
Test status
Simulation time 1040225108 ps
CPU time 28.48 seconds
Started Jan 10 12:39:43 PM PST 24
Finished Jan 10 12:40:42 PM PST 24
Peak memory 251096 kb
Host smart-ddfdf489-34d6-4db5-94ae-775eeb2c9044
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754644497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2754644497
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1360838852
Short name T316
Test name
Test status
Simulation time 3380139287 ps
CPU time 27.91 seconds
Started Jan 10 12:39:28 PM PST 24
Finished Jan 10 12:40:27 PM PST 24
Peak memory 251132 kb
Host smart-821bd025-a616-4763-8c86-5c387ae85b50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360838852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1360838852
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2958954047
Short name T534
Test name
Test status
Simulation time 29895285 ps
CPU time 2.23 seconds
Started Jan 10 01:33:02 PM PST 24
Finished Jan 10 01:33:07 PM PST 24
Peak memory 218208 kb
Host smart-7a4429c9-53aa-4bd0-ab24-f8829b747f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958954047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2958954047
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1866075997
Short name T680
Test name
Test status
Simulation time 1572655113 ps
CPU time 16.71 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:09 PM PST 24
Peak memory 219208 kb
Host smart-121d784a-5d6b-4cf9-bdc7-55cda8774b02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866075997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1866075997
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1653629644
Short name T927
Test name
Test status
Simulation time 2256984012 ps
CPU time 10.84 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:35:08 PM PST 24
Peak memory 218160 kb
Host smart-a7f4a53e-bf03-40cc-980a-2578a6535b51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653629644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1653629644
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.662040555
Short name T414
Test name
Test status
Simulation time 313761296 ps
CPU time 7.38 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:03 PM PST 24
Peak memory 218096 kb
Host smart-36b60db0-ce11-4dec-8ced-380c4a64099b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662040555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.662040555
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1245673647
Short name T722
Test name
Test status
Simulation time 107468612 ps
CPU time 2.06 seconds
Started Jan 10 12:48:18 PM PST 24
Finished Jan 10 12:49:45 PM PST 24
Peak memory 213472 kb
Host smart-e245ada8-53b1-4ad2-be44-ac2e654cf880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245673647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1245673647
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3204752412
Short name T959
Test name
Test status
Simulation time 321264221 ps
CPU time 18.66 seconds
Started Jan 10 12:45:47 PM PST 24
Finished Jan 10 12:47:27 PM PST 24
Peak memory 250988 kb
Host smart-6fb3dbe7-2f34-4805-aacd-93b7f16627d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204752412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3204752412
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2903451468
Short name T700
Test name
Test status
Simulation time 218896603 ps
CPU time 7.97 seconds
Started Jan 10 12:39:29 PM PST 24
Finished Jan 10 12:40:07 PM PST 24
Peak memory 251088 kb
Host smart-a3848d6d-2937-4548-b64b-d6fc9e6ccf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903451468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2903451468
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.610569343
Short name T812
Test name
Test status
Simulation time 51082198390 ps
CPU time 273.41 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:39:17 PM PST 24
Peak memory 267776 kb
Host smart-e0fcd17c-6c53-40d9-bcd3-41860b1e44a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=610569343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.610569343
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3560855740
Short name T49
Test name
Test status
Simulation time 16401090 ps
CPU time 0.83 seconds
Started Jan 10 12:58:04 PM PST 24
Finished Jan 10 12:59:25 PM PST 24
Peak memory 208264 kb
Host smart-1984463b-d299-472c-8549-a910d1cccbd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560855740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3560855740
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3749645061
Short name T341
Test name
Test status
Simulation time 17110664 ps
CPU time 1.07 seconds
Started Jan 10 12:34:09 PM PST 24
Finished Jan 10 12:34:40 PM PST 24
Peak memory 209660 kb
Host smart-b60cc69e-f527-46a4-9b96-e49949acf04f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749645061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3749645061
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3276608773
Short name T828
Test name
Test status
Simulation time 479622520 ps
CPU time 12.06 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:15 PM PST 24
Peak memory 218032 kb
Host smart-ec880250-657b-4ea0-904d-33274879c069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276608773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3276608773
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.640038338
Short name T642
Test name
Test status
Simulation time 357724501 ps
CPU time 7.78 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 209560 kb
Host smart-f63fc922-191e-4471-b930-b209d3ce1c46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640038338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_ac
cess.640038338
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.4217315050
Short name T825
Test name
Test status
Simulation time 5838402573 ps
CPU time 40.19 seconds
Started Jan 10 12:34:38 PM PST 24
Finished Jan 10 12:35:59 PM PST 24
Peak memory 219520 kb
Host smart-142f3b6f-d0aa-4367-b845-ba265e81d9ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217315050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.4217315050
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1193286555
Short name T902
Test name
Test status
Simulation time 532312669 ps
CPU time 4.72 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:07 PM PST 24
Peak memory 217964 kb
Host smart-b50711af-d78c-4795-b293-158583df75a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193286555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1193286555
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3258908692
Short name T931
Test name
Test status
Simulation time 335695183 ps
CPU time 8.99 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:35:08 PM PST 24
Peak memory 213512 kb
Host smart-834b0c9a-1aa3-4215-8271-aeb06f5b6220
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258908692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3258908692
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2770987020
Short name T18
Test name
Test status
Simulation time 1015739733 ps
CPU time 45.83 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:35:43 PM PST 24
Peak memory 251008 kb
Host smart-a240b18a-a3a0-45e7-9cb5-7b3a43e15ff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770987020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2770987020
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4254158387
Short name T606
Test name
Test status
Simulation time 1705525513 ps
CPU time 12.11 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:24 PM PST 24
Peak memory 247308 kb
Host smart-8755fa1d-3566-4d90-a865-4477f11b7082
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254158387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4254158387
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2071925533
Short name T908
Test name
Test status
Simulation time 85637751 ps
CPU time 3.76 seconds
Started Jan 10 12:34:17 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 218068 kb
Host smart-3d081dcb-2548-4778-b45f-99e9b2f7cb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071925533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2071925533
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1635414665
Short name T303
Test name
Test status
Simulation time 1156869734 ps
CPU time 8.24 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:18 PM PST 24
Peak memory 218060 kb
Host smart-a0a84b56-ae5a-4680-91cf-3b1f9559bda4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635414665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1635414665
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.854036081
Short name T686
Test name
Test status
Simulation time 582039105 ps
CPU time 13.92 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:17 PM PST 24
Peak memory 217960 kb
Host smart-93951b86-9d77-4414-a310-6709d424d7ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854036081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.854036081
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3531874405
Short name T493
Test name
Test status
Simulation time 1122412377 ps
CPU time 8.05 seconds
Started Jan 10 12:34:33 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 218028 kb
Host smart-1846d0b9-1fb1-4e18-b48e-49d699e9a065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531874405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3531874405
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2499831564
Short name T27
Test name
Test status
Simulation time 740085418 ps
CPU time 13.57 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:35:11 PM PST 24
Peak memory 218024 kb
Host smart-b636c536-16b9-43d0-90d9-0f99be87b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499831564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2499831564
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1529741870
Short name T593
Test name
Test status
Simulation time 71080327 ps
CPU time 1.57 seconds
Started Jan 10 12:34:20 PM PST 24
Finished Jan 10 12:34:54 PM PST 24
Peak memory 213424 kb
Host smart-726b7407-e5ea-4c33-b5e7-c788c5334e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529741870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1529741870
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.436551524
Short name T772
Test name
Test status
Simulation time 1888014793 ps
CPU time 24.75 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:37 PM PST 24
Peak memory 250820 kb
Host smart-51a442aa-9b17-4c8f-9c23-e4879f9cce1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436551524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.436551524
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1260575444
Short name T743
Test name
Test status
Simulation time 79194320 ps
CPU time 3.11 seconds
Started Jan 10 12:34:17 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 218076 kb
Host smart-0766142d-83a7-44eb-bd7b-aca93bd17e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260575444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1260575444
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2595573636
Short name T466
Test name
Test status
Simulation time 1576179129 ps
CPU time 57.72 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:53 PM PST 24
Peak memory 268288 kb
Host smart-a446b58c-dbfa-4aa4-85f7-635364e1993c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595573636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2595573636
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.232529717
Short name T883
Test name
Test status
Simulation time 60881358 ps
CPU time 0.88 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 208272 kb
Host smart-fc8ec448-5987-406f-94a1-35dc6f26fbf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232529717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.232529717
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2307692082
Short name T592
Test name
Test status
Simulation time 538662976 ps
CPU time 14 seconds
Started Jan 10 12:34:14 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 218076 kb
Host smart-c90ab695-958b-469a-bbc1-64617249b7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307692082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2307692082
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2154558962
Short name T845
Test name
Test status
Simulation time 1899050011 ps
CPU time 11.98 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:08 PM PST 24
Peak memory 209452 kb
Host smart-a6a7807e-fdd3-4520-b816-74bc5d91e7bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154558962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.2154558962
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1580299807
Short name T617
Test name
Test status
Simulation time 1776264829 ps
CPU time 27.59 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:35:24 PM PST 24
Peak memory 217960 kb
Host smart-55564e7a-48cd-4ab0-ae9c-529f0445287b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580299807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1580299807
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2508128683
Short name T314
Test name
Test status
Simulation time 447029028 ps
CPU time 7.1 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:19 PM PST 24
Peak memory 218000 kb
Host smart-56b53bc6-8bcb-40d1-af40-7e431e5800a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508128683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2508128683
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.4266918047
Short name T340
Test name
Test status
Simulation time 82703512 ps
CPU time 1.69 seconds
Started Jan 10 12:34:16 PM PST 24
Finished Jan 10 12:34:49 PM PST 24
Peak memory 212356 kb
Host smart-53d6542d-8009-4b12-9b24-d4fd660cc26b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266918047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.4266918047
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2644037282
Short name T850
Test name
Test status
Simulation time 1585473994 ps
CPU time 56.22 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:35:43 PM PST 24
Peak memory 252556 kb
Host smart-d934ec05-0676-43ae-825c-1b35b712a765
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644037282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2644037282
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.170759702
Short name T941
Test name
Test status
Simulation time 475144439 ps
CPU time 14.15 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:35:08 PM PST 24
Peak memory 222720 kb
Host smart-261fafd3-2fb7-4d1e-8bd3-cf61a206ed12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170759702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.170759702
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.9946248
Short name T394
Test name
Test status
Simulation time 112430407 ps
CPU time 2.28 seconds
Started Jan 10 12:34:14 PM PST 24
Finished Jan 10 12:34:47 PM PST 24
Peak memory 218036 kb
Host smart-bc80e1da-29e8-464d-9646-542bf8df5056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9946248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.9946248
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3684284203
Short name T897
Test name
Test status
Simulation time 1097247478 ps
CPU time 9.81 seconds
Started Jan 10 12:34:17 PM PST 24
Finished Jan 10 12:35:00 PM PST 24
Peak memory 218072 kb
Host smart-f290c874-0253-4bb7-af1b-1fa07d0e9b84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684284203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3684284203
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3075646006
Short name T720
Test name
Test status
Simulation time 8009673191 ps
CPU time 19.86 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 218140 kb
Host smart-fc987502-43f8-4af4-84fe-ed8723981fc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075646006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3075646006
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.791298831
Short name T454
Test name
Test status
Simulation time 311649160 ps
CPU time 11.37 seconds
Started Jan 10 12:34:25 PM PST 24
Finished Jan 10 12:35:12 PM PST 24
Peak memory 218012 kb
Host smart-e9485e69-b790-4a22-b2fb-0b6d3c5f65e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791298831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.791298831
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3330027317
Short name T960
Test name
Test status
Simulation time 500409634 ps
CPU time 9.42 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:34:56 PM PST 24
Peak memory 218080 kb
Host smart-b08744dd-a64f-41ab-ae74-1aa5211a7cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330027317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3330027317
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3457641565
Short name T490
Test name
Test status
Simulation time 133139273 ps
CPU time 4.26 seconds
Started Jan 10 12:34:11 PM PST 24
Finished Jan 10 12:34:46 PM PST 24
Peak memory 213472 kb
Host smart-3f9eba5a-718e-4fe3-b571-812f50483458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457641565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3457641565
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3987725327
Short name T672
Test name
Test status
Simulation time 248709123 ps
CPU time 24.43 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:28 PM PST 24
Peak memory 251096 kb
Host smart-b8d08e4b-516e-4a7f-876e-e26538606d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987725327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3987725327
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2543962982
Short name T859
Test name
Test status
Simulation time 99854450 ps
CPU time 7.13 seconds
Started Jan 10 12:34:11 PM PST 24
Finished Jan 10 12:34:49 PM PST 24
Peak memory 246980 kb
Host smart-5911aa07-1bd3-4bfe-9515-61f307d252da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543962982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2543962982
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.826295371
Short name T368
Test name
Test status
Simulation time 9139574931 ps
CPU time 72.39 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:36:23 PM PST 24
Peak memory 251032 kb
Host smart-ac6658f9-dead-4ac4-8272-ecd0a2bb03bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826295371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.826295371
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1882678119
Short name T640
Test name
Test status
Simulation time 70548944 ps
CPU time 0.73 seconds
Started Jan 10 12:34:13 PM PST 24
Finished Jan 10 12:34:45 PM PST 24
Peak memory 208044 kb
Host smart-57caa5b3-8817-48de-afcb-228d0bf08c0f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882678119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1882678119
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.815233202
Short name T73
Test name
Test status
Simulation time 47590575 ps
CPU time 0.8 seconds
Started Jan 10 12:46:15 PM PST 24
Finished Jan 10 12:47:33 PM PST 24
Peak memory 209556 kb
Host smart-1bc083f3-cc28-426e-8d77-abc0be2df3bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815233202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.815233202
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2174857139
Short name T347
Test name
Test status
Simulation time 326308958 ps
CPU time 8.23 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:12 PM PST 24
Peak memory 218140 kb
Host smart-c6f5246c-52d0-4418-8d9d-ac644733ec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174857139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2174857139
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.709626207
Short name T844
Test name
Test status
Simulation time 391735140 ps
CPU time 6.29 seconds
Started Jan 10 12:34:35 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 209652 kb
Host smart-7efd3e4a-2693-4a1f-9aa7-c6c24ef28c6b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709626207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_ac
cess.709626207
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3739147012
Short name T912
Test name
Test status
Simulation time 7533878753 ps
CPU time 53.84 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:36:07 PM PST 24
Peak memory 218404 kb
Host smart-2b2889cb-1178-4467-9a1b-0b15a71bfc32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739147012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3739147012
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3457349445
Short name T942
Test name
Test status
Simulation time 646782493 ps
CPU time 3.42 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 217988 kb
Host smart-6cedc431-4056-4f77-ae60-d2e07a3adcb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457349445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3457349445
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2859408186
Short name T923
Test name
Test status
Simulation time 1828232151 ps
CPU time 4.97 seconds
Started Jan 10 12:34:25 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 212872 kb
Host smart-8012ba40-68c3-4174-a1f4-9e11cae89db2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859408186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2859408186
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3834758597
Short name T868
Test name
Test status
Simulation time 7326925949 ps
CPU time 61.63 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:36:06 PM PST 24
Peak memory 276132 kb
Host smart-e716b997-4bcf-4d4f-a252-1730084b66d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834758597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3834758597
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3730491472
Short name T20
Test name
Test status
Simulation time 4881411486 ps
CPU time 8.33 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 223356 kb
Host smart-72d89d0f-1e50-4914-b788-a3182735ba32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730491472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3730491472
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3169575756
Short name T742
Test name
Test status
Simulation time 25118731 ps
CPU time 1.56 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:07 PM PST 24
Peak memory 218052 kb
Host smart-d1f6700d-eec6-4a10-8923-84d598485035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169575756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3169575756
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2039298823
Short name T628
Test name
Test status
Simulation time 766840506 ps
CPU time 10.48 seconds
Started Jan 10 01:02:04 PM PST 24
Finished Jan 10 01:03:51 PM PST 24
Peak memory 218204 kb
Host smart-6e945403-2c77-448f-be53-e8fc5a6feb15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039298823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2039298823
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1827777117
Short name T453
Test name
Test status
Simulation time 1411810607 ps
CPU time 13.2 seconds
Started Jan 10 12:40:24 PM PST 24
Finished Jan 10 12:41:24 PM PST 24
Peak memory 217976 kb
Host smart-575bad47-6afd-4775-97b4-76de25cd72a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827777117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1827777117
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2471390047
Short name T615
Test name
Test status
Simulation time 1103005117 ps
CPU time 10.11 seconds
Started Jan 10 12:41:13 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 218008 kb
Host smart-6ef1ef62-35b8-483f-a1e3-6883067e5c7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471390047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2471390047
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1207503465
Short name T683
Test name
Test status
Simulation time 316372861 ps
CPU time 7.74 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:18 PM PST 24
Peak memory 218032 kb
Host smart-2035a529-f157-426d-98f9-38c2cc02e826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207503465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1207503465
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1485391515
Short name T82
Test name
Test status
Simulation time 58101375 ps
CPU time 1.42 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 213424 kb
Host smart-e01a229c-1dbe-4b5f-ac0d-8ff5500e9ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485391515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1485391515
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2051007774
Short name T526
Test name
Test status
Simulation time 367033143 ps
CPU time 33.21 seconds
Started Jan 10 12:34:32 PM PST 24
Finished Jan 10 12:35:46 PM PST 24
Peak memory 250984 kb
Host smart-f69f9196-f8f8-4b49-a36e-a355b308e103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051007774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2051007774
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2494145656
Short name T528
Test name
Test status
Simulation time 710351699 ps
CPU time 5.01 seconds
Started Jan 10 12:34:25 PM PST 24
Finished Jan 10 12:35:05 PM PST 24
Peak memory 221880 kb
Host smart-aca2b728-60d6-462c-9166-947e3d41bd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494145656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2494145656
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.683540894
Short name T920
Test name
Test status
Simulation time 2425617358 ps
CPU time 92.73 seconds
Started Jan 10 12:42:19 PM PST 24
Finished Jan 10 12:45:05 PM PST 24
Peak memory 226316 kb
Host smart-fc36ab32-f88e-4eb2-8f37-72a25d636655
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683540894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.683540894
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1097560931
Short name T578
Test name
Test status
Simulation time 10394841 ps
CPU time 0.74 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:10 PM PST 24
Peak memory 207860 kb
Host smart-00e72762-e8fb-4af4-93c0-ba8963fd3b14
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097560931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1097560931
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3205805450
Short name T599
Test name
Test status
Simulation time 80533175 ps
CPU time 0.91 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:11 PM PST 24
Peak memory 209576 kb
Host smart-77e0e6bf-1b12-44de-a50f-594019028043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205805450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3205805450
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3271622086
Short name T696
Test name
Test status
Simulation time 227485974 ps
CPU time 7.22 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 218188 kb
Host smart-428f28b1-6342-40d8-acb7-7ad3a6aeec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271622086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3271622086
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1872158697
Short name T938
Test name
Test status
Simulation time 1563845950 ps
CPU time 10.02 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:05 PM PST 24
Peak memory 209624 kb
Host smart-2571e10e-072e-4dd9-8523-437c9df89165
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872158697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.1872158697
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1417482890
Short name T724
Test name
Test status
Simulation time 4391093026 ps
CPU time 35.24 seconds
Started Jan 10 12:34:10 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 219104 kb
Host smart-be18a819-e564-431a-baa2-40dffc4c957b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417482890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1417482890
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3111216324
Short name T648
Test name
Test status
Simulation time 363367098 ps
CPU time 5.55 seconds
Started Jan 10 12:34:03 PM PST 24
Finished Jan 10 12:34:37 PM PST 24
Peak memory 218336 kb
Host smart-e591650c-58aa-42a1-b255-d0a9004837fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111216324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3111216324
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2859254783
Short name T769
Test name
Test status
Simulation time 133488963 ps
CPU time 2.74 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:34:57 PM PST 24
Peak memory 213100 kb
Host smart-f67dc58d-54f5-472e-b004-26d2f3380b15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859254783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2859254783
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2808693937
Short name T948
Test name
Test status
Simulation time 4278887676 ps
CPU time 32.94 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:35:30 PM PST 24
Peak memory 252036 kb
Host smart-f8316672-28e4-45a6-b92e-00cb75c62e36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808693937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2808693937
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.146822215
Short name T831
Test name
Test status
Simulation time 3025481738 ps
CPU time 14.86 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:10 PM PST 24
Peak memory 247100 kb
Host smart-2e15b3e9-0141-49af-bebb-2da75e248134
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146822215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.146822215
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3628934656
Short name T733
Test name
Test status
Simulation time 329493340 ps
CPU time 2.06 seconds
Started Jan 10 12:40:50 PM PST 24
Finished Jan 10 12:41:41 PM PST 24
Peak memory 218152 kb
Host smart-b6923d2c-a6ca-4298-8c8a-1cb7c7c9b649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628934656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3628934656
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3096122919
Short name T884
Test name
Test status
Simulation time 305720164 ps
CPU time 10.35 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:05 PM PST 24
Peak memory 218152 kb
Host smart-ff76a3b4-42a8-4867-9e55-9f66a8515b65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096122919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3096122919
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2969832372
Short name T313
Test name
Test status
Simulation time 1223646961 ps
CPU time 11.91 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:34:57 PM PST 24
Peak memory 218020 kb
Host smart-44412d3d-1a1c-4291-acff-0be58caf336b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969832372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2969832372
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2875732644
Short name T954
Test name
Test status
Simulation time 4095986853 ps
CPU time 8.27 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:00 PM PST 24
Peak memory 218104 kb
Host smart-155def21-f7de-4eca-ab32-6862239cfd1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875732644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2875732644
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1002891837
Short name T625
Test name
Test status
Simulation time 1980915725 ps
CPU time 11.6 seconds
Started Jan 10 12:34:01 PM PST 24
Finished Jan 10 12:34:46 PM PST 24
Peak memory 218152 kb
Host smart-5478aa97-de7e-47a0-b93e-6aac9eecd437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002891837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1002891837
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3807818914
Short name T843
Test name
Test status
Simulation time 57135742 ps
CPU time 2.31 seconds
Started Jan 10 12:44:35 PM PST 24
Finished Jan 10 12:45:54 PM PST 24
Peak memory 213720 kb
Host smart-ebec72b3-7f88-4a15-b41b-371b0e3df06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807818914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3807818914
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1514074875
Short name T475
Test name
Test status
Simulation time 330731972 ps
CPU time 31.44 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:41:07 PM PST 24
Peak memory 251024 kb
Host smart-da196ed1-b8ad-4464-9be8-c98e2da747b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514074875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1514074875
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.183032052
Short name T762
Test name
Test status
Simulation time 217683967 ps
CPU time 7.61 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:57 PM PST 24
Peak memory 250996 kb
Host smart-1e4c6c1e-5a20-43a8-87a0-06baa397f4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183032052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.183032052
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.4126693637
Short name T879
Test name
Test status
Simulation time 6262143395 ps
CPU time 116.89 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:36:54 PM PST 24
Peak memory 241364 kb
Host smart-173c5126-e2b1-41c3-81c0-9bdca7ec173a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126693637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.4126693637
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.719776659
Short name T86
Test name
Test status
Simulation time 36460470 ps
CPU time 0.94 seconds
Started Jan 10 12:46:59 PM PST 24
Finished Jan 10 12:48:18 PM PST 24
Peak memory 211280 kb
Host smart-56c3c593-1dec-4b4c-924f-9a4c312538d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719776659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.719776659
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.710704843
Short name T41
Test name
Test status
Simulation time 59975068 ps
CPU time 0.87 seconds
Started Jan 10 12:39:00 PM PST 24
Finished Jan 10 12:39:33 PM PST 24
Peak memory 209608 kb
Host smart-484bae85-049f-45f7-98e8-7ced0f15dc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710704843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.710704843
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3660897098
Short name T659
Test name
Test status
Simulation time 4884110205 ps
CPU time 14.02 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:17 PM PST 24
Peak memory 218164 kb
Host smart-f1f98548-b9ec-4d8f-8d23-6d49ad3bdc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660897098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3660897098
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2628421046
Short name T756
Test name
Test status
Simulation time 585057188 ps
CPU time 6.87 seconds
Started Jan 10 01:10:25 PM PST 24
Finished Jan 10 01:11:49 PM PST 24
Peak memory 209552 kb
Host smart-f4bc31f8-f78d-44ff-89b6-f4ef74577cfc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628421046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.2628421046
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3672617024
Short name T425
Test name
Test status
Simulation time 14993889130 ps
CPU time 34.39 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:49 PM PST 24
Peak memory 218532 kb
Host smart-479a71a2-93e7-4e43-b552-a446add1087c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672617024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3672617024
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4021261895
Short name T350
Test name
Test status
Simulation time 385079003 ps
CPU time 4.18 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:09 PM PST 24
Peak memory 218108 kb
Host smart-ec7f81e4-c09e-4eec-b416-503a838877a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021261895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.4021261895
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.415722199
Short name T128
Test name
Test status
Simulation time 682853246 ps
CPU time 7.85 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 213572 kb
Host smart-28b4f3b6-cf47-434f-bfb2-89dd7d12faf4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415722199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
415722199
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.860064584
Short name T719
Test name
Test status
Simulation time 4570143408 ps
CPU time 49.57 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:54 PM PST 24
Peak memory 268144 kb
Host smart-f901a921-27a4-429f-bc59-64858d972ba5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860064584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.860064584
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.816789426
Short name T712
Test name
Test status
Simulation time 1689976478 ps
CPU time 10.92 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:22 PM PST 24
Peak memory 249864 kb
Host smart-13a344fe-eca9-4997-91d3-956405e59a77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816789426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.816789426
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.537980177
Short name T739
Test name
Test status
Simulation time 19441002 ps
CPU time 1.58 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 218076 kb
Host smart-7d363fd5-248a-4e8b-aa7f-6ed9eb82a23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537980177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.537980177
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.250495382
Short name T710
Test name
Test status
Simulation time 722999143 ps
CPU time 8.65 seconds
Started Jan 10 12:52:40 PM PST 24
Finished Jan 10 12:54:00 PM PST 24
Peak memory 218396 kb
Host smart-dbbe08f5-a494-4744-8222-3cad8456de73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250495382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.250495382
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.855602136
Short name T613
Test name
Test status
Simulation time 1958875560 ps
CPU time 12.03 seconds
Started Jan 10 01:01:37 PM PST 24
Finished Jan 10 01:03:24 PM PST 24
Peak memory 218192 kb
Host smart-36a1eb1a-1822-4ad8-9e6b-3971e3e22144
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855602136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.855602136
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2068730003
Short name T429
Test name
Test status
Simulation time 2054056256 ps
CPU time 10.04 seconds
Started Jan 10 12:57:17 PM PST 24
Finished Jan 10 12:58:40 PM PST 24
Peak memory 218028 kb
Host smart-db79436a-c878-4ee6-9416-bf3b1cee92a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068730003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2068730003
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.4077341446
Short name T688
Test name
Test status
Simulation time 411186082 ps
CPU time 10.18 seconds
Started Jan 10 12:34:32 PM PST 24
Finished Jan 10 12:35:23 PM PST 24
Peak memory 218088 kb
Host smart-7aec3ae1-db78-4db7-b919-03a5d145f27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077341446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.4077341446
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3752974920
Short name T735
Test name
Test status
Simulation time 239563815 ps
CPU time 3.45 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:35:03 PM PST 24
Peak memory 213472 kb
Host smart-3111cf6d-3d78-4f7b-82a2-c6eb1177b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752974920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3752974920
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.438418113
Short name T333
Test name
Test status
Simulation time 1060090580 ps
CPU time 27.91 seconds
Started Jan 10 12:34:20 PM PST 24
Finished Jan 10 12:35:20 PM PST 24
Peak memory 250020 kb
Host smart-9cbe1be7-b37b-46d6-9209-a8a2bd285499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438418113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.438418113
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.482813697
Short name T323
Test name
Test status
Simulation time 209239339 ps
CPU time 4.66 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:15 PM PST 24
Peak memory 222312 kb
Host smart-fb98d5e6-2f72-430c-b308-f5c1036d302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482813697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.482813697
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.621196831
Short name T661
Test name
Test status
Simulation time 4872403901 ps
CPU time 91.99 seconds
Started Jan 10 01:23:54 PM PST 24
Finished Jan 10 01:25:34 PM PST 24
Peak memory 274416 kb
Host smart-2997972e-c147-4ed7-bf65-95b3363bb882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621196831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.621196831
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.534886279
Short name T610
Test name
Test status
Simulation time 20495051 ps
CPU time 0.77 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 207996 kb
Host smart-f3d96ba8-cc36-40a6-ab5c-4f650d562768
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534886279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.534886279
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3749591913
Short name T329
Test name
Test status
Simulation time 68946776 ps
CPU time 1.07 seconds
Started Jan 10 12:40:31 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 209568 kb
Host smart-35d681cb-243e-4da0-9223-0ed6c40ed04a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749591913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3749591913
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1764304313
Short name T851
Test name
Test status
Simulation time 1462683153 ps
CPU time 13.82 seconds
Started Jan 10 12:47:47 PM PST 24
Finished Jan 10 12:49:29 PM PST 24
Peak memory 218072 kb
Host smart-d55783e8-3070-47e0-a958-3b96b09d96b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764304313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1764304313
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1240790925
Short name T508
Test name
Test status
Simulation time 339872021 ps
CPU time 4.65 seconds
Started Jan 10 01:01:18 PM PST 24
Finished Jan 10 01:02:53 PM PST 24
Peak memory 209704 kb
Host smart-bba11669-dc7d-4238-b865-23930a9438e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240790925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.1240790925
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1100664733
Short name T737
Test name
Test status
Simulation time 2157758555 ps
CPU time 17.22 seconds
Started Jan 10 12:37:44 PM PST 24
Finished Jan 10 12:38:36 PM PST 24
Peak memory 218160 kb
Host smart-a1eb26a9-f7fd-4038-97fd-31e79c11d3cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100664733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1100664733
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4014341407
Short name T440
Test name
Test status
Simulation time 568678101 ps
CPU time 14.85 seconds
Started Jan 10 12:50:02 PM PST 24
Finished Jan 10 12:52:13 PM PST 24
Peak memory 217992 kb
Host smart-79af10ce-8f18-4358-8bc7-867762ec9aff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014341407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4014341407
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2821661656
Short name T567
Test name
Test status
Simulation time 383440769 ps
CPU time 4.92 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:15 PM PST 24
Peak memory 213024 kb
Host smart-a1aefc69-355b-4477-a85c-f8a0d82c5d9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821661656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2821661656
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.195380605
Short name T895
Test name
Test status
Simulation time 1623393492 ps
CPU time 24.02 seconds
Started Jan 10 12:39:33 PM PST 24
Finished Jan 10 12:40:26 PM PST 24
Peak memory 251076 kb
Host smart-ac2a3619-4404-4416-b776-30661838814d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195380605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.195380605
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3480901116
Short name T406
Test name
Test status
Simulation time 1873387777 ps
CPU time 10.43 seconds
Started Jan 10 01:23:45 PM PST 24
Finished Jan 10 01:24:05 PM PST 24
Peak memory 250104 kb
Host smart-e87a5d13-1121-456d-80d5-70ec4d00ae0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480901116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3480901116
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2630721232
Short name T361
Test name
Test status
Simulation time 209899248 ps
CPU time 2.55 seconds
Started Jan 10 12:45:01 PM PST 24
Finished Jan 10 12:46:26 PM PST 24
Peak memory 218200 kb
Host smart-3276da4f-ac8a-409d-a8b9-9f314329f4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630721232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2630721232
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.4011677158
Short name T359
Test name
Test status
Simulation time 1369539408 ps
CPU time 15.7 seconds
Started Jan 10 01:08:12 PM PST 24
Finished Jan 10 01:09:56 PM PST 24
Peak memory 219236 kb
Host smart-bb2b9cfc-edf1-424c-9eef-2050cf53fea3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011677158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4011677158
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.366071895
Short name T626
Test name
Test status
Simulation time 674957441 ps
CPU time 8.93 seconds
Started Jan 10 12:43:10 PM PST 24
Finished Jan 10 12:44:39 PM PST 24
Peak memory 218008 kb
Host smart-27395fb7-8d11-4014-864e-2a7fa7c83590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366071895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.366071895
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2989579634
Short name T412
Test name
Test status
Simulation time 251458881 ps
CPU time 9.99 seconds
Started Jan 10 12:45:01 PM PST 24
Finished Jan 10 12:46:33 PM PST 24
Peak memory 218008 kb
Host smart-e9588fdf-edf5-459a-a386-1cd07da88c8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989579634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2989579634
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.4200767019
Short name T800
Test name
Test status
Simulation time 206539367 ps
CPU time 8.45 seconds
Started Jan 10 12:44:05 PM PST 24
Finished Jan 10 12:45:28 PM PST 24
Peak memory 218124 kb
Host smart-12305931-03ba-4fd3-b88f-2d7691e70a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200767019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.4200767019
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.4087719899
Short name T38
Test name
Test status
Simulation time 311750809 ps
CPU time 2.06 seconds
Started Jan 10 12:43:17 PM PST 24
Finished Jan 10 12:44:33 PM PST 24
Peak memory 213928 kb
Host smart-1ee41f08-b8f9-455b-8e80-c9eccbad5190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087719899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.4087719899
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.75780377
Short name T536
Test name
Test status
Simulation time 581344953 ps
CPU time 25.25 seconds
Started Jan 10 12:50:10 PM PST 24
Finished Jan 10 12:51:58 PM PST 24
Peak memory 251116 kb
Host smart-6a4caa87-6481-41c6-bc62-95c1db576eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75780377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.75780377
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2180464469
Short name T371
Test name
Test status
Simulation time 88091516 ps
CPU time 7.23 seconds
Started Jan 10 12:39:43 PM PST 24
Finished Jan 10 12:40:20 PM PST 24
Peak memory 246508 kb
Host smart-45081894-72e3-450c-94d5-ae7d3c00a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180464469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2180464469
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.876832918
Short name T801
Test name
Test status
Simulation time 14214948 ps
CPU time 0.77 seconds
Started Jan 10 12:38:41 PM PST 24
Finished Jan 10 12:39:14 PM PST 24
Peak memory 207956 kb
Host smart-8ed351ae-e2c2-4326-945c-af247c140968
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876832918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.876832918
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3438662643
Short name T102
Test name
Test status
Simulation time 51900859 ps
CPU time 1.08 seconds
Started Jan 10 12:42:12 PM PST 24
Finished Jan 10 12:43:26 PM PST 24
Peak memory 209656 kb
Host smart-f4e2b257-617c-4552-bbd4-d934bb73d72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438662643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3438662643
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.46946610
Short name T603
Test name
Test status
Simulation time 17287402 ps
CPU time 0.76 seconds
Started Jan 10 12:42:37 PM PST 24
Finished Jan 10 12:43:55 PM PST 24
Peak memory 209384 kb
Host smart-a9c01780-f967-43e9-b44c-d9c0e420026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46946610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.46946610
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2410724175
Short name T506
Test name
Test status
Simulation time 2208523395 ps
CPU time 14.24 seconds
Started Jan 10 12:47:28 PM PST 24
Finished Jan 10 12:49:05 PM PST 24
Peak memory 218168 kb
Host smart-dcd68f0f-9183-40db-b983-e18c61098106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410724175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2410724175
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2992667116
Short name T532
Test name
Test status
Simulation time 1326239823 ps
CPU time 4.14 seconds
Started Jan 10 12:50:10 PM PST 24
Finished Jan 10 12:51:37 PM PST 24
Peak memory 209656 kb
Host smart-9f1498ee-3c3e-4285-a4e7-805ef270b065
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992667116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ac
cess.2992667116
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3507530090
Short name T926
Test name
Test status
Simulation time 3499298527 ps
CPU time 42.84 seconds
Started Jan 10 12:54:17 PM PST 24
Finished Jan 10 12:56:05 PM PST 24
Peak memory 219080 kb
Host smart-73841d1e-e827-4d17-b63a-b4383ec872c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507530090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3507530090
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1885114729
Short name T481
Test name
Test status
Simulation time 2018053301 ps
CPU time 4.42 seconds
Started Jan 10 12:56:47 PM PST 24
Finished Jan 10 12:58:02 PM PST 24
Peak memory 209684 kb
Host smart-e3f5ed7b-5d96-4b51-8d95-aac309fbb905
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885114729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.1885114729
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3036827434
Short name T395
Test name
Test status
Simulation time 822901397 ps
CPU time 11.45 seconds
Started Jan 10 01:13:10 PM PST 24
Finished Jan 10 01:14:48 PM PST 24
Peak memory 218048 kb
Host smart-610c5c68-4015-4438-abf7-c857e82f5f95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036827434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3036827434
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3946847786
Short name T760
Test name
Test status
Simulation time 1597055139 ps
CPU time 6.93 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:36:43 PM PST 24
Peak memory 212768 kb
Host smart-bdae2890-723e-4b36-8fa2-2f81cca7a1cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946847786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3946847786
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.901930330
Short name T124
Test name
Test status
Simulation time 735716572 ps
CPU time 6.38 seconds
Started Jan 10 12:56:28 PM PST 24
Finished Jan 10 12:57:44 PM PST 24
Peak memory 213664 kb
Host smart-ed64d9a5-bbbd-4ddf-8499-9dd026eb7383
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901930330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.901930330
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2550842781
Short name T833
Test name
Test status
Simulation time 14675923471 ps
CPU time 114.24 seconds
Started Jan 10 12:40:21 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 283888 kb
Host smart-9eb4835e-e377-4d0a-a375-cdd1a0cd4453
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550842781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2550842781
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.551973094
Short name T417
Test name
Test status
Simulation time 2089316005 ps
CPU time 12.03 seconds
Started Jan 10 12:47:11 PM PST 24
Finished Jan 10 12:48:52 PM PST 24
Peak memory 221692 kb
Host smart-77f44391-54b9-4b43-a818-00774d7df8c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551973094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.551973094
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2821678997
Short name T69
Test name
Test status
Simulation time 75923266 ps
CPU time 3.07 seconds
Started Jan 10 12:59:04 PM PST 24
Finished Jan 10 01:00:39 PM PST 24
Peak memory 218172 kb
Host smart-88afb753-ff24-482b-906f-42770e76ab02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821678997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2821678997
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2114007800
Short name T520
Test name
Test status
Simulation time 1069634405 ps
CPU time 7.54 seconds
Started Jan 10 12:47:09 PM PST 24
Finished Jan 10 12:48:34 PM PST 24
Peak memory 213544 kb
Host smart-8a644a8f-bfba-4680-83a8-6677576246a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114007800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2114007800
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1757677139
Short name T122
Test name
Test status
Simulation time 417506647 ps
CPU time 35.18 seconds
Started Jan 10 12:36:02 PM PST 24
Finished Jan 10 12:37:01 PM PST 24
Peak memory 269292 kb
Host smart-ca0fcbce-1938-4e4e-92c4-84a81d375cbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757677139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1757677139
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2761566828
Short name T687
Test name
Test status
Simulation time 425260161 ps
CPU time 13.59 seconds
Started Jan 10 12:35:39 PM PST 24
Finished Jan 10 12:36:18 PM PST 24
Peak memory 218124 kb
Host smart-743c173f-bff1-49c3-b90a-5bfcf25a7a3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761566828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2761566828
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2914930515
Short name T790
Test name
Test status
Simulation time 501379299 ps
CPU time 8.18 seconds
Started Jan 10 12:39:05 PM PST 24
Finished Jan 10 12:39:45 PM PST 24
Peak memory 218024 kb
Host smart-091f6309-ea3d-4cba-96d3-d020518e444e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914930515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2914930515
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.299833503
Short name T669
Test name
Test status
Simulation time 278840906 ps
CPU time 8.22 seconds
Started Jan 10 12:48:26 PM PST 24
Finished Jan 10 12:49:58 PM PST 24
Peak memory 218168 kb
Host smart-9a81eb72-0cba-4c61-a3c7-cfdbd2229a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299833503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.299833503
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.648813049
Short name T915
Test name
Test status
Simulation time 98894906 ps
CPU time 3.26 seconds
Started Jan 10 12:49:09 PM PST 24
Finished Jan 10 12:50:43 PM PST 24
Peak memory 217900 kb
Host smart-7e9f29c4-eb86-429f-bdef-75ad3e8c2320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648813049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.648813049
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.71298181
Short name T807
Test name
Test status
Simulation time 403360936 ps
CPU time 24.17 seconds
Started Jan 10 01:02:01 PM PST 24
Finished Jan 10 01:04:07 PM PST 24
Peak memory 250948 kb
Host smart-22c47ffc-aa3d-4c9a-8112-acc1dd3bb0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71298181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.71298181
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3021692101
Short name T301
Test name
Test status
Simulation time 186216833 ps
CPU time 6.37 seconds
Started Jan 10 12:53:43 PM PST 24
Finished Jan 10 12:55:00 PM PST 24
Peak memory 246528 kb
Host smart-14d46b3f-7ba6-4669-a7c4-951bd4828310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021692101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3021692101
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2945182739
Short name T468
Test name
Test status
Simulation time 17418428335 ps
CPU time 150.73 seconds
Started Jan 10 01:10:55 PM PST 24
Finished Jan 10 01:14:49 PM PST 24
Peak memory 251256 kb
Host smart-af4398ef-4d2e-40ae-ba79-0e46b17606fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945182739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2945182739
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.160499526
Short name T730
Test name
Test status
Simulation time 25724687 ps
CPU time 0.82 seconds
Started Jan 10 12:40:42 PM PST 24
Finished Jan 10 12:41:28 PM PST 24
Peak memory 208256 kb
Host smart-18fd00ae-5884-4d01-8ee8-749be35f8f48
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160499526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.160499526
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.300549501
Short name T616
Test name
Test status
Simulation time 43048089 ps
CPU time 0.95 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:34:56 PM PST 24
Peak memory 208360 kb
Host smart-22077c4b-4bbd-4d21-b708-c01601273716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300549501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.300549501
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3915527960
Short name T499
Test name
Test status
Simulation time 1726048195 ps
CPU time 12.84 seconds
Started Jan 10 12:48:34 PM PST 24
Finished Jan 10 12:50:14 PM PST 24
Peak memory 218084 kb
Host smart-db46da89-f88d-43b9-9caa-21084e8a5d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915527960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3915527960
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3342884219
Short name T7
Test name
Test status
Simulation time 982422229 ps
CPU time 9.22 seconds
Started Jan 10 01:01:26 PM PST 24
Finished Jan 10 01:03:06 PM PST 24
Peak memory 209668 kb
Host smart-e19a10c3-dda7-4c5d-a772-0ea7f7db1ef6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342884219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.3342884219
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2764408167
Short name T804
Test name
Test status
Simulation time 147210544 ps
CPU time 2.64 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:23:18 PM PST 24
Peak memory 218196 kb
Host smart-0b41d55d-3fb9-455e-b17d-f3a01cc3a448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764408167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2764408167
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1199685432
Short name T437
Test name
Test status
Simulation time 847395017 ps
CPU time 13.07 seconds
Started Jan 10 01:06:43 PM PST 24
Finished Jan 10 01:08:09 PM PST 24
Peak memory 218144 kb
Host smart-26ef9db0-c1b9-4074-9d2d-c861b383e16d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199685432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1199685432
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3249090223
Short name T439
Test name
Test status
Simulation time 1450476492 ps
CPU time 18.76 seconds
Started Jan 10 12:40:09 PM PST 24
Finished Jan 10 12:41:14 PM PST 24
Peak memory 218120 kb
Host smart-70eae448-4898-4fa9-a3a6-c9e687d63f5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249090223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3249090223
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1822559763
Short name T44
Test name
Test status
Simulation time 371245590 ps
CPU time 9.61 seconds
Started Jan 10 12:34:01 PM PST 24
Finished Jan 10 12:34:44 PM PST 24
Peak memory 217984 kb
Host smart-f1348625-de9e-4a5d-b3c9-6a77d82158cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822559763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1822559763
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1148472727
Short name T88
Test name
Test status
Simulation time 896516908 ps
CPU time 12.41 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:59 PM PST 24
Peak memory 218124 kb
Host smart-f3bba9e4-99fa-4e66-9095-d2905f4bb6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148472727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1148472727
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3173423561
Short name T84
Test name
Test status
Simulation time 83885851 ps
CPU time 1.6 seconds
Started Jan 10 12:56:34 PM PST 24
Finished Jan 10 12:57:44 PM PST 24
Peak memory 213352 kb
Host smart-e2d8e4dd-51ab-4c27-9cf0-04f0c3d30dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173423561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3173423561
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3695376795
Short name T11
Test name
Test status
Simulation time 280429068 ps
CPU time 26.86 seconds
Started Jan 10 12:40:51 PM PST 24
Finished Jan 10 12:42:07 PM PST 24
Peak memory 251032 kb
Host smart-6682fb01-acb9-4134-8769-8715569010af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695376795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3695376795
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4251343887
Short name T910
Test name
Test status
Simulation time 439447271 ps
CPU time 3.04 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:42 PM PST 24
Peak memory 222200 kb
Host smart-8efcf5ae-81fb-4787-97cf-6a440693d613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251343887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4251343887
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2912441914
Short name T854
Test name
Test status
Simulation time 29005996328 ps
CPU time 123.8 seconds
Started Jan 10 12:40:17 PM PST 24
Finished Jan 10 12:43:08 PM PST 24
Peak memory 284024 kb
Host smart-a6c00807-e084-4b1b-814a-b3c3b8b4bddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912441914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2912441914
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3533373795
Short name T132
Test name
Test status
Simulation time 39163155864 ps
CPU time 885.98 seconds
Started Jan 10 01:19:08 PM PST 24
Finished Jan 10 01:33:55 PM PST 24
Peak memory 513500 kb
Host smart-92cb99a7-405f-44f2-b15d-d75dbaec3ce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3533373795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.3533373795
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.751453063
Short name T690
Test name
Test status
Simulation time 47861805 ps
CPU time 1.03 seconds
Started Jan 10 12:44:29 PM PST 24
Finished Jan 10 12:45:47 PM PST 24
Peak memory 211472 kb
Host smart-8a6e09ba-99ad-4fc1-a79d-9241d07b2857
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751453063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.751453063
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1739432904
Short name T914
Test name
Test status
Simulation time 91791741 ps
CPU time 0.94 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:34:43 PM PST 24
Peak memory 209704 kb
Host smart-f81da69b-ec88-408c-bd12-400407bd95c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739432904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1739432904
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3298183176
Short name T796
Test name
Test status
Simulation time 858966589 ps
CPU time 7.4 seconds
Started Jan 10 12:34:03 PM PST 24
Finished Jan 10 12:34:39 PM PST 24
Peak memory 218056 kb
Host smart-59ff9251-0d9a-4f27-85bb-3487e53ccd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298183176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3298183176
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1096399274
Short name T846
Test name
Test status
Simulation time 704609669 ps
CPU time 5.06 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:41:02 PM PST 24
Peak memory 209592 kb
Host smart-a77c46a0-7f6c-40de-b7e6-b80e4306e816
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096399274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.1096399274
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.475273078
Short name T973
Test name
Test status
Simulation time 234300884 ps
CPU time 3.03 seconds
Started Jan 10 12:49:43 PM PST 24
Finished Jan 10 12:51:21 PM PST 24
Peak memory 218096 kb
Host smart-f4a63c39-ff3c-4444-af2c-4c74428ef5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475273078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.475273078
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.21043328
Short name T462
Test name
Test status
Simulation time 1248054827 ps
CPU time 15.56 seconds
Started Jan 10 12:34:03 PM PST 24
Finished Jan 10 12:34:47 PM PST 24
Peak memory 218480 kb
Host smart-0d02f80b-f25b-4a02-9341-fc8c816db97b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.21043328
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2961900935
Short name T594
Test name
Test status
Simulation time 341324741 ps
CPU time 13.9 seconds
Started Jan 10 12:34:07 PM PST 24
Finished Jan 10 12:34:50 PM PST 24
Peak memory 217980 kb
Host smart-eaf8386c-c05d-472d-9c24-766c80d7b053
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961900935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2961900935
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2073311781
Short name T401
Test name
Test status
Simulation time 446058545 ps
CPU time 9.87 seconds
Started Jan 10 12:34:02 PM PST 24
Finished Jan 10 12:34:41 PM PST 24
Peak memory 218336 kb
Host smart-3c849766-9923-4369-9ff4-bd029d0681e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073311781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2073311781
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.4155405849
Short name T43
Test name
Test status
Simulation time 1198408621 ps
CPU time 12.14 seconds
Started Jan 10 12:47:45 PM PST 24
Finished Jan 10 12:49:21 PM PST 24
Peak memory 218188 kb
Host smart-a879a010-1990-4016-91a6-fd37a522f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155405849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.4155405849
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3317185870
Short name T768
Test name
Test status
Simulation time 22249933 ps
CPU time 1.03 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:34:58 PM PST 24
Peak memory 211628 kb
Host smart-f716b9f7-3554-4fa5-a338-df26dc1597b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317185870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3317185870
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2273251419
Short name T449
Test name
Test status
Simulation time 1298504250 ps
CPU time 31.46 seconds
Started Jan 10 12:52:03 PM PST 24
Finished Jan 10 12:54:07 PM PST 24
Peak memory 251104 kb
Host smart-81a33c5f-24d5-4778-ba92-43d4c419ed15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273251419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2273251419
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.640643114
Short name T491
Test name
Test status
Simulation time 60037993 ps
CPU time 2.97 seconds
Started Jan 10 12:34:20 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 222284 kb
Host smart-35f667c3-3249-4ceb-9b97-e81a2add420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640643114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.640643114
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3585538585
Short name T922
Test name
Test status
Simulation time 2207942667 ps
CPU time 24.88 seconds
Started Jan 10 12:33:57 PM PST 24
Finished Jan 10 12:34:52 PM PST 24
Peak memory 251200 kb
Host smart-1cd41aeb-e6ab-4bc3-8508-3e744fdae941
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585538585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3585538585
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3241590756
Short name T964
Test name
Test status
Simulation time 20088742 ps
CPU time 0.71 seconds
Started Jan 10 12:34:04 PM PST 24
Finished Jan 10 12:34:34 PM PST 24
Peak memory 206860 kb
Host smart-370bed35-8798-4873-bfdb-0792915426a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241590756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3241590756
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3424796121
Short name T775
Test name
Test status
Simulation time 19686764 ps
CPU time 0.88 seconds
Started Jan 10 12:34:25 PM PST 24
Finished Jan 10 12:35:02 PM PST 24
Peak memory 209588 kb
Host smart-d0907885-a42c-48fe-a374-30eba280bd6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424796121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3424796121
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.687344546
Short name T57
Test name
Test status
Simulation time 1537297530 ps
CPU time 16.29 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 218004 kb
Host smart-120c7a03-afc6-425b-855e-8c324850480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687344546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.687344546
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1363528440
Short name T32
Test name
Test status
Simulation time 262096538 ps
CPU time 7.12 seconds
Started Jan 10 12:34:11 PM PST 24
Finished Jan 10 12:34:49 PM PST 24
Peak memory 209640 kb
Host smart-528895d6-7f2d-4024-a2aa-e9621f433159
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363528440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.1363528440
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3543996953
Short name T452
Test name
Test status
Simulation time 68033990 ps
CPU time 1.7 seconds
Started Jan 10 12:34:18 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 218236 kb
Host smart-1743ab14-1f33-4188-b27b-09269ba09726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543996953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3543996953
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2561340516
Short name T891
Test name
Test status
Simulation time 2149821798 ps
CPU time 19.04 seconds
Started Jan 10 12:34:16 PM PST 24
Finished Jan 10 12:35:08 PM PST 24
Peak memory 219480 kb
Host smart-8657b3a1-848f-4776-8e23-c0922285d3fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561340516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2561340516
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3722877438
Short name T721
Test name
Test status
Simulation time 473834974 ps
CPU time 10.67 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:34:58 PM PST 24
Peak memory 217984 kb
Host smart-a9f0d84e-26d5-4ccd-88ea-0903681bdc81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722877438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3722877438
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3391263817
Short name T342
Test name
Test status
Simulation time 326964985 ps
CPU time 11.55 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:03 PM PST 24
Peak memory 218120 kb
Host smart-b94be7d1-6793-4418-8a4c-699ed3eb08ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391263817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3391263817
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.108964753
Short name T343
Test name
Test status
Simulation time 1097050167 ps
CPU time 9.93 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 218088 kb
Host smart-a63d69e0-3ac2-4ae8-975d-7ccb19727365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108964753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.108964753
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3970326394
Short name T320
Test name
Test status
Simulation time 185684548 ps
CPU time 3.12 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 214256 kb
Host smart-80219e3b-3a5b-424f-ac4e-34904cafaa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970326394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3970326394
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2022960719
Short name T890
Test name
Test status
Simulation time 381951035 ps
CPU time 18.1 seconds
Started Jan 10 12:34:07 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 250964 kb
Host smart-5378376c-4159-47c3-b532-9e7b6181f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022960719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2022960719
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.749171359
Short name T763
Test name
Test status
Simulation time 97618512 ps
CPU time 6.69 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 250360 kb
Host smart-a2789df4-56d1-4920-a56a-eb36060891e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749171359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.749171359
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1730504355
Short name T134
Test name
Test status
Simulation time 27267947081 ps
CPU time 137.03 seconds
Started Jan 10 12:34:17 PM PST 24
Finished Jan 10 12:37:07 PM PST 24
Peak memory 271972 kb
Host smart-e0928ab0-2332-48bb-8734-2f740a15a773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730504355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1730504355
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2240314501
Short name T48
Test name
Test status
Simulation time 19343721 ps
CPU time 0.84 seconds
Started Jan 10 12:34:03 PM PST 24
Finished Jan 10 12:34:32 PM PST 24
Peak memory 207992 kb
Host smart-f53b8185-4158-45db-a553-01048e66bb84
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240314501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2240314501
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3434453805
Short name T37
Test name
Test status
Simulation time 152980322 ps
CPU time 0.99 seconds
Started Jan 10 12:50:59 PM PST 24
Finished Jan 10 12:52:30 PM PST 24
Peak memory 209660 kb
Host smart-79551fff-839e-4e9c-a0e0-85340173c9f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434453805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3434453805
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1074043143
Short name T533
Test name
Test status
Simulation time 294046752 ps
CPU time 8.35 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:43 PM PST 24
Peak memory 217968 kb
Host smart-a165348a-8334-46c8-a142-4bb19875fbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074043143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1074043143
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1519338944
Short name T72
Test name
Test status
Simulation time 92503203 ps
CPU time 2.99 seconds
Started Jan 10 12:40:09 PM PST 24
Finished Jan 10 12:40:58 PM PST 24
Peak memory 209672 kb
Host smart-a25b1da0-b8c6-46d1-9a41-98a0965806f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519338944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.1519338944
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2135064912
Short name T934
Test name
Test status
Simulation time 1001633031 ps
CPU time 4.25 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:09 PM PST 24
Peak memory 218172 kb
Host smart-684189d5-16f2-4261-8129-04f55daa5008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135064912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2135064912
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3040675840
Short name T463
Test name
Test status
Simulation time 444653560 ps
CPU time 14.1 seconds
Started Jan 10 12:40:31 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 219200 kb
Host smart-12259075-e7b9-4924-a193-67381ec1b570
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040675840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3040675840
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1006540581
Short name T574
Test name
Test status
Simulation time 272957317 ps
CPU time 9.53 seconds
Started Jan 10 12:43:43 PM PST 24
Finished Jan 10 12:45:08 PM PST 24
Peak memory 217996 kb
Host smart-80399d95-dca2-4413-9fa3-1c76b2752987
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006540581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1006540581
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.901026752
Short name T886
Test name
Test status
Simulation time 1624716024 ps
CPU time 10.16 seconds
Started Jan 10 12:48:45 PM PST 24
Finished Jan 10 12:50:22 PM PST 24
Peak memory 217928 kb
Host smart-3c1d46cc-4d0d-4127-a4cb-b539b640274e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901026752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.901026752
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2464375469
Short name T540
Test name
Test status
Simulation time 204793013 ps
CPU time 8.67 seconds
Started Jan 10 01:01:26 PM PST 24
Finished Jan 10 01:03:01 PM PST 24
Peak memory 218148 kb
Host smart-6d42601c-38fd-4222-806e-b8a224a8ade0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464375469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2464375469
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3498476824
Short name T970
Test name
Test status
Simulation time 163421849 ps
CPU time 2.32 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:34:56 PM PST 24
Peak memory 213840 kb
Host smart-2b3b0c06-39d5-4bc4-a2f9-3831e09cbf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498476824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3498476824
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1415807090
Short name T744
Test name
Test status
Simulation time 1342928245 ps
CPU time 34.5 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:35:34 PM PST 24
Peak memory 250996 kb
Host smart-80827904-a5cc-443a-8a1e-a5b19cc5ac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415807090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1415807090
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.458133406
Short name T956
Test name
Test status
Simulation time 308530034 ps
CPU time 7.38 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:02 PM PST 24
Peak memory 246744 kb
Host smart-8c5d4980-ab8f-4751-adda-83c258cdb7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458133406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.458133406
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3820886100
Short name T428
Test name
Test status
Simulation time 82129706443 ps
CPU time 538.51 seconds
Started Jan 10 12:48:36 PM PST 24
Finished Jan 10 12:58:59 PM PST 24
Peak memory 316736 kb
Host smart-d792d549-0efd-4d85-b745-5b53d4a66bc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820886100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3820886100
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3840228192
Short name T47
Test name
Test status
Simulation time 11589525 ps
CPU time 1.07 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:11 PM PST 24
Peak memory 211404 kb
Host smart-d04d1030-c1cf-4d9e-8035-4e9144b7b275
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840228192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3840228192
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1949369796
Short name T459
Test name
Test status
Simulation time 34901431 ps
CPU time 1.16 seconds
Started Jan 10 12:34:09 PM PST 24
Finished Jan 10 12:34:40 PM PST 24
Peak memory 209688 kb
Host smart-267aa745-1b2b-4dff-8040-e9bf536ebc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949369796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1949369796
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2665161534
Short name T543
Test name
Test status
Simulation time 1112554728 ps
CPU time 16.19 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:19 PM PST 24
Peak memory 218028 kb
Host smart-51463b0a-e6d5-47d7-8824-e43b944b986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665161534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2665161534
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3433222015
Short name T9
Test name
Test status
Simulation time 672499901 ps
CPU time 6.38 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:17 PM PST 24
Peak memory 209636 kb
Host smart-20b98db3-334d-44d9-b072-4d70e99e984a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433222015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_a
ccess.3433222015
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2606199126
Short name T666
Test name
Test status
Simulation time 57680344 ps
CPU time 2.95 seconds
Started Jan 10 12:34:04 PM PST 24
Finished Jan 10 12:34:37 PM PST 24
Peak memory 218096 kb
Host smart-55958f42-60fa-47a5-b4b0-7a60cdd32b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606199126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2606199126
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3938189132
Short name T609
Test name
Test status
Simulation time 430692306 ps
CPU time 19.09 seconds
Started Jan 10 12:34:20 PM PST 24
Finished Jan 10 12:35:12 PM PST 24
Peak memory 219064 kb
Host smart-689435de-711d-49bc-9373-cfeb02be2431
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938189132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3938189132
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2146335514
Short name T582
Test name
Test status
Simulation time 2174136381 ps
CPU time 12.46 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:35 PM PST 24
Peak memory 218088 kb
Host smart-42569b9e-7c3f-4d85-a578-403b95fe2135
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146335514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2146335514
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1124720320
Short name T808
Test name
Test status
Simulation time 640299942 ps
CPU time 8.85 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:54:43 PM PST 24
Peak memory 218052 kb
Host smart-7754ec44-5634-48a3-885c-d4713c63b794
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124720320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1124720320
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2071865434
Short name T476
Test name
Test status
Simulation time 1187199051 ps
CPU time 12.54 seconds
Started Jan 10 12:39:10 PM PST 24
Finished Jan 10 12:39:54 PM PST 24
Peak memory 218056 kb
Host smart-6b8495b3-40a2-498f-8767-8851ee744af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071865434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2071865434
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2807274536
Short name T837
Test name
Test status
Simulation time 39782391 ps
CPU time 1.79 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 213324 kb
Host smart-f1847fd1-0882-4c78-bf68-0cb50521462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807274536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2807274536
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2227701471
Short name T133
Test name
Test status
Simulation time 1233213667 ps
CPU time 29.49 seconds
Started Jan 10 12:34:01 PM PST 24
Finished Jan 10 12:35:00 PM PST 24
Peak memory 250092 kb
Host smart-9f089be5-5f97-44fa-b578-e9d1e18b4d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227701471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2227701471
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3370428869
Short name T384
Test name
Test status
Simulation time 51349043 ps
CPU time 7.87 seconds
Started Jan 10 01:15:09 PM PST 24
Finished Jan 10 01:15:20 PM PST 24
Peak memory 251200 kb
Host smart-a455c103-8448-4006-96d9-abda9494b6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370428869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3370428869
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1051654005
Short name T685
Test name
Test status
Simulation time 27226658032 ps
CPU time 145.21 seconds
Started Jan 10 12:38:33 PM PST 24
Finished Jan 10 12:41:30 PM PST 24
Peak memory 274076 kb
Host smart-19a841ae-47e6-4864-a724-705030def97f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051654005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1051654005
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3099261993
Short name T701
Test name
Test status
Simulation time 19811391 ps
CPU time 0.72 seconds
Started Jan 10 12:45:03 PM PST 24
Finished Jan 10 12:46:26 PM PST 24
Peak memory 206936 kb
Host smart-19e2b396-81a7-471c-9d4c-2cf2faf12b8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099261993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3099261993
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3440738329
Short name T355
Test name
Test status
Simulation time 17031763 ps
CPU time 1.06 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 208468 kb
Host smart-11ecf5d6-126a-4877-acbc-84fd97f6e88d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440738329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3440738329
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.749184819
Short name T651
Test name
Test status
Simulation time 457340296 ps
CPU time 7.38 seconds
Started Jan 10 12:59:41 PM PST 24
Finished Jan 10 01:01:25 PM PST 24
Peak memory 218204 kb
Host smart-73cf7e19-176d-4b83-8f86-0b7bcab93b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749184819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.749184819
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2735050636
Short name T366
Test name
Test status
Simulation time 62614200 ps
CPU time 1.53 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 209564 kb
Host smart-d5ff91be-a605-4895-8721-73d5a3dc60b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735050636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_a
ccess.2735050636
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.4260569192
Short name T356
Test name
Test status
Simulation time 203608312 ps
CPU time 3.34 seconds
Started Jan 10 01:01:07 PM PST 24
Finished Jan 10 01:02:37 PM PST 24
Peak memory 218088 kb
Host smart-654bb60e-4e10-4dc7-a3c6-e7c5264674e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260569192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4260569192
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.522467304
Short name T858
Test name
Test status
Simulation time 368026005 ps
CPU time 15.18 seconds
Started Jan 10 12:42:34 PM PST 24
Finished Jan 10 12:44:02 PM PST 24
Peak memory 219120 kb
Host smart-1cb4c9c8-b768-4802-b181-7238aab89c4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522467304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.522467304
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2758991251
Short name T410
Test name
Test status
Simulation time 1512538025 ps
CPU time 11.94 seconds
Started Jan 10 12:38:45 PM PST 24
Finished Jan 10 12:39:30 PM PST 24
Peak memory 218076 kb
Host smart-8213a1b9-a109-4e92-807c-7c2711bdd59a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758991251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2758991251
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3484019260
Short name T771
Test name
Test status
Simulation time 2246099765 ps
CPU time 7.51 seconds
Started Jan 10 12:39:40 PM PST 24
Finished Jan 10 12:40:17 PM PST 24
Peak memory 218092 kb
Host smart-1cc8ed07-6c87-4b98-9a9a-720de84da085
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484019260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3484019260
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3603777350
Short name T349
Test name
Test status
Simulation time 316567149 ps
CPU time 14.26 seconds
Started Jan 10 12:37:50 PM PST 24
Finished Jan 10 12:38:39 PM PST 24
Peak memory 218188 kb
Host smart-bf54bf18-ecc2-4663-923e-f5a650a0d594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603777350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3603777350
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.759145283
Short name T577
Test name
Test status
Simulation time 73430518 ps
CPU time 3.02 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 214296 kb
Host smart-49a7c346-b751-4daf-aec1-b3f09e042dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759145283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.759145283
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3501161102
Short name T456
Test name
Test status
Simulation time 239637808 ps
CPU time 20.18 seconds
Started Jan 10 12:38:04 PM PST 24
Finished Jan 10 12:38:57 PM PST 24
Peak memory 250976 kb
Host smart-4aeef306-a74f-42db-a16b-7c07c7cc9769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501161102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3501161102
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.244773282
Short name T732
Test name
Test status
Simulation time 304766729 ps
CPU time 10.42 seconds
Started Jan 10 12:39:34 PM PST 24
Finished Jan 10 12:40:13 PM PST 24
Peak memory 251080 kb
Host smart-6f36427f-c8df-4add-922c-b9c408697881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244773282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.244773282
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.153458041
Short name T494
Test name
Test status
Simulation time 6550006053 ps
CPU time 224.54 seconds
Started Jan 10 12:33:58 PM PST 24
Finished Jan 10 12:38:13 PM PST 24
Peak memory 282292 kb
Host smart-48b8c402-0a06-4370-a4cb-8601cae8f7f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153458041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.153458041
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2559954707
Short name T455
Test name
Test status
Simulation time 17181774 ps
CPU time 0.75 seconds
Started Jan 10 12:34:16 PM PST 24
Finished Jan 10 12:34:49 PM PST 24
Peak memory 208088 kb
Host smart-94dfa1e5-d05b-4cd0-ba69-638e4b7e4be1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559954707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2559954707
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1058286678
Short name T917
Test name
Test status
Simulation time 110981769 ps
CPU time 1.03 seconds
Started Jan 10 12:34:18 PM PST 24
Finished Jan 10 12:34:52 PM PST 24
Peak memory 209732 kb
Host smart-32ef96d9-acc8-4eab-9111-a4233a8aec6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058286678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1058286678
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3566062729
Short name T835
Test name
Test status
Simulation time 342642538 ps
CPU time 10.38 seconds
Started Jan 10 12:34:13 PM PST 24
Finished Jan 10 12:34:56 PM PST 24
Peak memory 218040 kb
Host smart-38e02a7d-fce5-4399-bdda-b21f566d114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566062729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3566062729
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.556083617
Short name T560
Test name
Test status
Simulation time 247567617 ps
CPU time 2.19 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:34:49 PM PST 24
Peak memory 209616 kb
Host smart-b4960611-c542-4248-b0d1-52a593af721e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556083617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_ac
cess.556083617
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.251080369
Short name T968
Test name
Test status
Simulation time 42884728 ps
CPU time 1.55 seconds
Started Jan 10 12:34:08 PM PST 24
Finished Jan 10 12:34:40 PM PST 24
Peak memory 218060 kb
Host smart-b016a838-bf91-4322-9128-1bf1f869f50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251080369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.251080369
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.303565653
Short name T545
Test name
Test status
Simulation time 302791410 ps
CPU time 9.74 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:34:52 PM PST 24
Peak memory 218200 kb
Host smart-83b4f630-a10b-456b-a42b-87b49324fd07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303565653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.303565653
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1841270183
Short name T420
Test name
Test status
Simulation time 1215475576 ps
CPU time 11.78 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:47 PM PST 24
Peak memory 217972 kb
Host smart-0defa9cb-1743-475f-a371-f6e94d05ee37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841270183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1841270183
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.367633902
Short name T380
Test name
Test status
Simulation time 574947056 ps
CPU time 12.44 seconds
Started Jan 10 12:34:18 PM PST 24
Finished Jan 10 12:35:04 PM PST 24
Peak memory 218172 kb
Host smart-bf79f142-800f-4359-b136-36540b1eec7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367633902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.367633902
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1623437324
Short name T723
Test name
Test status
Simulation time 234610992 ps
CPU time 9.02 seconds
Started Jan 10 12:34:07 PM PST 24
Finished Jan 10 12:34:46 PM PST 24
Peak memory 218024 kb
Host smart-e60660d3-aa49-4336-ac04-59c689dafa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623437324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1623437324
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1628029316
Short name T749
Test name
Test status
Simulation time 1119153006 ps
CPU time 4.02 seconds
Started Jan 10 12:34:02 PM PST 24
Finished Jan 10 12:34:35 PM PST 24
Peak memory 214208 kb
Host smart-9865d05d-4098-4371-b275-6d5f91c0a4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628029316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1628029316
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1704891287
Short name T504
Test name
Test status
Simulation time 176194111 ps
CPU time 19.92 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:23 PM PST 24
Peak memory 246024 kb
Host smart-21658771-86bf-4da3-a1de-9c99540eb435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704891287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1704891287
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1034031749
Short name T2
Test name
Test status
Simulation time 48820564 ps
CPU time 7.77 seconds
Started Jan 10 12:34:04 PM PST 24
Finished Jan 10 12:34:42 PM PST 24
Peak memory 251060 kb
Host smart-cf3fcb66-0e38-417d-bf6a-be90000d0c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034031749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1034031749
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1929141726
Short name T123
Test name
Test status
Simulation time 3503477441 ps
CPU time 98.34 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:36:30 PM PST 24
Peak memory 220520 kb
Host smart-f8c898d3-b4a9-462c-a5fb-e9ba9d0429e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929141726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1929141726
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1059901786
Short name T587
Test name
Test status
Simulation time 12122436 ps
CPU time 0.78 seconds
Started Jan 10 12:34:02 PM PST 24
Finished Jan 10 12:34:32 PM PST 24
Peak memory 207952 kb
Host smart-ed16ec6b-479e-4031-8451-c6b64d16b197
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059901786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1059901786
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4107743110
Short name T351
Test name
Test status
Simulation time 17188175 ps
CPU time 1.06 seconds
Started Jan 10 12:34:05 PM PST 24
Finished Jan 10 12:34:36 PM PST 24
Peak memory 209408 kb
Host smart-212b173b-98a0-4b5d-b805-de504c6d5f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107743110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4107743110
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2214463995
Short name T621
Test name
Test status
Simulation time 612693005 ps
CPU time 12.26 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:48 PM PST 24
Peak memory 218048 kb
Host smart-812103e5-57b8-4bec-98f7-fad0e8848aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214463995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2214463995
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1271097283
Short name T715
Test name
Test status
Simulation time 834966267 ps
CPU time 1.69 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:34:44 PM PST 24
Peak memory 209536 kb
Host smart-242e9dfa-c233-4399-9b46-138c9e705d30
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271097283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.1271097283
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.488091755
Short name T758
Test name
Test status
Simulation time 199973032 ps
CPU time 3.21 seconds
Started Jan 10 12:34:02 PM PST 24
Finished Jan 10 12:34:34 PM PST 24
Peak memory 218044 kb
Host smart-60f96d36-d7ba-4610-b5e4-9bc45a421eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488091755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.488091755
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.404729553
Short name T448
Test name
Test status
Simulation time 656381627 ps
CPU time 10.33 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:47 PM PST 24
Peak memory 218040 kb
Host smart-696fbc9c-4b84-4ea0-8431-90a40bad398a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404729553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.404729553
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1537271062
Short name T570
Test name
Test status
Simulation time 658530671 ps
CPU time 14.72 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:25 PM PST 24
Peak memory 218008 kb
Host smart-281e1050-d676-4112-8c57-16952e6c78d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537271062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1537271062
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.552271807
Short name T584
Test name
Test status
Simulation time 188494388 ps
CPU time 7.99 seconds
Started Jan 10 12:34:09 PM PST 24
Finished Jan 10 12:34:47 PM PST 24
Peak memory 218024 kb
Host smart-71807a4a-42ba-4e79-b0c9-f025aade0027
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552271807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.552271807
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2373144937
Short name T783
Test name
Test status
Simulation time 431061624 ps
CPU time 14.34 seconds
Started Jan 10 12:34:04 PM PST 24
Finished Jan 10 12:34:46 PM PST 24
Peak memory 218072 kb
Host smart-47a949be-cafd-4319-9af5-24f1e7d120f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373144937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2373144937
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1565803367
Short name T479
Test name
Test status
Simulation time 114989469 ps
CPU time 1.67 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 213416 kb
Host smart-8e4f692d-eb3a-49ef-831e-5aaaad45f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565803367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1565803367
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1927128751
Short name T379
Test name
Test status
Simulation time 1047054232 ps
CPU time 28.5 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:32 PM PST 24
Peak memory 250804 kb
Host smart-fcf28dab-1125-4071-b44e-1c8169b3ecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927128751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1927128751
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1003516212
Short name T325
Test name
Test status
Simulation time 1419690063 ps
CPU time 5.53 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:01 PM PST 24
Peak memory 222152 kb
Host smart-bb0945af-628a-4030-a25c-22d899bf2e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003516212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1003516212
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3672158433
Short name T387
Test name
Test status
Simulation time 16434085256 ps
CPU time 69.46 seconds
Started Jan 10 12:34:03 PM PST 24
Finished Jan 10 12:35:40 PM PST 24
Peak memory 271032 kb
Host smart-24c168d1-8cc2-46fc-a391-9d70099ed73e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672158433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3672158433
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3778288935
Short name T955
Test name
Test status
Simulation time 40579663 ps
CPU time 0.75 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 206640 kb
Host smart-19cfc64f-3fd0-449e-bada-2f9a22a68f5c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778288935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3778288935
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.630654777
Short name T556
Test name
Test status
Simulation time 21087931 ps
CPU time 1.07 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 209576 kb
Host smart-8c28066e-5d87-4829-8694-8b2272c6574b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630654777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.630654777
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3645675375
Short name T535
Test name
Test status
Simulation time 581451961 ps
CPU time 14.71 seconds
Started Jan 10 12:34:04 PM PST 24
Finished Jan 10 12:34:49 PM PST 24
Peak memory 218052 kb
Host smart-0ab8f04e-1557-4b5f-884c-b4f5ca05942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645675375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3645675375
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1731201102
Short name T34
Test name
Test status
Simulation time 1115754016 ps
CPU time 2.36 seconds
Started Jan 10 12:34:04 PM PST 24
Finished Jan 10 12:34:36 PM PST 24
Peak memory 209648 kb
Host smart-30b39260-5260-4e44-850a-451233a55a19
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731201102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.1731201102
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2090090175
Short name T432
Test name
Test status
Simulation time 24423574 ps
CPU time 1.6 seconds
Started Jan 10 12:34:03 PM PST 24
Finished Jan 10 12:34:33 PM PST 24
Peak memory 218172 kb
Host smart-f2e396ee-1951-4e3a-a097-06d19d43b789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090090175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2090090175
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1354313915
Short name T753
Test name
Test status
Simulation time 459386771 ps
CPU time 12.38 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 218076 kb
Host smart-1de5b1ce-7eeb-4582-b0f0-a2c1be10ea07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354313915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1354313915
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3778937426
Short name T928
Test name
Test status
Simulation time 2273180664 ps
CPU time 11.66 seconds
Started Jan 10 12:34:05 PM PST 24
Finished Jan 10 12:34:47 PM PST 24
Peak memory 217920 kb
Host smart-dc1e06f9-ae4e-4117-8aa6-01078c26949f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778937426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3778937426
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.930003799
Short name T362
Test name
Test status
Simulation time 334591129 ps
CPU time 8.32 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:34:51 PM PST 24
Peak memory 218000 kb
Host smart-8c418ccd-a85d-48e2-9416-36aee75413ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930003799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.930003799
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3883512904
Short name T438
Test name
Test status
Simulation time 378130478 ps
CPU time 12.59 seconds
Started Jan 10 12:34:07 PM PST 24
Finished Jan 10 12:34:50 PM PST 24
Peak memory 218044 kb
Host smart-0903b56d-21bf-41b8-9ceb-c64f5bedc738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883512904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3883512904
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.842617776
Short name T393
Test name
Test status
Simulation time 30086936 ps
CPU time 1.26 seconds
Started Jan 10 12:34:07 PM PST 24
Finished Jan 10 12:34:38 PM PST 24
Peak memory 213100 kb
Host smart-6984ffe6-bc9b-411e-8b42-8c9a4697c84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842617776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.842617776
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2486562605
Short name T873
Test name
Test status
Simulation time 312084208 ps
CPU time 28.06 seconds
Started Jan 10 12:34:11 PM PST 24
Finished Jan 10 12:35:10 PM PST 24
Peak memory 251232 kb
Host smart-d4083f63-38f0-41aa-85d6-5ef929076e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486562605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2486562605
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.885172688
Short name T684
Test name
Test status
Simulation time 67696144 ps
CPU time 6.87 seconds
Started Jan 10 12:34:16 PM PST 24
Finished Jan 10 12:34:56 PM PST 24
Peak memory 246528 kb
Host smart-8f02f2c4-5425-4c7b-b9b2-d9d32f5d09e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885172688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.885172688
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.104622247
Short name T791
Test name
Test status
Simulation time 9260264162 ps
CPU time 183.51 seconds
Started Jan 10 12:34:04 PM PST 24
Finished Jan 10 12:37:38 PM PST 24
Peak memory 283048 kb
Host smart-2b29bdb3-fa2e-49f9-9e8f-6f91819ec41e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104622247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.104622247
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1361719464
Short name T827
Test name
Test status
Simulation time 15085419 ps
CPU time 0.82 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:34:48 PM PST 24
Peak memory 208248 kb
Host smart-13df5f88-6cc1-4dc7-a5d8-a0090e2b9aa7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361719464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1361719464
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4289556366
Short name T839
Test name
Test status
Simulation time 16413996 ps
CPU time 1.09 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 209592 kb
Host smart-8d4ea93a-30d8-439f-a321-8b6d5e36f418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289556366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4289556366
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4232442751
Short name T704
Test name
Test status
Simulation time 1526391613 ps
CPU time 11.25 seconds
Started Jan 10 12:34:10 PM PST 24
Finished Jan 10 12:34:52 PM PST 24
Peak memory 218168 kb
Host smart-88be6d8a-5015-4758-b2c2-b3cdc010b003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232442751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4232442751
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2249589232
Short name T30
Test name
Test status
Simulation time 932661832 ps
CPU time 5.22 seconds
Started Jan 10 12:34:18 PM PST 24
Finished Jan 10 12:34:56 PM PST 24
Peak memory 209460 kb
Host smart-e0275f30-1175-4959-acb7-9b7ca054d619
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249589232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.2249589232
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2402923786
Short name T334
Test name
Test status
Simulation time 48725507 ps
CPU time 2.83 seconds
Started Jan 10 12:34:05 PM PST 24
Finished Jan 10 12:34:38 PM PST 24
Peak memory 218064 kb
Host smart-f512fb79-0e1f-4b57-abc9-b025b6d244ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402923786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2402923786
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3191556885
Short name T407
Test name
Test status
Simulation time 670064827 ps
CPU time 18.05 seconds
Started Jan 10 12:34:20 PM PST 24
Finished Jan 10 12:35:11 PM PST 24
Peak memory 219204 kb
Host smart-30ce2549-b959-40ff-a650-059437633ab3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191556885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3191556885
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3653403772
Short name T635
Test name
Test status
Simulation time 299634037 ps
CPU time 10.84 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:03 PM PST 24
Peak memory 217932 kb
Host smart-b672396e-cb01-46a7-b702-c1aba3a1df36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653403772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3653403772
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3582127985
Short name T498
Test name
Test status
Simulation time 374013164 ps
CPU time 13.47 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 217952 kb
Host smart-bd630a37-865e-4a66-92e4-1ebc315a284f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582127985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3582127985
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1442199567
Short name T957
Test name
Test status
Simulation time 1640100404 ps
CPU time 9.32 seconds
Started Jan 10 12:34:08 PM PST 24
Finished Jan 10 12:34:48 PM PST 24
Peak memory 218076 kb
Host smart-d00ab358-080e-4cfb-bad4-ae3523f3bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442199567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1442199567
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2163391286
Short name T547
Test name
Test status
Simulation time 48382080 ps
CPU time 1.57 seconds
Started Jan 10 12:34:25 PM PST 24
Finished Jan 10 12:35:01 PM PST 24
Peak memory 213444 kb
Host smart-57944aa4-b5ff-42cf-8fda-3f5a9dcf47aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163391286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2163391286
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.106577180
Short name T450
Test name
Test status
Simulation time 677791808 ps
CPU time 17.33 seconds
Started Jan 10 12:34:14 PM PST 24
Finished Jan 10 12:35:02 PM PST 24
Peak memory 250928 kb
Host smart-51d85dfc-9918-47bd-bfdf-d634e86d0047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106577180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.106577180
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2073701141
Short name T517
Test name
Test status
Simulation time 130521782 ps
CPU time 8.85 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:44 PM PST 24
Peak memory 251000 kb
Host smart-ddd191b0-f9bd-441e-935c-a0d1bb0042db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073701141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2073701141
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.146363537
Short name T61
Test name
Test status
Simulation time 3745685974 ps
CPU time 61.69 seconds
Started Jan 10 12:34:32 PM PST 24
Finished Jan 10 12:36:15 PM PST 24
Peak memory 250664 kb
Host smart-5ae68b23-5f48-40d5-88e4-69868d81b00b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146363537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.146363537
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3500132862
Short name T706
Test name
Test status
Simulation time 50902973187 ps
CPU time 5115.5 seconds
Started Jan 10 12:34:09 PM PST 24
Finished Jan 10 01:59:55 PM PST 24
Peak memory 693388 kb
Host smart-a25f155a-8d74-41bd-8d07-408906babde6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3500132862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3500132862
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4186820261
Short name T607
Test name
Test status
Simulation time 40340324 ps
CPU time 0.84 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:34:48 PM PST 24
Peak memory 211420 kb
Host smart-9069e367-7a26-4df1-9e8c-f044e6cfdcf0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186820261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4186820261
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.554176943
Short name T392
Test name
Test status
Simulation time 36528704 ps
CPU time 1.16 seconds
Started Jan 10 12:38:44 PM PST 24
Finished Jan 10 12:39:19 PM PST 24
Peak memory 208528 kb
Host smart-3f25fde0-f906-4493-8dc4-a9535afa77d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554176943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.554176943
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3674933551
Short name T77
Test name
Test status
Simulation time 10448571 ps
CPU time 0.8 seconds
Started Jan 10 12:50:32 PM PST 24
Finished Jan 10 12:51:59 PM PST 24
Peak memory 209352 kb
Host smart-1a60ad57-4188-4fed-9ea6-f6796dc6b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674933551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3674933551
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2689103094
Short name T576
Test name
Test status
Simulation time 532449853 ps
CPU time 14.77 seconds
Started Jan 10 12:39:08 PM PST 24
Finished Jan 10 12:39:55 PM PST 24
Peak memory 218196 kb
Host smart-1696e8fb-3ad9-49ae-8b94-cf8a49896246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689103094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2689103094
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1120156280
Short name T489
Test name
Test status
Simulation time 891318315 ps
CPU time 2.99 seconds
Started Jan 10 12:42:59 PM PST 24
Finished Jan 10 12:44:15 PM PST 24
Peak memory 209564 kb
Host smart-25c1916a-c6e3-4a30-8f0b-3f95e817bb39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120156280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.1120156280
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1807707537
Short name T546
Test name
Test status
Simulation time 6328159994 ps
CPU time 85.08 seconds
Started Jan 10 12:37:54 PM PST 24
Finished Jan 10 12:39:52 PM PST 24
Peak memory 218688 kb
Host smart-6abb43a8-acb6-488e-b444-8642cdbba13e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807707537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1807707537
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2077034488
Short name T919
Test name
Test status
Simulation time 383723565 ps
CPU time 4.58 seconds
Started Jan 10 12:50:14 PM PST 24
Finished Jan 10 12:51:55 PM PST 24
Peak memory 209612 kb
Host smart-b05a3d67-faf0-4dac-8d56-b1a2c1594a5f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077034488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.2077034488
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3798580441
Short name T399
Test name
Test status
Simulation time 2079610982 ps
CPU time 3.46 seconds
Started Jan 10 01:07:04 PM PST 24
Finished Jan 10 01:08:29 PM PST 24
Peak memory 218248 kb
Host smart-d7e4929d-f4ac-4688-a239-3aa8cf7bda2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798580441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3798580441
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1331586939
Short name T24
Test name
Test status
Simulation time 3368455904 ps
CPU time 11.75 seconds
Started Jan 10 12:42:52 PM PST 24
Finished Jan 10 12:44:18 PM PST 24
Peak memory 213244 kb
Host smart-28424209-aba9-4d4b-a416-6748b2904679
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331586939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1331586939
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1744544042
Short name T787
Test name
Test status
Simulation time 851990312 ps
CPU time 3.97 seconds
Started Jan 10 12:50:14 PM PST 24
Finished Jan 10 12:51:46 PM PST 24
Peak memory 213452 kb
Host smart-5fc79af2-345a-4b20-a43b-d3c61dc23431
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744544042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1744544042
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1178140545
Short name T632
Test name
Test status
Simulation time 59450684440 ps
CPU time 68.98 seconds
Started Jan 10 12:38:00 PM PST 24
Finished Jan 10 12:39:42 PM PST 24
Peak memory 283740 kb
Host smart-29841749-c5fa-45cd-b9b4-d14a6ef93e97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178140545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1178140545
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.424323416
Short name T130
Test name
Test status
Simulation time 550060000 ps
CPU time 12.45 seconds
Started Jan 10 12:59:26 PM PST 24
Finished Jan 10 01:01:11 PM PST 24
Peak memory 245784 kb
Host smart-27314156-b838-4c54-9a56-52343eb19d36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424323416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.424323416
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3417927254
Short name T482
Test name
Test status
Simulation time 356851929 ps
CPU time 3.49 seconds
Started Jan 10 12:36:32 PM PST 24
Finished Jan 10 12:37:08 PM PST 24
Peak memory 218072 kb
Host smart-9360bba5-7350-4306-aa65-af247ac030b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417927254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3417927254
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2645598073
Short name T961
Test name
Test status
Simulation time 1045129959 ps
CPU time 14.72 seconds
Started Jan 10 12:42:29 PM PST 24
Finished Jan 10 12:43:57 PM PST 24
Peak memory 213576 kb
Host smart-4681dbd5-5205-40c1-a251-de4ee98f12a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645598073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2645598073
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1255773717
Short name T99
Test name
Test status
Simulation time 454385220 ps
CPU time 35.01 seconds
Started Jan 10 12:34:47 PM PST 24
Finished Jan 10 12:36:05 PM PST 24
Peak memory 268624 kb
Host smart-0f2b3740-d7f1-4425-bd95-7b8ba9af4905
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255773717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1255773717
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2568090679
Short name T881
Test name
Test status
Simulation time 1332940981 ps
CPU time 10.36 seconds
Started Jan 10 12:46:00 PM PST 24
Finished Jan 10 12:47:32 PM PST 24
Peak memory 218280 kb
Host smart-bcabce38-1f93-4b66-bdcc-5b3f458cbdf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568090679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2568090679
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.910767922
Short name T513
Test name
Test status
Simulation time 251061198 ps
CPU time 6.96 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:54:47 PM PST 24
Peak memory 218048 kb
Host smart-c2ff16be-b955-480f-bcd9-bbafd9f0bb3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910767922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.910767922
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1080796079
Short name T530
Test name
Test status
Simulation time 282700086 ps
CPU time 6.84 seconds
Started Jan 10 12:51:58 PM PST 24
Finished Jan 10 12:53:27 PM PST 24
Peak memory 218120 kb
Host smart-00c27126-1a1c-466b-b0f1-18b2331fc61f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080796079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
080796079
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1183321797
Short name T403
Test name
Test status
Simulation time 64860227 ps
CPU time 2.37 seconds
Started Jan 10 12:43:13 PM PST 24
Finished Jan 10 12:44:29 PM PST 24
Peak memory 213620 kb
Host smart-c0c562b5-7df8-403d-8905-098b0278c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183321797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1183321797
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.4270860545
Short name T765
Test name
Test status
Simulation time 928788921 ps
CPU time 27.99 seconds
Started Jan 10 12:54:13 PM PST 24
Finished Jan 10 12:55:47 PM PST 24
Peak memory 251136 kb
Host smart-ef6e7877-9812-41a6-aa57-242fd98d52c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270860545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.4270860545
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2821522981
Short name T627
Test name
Test status
Simulation time 120407006 ps
CPU time 7.36 seconds
Started Jan 10 01:16:29 PM PST 24
Finished Jan 10 01:17:39 PM PST 24
Peak memory 251000 kb
Host smart-b93fdce3-c903-4e50-8e69-624b69a85448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821522981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2821522981
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3004790317
Short name T21
Test name
Test status
Simulation time 14914041689 ps
CPU time 139.57 seconds
Started Jan 10 12:42:46 PM PST 24
Finished Jan 10 12:46:19 PM PST 24
Peak memory 291728 kb
Host smart-647881c2-d583-4484-9d28-d7bb179230c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004790317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3004790317
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1162723185
Short name T782
Test name
Test status
Simulation time 11543604 ps
CPU time 0.73 seconds
Started Jan 10 12:52:25 PM PST 24
Finished Jan 10 12:53:40 PM PST 24
Peak memory 207520 kb
Host smart-be0ec096-94b2-4649-95fd-dab10c527afe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162723185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1162723185
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2657745848
Short name T860
Test name
Test status
Simulation time 43889312 ps
CPU time 0.91 seconds
Started Jan 10 12:34:17 PM PST 24
Finished Jan 10 12:34:50 PM PST 24
Peak memory 209532 kb
Host smart-cb3f26ac-15ec-49ce-b3ad-8f9138458536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657745848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2657745848
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.657714157
Short name T747
Test name
Test status
Simulation time 611062160 ps
CPU time 11.78 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 218052 kb
Host smart-14e4a480-de54-408a-804b-1a323a6dfae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657714157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.657714157
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3754311130
Short name T631
Test name
Test status
Simulation time 358184407 ps
CPU time 4.45 seconds
Started Jan 10 12:34:16 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 209752 kb
Host smart-31e2941a-d384-4deb-929e-1ef88b4c809f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754311130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.3754311130
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1571797097
Short name T813
Test name
Test status
Simulation time 18390928 ps
CPU time 1.49 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:34:49 PM PST 24
Peak memory 218216 kb
Host smart-5c4d3ecd-4f9f-45b2-8930-d82f25c074e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571797097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1571797097
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3501360874
Short name T353
Test name
Test status
Simulation time 1371619183 ps
CPU time 14.45 seconds
Started Jan 10 12:34:18 PM PST 24
Finished Jan 10 12:35:05 PM PST 24
Peak memory 218024 kb
Host smart-72f68fc1-c491-4144-afb7-6fab663e5127
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501360874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3501360874
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1302534630
Short name T598
Test name
Test status
Simulation time 2866894388 ps
CPU time 11.06 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 218192 kb
Host smart-3b55f863-608b-4434-96b4-0c06b824f628
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302534630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1302534630
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.323099542
Short name T794
Test name
Test status
Simulation time 667400427 ps
CPU time 9.04 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:35:03 PM PST 24
Peak memory 218148 kb
Host smart-40f08db9-9550-4538-9e84-b572998d68ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323099542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.323099542
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.575634932
Short name T568
Test name
Test status
Simulation time 544038211 ps
CPU time 17.25 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 218164 kb
Host smart-6055beeb-9ba6-4546-8518-96ee86ae3f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575634932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.575634932
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.392279242
Short name T699
Test name
Test status
Simulation time 298890468 ps
CPU time 2.65 seconds
Started Jan 10 12:34:14 PM PST 24
Finished Jan 10 12:34:48 PM PST 24
Peak memory 213688 kb
Host smart-2669deb0-a2dd-449b-8fd4-d855ce525120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392279242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.392279242
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.724024892
Short name T444
Test name
Test status
Simulation time 255304657 ps
CPU time 17.13 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 250792 kb
Host smart-1b03882e-ba15-4e9b-8e63-e02b4acddb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724024892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.724024892
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1571427013
Short name T663
Test name
Test status
Simulation time 127284035 ps
CPU time 7.82 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:00 PM PST 24
Peak memory 250892 kb
Host smart-eba5af82-c64b-4240-9096-94a5d1da7728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571427013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1571427013
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2616626996
Short name T541
Test name
Test status
Simulation time 20381156502 ps
CPU time 118.79 seconds
Started Jan 10 12:34:15 PM PST 24
Finished Jan 10 12:36:46 PM PST 24
Peak memory 247092 kb
Host smart-571787d8-8b5d-4229-b6da-44271082ec02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616626996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2616626996
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1497095664
Short name T692
Test name
Test status
Simulation time 17717042 ps
CPU time 0.84 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:53 PM PST 24
Peak memory 208264 kb
Host smart-3fe868bd-3a3a-4321-b43c-cbc9a30ec87a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497095664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1497095664
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3694564045
Short name T667
Test name
Test status
Simulation time 27579929 ps
CPU time 1.11 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:04 PM PST 24
Peak memory 209592 kb
Host smart-8b5664da-d0e9-494f-9abb-1e78c3205f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694564045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3694564045
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2055576193
Short name T331
Test name
Test status
Simulation time 647464334 ps
CPU time 24.59 seconds
Started Jan 10 12:34:16 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 218212 kb
Host smart-c16c0ef7-ab5b-4011-968f-5fe0fd502135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055576193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2055576193
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2466962127
Short name T975
Test name
Test status
Simulation time 324146535 ps
CPU time 7.73 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:12 PM PST 24
Peak memory 209504 kb
Host smart-0006b55f-100f-4869-bbaa-30c50232e1eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466962127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.2466962127
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3452754055
Short name T477
Test name
Test status
Simulation time 334123949 ps
CPU time 3.2 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:35:01 PM PST 24
Peak memory 218156 kb
Host smart-e178eb39-fdba-4b76-92d7-dbe32ce08d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452754055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3452754055
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2779552100
Short name T660
Test name
Test status
Simulation time 3820394943 ps
CPU time 13.7 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 218876 kb
Host smart-3fbcf075-280b-476c-8f31-8a1db4ba95dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779552100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2779552100
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1771604698
Short name T905
Test name
Test status
Simulation time 476267756 ps
CPU time 8.28 seconds
Started Jan 10 12:34:29 PM PST 24
Finished Jan 10 12:35:15 PM PST 24
Peak memory 217988 kb
Host smart-c73e5f87-c6ab-4ac4-a378-27592d7e4f72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771604698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1771604698
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1052790440
Short name T664
Test name
Test status
Simulation time 1714603869 ps
CPU time 9.96 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:02 PM PST 24
Peak memory 218088 kb
Host smart-387e2b60-4d58-4fad-b631-3671895f8f27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052790440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1052790440
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.116293088
Short name T537
Test name
Test status
Simulation time 764730787 ps
CPU time 7.68 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:03 PM PST 24
Peak memory 217972 kb
Host smart-3e0f1442-b604-4241-8587-e92b125ce6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116293088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.116293088
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1296804173
Short name T315
Test name
Test status
Simulation time 97307982 ps
CPU time 1.46 seconds
Started Jan 10 12:34:18 PM PST 24
Finished Jan 10 12:34:52 PM PST 24
Peak memory 213004 kb
Host smart-87e33de5-ab57-4205-937b-0d18a8dbc93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296804173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1296804173
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2010216986
Short name T793
Test name
Test status
Simulation time 177099350 ps
CPU time 24.12 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:30 PM PST 24
Peak memory 250992 kb
Host smart-c93de83e-d1a1-4495-a85a-75bd5f80f6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010216986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2010216986
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.587509923
Short name T619
Test name
Test status
Simulation time 47386193 ps
CPU time 6.29 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:34:58 PM PST 24
Peak memory 246600 kb
Host smart-0f5ddffd-8ed1-43f4-857d-ec586da766c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587509923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.587509923
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1655333797
Short name T903
Test name
Test status
Simulation time 35280129591 ps
CPU time 268.6 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:39:41 PM PST 24
Peak memory 251152 kb
Host smart-5e61d661-70ba-4ae6-8e62-cc5f1f5105fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655333797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1655333797
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3875092362
Short name T770
Test name
Test status
Simulation time 58592816 ps
CPU time 0.84 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 209540 kb
Host smart-573987f3-d229-49d6-8e33-e027f7b65724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875092362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3875092362
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2921784728
Short name T707
Test name
Test status
Simulation time 527492139 ps
CPU time 18.67 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 218036 kb
Host smart-582e8c58-8594-475d-b915-a8a064ef9393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921784728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2921784728
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2114116120
Short name T348
Test name
Test status
Simulation time 1022434887 ps
CPU time 2.75 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 209536 kb
Host smart-0e05f8df-62f2-4e3f-bcb2-6618bd06d398
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114116120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.2114116120
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.297889457
Short name T1
Test name
Test status
Simulation time 99365363 ps
CPU time 4.03 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 218084 kb
Host smart-10cb7b2a-848b-41ef-8dd1-4ebdb8b29fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297889457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.297889457
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3963759756
Short name T899
Test name
Test status
Simulation time 1503758258 ps
CPU time 14.76 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:17 PM PST 24
Peak memory 218268 kb
Host smart-cb66992e-ef1d-4669-a672-63ecbeb9f9dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963759756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3963759756
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3155886559
Short name T404
Test name
Test status
Simulation time 2024891987 ps
CPU time 13.3 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:18 PM PST 24
Peak memory 217964 kb
Host smart-2dffd3a4-d452-4948-9541-88ad56b7b477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155886559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3155886559
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2625071669
Short name T726
Test name
Test status
Simulation time 426230721 ps
CPU time 11.16 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:18 PM PST 24
Peak memory 218088 kb
Host smart-f00faacf-d7d4-4a16-83e1-c67fc97b09d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625071669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2625071669
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3618437293
Short name T786
Test name
Test status
Simulation time 320423463 ps
CPU time 7.71 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 218092 kb
Host smart-108706bd-59ac-44ec-a74b-09dea51d6c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618437293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3618437293
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2604928917
Short name T510
Test name
Test status
Simulation time 50252947 ps
CPU time 1.19 seconds
Started Jan 10 12:34:24 PM PST 24
Finished Jan 10 12:35:00 PM PST 24
Peak memory 213008 kb
Host smart-2463fe15-cc85-45ca-9014-ba3ec8c56470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604928917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2604928917
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.4171245566
Short name T552
Test name
Test status
Simulation time 379094723 ps
CPU time 31.41 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:41 PM PST 24
Peak memory 250980 kb
Host smart-db4a912f-3873-4e9f-883b-aaa52cf09308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171245566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4171245566
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.4038058348
Short name T372
Test name
Test status
Simulation time 80441067 ps
CPU time 2.98 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 222120 kb
Host smart-4e9258f6-ba62-4dbf-b6be-5124a0e9e870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038058348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.4038058348
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2381208254
Short name T564
Test name
Test status
Simulation time 16702396256 ps
CPU time 263.38 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:39:26 PM PST 24
Peak memory 277344 kb
Host smart-4c673bc1-3789-449c-8f2c-c13ce7d24d54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381208254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2381208254
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3352785330
Short name T745
Test name
Test status
Simulation time 19806127 ps
CPU time 0.84 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 208320 kb
Host smart-3ccd1ff0-c419-4e3e-9418-344160bbdee1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352785330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3352785330
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.863093037
Short name T798
Test name
Test status
Simulation time 39260570 ps
CPU time 0.9 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:15 PM PST 24
Peak memory 209696 kb
Host smart-8f6fce7b-c06d-4c35-9634-02b38e530387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863093037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.863093037
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2083337112
Short name T433
Test name
Test status
Simulation time 3748188945 ps
CPU time 13.68 seconds
Started Jan 10 12:34:35 PM PST 24
Finished Jan 10 12:35:29 PM PST 24
Peak memory 219260 kb
Host smart-6ab6ab6f-e40d-4ea8-8448-3fb131aa6172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083337112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2083337112
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2331294894
Short name T569
Test name
Test status
Simulation time 130352401 ps
CPU time 3.87 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:17 PM PST 24
Peak memory 209552 kb
Host smart-9662afd5-80a4-455f-9f2c-bc5b11c0727e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331294894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.2331294894
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1862231343
Short name T856
Test name
Test status
Simulation time 325781007 ps
CPU time 3.08 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:18 PM PST 24
Peak memory 218188 kb
Host smart-9417d3b8-049a-42c7-ad3f-460f13881a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862231343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1862231343
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.145648138
Short name T848
Test name
Test status
Simulation time 714024724 ps
CPU time 13.95 seconds
Started Jan 10 12:34:35 PM PST 24
Finished Jan 10 12:35:29 PM PST 24
Peak memory 219100 kb
Host smart-2d70cd62-803b-4286-8b41-4ddfbf1ee13f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145648138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.145648138
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3901186146
Short name T792
Test name
Test status
Simulation time 172546763 ps
CPU time 8.45 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:23 PM PST 24
Peak memory 218012 kb
Host smart-e58e556b-946e-4ed9-b575-3957e3e9aff1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901186146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3901186146
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3949146665
Short name T861
Test name
Test status
Simulation time 317765048 ps
CPU time 12.11 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:26 PM PST 24
Peak memory 218004 kb
Host smart-ba121e3b-dd92-4568-8c6c-5fda89ab53fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949146665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3949146665
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2797117676
Short name T431
Test name
Test status
Simulation time 1168419363 ps
CPU time 10.45 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 218124 kb
Host smart-fd333628-6948-4fc5-92da-3a1291e060ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797117676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2797117676
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.536111268
Short name T81
Test name
Test status
Simulation time 190413808 ps
CPU time 2.21 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 213844 kb
Host smart-768f9cf8-3f1d-4344-ad9b-67bb24c78376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536111268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.536111268
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.504162882
Short name T549
Test name
Test status
Simulation time 1412999312 ps
CPU time 32.99 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:35:27 PM PST 24
Peak memory 251164 kb
Host smart-4bd7483a-46ba-4e3a-aa54-d6a24e595ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504162882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.504162882
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.4243702352
Short name T566
Test name
Test status
Simulation time 60783122 ps
CPU time 7.16 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:15 PM PST 24
Peak memory 251144 kb
Host smart-9cd93eea-e9ff-4fac-b099-d34a27919771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243702352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.4243702352
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2453729873
Short name T885
Test name
Test status
Simulation time 25444820579 ps
CPU time 121.31 seconds
Started Jan 10 12:34:35 PM PST 24
Finished Jan 10 12:37:16 PM PST 24
Peak memory 276096 kb
Host smart-7817779b-1ac1-420f-a0b3-fffab4e607b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453729873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2453729873
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3639945318
Short name T419
Test name
Test status
Simulation time 17644411 ps
CPU time 0.92 seconds
Started Jan 10 12:34:33 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 207756 kb
Host smart-d5bc923e-7634-4fbd-8ede-43bcc0c2bb6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639945318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3639945318
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2169308999
Short name T945
Test name
Test status
Simulation time 67713340 ps
CPU time 0.93 seconds
Started Jan 10 12:34:51 PM PST 24
Finished Jan 10 12:35:33 PM PST 24
Peak memory 209588 kb
Host smart-b0779ad4-19fd-45bb-9870-094aae05ce71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169308999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2169308999
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2482975291
Short name T56
Test name
Test status
Simulation time 1194422158 ps
CPU time 10.56 seconds
Started Jan 10 12:34:52 PM PST 24
Finished Jan 10 12:35:43 PM PST 24
Peak memory 218112 kb
Host smart-98f99c77-5f71-4fec-b563-c018b5188861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482975291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2482975291
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4258414914
Short name T940
Test name
Test status
Simulation time 706026379 ps
CPU time 4.23 seconds
Started Jan 10 12:34:54 PM PST 24
Finished Jan 10 12:35:39 PM PST 24
Peak memory 209596 kb
Host smart-b107b362-05cb-4af6-899e-4a1c401182dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258414914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.4258414914
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1956268430
Short name T829
Test name
Test status
Simulation time 37530055 ps
CPU time 1.91 seconds
Started Jan 10 12:34:52 PM PST 24
Finished Jan 10 12:35:35 PM PST 24
Peak memory 218116 kb
Host smart-20cdc152-0f6c-4052-9804-55fe71645787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956268430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1956268430
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1323511450
Short name T876
Test name
Test status
Simulation time 4074854206 ps
CPU time 14.55 seconds
Started Jan 10 12:34:43 PM PST 24
Finished Jan 10 12:35:39 PM PST 24
Peak memory 219688 kb
Host smart-b2fb4289-acee-44a8-823a-b3b84b6dc87c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323511450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1323511450
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.125555760
Short name T464
Test name
Test status
Simulation time 542029785 ps
CPU time 20.46 seconds
Started Jan 10 12:34:49 PM PST 24
Finished Jan 10 12:35:51 PM PST 24
Peak memory 218032 kb
Host smart-8f8dec97-0019-492f-b635-cf1027bbaeb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125555760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.125555760
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2522688393
Short name T377
Test name
Test status
Simulation time 6496560625 ps
CPU time 12.72 seconds
Started Jan 10 12:34:45 PM PST 24
Finished Jan 10 12:35:40 PM PST 24
Peak memory 218140 kb
Host smart-bbc714af-4066-4bfa-9a2d-5ae313e759ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522688393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2522688393
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3524917707
Short name T509
Test name
Test status
Simulation time 259992202 ps
CPU time 11.03 seconds
Started Jan 10 12:34:44 PM PST 24
Finished Jan 10 12:35:37 PM PST 24
Peak memory 218132 kb
Host smart-3233fa15-7490-4668-a8cc-b4083cb32ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524917707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3524917707
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2116339866
Short name T374
Test name
Test status
Simulation time 44677266 ps
CPU time 1.67 seconds
Started Jan 10 12:34:43 PM PST 24
Finished Jan 10 12:35:26 PM PST 24
Peak memory 218176 kb
Host smart-06adacc2-2ff3-4a44-b6d0-6fd3fbdf344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116339866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2116339866
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.4132801786
Short name T972
Test name
Test status
Simulation time 608903764 ps
CPU time 31.99 seconds
Started Jan 10 12:34:52 PM PST 24
Finished Jan 10 12:36:05 PM PST 24
Peak memory 251052 kb
Host smart-f5f549a7-e5f4-4086-b7ee-17b631f94031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132801786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4132801786
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.900547789
Short name T423
Test name
Test status
Simulation time 98693967 ps
CPU time 6.15 seconds
Started Jan 10 12:34:35 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 245800 kb
Host smart-75a1745f-a889-4af9-a3bf-9215e2ab0e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900547789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.900547789
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3315875720
Short name T898
Test name
Test status
Simulation time 7277322744 ps
CPU time 143.2 seconds
Started Jan 10 12:34:53 PM PST 24
Finished Jan 10 12:37:57 PM PST 24
Peak memory 279812 kb
Host smart-c1ca69e0-ad37-4d9d-bfc5-2fa101418581
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315875720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3315875720
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1884400041
Short name T639
Test name
Test status
Simulation time 11839248 ps
CPU time 0.88 seconds
Started Jan 10 12:34:52 PM PST 24
Finished Jan 10 12:35:34 PM PST 24
Peak memory 208292 kb
Host smart-680b3d09-d62d-4f35-954a-036d205523b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884400041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1884400041
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2492655877
Short name T874
Test name
Test status
Simulation time 21128978 ps
CPU time 0.89 seconds
Started Jan 10 12:35:04 PM PST 24
Finished Jan 10 12:35:42 PM PST 24
Peak memory 208276 kb
Host smart-ed052b10-3f51-4851-95b2-79bd23106216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492655877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2492655877
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2123756246
Short name T312
Test name
Test status
Simulation time 976909764 ps
CPU time 10.06 seconds
Started Jan 10 12:34:57 PM PST 24
Finished Jan 10 12:35:48 PM PST 24
Peak memory 218084 kb
Host smart-a15495fa-09ee-4e56-994d-333106dc081d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123756246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2123756246
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2361123727
Short name T64
Test name
Test status
Simulation time 159653024 ps
CPU time 1.15 seconds
Started Jan 10 12:34:59 PM PST 24
Finished Jan 10 12:35:40 PM PST 24
Peak memory 209648 kb
Host smart-5f7bdd84-97f9-4466-af40-d8c5cd3b20cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361123727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.2361123727
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1115271708
Short name T656
Test name
Test status
Simulation time 103159582 ps
CPU time 3.86 seconds
Started Jan 10 12:35:03 PM PST 24
Finished Jan 10 12:35:45 PM PST 24
Peak memory 218092 kb
Host smart-91df3612-1d1e-4879-94ac-dc72544e96d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115271708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1115271708
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1357084572
Short name T28
Test name
Test status
Simulation time 903733768 ps
CPU time 12.23 seconds
Started Jan 10 12:34:55 PM PST 24
Finished Jan 10 12:35:48 PM PST 24
Peak memory 218084 kb
Host smart-b4cefccf-b539-4b3e-a618-154c60a30594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357084572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1357084572
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.134412174
Short name T913
Test name
Test status
Simulation time 1470564103 ps
CPU time 8.25 seconds
Started Jan 10 12:35:09 PM PST 24
Finished Jan 10 12:35:52 PM PST 24
Peak memory 218084 kb
Host smart-04142976-4fcc-430e-991d-6263eff1fe29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134412174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.134412174
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2935320575
Short name T698
Test name
Test status
Simulation time 271278104 ps
CPU time 9.05 seconds
Started Jan 10 12:35:12 PM PST 24
Finished Jan 10 12:35:55 PM PST 24
Peak memory 218008 kb
Host smart-d87921a3-5557-4fc7-b166-11ad06dabc42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935320575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2935320575
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2024280051
Short name T697
Test name
Test status
Simulation time 416350716 ps
CPU time 10.47 seconds
Started Jan 10 12:34:58 PM PST 24
Finished Jan 10 12:35:49 PM PST 24
Peak memory 218032 kb
Host smart-d71a017e-9f63-45ab-abc1-838ca6762cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024280051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2024280051
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.278992696
Short name T422
Test name
Test status
Simulation time 93409381 ps
CPU time 1.73 seconds
Started Jan 10 12:34:59 PM PST 24
Finished Jan 10 12:35:41 PM PST 24
Peak memory 213280 kb
Host smart-2c8d5fce-a383-421f-aab6-0451cc8e6618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278992696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.278992696
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3717583340
Short name T623
Test name
Test status
Simulation time 384626555 ps
CPU time 28.5 seconds
Started Jan 10 12:35:00 PM PST 24
Finished Jan 10 12:36:08 PM PST 24
Peak memory 250968 kb
Host smart-ca3351aa-2fa5-446b-b9a7-9c8dbaa5dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717583340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3717583340
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1134124340
Short name T467
Test name
Test status
Simulation time 94160751 ps
CPU time 8.02 seconds
Started Jan 10 12:34:59 PM PST 24
Finished Jan 10 12:35:47 PM PST 24
Peak memory 251072 kb
Host smart-c3da2c37-7c51-4f9f-b4f8-6097e39d8a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134124340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1134124340
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3308990706
Short name T516
Test name
Test status
Simulation time 35602771730 ps
CPU time 84.55 seconds
Started Jan 10 12:35:12 PM PST 24
Finished Jan 10 12:37:11 PM PST 24
Peak memory 275704 kb
Host smart-d81afb0e-ddf2-430e-8a6e-a381b0df8fc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308990706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3308990706
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.872357167
Short name T674
Test name
Test status
Simulation time 75320131371 ps
CPU time 426.15 seconds
Started Jan 10 12:34:58 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 292320 kb
Host smart-b83286c5-6c79-4c21-a121-ac4cb2c08352
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=872357167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.872357167
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2493984670
Short name T352
Test name
Test status
Simulation time 22284265 ps
CPU time 0.77 seconds
Started Jan 10 12:35:00 PM PST 24
Finished Jan 10 12:35:40 PM PST 24
Peak memory 207968 kb
Host smart-ee83c49e-d1c7-4f78-bfd9-ef88826b11f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493984670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2493984670
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3391992015
Short name T78
Test name
Test status
Simulation time 145914334 ps
CPU time 0.99 seconds
Started Jan 10 12:35:27 PM PST 24
Finished Jan 10 12:35:55 PM PST 24
Peak memory 209664 kb
Host smart-62ddb42d-88ca-4a95-859d-47a58ccfa600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391992015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3391992015
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2348284609
Short name T645
Test name
Test status
Simulation time 471975998 ps
CPU time 8.85 seconds
Started Jan 10 12:35:15 PM PST 24
Finished Jan 10 12:35:56 PM PST 24
Peak memory 218136 kb
Host smart-aba1c102-ecd3-4f6c-a621-c74f4e2718ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348284609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2348284609
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.697804632
Short name T930
Test name
Test status
Simulation time 434385173 ps
CPU time 2.16 seconds
Started Jan 10 12:35:08 PM PST 24
Finished Jan 10 12:35:46 PM PST 24
Peak memory 209708 kb
Host smart-053cb297-6310-4932-9e49-7caace3a7ccc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697804632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_ac
cess.697804632
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1766045274
Short name T741
Test name
Test status
Simulation time 246550487 ps
CPU time 2.78 seconds
Started Jan 10 12:35:06 PM PST 24
Finished Jan 10 12:35:46 PM PST 24
Peak memory 218096 kb
Host smart-4936f63e-d09b-43cc-baf2-bd142be6e93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766045274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1766045274
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1336694262
Short name T354
Test name
Test status
Simulation time 622972428 ps
CPU time 14.78 seconds
Started Jan 10 12:38:56 PM PST 24
Finished Jan 10 12:39:43 PM PST 24
Peak memory 218344 kb
Host smart-90f624a9-6d5d-4fa7-b0b7-f249db2be0fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336694262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1336694262
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2638658516
Short name T658
Test name
Test status
Simulation time 318732975 ps
CPU time 11.65 seconds
Started Jan 10 12:35:21 PM PST 24
Finished Jan 10 12:36:02 PM PST 24
Peak memory 217984 kb
Host smart-f30a2466-8637-49c7-9693-d1ebf7f23278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638658516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2638658516
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2492259895
Short name T634
Test name
Test status
Simulation time 560924073 ps
CPU time 7.89 seconds
Started Jan 10 12:35:10 PM PST 24
Finished Jan 10 12:35:53 PM PST 24
Peak memory 218080 kb
Host smart-f8aaf61d-1551-4309-9ca6-5f365874e1c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492259895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2492259895
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2323304071
Short name T17
Test name
Test status
Simulation time 921456042 ps
CPU time 9.99 seconds
Started Jan 10 12:35:11 PM PST 24
Finished Jan 10 12:35:55 PM PST 24
Peak memory 218180 kb
Host smart-a0df8111-7341-489f-8b6b-be07c0ead411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323304071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2323304071
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3513006471
Short name T310
Test name
Test status
Simulation time 129974040 ps
CPU time 3.94 seconds
Started Jan 10 12:35:09 PM PST 24
Finished Jan 10 12:35:48 PM PST 24
Peak memory 213600 kb
Host smart-5b5ada70-4066-43ec-8906-36659f37a9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513006471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3513006471
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3750766820
Short name T900
Test name
Test status
Simulation time 926655315 ps
CPU time 32.1 seconds
Started Jan 10 12:35:03 PM PST 24
Finished Jan 10 12:36:13 PM PST 24
Peak memory 250804 kb
Host smart-aa80cc8c-8429-4067-8f3f-c4ffd4d0d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750766820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3750766820
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1736070173
Short name T474
Test name
Test status
Simulation time 395086498 ps
CPU time 6.72 seconds
Started Jan 10 12:35:08 PM PST 24
Finished Jan 10 12:35:51 PM PST 24
Peak memory 251048 kb
Host smart-ba8122b4-b47d-46f1-8e75-0602667248a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736070173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1736070173
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2770015680
Short name T752
Test name
Test status
Simulation time 27739531 ps
CPU time 0.9 seconds
Started Jan 10 12:35:05 PM PST 24
Finished Jan 10 12:35:43 PM PST 24
Peak memory 211484 kb
Host smart-df5019c8-45f0-4a63-b22c-99bc6ee255be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770015680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2770015680
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3515839956
Short name T572
Test name
Test status
Simulation time 73742900 ps
CPU time 1.2 seconds
Started Jan 10 12:35:38 PM PST 24
Finished Jan 10 12:36:05 PM PST 24
Peak memory 209600 kb
Host smart-f41a2604-ec27-4a6f-82ba-623ee06f305b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515839956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3515839956
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.4218520145
Short name T308
Test name
Test status
Simulation time 1808010751 ps
CPU time 14 seconds
Started Jan 10 12:35:39 PM PST 24
Finished Jan 10 12:36:18 PM PST 24
Peak memory 218092 kb
Host smart-bd56c75a-be73-4c3b-9ffd-b647d8c20090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218520145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.4218520145
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.306914484
Short name T539
Test name
Test status
Simulation time 1414776159 ps
CPU time 15.16 seconds
Started Jan 10 12:35:30 PM PST 24
Finished Jan 10 12:36:12 PM PST 24
Peak memory 209536 kb
Host smart-088bf68d-1230-4d68-863a-31e821744e2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306914484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_ac
cess.306914484
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2251360468
Short name T695
Test name
Test status
Simulation time 69534283 ps
CPU time 3.3 seconds
Started Jan 10 12:35:31 PM PST 24
Finished Jan 10 12:36:01 PM PST 24
Peak memory 218076 kb
Host smart-91f47735-2221-4d39-9f0f-826b55205007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251360468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2251360468
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1271172404
Short name T748
Test name
Test status
Simulation time 1393953969 ps
CPU time 10.83 seconds
Started Jan 10 12:35:39 PM PST 24
Finished Jan 10 12:36:16 PM PST 24
Peak memory 218588 kb
Host smart-37777525-fd42-4789-8e3e-690c8abe6bf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271172404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1271172404
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.4115660198
Short name T345
Test name
Test status
Simulation time 692329464 ps
CPU time 7.05 seconds
Started Jan 10 12:35:29 PM PST 24
Finished Jan 10 12:36:03 PM PST 24
Peak memory 218020 kb
Host smart-cf06f66b-0299-4ab8-9293-e6f3f970223e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115660198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.4115660198
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3328675071
Short name T818
Test name
Test status
Simulation time 680525347 ps
CPU time 12.35 seconds
Started Jan 10 12:35:30 PM PST 24
Finished Jan 10 12:36:09 PM PST 24
Peak memory 218084 kb
Host smart-b191c217-09ac-4d05-9915-63b3e3e224f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328675071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3328675071
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4194725794
Short name T826
Test name
Test status
Simulation time 1216900345 ps
CPU time 13.74 seconds
Started Jan 10 12:35:34 PM PST 24
Finished Jan 10 12:36:14 PM PST 24
Peak memory 218072 kb
Host smart-28a0b892-8e67-450a-802b-e1e54d0bd265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194725794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4194725794
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1367700387
Short name T624
Test name
Test status
Simulation time 59986998 ps
CPU time 1.66 seconds
Started Jan 10 12:35:21 PM PST 24
Finished Jan 10 12:35:53 PM PST 24
Peak memory 213404 kb
Host smart-0b9fe066-9656-4b60-93ed-79a8118e9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367700387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1367700387
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3583023454
Short name T906
Test name
Test status
Simulation time 1477944756 ps
CPU time 38.94 seconds
Started Jan 10 12:35:39 PM PST 24
Finished Jan 10 12:36:44 PM PST 24
Peak memory 251020 kb
Host smart-0088e517-dff3-4bcd-831b-ca140e9bc45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583023454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3583023454
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3912994599
Short name T803
Test name
Test status
Simulation time 48449360 ps
CPU time 6.32 seconds
Started Jan 10 12:35:37 PM PST 24
Finished Jan 10 12:36:09 PM PST 24
Peak memory 250588 kb
Host smart-7ae656c7-ad6f-4d63-bbe7-cc154ab631bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912994599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3912994599
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1665041513
Short name T678
Test name
Test status
Simulation time 5026755235 ps
CPU time 155.19 seconds
Started Jan 10 12:35:38 PM PST 24
Finished Jan 10 12:38:39 PM PST 24
Peak memory 271884 kb
Host smart-6a899b67-5ca4-440d-95d1-463b95dfd45f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665041513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1665041513
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1598551806
Short name T857
Test name
Test status
Simulation time 32341823 ps
CPU time 0.83 seconds
Started Jan 10 12:35:30 PM PST 24
Finished Jan 10 12:35:58 PM PST 24
Peak memory 211356 kb
Host smart-ebdd7cdc-7929-4d4b-aa12-2f5b2c83c95e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598551806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1598551806
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.644661166
Short name T731
Test name
Test status
Simulation time 16164175 ps
CPU time 0.91 seconds
Started Jan 10 12:35:30 PM PST 24
Finished Jan 10 12:35:58 PM PST 24
Peak memory 209584 kb
Host smart-289f58bb-8260-4cef-ab0a-f5dfff042dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644661166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.644661166
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.322635593
Short name T39
Test name
Test status
Simulation time 1821474741 ps
CPU time 18.59 seconds
Started Jan 10 12:35:38 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 218084 kb
Host smart-fc70df09-948c-4fae-9aac-c4d1a3f6e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322635593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.322635593
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3464469613
Short name T360
Test name
Test status
Simulation time 111500420 ps
CPU time 3.38 seconds
Started Jan 10 12:35:29 PM PST 24
Finished Jan 10 12:36:00 PM PST 24
Peak memory 209640 kb
Host smart-592ed372-2ce0-4a20-9c14-5622d4d5633f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464469613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.3464469613
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3108161088
Short name T591
Test name
Test status
Simulation time 45057528 ps
CPU time 2.54 seconds
Started Jan 10 12:35:42 PM PST 24
Finished Jan 10 12:36:09 PM PST 24
Peak memory 218100 kb
Host smart-94087250-3766-4eea-a11e-60465e51e4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108161088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3108161088
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2089352850
Short name T728
Test name
Test status
Simulation time 1278350635 ps
CPU time 12.96 seconds
Started Jan 10 12:35:30 PM PST 24
Finished Jan 10 12:36:10 PM PST 24
Peak memory 219096 kb
Host smart-8420a03a-3023-428e-bb45-77640c04865d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089352850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2089352850
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2263339096
Short name T705
Test name
Test status
Simulation time 1273362459 ps
CPU time 14.78 seconds
Started Jan 10 12:35:29 PM PST 24
Finished Jan 10 12:36:11 PM PST 24
Peak memory 218128 kb
Host smart-944749b3-2485-4d9e-b957-47eb6fc3fb83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263339096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2263339096
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1496700711
Short name T643
Test name
Test status
Simulation time 1044163845 ps
CPU time 8.13 seconds
Started Jan 10 12:35:30 PM PST 24
Finished Jan 10 12:36:05 PM PST 24
Peak memory 218012 kb
Host smart-76047b1f-e28e-4734-bee4-60a64bed8a76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496700711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1496700711
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1376988808
Short name T385
Test name
Test status
Simulation time 493757826 ps
CPU time 14.42 seconds
Started Jan 10 12:35:39 PM PST 24
Finished Jan 10 12:36:19 PM PST 24
Peak memory 218088 kb
Host smart-6e0b4ce8-fc30-4607-ae74-37ee1f92e3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376988808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1376988808
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.752305380
Short name T68
Test name
Test status
Simulation time 237482557 ps
CPU time 3.83 seconds
Started Jan 10 12:35:27 PM PST 24
Finished Jan 10 12:35:58 PM PST 24
Peak memory 214072 kb
Host smart-e38b9e49-c775-4680-9791-b808a50f052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752305380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.752305380
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3244865710
Short name T716
Test name
Test status
Simulation time 1127141569 ps
CPU time 35.79 seconds
Started Jan 10 12:35:38 PM PST 24
Finished Jan 10 12:36:40 PM PST 24
Peak memory 251080 kb
Host smart-a6346e77-9cd2-41ab-9825-825837a74180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244865710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3244865710
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.4031165723
Short name T338
Test name
Test status
Simulation time 312896385 ps
CPU time 8.6 seconds
Started Jan 10 12:35:29 PM PST 24
Finished Jan 10 12:36:05 PM PST 24
Peak memory 251172 kb
Host smart-8fe18ba1-4a51-4f71-81e2-ee6d6ef080f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031165723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.4031165723
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2674820935
Short name T357
Test name
Test status
Simulation time 7684202573 ps
CPU time 246.91 seconds
Started Jan 10 12:35:39 PM PST 24
Finished Jan 10 12:40:11 PM PST 24
Peak memory 267436 kb
Host smart-ecef5142-52ea-4269-b675-bfb4f30d8478
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674820935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2674820935
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2081097498
Short name T426
Test name
Test status
Simulation time 48385275 ps
CPU time 0.91 seconds
Started Jan 10 12:35:27 PM PST 24
Finished Jan 10 12:35:55 PM PST 24
Peak memory 211320 kb
Host smart-13a68d91-6de0-4fc5-96d4-fc8bf307fe7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081097498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2081097498
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.528762610
Short name T836
Test name
Test status
Simulation time 69588366 ps
CPU time 0.91 seconds
Started Jan 10 12:35:43 PM PST 24
Finished Jan 10 12:36:08 PM PST 24
Peak memory 209924 kb
Host smart-409014d2-cdbf-4cec-af36-61859da7d601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528762610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.528762610
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2053209560
Short name T888
Test name
Test status
Simulation time 1241581529 ps
CPU time 16.96 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:39 PM PST 24
Peak memory 218048 kb
Host smart-d9fa6bc5-9550-426c-b813-1ff202be504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053209560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2053209560
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1924524499
Short name T492
Test name
Test status
Simulation time 175380503 ps
CPU time 4.86 seconds
Started Jan 10 12:35:41 PM PST 24
Finished Jan 10 12:36:11 PM PST 24
Peak memory 209560 kb
Host smart-50b0ccec-f786-4455-ab01-cff62179f78d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924524499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.1924524499
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2332528812
Short name T519
Test name
Test status
Simulation time 30739872 ps
CPU time 2.11 seconds
Started Jan 10 12:35:54 PM PST 24
Finished Jan 10 12:36:20 PM PST 24
Peak memory 218052 kb
Host smart-4b59ef16-0b48-4f0c-94a1-8a5ff5d2dc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332528812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2332528812
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1101601507
Short name T602
Test name
Test status
Simulation time 1056426631 ps
CPU time 11.04 seconds
Started Jan 10 12:35:43 PM PST 24
Finished Jan 10 12:36:19 PM PST 24
Peak memory 218088 kb
Host smart-476f19ab-81a4-4820-b11e-aadc5de4032a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101601507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1101601507
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.313646226
Short name T810
Test name
Test status
Simulation time 4359573137 ps
CPU time 15.76 seconds
Started Jan 10 12:35:53 PM PST 24
Finished Jan 10 12:36:33 PM PST 24
Peak memory 218056 kb
Host smart-858a37cb-8c69-4ea6-bf93-f3d845a5a5b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313646226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.313646226
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.729505276
Short name T65
Test name
Test status
Simulation time 1607841868 ps
CPU time 9.54 seconds
Started Jan 10 12:35:45 PM PST 24
Finished Jan 10 12:36:19 PM PST 24
Peak memory 218112 kb
Host smart-d342e16d-a53c-4549-a8ee-46498399b7d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729505276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.729505276
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2426537369
Short name T665
Test name
Test status
Simulation time 1307057211 ps
CPU time 11.71 seconds
Started Jan 10 12:35:46 PM PST 24
Finished Jan 10 12:36:21 PM PST 24
Peak memory 218072 kb
Host smart-ad62be87-2597-4174-a4b4-21ce2cd05bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426537369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2426537369
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3522500710
Short name T614
Test name
Test status
Simulation time 1862197242 ps
CPU time 3.42 seconds
Started Jan 10 12:35:31 PM PST 24
Finished Jan 10 12:36:01 PM PST 24
Peak memory 222652 kb
Host smart-02604377-5248-49c7-8a9d-74df59a49ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522500710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3522500710
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3782750028
Short name T585
Test name
Test status
Simulation time 810556671 ps
CPU time 16.42 seconds
Started Jan 10 12:35:38 PM PST 24
Finished Jan 10 12:36:20 PM PST 24
Peak memory 250992 kb
Host smart-3acaedde-70f2-4254-99e8-44c47c59693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782750028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3782750028
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.917024608
Short name T193
Test name
Test status
Simulation time 121014342 ps
CPU time 7.98 seconds
Started Jan 10 12:35:31 PM PST 24
Finished Jan 10 12:36:06 PM PST 24
Peak memory 251052 kb
Host smart-bc4b3f95-0638-421c-a737-e31b0c72d1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917024608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.917024608
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2695885361
Short name T373
Test name
Test status
Simulation time 83341126011 ps
CPU time 175.78 seconds
Started Jan 10 12:35:45 PM PST 24
Finished Jan 10 12:39:05 PM PST 24
Peak memory 283996 kb
Host smart-3bccca57-db26-4594-8046-083df8e0b7f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695885361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2695885361
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.428294563
Short name T131
Test name
Test status
Simulation time 35548933 ps
CPU time 0.73 seconds
Started Jan 10 12:35:38 PM PST 24
Finished Jan 10 12:36:04 PM PST 24
Peak memory 208076 kb
Host smart-f027f9bb-0479-43d6-afef-15dd709504b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428294563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.428294563
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3262002028
Short name T441
Test name
Test status
Simulation time 22633827 ps
CPU time 1.22 seconds
Started Jan 10 12:54:41 PM PST 24
Finished Jan 10 12:55:48 PM PST 24
Peak memory 208492 kb
Host smart-b9700d9c-beed-4f3a-830c-3a416fd17b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262002028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3262002028
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.4172736781
Short name T962
Test name
Test status
Simulation time 642084095 ps
CPU time 10.47 seconds
Started Jan 10 12:41:13 PM PST 24
Finished Jan 10 12:42:25 PM PST 24
Peak memory 218212 kb
Host smart-a8ccfde7-6811-46f4-b0d2-d4a22c8d9e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172736781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.4172736781
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2434643103
Short name T894
Test name
Test status
Simulation time 9471339156 ps
CPU time 97.23 seconds
Started Jan 10 01:02:03 PM PST 24
Finished Jan 10 01:05:15 PM PST 24
Peak memory 219544 kb
Host smart-308f1ea9-995c-4cbc-bd3e-08355027659a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434643103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2434643103
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.528469024
Short name T911
Test name
Test status
Simulation time 1173872496 ps
CPU time 11.61 seconds
Started Jan 10 12:37:54 PM PST 24
Finished Jan 10 12:38:39 PM PST 24
Peak memory 217768 kb
Host smart-8c81c9aa-04d0-41fc-b58a-ce9ab6ba67db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528469024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_p
riority.528469024
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.392310432
Short name T542
Test name
Test status
Simulation time 1630778735 ps
CPU time 12.34 seconds
Started Jan 10 12:57:50 PM PST 24
Finished Jan 10 12:59:21 PM PST 24
Peak memory 218108 kb
Host smart-02c25900-4c94-4324-a485-48dfc74f0bbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392310432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.392310432
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2345228107
Short name T311
Test name
Test status
Simulation time 5019954465 ps
CPU time 16.66 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:33 PM PST 24
Peak memory 213680 kb
Host smart-61de1253-64ba-4bb2-8b32-a8533dff9df1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345228107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2345228107
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.340919606
Short name T465
Test name
Test status
Simulation time 511068134 ps
CPU time 2.06 seconds
Started Jan 10 12:40:03 PM PST 24
Finished Jan 10 12:40:49 PM PST 24
Peak memory 212688 kb
Host smart-60d27743-24d0-47dd-9533-d82f22b19982
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340919606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.340919606
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3038310928
Short name T754
Test name
Test status
Simulation time 6790489564 ps
CPU time 65.94 seconds
Started Jan 10 12:43:35 PM PST 24
Finished Jan 10 12:45:56 PM PST 24
Peak memory 275680 kb
Host smart-7ee6da04-9b8d-4b45-865e-9505ac9d2022
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038310928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3038310928
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1870400267
Short name T424
Test name
Test status
Simulation time 1151103129 ps
CPU time 15.73 seconds
Started Jan 10 12:46:55 PM PST 24
Finished Jan 10 12:48:28 PM PST 24
Peak memory 251124 kb
Host smart-d4b76fb3-285a-4cd7-bfbc-003448036e23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870400267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1870400267
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.553463013
Short name T501
Test name
Test status
Simulation time 79336191 ps
CPU time 1.57 seconds
Started Jan 10 12:56:32 PM PST 24
Finished Jan 10 12:57:43 PM PST 24
Peak memory 218096 kb
Host smart-d9711522-8cf7-4557-a22e-dc51d3f317e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553463013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.553463013
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3832609116
Short name T630
Test name
Test status
Simulation time 3977433428 ps
CPU time 14.72 seconds
Started Jan 10 12:44:08 PM PST 24
Finished Jan 10 12:45:39 PM PST 24
Peak memory 214944 kb
Host smart-e87b8e3d-8d37-4ef2-9b2d-2f00de54e65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832609116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3832609116
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1271838212
Short name T100
Test name
Test status
Simulation time 151803817 ps
CPU time 25.46 seconds
Started Jan 10 12:41:41 PM PST 24
Finished Jan 10 12:43:13 PM PST 24
Peak memory 281420 kb
Host smart-9a0cbcd7-b9a8-4c84-9b88-d9dd6da6bc82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271838212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1271838212
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3537832872
Short name T521
Test name
Test status
Simulation time 286947466 ps
CPU time 10.21 seconds
Started Jan 10 12:50:01 PM PST 24
Finished Jan 10 12:52:06 PM PST 24
Peak memory 218112 kb
Host smart-bf5052e3-0d22-4e95-81ee-fea5b52570c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537832872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3537832872
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2466573306
Short name T581
Test name
Test status
Simulation time 3923815443 ps
CPU time 15.51 seconds
Started Jan 10 01:04:59 PM PST 24
Finished Jan 10 01:06:42 PM PST 24
Peak memory 218212 kb
Host smart-e466d6b3-f0ea-4670-b639-fa657474ff69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466573306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2466573306
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.634164383
Short name T966
Test name
Test status
Simulation time 307724374 ps
CPU time 7.18 seconds
Started Jan 10 12:44:48 PM PST 24
Finished Jan 10 12:46:13 PM PST 24
Peak memory 217956 kb
Host smart-a44faabf-5710-49cf-9c82-711bc9b0f0fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634164383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.634164383
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3118801084
Short name T53
Test name
Test status
Simulation time 881432971 ps
CPU time 8.96 seconds
Started Jan 10 12:34:52 PM PST 24
Finished Jan 10 12:35:42 PM PST 24
Peak memory 218088 kb
Host smart-abadfb1a-e264-4f0a-96ac-c1b7b3fc9d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118801084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3118801084
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3024180455
Short name T330
Test name
Test status
Simulation time 747088617 ps
CPU time 3.09 seconds
Started Jan 10 01:14:14 PM PST 24
Finished Jan 10 01:15:11 PM PST 24
Peak memory 213992 kb
Host smart-df6eca31-c67c-46c5-948f-e68954313dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024180455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3024180455
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2446370612
Short name T336
Test name
Test status
Simulation time 2218849567 ps
CPU time 20.14 seconds
Started Jan 10 12:56:25 PM PST 24
Finished Jan 10 12:57:56 PM PST 24
Peak memory 251124 kb
Host smart-938f1b59-8f36-4877-9aaf-0336fa9b7f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446370612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2446370612
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2751652624
Short name T71
Test name
Test status
Simulation time 193486888 ps
CPU time 8.12 seconds
Started Jan 10 01:12:25 PM PST 24
Finished Jan 10 01:13:55 PM PST 24
Peak memory 247096 kb
Host smart-f2cebdfc-6d62-4e29-8b05-495da0c717e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751652624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2751652624
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2246018919
Short name T638
Test name
Test status
Simulation time 29925975314 ps
CPU time 430.31 seconds
Started Jan 10 12:55:49 PM PST 24
Finished Jan 10 01:04:06 PM PST 24
Peak memory 251164 kb
Host smart-7a12ea55-4951-474f-b058-ae14def23e16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246018919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2246018919
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2800949763
Short name T29
Test name
Test status
Simulation time 73757241 ps
CPU time 1.42 seconds
Started Jan 10 01:00:24 PM PST 24
Finished Jan 10 01:02:11 PM PST 24
Peak memory 212560 kb
Host smart-b6b8317f-8e29-4a56-8d7a-ae6be2d091fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800949763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2800949763
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3342087529
Short name T390
Test name
Test status
Simulation time 28331139 ps
CPU time 0.86 seconds
Started Jan 10 12:35:53 PM PST 24
Finished Jan 10 12:36:17 PM PST 24
Peak memory 209552 kb
Host smart-56338fdc-9f1b-4333-86fa-d97738204c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342087529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3342087529
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1363257248
Short name T832
Test name
Test status
Simulation time 362062485 ps
CPU time 9.19 seconds
Started Jan 10 12:35:53 PM PST 24
Finished Jan 10 12:36:26 PM PST 24
Peak memory 218048 kb
Host smart-75ada5ab-89fc-4ca4-a198-24dcf1011822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363257248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1363257248
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2135709783
Short name T887
Test name
Test status
Simulation time 356316439 ps
CPU time 9.33 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:31 PM PST 24
Peak memory 209492 kb
Host smart-29569ce3-f928-439e-a4f0-e2b9668b3acf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135709783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.2135709783
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1352097147
Short name T573
Test name
Test status
Simulation time 31397540 ps
CPU time 2.03 seconds
Started Jan 10 12:35:41 PM PST 24
Finished Jan 10 12:36:09 PM PST 24
Peak memory 218148 kb
Host smart-f1b3d7aa-9fbf-4888-a6bd-f8a229799696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352097147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1352097147
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3502756324
Short name T671
Test name
Test status
Simulation time 1403983262 ps
CPU time 15.24 seconds
Started Jan 10 12:35:44 PM PST 24
Finished Jan 10 12:36:23 PM PST 24
Peak memory 219220 kb
Host smart-2f8a5f3e-b102-4956-9926-c19ca5d19d92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502756324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3502756324
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3829801044
Short name T378
Test name
Test status
Simulation time 234542587 ps
CPU time 10.28 seconds
Started Jan 10 12:35:47 PM PST 24
Finished Jan 10 12:36:20 PM PST 24
Peak memory 218012 kb
Host smart-4205ea9d-705e-4b1c-b931-99d9ccfd1633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829801044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3829801044
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4183562413
Short name T421
Test name
Test status
Simulation time 829125941 ps
CPU time 15.91 seconds
Started Jan 10 12:35:46 PM PST 24
Finished Jan 10 12:36:25 PM PST 24
Peak memory 218012 kb
Host smart-da1ed77d-23bb-4a3b-9e90-f078934d47f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183562413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4183562413
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1958375098
Short name T192
Test name
Test status
Simulation time 272009705 ps
CPU time 8.54 seconds
Started Jan 10 12:35:45 PM PST 24
Finished Jan 10 12:36:17 PM PST 24
Peak memory 218196 kb
Host smart-11952766-a07e-4e35-b008-df59fed685a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958375098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1958375098
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.773483708
Short name T882
Test name
Test status
Simulation time 23328248 ps
CPU time 1.74 seconds
Started Jan 10 12:35:44 PM PST 24
Finished Jan 10 12:36:10 PM PST 24
Peak memory 213468 kb
Host smart-8ae90499-ee72-4029-b751-7a24eb5c0f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773483708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.773483708
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.913931619
Short name T703
Test name
Test status
Simulation time 682685670 ps
CPU time 30.7 seconds
Started Jan 10 12:35:44 PM PST 24
Finished Jan 10 12:36:39 PM PST 24
Peak memory 251084 kb
Host smart-87a7f02e-84b4-43b3-bff2-339a7f79efc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913931619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.913931619
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.60467219
Short name T864
Test name
Test status
Simulation time 90590590 ps
CPU time 4.15 seconds
Started Jan 10 12:35:46 PM PST 24
Finished Jan 10 12:36:14 PM PST 24
Peak memory 222020 kb
Host smart-666c0025-09fb-4870-99bb-5cefaf3762d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60467219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.60467219
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2276394699
Short name T503
Test name
Test status
Simulation time 15081763552 ps
CPU time 290.82 seconds
Started Jan 10 12:35:46 PM PST 24
Finished Jan 10 12:41:00 PM PST 24
Peak memory 283840 kb
Host smart-ed9cf751-f248-4fad-a261-071897e65820
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276394699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2276394699
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2557505487
Short name T904
Test name
Test status
Simulation time 13357851 ps
CPU time 0.77 seconds
Started Jan 10 12:35:53 PM PST 24
Finished Jan 10 12:36:17 PM PST 24
Peak memory 207952 kb
Host smart-201da6e9-e9f5-4b68-be82-2e1c54e3b6fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557505487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2557505487
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1968190745
Short name T297
Test name
Test status
Simulation time 65811957 ps
CPU time 1.09 seconds
Started Jan 10 12:35:47 PM PST 24
Finished Jan 10 12:36:12 PM PST 24
Peak memory 209704 kb
Host smart-43c47816-130c-4ccc-abd4-c8dc2c34cb7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968190745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1968190745
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.329825766
Short name T324
Test name
Test status
Simulation time 1392714823 ps
CPU time 10.68 seconds
Started Jan 10 12:35:47 PM PST 24
Finished Jan 10 12:36:20 PM PST 24
Peak memory 218056 kb
Host smart-efd9ccb6-e36a-428b-a71a-36e0274d705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329825766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.329825766
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1673749226
Short name T402
Test name
Test status
Simulation time 187504138 ps
CPU time 1.42 seconds
Started Jan 10 02:03:34 PM PST 24
Finished Jan 10 02:04:01 PM PST 24
Peak memory 209612 kb
Host smart-a29b5b2b-b120-41d7-a152-026c9ec46a2a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673749226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.1673749226
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3376547480
Short name T408
Test name
Test status
Simulation time 170579666 ps
CPU time 3.81 seconds
Started Jan 10 12:35:54 PM PST 24
Finished Jan 10 12:36:21 PM PST 24
Peak memory 218048 kb
Host smart-51005775-2ed7-400e-9adb-accc1b0b687c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376547480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3376547480
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3334777334
Short name T445
Test name
Test status
Simulation time 4828618465 ps
CPU time 14.22 seconds
Started Jan 10 12:35:47 PM PST 24
Finished Jan 10 12:36:24 PM PST 24
Peak memory 219232 kb
Host smart-b6bb9365-ed64-49d6-80f0-cdf9170db950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334777334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3334777334
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2454100081
Short name T629
Test name
Test status
Simulation time 486260452 ps
CPU time 9.84 seconds
Started Jan 10 12:35:45 PM PST 24
Finished Jan 10 12:36:19 PM PST 24
Peak memory 218108 kb
Host smart-99d2fe1c-db4d-412a-a113-2856e767668a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454100081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2454100081
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1523430721
Short name T738
Test name
Test status
Simulation time 236348530 ps
CPU time 7.76 seconds
Started Jan 10 12:35:45 PM PST 24
Finished Jan 10 12:36:16 PM PST 24
Peak memory 218012 kb
Host smart-0d03dbc0-8793-44e6-b7e7-0ef07433db60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523430721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1523430721
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.546639818
Short name T821
Test name
Test status
Simulation time 1494527413 ps
CPU time 8.14 seconds
Started Jan 10 12:35:54 PM PST 24
Finished Jan 10 12:36:25 PM PST 24
Peak memory 218048 kb
Host smart-a067e28a-f3fc-4120-a179-652d2ee109d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546639818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.546639818
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2293098726
Short name T83
Test name
Test status
Simulation time 55355754 ps
CPU time 2.29 seconds
Started Jan 10 12:35:46 PM PST 24
Finished Jan 10 12:36:12 PM PST 24
Peak memory 213872 kb
Host smart-52cf6ae9-6407-4f65-9276-383f878bda8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293098726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2293098726
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2461001888
Short name T376
Test name
Test status
Simulation time 1049101779 ps
CPU time 27.9 seconds
Started Jan 10 12:35:42 PM PST 24
Finished Jan 10 12:36:35 PM PST 24
Peak memory 251128 kb
Host smart-72c5e3ed-cd0c-4919-b2b3-c4ee185e6385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461001888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2461001888
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4034961963
Short name T777
Test name
Test status
Simulation time 326797970 ps
CPU time 3.49 seconds
Started Jan 10 12:35:43 PM PST 24
Finished Jan 10 12:36:11 PM PST 24
Peak memory 222052 kb
Host smart-b9e930ac-885c-475b-b680-97ef3fa10913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034961963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4034961963
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.4192469653
Short name T952
Test name
Test status
Simulation time 940100190 ps
CPU time 19.14 seconds
Started Jan 10 12:35:43 PM PST 24
Finished Jan 10 12:36:27 PM PST 24
Peak memory 225796 kb
Host smart-1722a6e7-c191-40d4-a25d-c903a6e5f686
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192469653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.4192469653
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3807607862
Short name T946
Test name
Test status
Simulation time 15743654 ps
CPU time 0.8 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 208240 kb
Host smart-0ae7186c-c5c1-4287-80a2-5141307a8225
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807607862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3807607862
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.201256514
Short name T953
Test name
Test status
Simulation time 100319306 ps
CPU time 0.97 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:19 PM PST 24
Peak memory 209652 kb
Host smart-0c406d47-ead3-4ffd-9c8e-299aad3dd027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201256514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.201256514
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2900527107
Short name T740
Test name
Test status
Simulation time 1640205530 ps
CPU time 14.15 seconds
Started Jan 10 12:35:47 PM PST 24
Finished Jan 10 12:36:24 PM PST 24
Peak memory 218056 kb
Host smart-dbc2b09e-fe9f-47f9-ad22-e11f4236ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900527107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2900527107
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3270562578
Short name T33
Test name
Test status
Simulation time 1421414704 ps
CPU time 5.26 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:36:41 PM PST 24
Peak memory 209676 kb
Host smart-2ca31113-32b0-453b-82fd-24488548a010
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270562578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.3270562578
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.853030649
Short name T781
Test name
Test status
Simulation time 101004712 ps
CPU time 3.18 seconds
Started Jan 10 12:35:42 PM PST 24
Finished Jan 10 12:36:10 PM PST 24
Peak memory 218092 kb
Host smart-fd7423cb-e789-498b-81a1-f51de47919af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853030649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.853030649
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3909290412
Short name T322
Test name
Test status
Simulation time 448684010 ps
CPU time 13.78 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 219112 kb
Host smart-adffac8c-111b-4717-a7cc-946058d6783b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909290412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3909290412
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1305229380
Short name T589
Test name
Test status
Simulation time 222705008 ps
CPU time 8.82 seconds
Started Jan 10 12:35:57 PM PST 24
Finished Jan 10 12:36:29 PM PST 24
Peak memory 218032 kb
Host smart-ffd9d155-f024-4d1d-975a-d288b6adbcaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305229380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1305229380
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1887471986
Short name T327
Test name
Test status
Simulation time 1567885208 ps
CPU time 14.03 seconds
Started Jan 10 12:35:53 PM PST 24
Finished Jan 10 12:36:30 PM PST 24
Peak memory 217964 kb
Host smart-76b2a0af-29eb-45f7-8ce5-7a29fc26fa83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887471986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1887471986
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.306957136
Short name T550
Test name
Test status
Simulation time 294817157 ps
CPU time 7.07 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:25 PM PST 24
Peak memory 218204 kb
Host smart-32f04f84-72fe-4d6d-9e06-ff8651c1056d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306957136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.306957136
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.655174134
Short name T849
Test name
Test status
Simulation time 277741750 ps
CPU time 2.4 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:24 PM PST 24
Peak memory 213784 kb
Host smart-d0d143bf-db81-45eb-b915-489ced21949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655174134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.655174134
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.339949269
Short name T750
Test name
Test status
Simulation time 270353998 ps
CPU time 29.78 seconds
Started Jan 10 12:35:41 PM PST 24
Finished Jan 10 12:36:36 PM PST 24
Peak memory 251044 kb
Host smart-1959a7ac-cabd-43dc-9f2d-cbee4d24e924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339949269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.339949269
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3321832292
Short name T346
Test name
Test status
Simulation time 143527970 ps
CPU time 7.39 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:29 PM PST 24
Peak memory 251044 kb
Host smart-f2e9f2bf-df24-4dfd-b711-b33188c7f6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321832292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3321832292
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1381144034
Short name T400
Test name
Test status
Simulation time 539632247 ps
CPU time 16.12 seconds
Started Jan 10 12:35:52 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 251152 kb
Host smart-bce23f84-39a1-4f3a-ae61-e7793af8e051
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381144034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1381144034
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2500787720
Short name T127
Test name
Test status
Simulation time 30163290 ps
CPU time 0.74 seconds
Started Jan 10 12:35:44 PM PST 24
Finished Jan 10 12:36:09 PM PST 24
Peak memory 208324 kb
Host smart-f5f4c36a-9774-43a5-afd6-83dfa037a145
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500787720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2500787720
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3019281288
Short name T14
Test name
Test status
Simulation time 163212481 ps
CPU time 0.91 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:23 PM PST 24
Peak memory 209576 kb
Host smart-920f7407-4042-4b32-aa80-5718e0f419fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019281288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3019281288
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.232051620
Short name T434
Test name
Test status
Simulation time 237082176 ps
CPU time 10.39 seconds
Started Jan 10 12:35:52 PM PST 24
Finished Jan 10 12:36:26 PM PST 24
Peak memory 218140 kb
Host smart-029fcc48-cd9f-456e-9eef-6fdb2f01c3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232051620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.232051620
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3610758534
Short name T604
Test name
Test status
Simulation time 965705283 ps
CPU time 10.53 seconds
Started Jan 10 12:35:57 PM PST 24
Finished Jan 10 12:36:31 PM PST 24
Peak memory 217828 kb
Host smart-8fdcc70b-57d1-4928-a373-74558982c75d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610758534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.3610758534
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3302046206
Short name T554
Test name
Test status
Simulation time 77618442 ps
CPU time 3.85 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 218092 kb
Host smart-563ec395-4e98-4447-b925-8f33932b7cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302046206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3302046206
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1833649792
Short name T622
Test name
Test status
Simulation time 360272910 ps
CPU time 15.49 seconds
Started Jan 10 12:35:57 PM PST 24
Finished Jan 10 12:36:36 PM PST 24
Peak memory 219088 kb
Host smart-00656403-dc4e-46ba-8bd7-5e12b8c587e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833649792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1833649792
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1255522260
Short name T944
Test name
Test status
Simulation time 3358161831 ps
CPU time 13.98 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:39 PM PST 24
Peak memory 218088 kb
Host smart-724edc7e-b24f-4410-bf50-5f495c1af840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255522260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1255522260
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3259099081
Short name T761
Test name
Test status
Simulation time 1879355521 ps
CPU time 12.94 seconds
Started Jan 10 12:35:56 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 218028 kb
Host smart-a72be8e5-4e45-4c19-85ef-d8bfb1cd996d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259099081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3259099081
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1218653145
Short name T965
Test name
Test status
Simulation time 364315534 ps
CPU time 12.56 seconds
Started Jan 10 12:36:03 PM PST 24
Finished Jan 10 12:36:40 PM PST 24
Peak memory 218168 kb
Host smart-86b89677-c219-4538-8ad0-982770cf08cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218653145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1218653145
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1471029761
Short name T736
Test name
Test status
Simulation time 84941719 ps
CPU time 3.27 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 214180 kb
Host smart-d4f5bc7a-9afa-46f2-bd46-ef5cae06cc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471029761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1471029761
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3516616085
Short name T307
Test name
Test status
Simulation time 309325356 ps
CPU time 7.39 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:36:43 PM PST 24
Peak memory 250788 kb
Host smart-95cdcff5-0a89-476b-8b5b-72b2a778f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516616085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3516616085
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1154270620
Short name T636
Test name
Test status
Simulation time 45017000966 ps
CPU time 219.17 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:39:57 PM PST 24
Peak memory 283880 kb
Host smart-6c497c7b-c808-4991-a2f5-9b6119838eac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154270620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1154270620
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.684225578
Short name T597
Test name
Test status
Simulation time 56436049 ps
CPU time 0.88 seconds
Started Jan 10 12:35:57 PM PST 24
Finished Jan 10 12:36:21 PM PST 24
Peak memory 211388 kb
Host smart-ea4a4483-17fc-4e7c-b964-72b67c03db8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684225578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.684225578
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1216212980
Short name T852
Test name
Test status
Simulation time 40544501 ps
CPU time 1.19 seconds
Started Jan 10 12:35:56 PM PST 24
Finished Jan 10 12:36:20 PM PST 24
Peak memory 208380 kb
Host smart-57b78912-cac6-4002-86a0-18d46f422c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216212980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1216212980
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1817365282
Short name T309
Test name
Test status
Simulation time 433666497 ps
CPU time 16.79 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:38 PM PST 24
Peak memory 218188 kb
Host smart-a612f2cb-3c93-4324-be32-8eefc12a9578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817365282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1817365282
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.4287991079
Short name T8
Test name
Test status
Simulation time 773691278 ps
CPU time 18.58 seconds
Started Jan 10 12:35:57 PM PST 24
Finished Jan 10 12:36:38 PM PST 24
Peak memory 209536 kb
Host smart-f3d8bb3d-434e-429e-b7ba-11cfb4ca8009
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287991079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.4287991079
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.845881640
Short name T612
Test name
Test status
Simulation time 412229898 ps
CPU time 3.11 seconds
Started Jan 10 12:35:56 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 218068 kb
Host smart-88413c59-64a5-47f0-8d79-6cfeee822953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845881640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.845881640
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.325128353
Short name T655
Test name
Test status
Simulation time 1582122059 ps
CPU time 9 seconds
Started Jan 10 12:35:53 PM PST 24
Finished Jan 10 12:36:26 PM PST 24
Peak memory 219172 kb
Host smart-34d380d0-92e2-4716-a232-c392ce29dfe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325128353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.325128353
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2538324102
Short name T797
Test name
Test status
Simulation time 242430530 ps
CPU time 7.85 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:27 PM PST 24
Peak memory 218020 kb
Host smart-d04dfcf3-0a6a-4ac7-95fa-e117255ec891
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538324102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2538324102
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1915352444
Short name T637
Test name
Test status
Simulation time 1004529637 ps
CPU time 5.71 seconds
Started Jan 10 12:35:57 PM PST 24
Finished Jan 10 12:36:26 PM PST 24
Peak memory 218088 kb
Host smart-8916c72b-47a7-490f-8df7-2c99947f9fb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915352444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1915352444
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1967018173
Short name T522
Test name
Test status
Simulation time 4384456957 ps
CPU time 9.02 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:27 PM PST 24
Peak memory 218128 kb
Host smart-2e16e689-4028-475e-938e-fc87d02bafbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967018173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1967018173
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3312959620
Short name T129
Test name
Test status
Simulation time 126646575 ps
CPU time 7.57 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:26 PM PST 24
Peak memory 214024 kb
Host smart-e2f377d1-98a7-4e3f-bead-acbbf3444308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312959620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3312959620
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.4205553059
Short name T866
Test name
Test status
Simulation time 1438064634 ps
CPU time 26.78 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:45 PM PST 24
Peak memory 251020 kb
Host smart-7f1388eb-8209-489e-b36d-bb5f3549193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205553059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.4205553059
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3555426315
Short name T299
Test name
Test status
Simulation time 128693074 ps
CPU time 8.51 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:33 PM PST 24
Peak memory 251084 kb
Host smart-15fc7be4-78f7-49ec-97cc-2474a902939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555426315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3555426315
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2716636550
Short name T755
Test name
Test status
Simulation time 13753636180 ps
CPU time 474.13 seconds
Started Jan 10 12:36:03 PM PST 24
Finished Jan 10 12:44:22 PM PST 24
Peak memory 267624 kb
Host smart-e584800b-5d87-4416-a2a0-dce6c44c16a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716636550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2716636550
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1685427054
Short name T471
Test name
Test status
Simulation time 96113065 ps
CPU time 0.93 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:36:37 PM PST 24
Peak memory 209548 kb
Host smart-9b289431-6e5f-416e-addc-0fd1769b364e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685427054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1685427054
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3070475374
Short name T865
Test name
Test status
Simulation time 2145478326 ps
CPU time 12.21 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:34 PM PST 24
Peak memory 218048 kb
Host smart-10a3b282-1f6b-48ab-bdfd-93ff29a5bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070475374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3070475374
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1274816390
Short name T538
Test name
Test status
Simulation time 2325065063 ps
CPU time 3.2 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:24 PM PST 24
Peak memory 209580 kb
Host smart-ae417fae-fbac-4f73-934c-8eb1220ad108
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274816390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.1274816390
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.4281991284
Short name T295
Test name
Test status
Simulation time 508261811 ps
CPU time 5.11 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:30 PM PST 24
Peak memory 218088 kb
Host smart-87db3700-97b1-474e-90e0-beb424dcade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281991284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.4281991284
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.753373022
Short name T802
Test name
Test status
Simulation time 268189151 ps
CPU time 11.64 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:36:46 PM PST 24
Peak memory 218184 kb
Host smart-0743ab4b-2e08-4824-ac14-2d618277ccd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753373022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.753373022
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1051543331
Short name T646
Test name
Test status
Simulation time 393391221 ps
CPU time 14.01 seconds
Started Jan 10 12:36:08 PM PST 24
Finished Jan 10 12:36:51 PM PST 24
Peak memory 218124 kb
Host smart-47fb3bf5-dbee-4930-b22e-b1e940bb9511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051543331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1051543331
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2682534724
Short name T939
Test name
Test status
Simulation time 238137596 ps
CPU time 7.91 seconds
Started Jan 10 12:35:52 PM PST 24
Finished Jan 10 12:36:24 PM PST 24
Peak memory 218032 kb
Host smart-eb48e7b5-e6c5-4188-a81f-7642f99def77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682534724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2682534724
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.4202406519
Short name T862
Test name
Test status
Simulation time 1375172288 ps
CPU time 12.24 seconds
Started Jan 10 12:35:52 PM PST 24
Finished Jan 10 12:36:28 PM PST 24
Peak memory 218188 kb
Host smart-7c344ad7-acbb-40de-9958-c945f261dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202406519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.4202406519
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.642598430
Short name T654
Test name
Test status
Simulation time 16223799 ps
CPU time 1.07 seconds
Started Jan 10 12:35:52 PM PST 24
Finished Jan 10 12:36:16 PM PST 24
Peak memory 211732 kb
Host smart-e853247b-fc8c-4dab-b3c3-e727cb9e62e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642598430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.642598430
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.191380393
Short name T300
Test name
Test status
Simulation time 335968937 ps
CPU time 31.04 seconds
Started Jan 10 12:35:57 PM PST 24
Finished Jan 10 12:36:52 PM PST 24
Peak memory 251052 kb
Host smart-cbd44e2c-a613-4e75-b7e5-8190d20271ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191380393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.191380393
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.823298404
Short name T389
Test name
Test status
Simulation time 170827843 ps
CPU time 9.29 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:36:45 PM PST 24
Peak memory 251004 kb
Host smart-5e2a25ed-0344-4600-8b2c-7bc64fbae582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823298404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.823298404
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1666778638
Short name T525
Test name
Test status
Simulation time 6118709913 ps
CPU time 177.76 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:39:34 PM PST 24
Peak memory 247364 kb
Host smart-1c3172c5-93b0-41cb-92e9-e7d52448a816
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666778638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1666778638
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3160555672
Short name T60
Test name
Test status
Simulation time 127604841810 ps
CPU time 4200.85 seconds
Started Jan 10 12:35:57 PM PST 24
Finished Jan 10 01:46:26 PM PST 24
Peak memory 922972 kb
Host smart-b319ec6e-171c-43d7-9093-073b70ede7b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3160555672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.3160555672
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1602033747
Short name T785
Test name
Test status
Simulation time 11812565 ps
CPU time 0.89 seconds
Started Jan 10 12:35:59 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 208180 kb
Host smart-ee9543a3-d86f-456e-9ad7-943694dff7a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602033747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1602033747
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.39132810
Short name T675
Test name
Test status
Simulation time 20756717 ps
CPU time 0.89 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:19 PM PST 24
Peak memory 208228 kb
Host smart-1ce63521-8c8a-4018-b88d-1ced48ca60b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39132810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.39132810
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1800051271
Short name T817
Test name
Test status
Simulation time 664223396 ps
CPU time 3.6 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:28 PM PST 24
Peak memory 209876 kb
Host smart-cdd51833-dcae-47ab-ac92-d1fc9527ffae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800051271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_a
ccess.1800051271
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1857273624
Short name T789
Test name
Test status
Simulation time 97334245 ps
CPU time 2.66 seconds
Started Jan 10 12:36:05 PM PST 24
Finished Jan 10 12:36:33 PM PST 24
Peak memory 218056 kb
Host smart-e46bb951-5915-4630-89f0-58b45ed8ce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857273624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1857273624
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1082196785
Short name T486
Test name
Test status
Simulation time 306459205 ps
CPU time 9.29 seconds
Started Jan 10 12:36:06 PM PST 24
Finished Jan 10 12:36:42 PM PST 24
Peak memory 218084 kb
Host smart-0900d98f-88d0-4a63-8c89-bad17b00a74e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082196785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1082196785
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1598510
Short name T195
Test name
Test status
Simulation time 261590890 ps
CPU time 10.09 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:31 PM PST 24
Peak memory 218036 kb
Host smart-ad8a2283-9294-40df-91f7-44f8ab748797
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_dige
st.1598510
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2078715796
Short name T729
Test name
Test status
Simulation time 6020830024 ps
CPU time 9.55 seconds
Started Jan 10 12:36:00 PM PST 24
Finished Jan 10 12:36:34 PM PST 24
Peak memory 218404 kb
Host smart-e4635aeb-ac74-4655-8932-d9a3364ec0a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078715796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2078715796
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3790029495
Short name T871
Test name
Test status
Simulation time 699759400 ps
CPU time 8.55 seconds
Started Jan 10 12:36:05 PM PST 24
Finished Jan 10 12:36:39 PM PST 24
Peak memory 218064 kb
Host smart-4acc92b1-8cdf-498a-b2f0-15e59f8c8ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790029495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3790029495
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2034561600
Short name T40
Test name
Test status
Simulation time 99220923 ps
CPU time 3.27 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 213892 kb
Host smart-2c21ff62-fa28-4785-bd86-78f944ae7a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034561600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2034561600
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1938682235
Short name T571
Test name
Test status
Simulation time 1263499022 ps
CPU time 29.18 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:50 PM PST 24
Peak memory 251024 kb
Host smart-10774dee-6b06-430d-87e8-b7bf2f210f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938682235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1938682235
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3234446960
Short name T767
Test name
Test status
Simulation time 83350140 ps
CPU time 4.1 seconds
Started Jan 10 12:36:08 PM PST 24
Finished Jan 10 12:36:40 PM PST 24
Peak memory 222300 kb
Host smart-f16d480f-aa81-4618-ae88-09efb1c00e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234446960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3234446960
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2431903082
Short name T55
Test name
Test status
Simulation time 64489360 ps
CPU time 0.93 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 212352 kb
Host smart-cf46ffcd-b1cb-403d-8125-128fb3b173e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431903082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2431903082
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1100746511
Short name T950
Test name
Test status
Simulation time 24038380 ps
CPU time 0.92 seconds
Started Jan 10 12:36:05 PM PST 24
Finished Jan 10 12:36:33 PM PST 24
Peak memory 209560 kb
Host smart-2f3fef61-2102-4060-a73e-45b75941bf42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100746511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1100746511
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1179728000
Short name T488
Test name
Test status
Simulation time 316965070 ps
CPU time 11.98 seconds
Started Jan 10 12:36:04 PM PST 24
Finished Jan 10 12:36:40 PM PST 24
Peak memory 218168 kb
Host smart-566ea9bb-9ba2-4e6c-9483-ce98b0715bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179728000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1179728000
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1233734576
Short name T847
Test name
Test status
Simulation time 172540802 ps
CPU time 2.62 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:21 PM PST 24
Peak memory 209620 kb
Host smart-66b5d051-2bcf-49f4-b0ca-815055a7f5e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233734576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_a
ccess.1233734576
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1058159596
Short name T867
Test name
Test status
Simulation time 126229811 ps
CPU time 3.43 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:24 PM PST 24
Peak memory 218096 kb
Host smart-04a2173a-a713-4b0a-928b-1875b28cda1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058159596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1058159596
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2085119098
Short name T16
Test name
Test status
Simulation time 742933525 ps
CPU time 11.68 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:33 PM PST 24
Peak memory 219128 kb
Host smart-2f8e850d-5197-4f1f-b9d9-71bc9411041c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085119098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2085119098
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1332657618
Short name T653
Test name
Test status
Simulation time 970518518 ps
CPU time 8.09 seconds
Started Jan 10 12:36:05 PM PST 24
Finished Jan 10 12:36:40 PM PST 24
Peak memory 217996 kb
Host smart-8393b976-af75-468f-a133-d13f6b6a62f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332657618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1332657618
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2853679273
Short name T693
Test name
Test status
Simulation time 295856645 ps
CPU time 6.52 seconds
Started Jan 10 12:36:05 PM PST 24
Finished Jan 10 12:36:39 PM PST 24
Peak memory 218000 kb
Host smart-8172bf1e-df18-408f-91ab-cb0f477a06ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853679273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2853679273
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2293253019
Short name T382
Test name
Test status
Simulation time 330887924 ps
CPU time 8.07 seconds
Started Jan 10 12:36:02 PM PST 24
Finished Jan 10 12:36:34 PM PST 24
Peak memory 218060 kb
Host smart-196d3a16-3e94-4bf3-8d96-bdf9af8e475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293253019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2293253019
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2488671378
Short name T67
Test name
Test status
Simulation time 58539948 ps
CPU time 2.19 seconds
Started Jan 10 12:35:55 PM PST 24
Finished Jan 10 12:36:20 PM PST 24
Peak memory 214064 kb
Host smart-53357946-291a-46fa-abf3-10e0eb46cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488671378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2488671378
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2788298901
Short name T649
Test name
Test status
Simulation time 903508993 ps
CPU time 28.63 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:53 PM PST 24
Peak memory 251092 kb
Host smart-7039fb9e-f60d-4789-9b98-71c8ab408818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788298901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2788298901
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.981492262
Short name T689
Test name
Test status
Simulation time 203171383 ps
CPU time 10.31 seconds
Started Jan 10 12:36:02 PM PST 24
Finished Jan 10 12:36:36 PM PST 24
Peak memory 251360 kb
Host smart-5df3dc2f-7d6a-4826-9817-9dc2060568a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981492262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.981492262
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1629443299
Short name T838
Test name
Test status
Simulation time 1022344386 ps
CPU time 38.83 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:37:04 PM PST 24
Peak memory 251096 kb
Host smart-99e1e34c-0ab9-49a5-89cc-72733f5fb6cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629443299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1629443299
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3839674019
Short name T967
Test name
Test status
Simulation time 216959295 ps
CPU time 0.87 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:25 PM PST 24
Peak memory 211708 kb
Host smart-ee75d98f-93c0-458f-a0d3-f0dccddb86b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839674019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3839674019
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1667270126
Short name T553
Test name
Test status
Simulation time 57580384 ps
CPU time 1.07 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:36:36 PM PST 24
Peak memory 209572 kb
Host smart-689a6703-b46b-46e8-8de5-ccc7350d44f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667270126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1667270126
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1951828469
Short name T523
Test name
Test status
Simulation time 1953364655 ps
CPU time 14.45 seconds
Started Jan 10 12:36:09 PM PST 24
Finished Jan 10 12:36:53 PM PST 24
Peak memory 218088 kb
Host smart-621bee65-5d4a-4c2e-a9af-b9bd97ecd4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951828469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1951828469
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1145682669
Short name T588
Test name
Test status
Simulation time 1123073530 ps
CPU time 8.21 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 209560 kb
Host smart-feb329d3-89bf-47c3-acf6-f00d0d51dbb3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145682669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.1145682669
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2803132601
Short name T677
Test name
Test status
Simulation time 130426121 ps
CPU time 1.65 seconds
Started Jan 10 12:36:06 PM PST 24
Finished Jan 10 12:36:34 PM PST 24
Peak memory 218060 kb
Host smart-c68f2e9f-06c4-4712-b082-8a0385103b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803132601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2803132601
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3687812441
Short name T58
Test name
Test status
Simulation time 699696212 ps
CPU time 21.81 seconds
Started Jan 10 12:36:02 PM PST 24
Finished Jan 10 12:36:48 PM PST 24
Peak memory 219204 kb
Host smart-7ccb657d-1a25-49e7-b30f-298a760fb3bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687812441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3687812441
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1593182462
Short name T580
Test name
Test status
Simulation time 523673002 ps
CPU time 20.18 seconds
Started Jan 10 12:36:06 PM PST 24
Finished Jan 10 12:36:53 PM PST 24
Peak memory 218092 kb
Host smart-59ddc057-5a7d-4dea-8621-895bbff65499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593182462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1593182462
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1035245066
Short name T544
Test name
Test status
Simulation time 619942676 ps
CPU time 8.89 seconds
Started Jan 10 12:36:13 PM PST 24
Finished Jan 10 12:36:53 PM PST 24
Peak memory 218112 kb
Host smart-15ccd0b1-3d91-4fec-906d-0239b5843efe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035245066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1035245066
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4254361395
Short name T435
Test name
Test status
Simulation time 1215741605 ps
CPU time 8.65 seconds
Started Jan 10 12:35:59 PM PST 24
Finished Jan 10 12:36:31 PM PST 24
Peak memory 218052 kb
Host smart-99a080ea-c1f5-4fc2-bd40-a8825df3c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254361395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4254361395
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2117705001
Short name T824
Test name
Test status
Simulation time 37035058 ps
CPU time 1.13 seconds
Started Jan 10 12:36:00 PM PST 24
Finished Jan 10 12:36:25 PM PST 24
Peak memory 213088 kb
Host smart-25d1db22-f406-4332-9cad-89155109fb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117705001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2117705001
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4174888754
Short name T370
Test name
Test status
Simulation time 894695696 ps
CPU time 27.54 seconds
Started Jan 10 12:36:04 PM PST 24
Finished Jan 10 12:36:57 PM PST 24
Peak memory 251068 kb
Host smart-488d81e7-8209-40a6-86f7-c3f6cd5befe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174888754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4174888754
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1220401842
Short name T551
Test name
Test status
Simulation time 117743971 ps
CPU time 2.89 seconds
Started Jan 10 12:36:00 PM PST 24
Finished Jan 10 12:36:27 PM PST 24
Peak memory 221932 kb
Host smart-2125238a-9a5c-4d09-a0a3-9b8e47bb0f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220401842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1220401842
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2101100862
Short name T531
Test name
Test status
Simulation time 32184883647 ps
CPU time 110.05 seconds
Started Jan 10 12:36:09 PM PST 24
Finished Jan 10 12:38:28 PM PST 24
Peak memory 274416 kb
Host smart-51ddb484-b4b5-4639-b748-f42efabbf255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101100862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2101100862
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3487565643
Short name T46
Test name
Test status
Simulation time 45237406 ps
CPU time 0.72 seconds
Started Jan 10 12:35:58 PM PST 24
Finished Jan 10 12:36:22 PM PST 24
Peak memory 207852 kb
Host smart-c664cba8-7254-4f95-909e-93214bffb2ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487565643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3487565643
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.522760091
Short name T505
Test name
Test status
Simulation time 191021002 ps
CPU time 1.07 seconds
Started Jan 10 12:36:02 PM PST 24
Finished Jan 10 12:36:27 PM PST 24
Peak memory 209584 kb
Host smart-009ff718-4683-4f24-b4ce-a653ccb62946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522760091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.522760091
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3160099310
Short name T524
Test name
Test status
Simulation time 277233988 ps
CPU time 9.8 seconds
Started Jan 10 12:36:10 PM PST 24
Finished Jan 10 12:36:50 PM PST 24
Peak memory 218092 kb
Host smart-67a3eed6-bc81-44e1-8097-067f0af49688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160099310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3160099310
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2421387357
Short name T778
Test name
Test status
Simulation time 271178983 ps
CPU time 3.35 seconds
Started Jan 10 12:36:10 PM PST 24
Finished Jan 10 12:36:50 PM PST 24
Peak memory 209620 kb
Host smart-86f30c8a-37e2-44bf-bb9a-0b69a5ef2443
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421387357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_a
ccess.2421387357
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3042779439
Short name T799
Test name
Test status
Simulation time 298203865 ps
CPU time 2.8 seconds
Started Jan 10 12:36:04 PM PST 24
Finished Jan 10 12:36:31 PM PST 24
Peak memory 218164 kb
Host smart-63f287af-330f-49e4-b388-b53501198f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042779439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3042779439
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1209241791
Short name T933
Test name
Test status
Simulation time 1234206139 ps
CPU time 11.5 seconds
Started Jan 10 12:36:02 PM PST 24
Finished Jan 10 12:36:38 PM PST 24
Peak memory 218332 kb
Host smart-6b8f75b6-9d87-4744-a57f-372445199483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209241791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1209241791
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.842405585
Short name T558
Test name
Test status
Simulation time 331137280 ps
CPU time 9.66 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:34 PM PST 24
Peak memory 218032 kb
Host smart-9b9b33dc-312a-4457-a95e-11da8887bc98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842405585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.842405585
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2043053185
Short name T909
Test name
Test status
Simulation time 397363051 ps
CPU time 8.38 seconds
Started Jan 10 12:36:00 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 218008 kb
Host smart-465c6892-4448-494c-a17a-99d23a9e95ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043053185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2043053185
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.865546473
Short name T820
Test name
Test status
Simulation time 1375174670 ps
CPU time 12.79 seconds
Started Jan 10 12:36:10 PM PST 24
Finished Jan 10 12:36:52 PM PST 24
Peak memory 218156 kb
Host smart-51ac804f-7a8f-4e73-8ddb-a7f4641868e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865546473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.865546473
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4117137490
Short name T605
Test name
Test status
Simulation time 42755707 ps
CPU time 1.25 seconds
Started Jan 10 12:36:07 PM PST 24
Finished Jan 10 12:36:36 PM PST 24
Peak memory 213056 kb
Host smart-97b34ac1-db1e-41fe-94aa-c5c125a60cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117137490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4117137490
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3099034713
Short name T337
Test name
Test status
Simulation time 318369301 ps
CPU time 27.28 seconds
Started Jan 10 12:36:04 PM PST 24
Finished Jan 10 12:36:57 PM PST 24
Peak memory 250912 kb
Host smart-33047520-7e3c-4a02-a129-72b3a5558984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099034713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3099034713
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2670482523
Short name T3
Test name
Test status
Simulation time 113038046 ps
CPU time 6.46 seconds
Started Jan 10 12:36:02 PM PST 24
Finished Jan 10 12:36:33 PM PST 24
Peak memory 243976 kb
Host smart-e444a6ed-eb35-4346-b7a0-2644ad812814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670482523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2670482523
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2793936069
Short name T949
Test name
Test status
Simulation time 8202789175 ps
CPU time 120.21 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:38:25 PM PST 24
Peak memory 251132 kb
Host smart-c8e1500c-df92-4789-b366-32574550b0bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793936069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2793936069
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1358672489
Short name T815
Test name
Test status
Simulation time 15817361 ps
CPU time 0.78 seconds
Started Jan 10 12:36:06 PM PST 24
Finished Jan 10 12:36:33 PM PST 24
Peak memory 208184 kb
Host smart-acb981bc-ca60-4e02-a480-d08e666bdb16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358672489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1358672489
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1758788008
Short name T644
Test name
Test status
Simulation time 71738224 ps
CPU time 1.08 seconds
Started Jan 10 12:42:35 PM PST 24
Finished Jan 10 12:43:50 PM PST 24
Peak memory 209572 kb
Host smart-98226298-503a-4153-bdbb-f7e063a05a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758788008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1758788008
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.664194952
Short name T823
Test name
Test status
Simulation time 578196600 ps
CPU time 14.86 seconds
Started Jan 10 12:50:06 PM PST 24
Finished Jan 10 12:51:54 PM PST 24
Peak memory 218236 kb
Host smart-ca0f2756-6870-4e84-91d5-9cd507656ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664194952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.664194952
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1647160091
Short name T863
Test name
Test status
Simulation time 1130977860 ps
CPU time 3.14 seconds
Started Jan 10 12:46:02 PM PST 24
Finished Jan 10 12:47:25 PM PST 24
Peak memory 209644 kb
Host smart-6f36bb55-565f-4c0e-839f-fc48ace2f825
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647160091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ac
cess.1647160091
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1551486616
Short name T647
Test name
Test status
Simulation time 4470552907 ps
CPU time 49.83 seconds
Started Jan 10 12:40:09 PM PST 24
Finished Jan 10 12:41:45 PM PST 24
Peak memory 217952 kb
Host smart-3c3a6d45-e707-471e-8421-4fb02eaa298b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551486616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.1551486616
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1134635545
Short name T601
Test name
Test status
Simulation time 724624950 ps
CPU time 10.3 seconds
Started Jan 10 12:50:05 PM PST 24
Finished Jan 10 12:52:02 PM PST 24
Peak memory 218112 kb
Host smart-2159175e-ce78-4ba4-9dd4-09f5dc0a000e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134635545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1134635545
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1814773094
Short name T608
Test name
Test status
Simulation time 1318458472 ps
CPU time 36.99 seconds
Started Jan 10 12:45:20 PM PST 24
Finished Jan 10 12:47:19 PM PST 24
Peak memory 213196 kb
Host smart-d953a9d3-6429-4405-97e0-9ef00a255be8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814773094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1814773094
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4177989139
Short name T565
Test name
Test status
Simulation time 2005858363 ps
CPU time 3.34 seconds
Started Jan 10 12:43:10 PM PST 24
Finished Jan 10 12:44:26 PM PST 24
Peak memory 212960 kb
Host smart-84f780a7-0e52-44ee-94ae-991c96f5cc41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177989139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
4177989139
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2042513599
Short name T714
Test name
Test status
Simulation time 11579272130 ps
CPU time 52.32 seconds
Started Jan 10 12:51:56 PM PST 24
Finished Jan 10 12:54:05 PM PST 24
Peak memory 278792 kb
Host smart-9513aa33-4fb5-4984-a69c-ec572ae61a26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042513599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2042513599
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2049277487
Short name T784
Test name
Test status
Simulation time 779972623 ps
CPU time 17.37 seconds
Started Jan 10 12:42:58 PM PST 24
Finished Jan 10 12:44:29 PM PST 24
Peak memory 251144 kb
Host smart-a0cbd4bb-3ea3-4e4f-bbf9-8851951a4031
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049277487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2049277487
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3126671476
Short name T814
Test name
Test status
Simulation time 69860596 ps
CPU time 3.33 seconds
Started Jan 10 12:44:33 PM PST 24
Finished Jan 10 12:45:54 PM PST 24
Peak memory 218188 kb
Host smart-877b4954-d356-4f41-8128-21e0a34fc1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126671476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3126671476
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1921700599
Short name T446
Test name
Test status
Simulation time 1332717136 ps
CPU time 5.16 seconds
Started Jan 10 12:46:38 PM PST 24
Finished Jan 10 12:47:56 PM PST 24
Peak memory 213972 kb
Host smart-0f8506aa-8c70-4e29-a929-57103f7ae9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921700599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1921700599
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3801277761
Short name T780
Test name
Test status
Simulation time 277319053 ps
CPU time 14.26 seconds
Started Jan 10 12:35:26 PM PST 24
Finished Jan 10 12:36:07 PM PST 24
Peak memory 218172 kb
Host smart-f3252372-8772-462a-99a8-907cbb211d0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801277761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3801277761
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2193910716
Short name T458
Test name
Test status
Simulation time 1672340651 ps
CPU time 16.65 seconds
Started Jan 10 12:40:16 PM PST 24
Finished Jan 10 12:41:21 PM PST 24
Peak memory 217908 kb
Host smart-20937d05-949b-4dd8-9171-9127fbf65fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193910716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2193910716
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3969639057
Short name T907
Test name
Test status
Simulation time 404734976 ps
CPU time 10.37 seconds
Started Jan 10 12:37:49 PM PST 24
Finished Jan 10 12:38:34 PM PST 24
Peak memory 218036 kb
Host smart-89cfa0a6-ba91-4c7d-a99d-a75f5a480186
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969639057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
969639057
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1661205218
Short name T892
Test name
Test status
Simulation time 1335291433 ps
CPU time 11.28 seconds
Started Jan 10 12:46:26 PM PST 24
Finished Jan 10 12:48:01 PM PST 24
Peak memory 218192 kb
Host smart-a8228be8-5a39-43b2-a5b1-c8a1c176c535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661205218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1661205218
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3882873930
Short name T795
Test name
Test status
Simulation time 64668291 ps
CPU time 2.08 seconds
Started Jan 10 01:13:06 PM PST 24
Finished Jan 10 01:14:35 PM PST 24
Peak memory 213736 kb
Host smart-6243c466-8166-461a-a9dc-c5b5e18b365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882873930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3882873930
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1081105164
Short name T332
Test name
Test status
Simulation time 995613332 ps
CPU time 23.81 seconds
Started Jan 10 01:18:50 PM PST 24
Finished Jan 10 01:19:16 PM PST 24
Peak memory 251068 kb
Host smart-1dad9884-eb9a-4261-b1f7-ba524c5163a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081105164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1081105164
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.240767978
Short name T708
Test name
Test status
Simulation time 321806548 ps
CPU time 5.89 seconds
Started Jan 10 12:40:23 PM PST 24
Finished Jan 10 12:41:16 PM PST 24
Peak memory 250932 kb
Host smart-99541922-23f7-4db4-b317-1ebf97ba6f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240767978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.240767978
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3076578541
Short name T42
Test name
Test status
Simulation time 21988944 ps
CPU time 0.9 seconds
Started Jan 10 12:44:06 PM PST 24
Finished Jan 10 12:45:22 PM PST 24
Peak memory 208252 kb
Host smart-6f128634-4b4d-4cb7-bca4-39c854c37eb1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076578541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3076578541
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.312540631
Short name T880
Test name
Test status
Simulation time 112313210 ps
CPU time 1.15 seconds
Started Jan 10 12:39:28 PM PST 24
Finished Jan 10 12:39:59 PM PST 24
Peak memory 209604 kb
Host smart-d1cd064b-4d2f-45d4-b6ca-390ead0eb762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312540631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.312540631
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3144953567
Short name T296
Test name
Test status
Simulation time 51463823 ps
CPU time 0.75 seconds
Started Jan 10 12:52:15 PM PST 24
Finished Jan 10 12:53:31 PM PST 24
Peak memory 209368 kb
Host smart-e4c54728-6974-454b-a352-b171beab9114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144953567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3144953567
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.323910632
Short name T830
Test name
Test status
Simulation time 248677990 ps
CPU time 11.22 seconds
Started Jan 10 01:33:21 PM PST 24
Finished Jan 10 01:33:44 PM PST 24
Peak memory 218156 kb
Host smart-3867e629-2128-4ca8-87de-6a76272234cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323910632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.323910632
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2023289758
Short name T596
Test name
Test status
Simulation time 843189949 ps
CPU time 3.13 seconds
Started Jan 10 12:38:19 PM PST 24
Finished Jan 10 12:38:57 PM PST 24
Peak memory 209576 kb
Host smart-8a0e3576-2d32-4c0c-b5a1-4d6c0b0b9a85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023289758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.2023289758
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2415729834
Short name T713
Test name
Test status
Simulation time 223757564 ps
CPU time 5.86 seconds
Started Jan 10 12:40:43 PM PST 24
Finished Jan 10 12:41:34 PM PST 24
Peak memory 217912 kb
Host smart-446bda64-901a-47f6-806c-0feeb68f1e6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415729834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.2415729834
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3089249795
Short name T872
Test name
Test status
Simulation time 2284700827 ps
CPU time 15.04 seconds
Started Jan 10 12:48:36 PM PST 24
Finished Jan 10 12:50:15 PM PST 24
Peak memory 218172 kb
Host smart-9f206c8c-96cd-4ef6-959c-91e682f815ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089249795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3089249795
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2319106203
Short name T480
Test name
Test status
Simulation time 3114894356 ps
CPU time 16.13 seconds
Started Jan 10 12:43:55 PM PST 24
Finished Jan 10 12:45:26 PM PST 24
Peak memory 213404 kb
Host smart-0a35587f-7e90-499b-8e5a-f3f443ce8f09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319106203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2319106203
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1879654918
Short name T657
Test name
Test status
Simulation time 1359165591 ps
CPU time 17.03 seconds
Started Jan 10 12:49:28 PM PST 24
Finished Jan 10 12:51:20 PM PST 24
Peak memory 213220 kb
Host smart-8f439fd8-7358-4060-833e-be691a2a56c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879654918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1879654918
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3392656176
Short name T321
Test name
Test status
Simulation time 2484394683 ps
CPU time 89.69 seconds
Started Jan 10 12:46:31 PM PST 24
Finished Jan 10 12:49:27 PM PST 24
Peak memory 279308 kb
Host smart-7183471c-a64d-460d-b5a2-3ff6703c1200
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392656176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3392656176
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.556362143
Short name T381
Test name
Test status
Simulation time 987700121 ps
CPU time 27.93 seconds
Started Jan 10 12:51:11 PM PST 24
Finished Jan 10 12:53:15 PM PST 24
Peak memory 225028 kb
Host smart-1fdf9b64-a800-469d-a54b-caa5b2b3d54e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556362143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.556362143
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1616662197
Short name T411
Test name
Test status
Simulation time 45886365 ps
CPU time 2.54 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:41 PM PST 24
Peak memory 218184 kb
Host smart-74f22965-2720-4435-87c2-9722b22ae113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616662197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1616662197
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2073105053
Short name T691
Test name
Test status
Simulation time 431239106 ps
CPU time 8.46 seconds
Started Jan 10 12:45:03 PM PST 24
Finished Jan 10 12:46:34 PM PST 24
Peak memory 213528 kb
Host smart-8611d462-515f-4528-b114-6aae6270869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073105053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2073105053
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3947278740
Short name T298
Test name
Test status
Simulation time 669693477 ps
CPU time 13.21 seconds
Started Jan 10 12:43:41 PM PST 24
Finished Jan 10 12:45:09 PM PST 24
Peak memory 218164 kb
Host smart-be03d7d9-3781-4756-b23c-860b12620959
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947278740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3947278740
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2934217787
Short name T901
Test name
Test status
Simulation time 393470223 ps
CPU time 9.39 seconds
Started Jan 10 12:53:50 PM PST 24
Finished Jan 10 12:55:09 PM PST 24
Peak memory 218152 kb
Host smart-9af3394f-4648-4182-bbfd-b7bd367712da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934217787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2934217787
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2275432206
Short name T375
Test name
Test status
Simulation time 1131779880 ps
CPU time 10.95 seconds
Started Jan 10 12:48:52 PM PST 24
Finished Jan 10 12:50:31 PM PST 24
Peak memory 218112 kb
Host smart-fd0c18d2-8b1f-4302-827a-95afd3af8469
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275432206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
275432206
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3421421731
Short name T822
Test name
Test status
Simulation time 831426885 ps
CPU time 9.64 seconds
Started Jan 10 12:44:21 PM PST 24
Finished Jan 10 12:45:47 PM PST 24
Peak memory 218048 kb
Host smart-dd756cb3-c7ca-4c19-b1f7-bb624ae8cf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421421731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3421421731
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2256163231
Short name T470
Test name
Test status
Simulation time 73929715 ps
CPU time 3.52 seconds
Started Jan 10 12:37:39 PM PST 24
Finished Jan 10 12:38:18 PM PST 24
Peak memory 214176 kb
Host smart-467acb5c-5439-42e4-9a1e-dc69fc75fab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256163231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2256163231
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.483325514
Short name T711
Test name
Test status
Simulation time 774273176 ps
CPU time 17.73 seconds
Started Jan 10 12:46:32 PM PST 24
Finished Jan 10 12:48:04 PM PST 24
Peak memory 251020 kb
Host smart-b745f5ae-c9a8-4e9d-9b7d-4d6832207344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483325514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.483325514
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.405794837
Short name T460
Test name
Test status
Simulation time 510704147 ps
CPU time 7.14 seconds
Started Jan 10 12:46:11 PM PST 24
Finished Jan 10 12:47:37 PM PST 24
Peak memory 251136 kb
Host smart-be2556f8-c0d6-4d7d-b28f-0958dfaaf5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405794837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.405794837
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2476559490
Short name T805
Test name
Test status
Simulation time 41357478111 ps
CPU time 283.82 seconds
Started Jan 10 12:39:40 PM PST 24
Finished Jan 10 12:44:53 PM PST 24
Peak memory 277744 kb
Host smart-a483d7d0-b1a2-4cfc-850e-d7559110be06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476559490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2476559490
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4247394709
Short name T652
Test name
Test status
Simulation time 37187796 ps
CPU time 0.85 seconds
Started Jan 10 12:54:36 PM PST 24
Finished Jan 10 12:55:42 PM PST 24
Peak memory 208352 kb
Host smart-18ac8b9d-1af8-4765-8979-d59a15426bd3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247394709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4247394709
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1261922424
Short name T335
Test name
Test status
Simulation time 15581725 ps
CPU time 1.06 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 208384 kb
Host smart-9280f5af-229d-422c-a87a-fcf607250310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261922424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1261922424
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1556499667
Short name T495
Test name
Test status
Simulation time 22430810 ps
CPU time 0.91 seconds
Started Jan 10 01:08:49 PM PST 24
Finished Jan 10 01:10:02 PM PST 24
Peak memory 209444 kb
Host smart-72a6c0ab-a253-496b-b5cf-2f5aac483930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556499667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1556499667
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1206043544
Short name T811
Test name
Test status
Simulation time 522887463 ps
CPU time 17.11 seconds
Started Jan 10 12:44:06 PM PST 24
Finished Jan 10 12:45:38 PM PST 24
Peak memory 218064 kb
Host smart-974b8425-1d74-4b5f-b26d-ac61e84c972e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206043544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1206043544
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3090339690
Short name T586
Test name
Test status
Simulation time 296713815 ps
CPU time 1.66 seconds
Started Jan 10 12:44:57 PM PST 24
Finished Jan 10 12:46:20 PM PST 24
Peak memory 209560 kb
Host smart-4d9ebd5c-e6a7-4089-8605-2b60d9ed7284
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090339690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.3090339690
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2277096223
Short name T925
Test name
Test status
Simulation time 1336165347 ps
CPU time 40.1 seconds
Started Jan 10 01:16:08 PM PST 24
Finished Jan 10 01:17:16 PM PST 24
Peak memory 218124 kb
Host smart-84109b63-4338-4534-a5fa-9f173422d73b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277096223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2277096223
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.659533370
Short name T383
Test name
Test status
Simulation time 416267198 ps
CPU time 5.6 seconds
Started Jan 10 12:40:19 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 217788 kb
Host smart-49639289-7de9-4e2d-8fe1-536b6161bad5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659533370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_p
riority.659533370
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.609585388
Short name T725
Test name
Test status
Simulation time 193157413 ps
CPU time 1.92 seconds
Started Jan 10 12:37:25 PM PST 24
Finished Jan 10 12:38:02 PM PST 24
Peak memory 218008 kb
Host smart-3b0908b6-b907-4c7b-a43b-19686a858f44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609585388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.609585388
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.744414209
Short name T563
Test name
Test status
Simulation time 3467651200 ps
CPU time 10.79 seconds
Started Jan 10 12:56:29 PM PST 24
Finished Jan 10 12:57:49 PM PST 24
Peak memory 213536 kb
Host smart-a09393d1-2eb0-46d8-b873-45f418dcec65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744414209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.744414209
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2831419943
Short name T418
Test name
Test status
Simulation time 54823841 ps
CPU time 1.3 seconds
Started Jan 10 12:44:07 PM PST 24
Finished Jan 10 12:45:27 PM PST 24
Peak memory 212380 kb
Host smart-0bc66af9-a0eb-4cad-a875-fe7a15c0f121
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831419943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2831419943
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.71810508
Short name T386
Test name
Test status
Simulation time 2911298491 ps
CPU time 61.84 seconds
Started Jan 10 12:37:40 PM PST 24
Finished Jan 10 12:39:17 PM PST 24
Peak memory 277048 kb
Host smart-630c288d-0f53-4dc4-b259-9cf4d284c4f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71810508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
state_failure.71810508
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.797176717
Short name T562
Test name
Test status
Simulation time 318854188 ps
CPU time 11.88 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 251068 kb
Host smart-2a01484d-ad80-44ba-96f8-3db7cef78e09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797176717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.797176717
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1062673812
Short name T679
Test name
Test status
Simulation time 93322275 ps
CPU time 2.92 seconds
Started Jan 10 12:45:38 PM PST 24
Finished Jan 10 12:46:59 PM PST 24
Peak memory 218180 kb
Host smart-5b606413-ed9c-49c3-bb92-fa6c0cf40830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062673812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1062673812
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.448691077
Short name T590
Test name
Test status
Simulation time 438595003 ps
CPU time 12.61 seconds
Started Jan 10 12:44:24 PM PST 24
Finished Jan 10 12:45:53 PM PST 24
Peak memory 213884 kb
Host smart-4155aad6-a7bf-4f0e-86b4-804003d00777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448691077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.448691077
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2320423535
Short name T344
Test name
Test status
Simulation time 1120220625 ps
CPU time 12.14 seconds
Started Jan 10 12:52:04 PM PST 24
Finished Jan 10 12:53:32 PM PST 24
Peak memory 218008 kb
Host smart-aaf4f606-127f-4ca0-9b00-cceb89b83cc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320423535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2320423535
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2616648790
Short name T916
Test name
Test status
Simulation time 1779819921 ps
CPU time 15.74 seconds
Started Jan 10 01:21:02 PM PST 24
Finished Jan 10 01:21:21 PM PST 24
Peak memory 218156 kb
Host smart-f6e55e7d-c9e4-477b-93e5-68a0007c2882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616648790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2616648790
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.180900609
Short name T947
Test name
Test status
Simulation time 459432014 ps
CPU time 9.34 seconds
Started Jan 10 01:03:51 PM PST 24
Finished Jan 10 01:05:12 PM PST 24
Peak memory 218132 kb
Host smart-17d0328a-29f1-410f-8354-4fa0ccb063b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180900609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.180900609
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1636333055
Short name T87
Test name
Test status
Simulation time 301309894 ps
CPU time 8.18 seconds
Started Jan 10 12:40:48 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 218004 kb
Host smart-8f343e79-f17e-45d3-a5e0-9d8940b8eec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636333055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1636333055
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2042363547
Short name T52
Test name
Test status
Simulation time 193983970 ps
CPU time 1.92 seconds
Started Jan 10 12:43:35 PM PST 24
Finished Jan 10 12:44:52 PM PST 24
Peak memory 213940 kb
Host smart-5aaeb109-721c-4c1c-b340-8e7e63aa941a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042363547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2042363547
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1785023488
Short name T497
Test name
Test status
Simulation time 378005497 ps
CPU time 33.43 seconds
Started Jan 10 12:47:08 PM PST 24
Finished Jan 10 12:49:15 PM PST 24
Peak memory 251032 kb
Host smart-edb7212c-8ab5-4f8c-b216-5989fe9fcb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785023488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1785023488
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.93639949
Short name T841
Test name
Test status
Simulation time 157794891 ps
CPU time 9.68 seconds
Started Jan 10 12:45:22 PM PST 24
Finished Jan 10 12:46:55 PM PST 24
Peak memory 251164 kb
Host smart-21342b19-8e51-4066-b8e4-d53ee53e76e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93639949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.93639949
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1732260120
Short name T6
Test name
Test status
Simulation time 17554092579 ps
CPU time 104.07 seconds
Started Jan 10 12:39:55 PM PST 24
Finished Jan 10 12:42:17 PM PST 24
Peak memory 251252 kb
Host smart-3132af1f-c754-46f1-b704-80de0aa35f67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732260120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1732260120
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1889585625
Short name T50
Test name
Test status
Simulation time 14371098 ps
CPU time 0.89 seconds
Started Jan 10 12:39:29 PM PST 24
Finished Jan 10 12:40:00 PM PST 24
Peak memory 208364 kb
Host smart-cbdfeb58-f0d1-46a3-922a-836c7f291e73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889585625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1889585625
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3313118188
Short name T15
Test name
Test status
Simulation time 18751289 ps
CPU time 0.88 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:05 PM PST 24
Peak memory 209604 kb
Host smart-0dddf0dc-fa86-4158-af38-2f88dd05d2dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313118188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3313118188
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2753051846
Short name T51
Test name
Test status
Simulation time 356151353 ps
CPU time 12.33 seconds
Started Jan 10 12:49:14 PM PST 24
Finished Jan 10 12:50:59 PM PST 24
Peak memory 218156 kb
Host smart-3fcff92c-7c79-4937-b9ba-3e7c1beb6570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753051846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2753051846
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2461699227
Short name T500
Test name
Test status
Simulation time 384322358 ps
CPU time 4.8 seconds
Started Jan 10 12:34:01 PM PST 24
Finished Jan 10 12:34:39 PM PST 24
Peak memory 209512 kb
Host smart-778f6120-4367-481f-b36b-e5bae333b5f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461699227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.2461699227
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2772085732
Short name T319
Test name
Test status
Simulation time 1382048523 ps
CPU time 42.9 seconds
Started Jan 10 12:34:33 PM PST 24
Finished Jan 10 12:35:56 PM PST 24
Peak memory 218112 kb
Host smart-a93c0836-7cfa-432a-a17f-df6d3ab0a67a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772085732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2772085732
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2936780827
Short name T773
Test name
Test status
Simulation time 523964987 ps
CPU time 3.89 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:39 PM PST 24
Peak memory 209408 kb
Host smart-94aa0e16-17ed-405b-a811-a2b5e0982e66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936780827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.2936780827
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.112638113
Short name T405
Test name
Test status
Simulation time 604434983 ps
CPU time 6.62 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:54 PM PST 24
Peak memory 218000 kb
Host smart-f6ada439-9f68-4af3-9df0-ab15960d0cfc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112638113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.112638113
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4029483635
Short name T367
Test name
Test status
Simulation time 4485149329 ps
CPU time 24.28 seconds
Started Jan 10 12:34:05 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 213556 kb
Host smart-13e92823-4efc-497a-bca9-7d43429af813
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029483635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4029483635
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3898247870
Short name T416
Test name
Test status
Simulation time 161469404 ps
CPU time 5.09 seconds
Started Jan 10 01:07:59 PM PST 24
Finished Jan 10 01:09:27 PM PST 24
Peak memory 213200 kb
Host smart-e11cd1de-a025-450a-bc43-b0765529e618
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898247870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3898247870
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3226272253
Short name T853
Test name
Test status
Simulation time 2849677153 ps
CPU time 60.5 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:36:11 PM PST 24
Peak memory 251112 kb
Host smart-0321c63f-67b4-4f15-aa3a-6d3e1f18894f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226272253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3226272253
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3190264087
Short name T936
Test name
Test status
Simulation time 508740120 ps
CPU time 19.55 seconds
Started Jan 10 12:34:01 PM PST 24
Finished Jan 10 12:34:54 PM PST 24
Peak memory 250984 kb
Host smart-4bed9b2c-ce5f-4d3b-acb9-a8b8231f37ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190264087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3190264087
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2117816699
Short name T766
Test name
Test status
Simulation time 20844847 ps
CPU time 1.48 seconds
Started Jan 10 12:40:57 PM PST 24
Finished Jan 10 12:41:54 PM PST 24
Peak memory 218136 kb
Host smart-749c6f37-ee43-4fd1-b1da-f3bd65a737e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117816699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2117816699
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.415453488
Short name T85
Test name
Test status
Simulation time 493035197 ps
CPU time 17.13 seconds
Started Jan 10 12:49:59 PM PST 24
Finished Jan 10 12:51:50 PM PST 24
Peak memory 214104 kb
Host smart-4139687d-e75e-44e1-a3d6-80fb39f0dd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415453488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.415453488
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3090503081
Short name T819
Test name
Test status
Simulation time 1091389305 ps
CPU time 15.43 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:11 PM PST 24
Peak memory 219176 kb
Host smart-7a6cbbac-6af7-4b12-8969-282a5cf5966d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090503081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3090503081
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2254536048
Short name T398
Test name
Test status
Simulation time 1202200956 ps
CPU time 8.66 seconds
Started Jan 10 12:34:06 PM PST 24
Finished Jan 10 12:34:45 PM PST 24
Peak memory 218008 kb
Host smart-6abfecb6-aeed-4f84-8f14-b0d32fde86d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254536048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2254536048
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1502832635
Short name T641
Test name
Test status
Simulation time 302965311 ps
CPU time 9.6 seconds
Started Jan 10 12:39:04 PM PST 24
Finished Jan 10 12:39:45 PM PST 24
Peak memory 218064 kb
Host smart-c6b509c6-bb54-42d7-bacb-b19a2894114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502832635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1502832635
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1551325484
Short name T427
Test name
Test status
Simulation time 48713781 ps
CPU time 2.03 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:34:56 PM PST 24
Peak memory 213624 kb
Host smart-f702e076-2b4e-4916-b532-edd77fe7a23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551325484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1551325484
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.4064554654
Short name T702
Test name
Test status
Simulation time 373386276 ps
CPU time 28.52 seconds
Started Jan 10 12:50:04 PM PST 24
Finished Jan 10 12:52:08 PM PST 24
Peak memory 251116 kb
Host smart-650b258e-19f5-4a05-b254-0db656a29f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064554654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.4064554654
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.856837855
Short name T326
Test name
Test status
Simulation time 300490690 ps
CPU time 6.51 seconds
Started Jan 10 01:40:00 PM PST 24
Finished Jan 10 01:40:08 PM PST 24
Peak memory 250588 kb
Host smart-3009144d-740d-4d5f-9815-7154d01cc5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856837855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.856837855
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2043069069
Short name T963
Test name
Test status
Simulation time 12260537611 ps
CPU time 109.67 seconds
Started Jan 10 12:34:12 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 251556 kb
Host smart-e5b1a83a-ea0a-41b8-a7ae-9d6e25f9c24b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043069069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2043069069
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2755950521
Short name T709
Test name
Test status
Simulation time 13344452 ps
CPU time 0.81 seconds
Started Jan 10 01:04:11 PM PST 24
Finished Jan 10 01:05:30 PM PST 24
Peak memory 208012 kb
Host smart-ff279810-20f1-4e4e-b5d0-512dfb21a1ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755950521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2755950521
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2700142653
Short name T79
Test name
Test status
Simulation time 17404705 ps
CPU time 0.87 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:04 PM PST 24
Peak memory 209572 kb
Host smart-b8950007-305a-43c8-97ef-d7361b12ca54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700142653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2700142653
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3538164569
Short name T189
Test name
Test status
Simulation time 21341936 ps
CPU time 0.78 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 208988 kb
Host smart-adff30d8-1eb6-4ba2-90b6-8a7a6690443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538164569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3538164569
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.899180249
Short name T776
Test name
Test status
Simulation time 315487878 ps
CPU time 10.07 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 218148 kb
Host smart-5eeb3649-170c-4056-a185-e21621169d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899180249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.899180249
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3771899007
Short name T511
Test name
Test status
Simulation time 378177746 ps
CPU time 4.12 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:19 PM PST 24
Peak memory 209880 kb
Host smart-719fb46a-cd9c-43ad-b321-cdd6325a76b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771899007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.3771899007
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3832047729
Short name T788
Test name
Test status
Simulation time 1101230913 ps
CPU time 32.33 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:40 PM PST 24
Peak memory 217992 kb
Host smart-6d28c8b8-7dde-4ff5-a0db-defe8f3b8484
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832047729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3832047729
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2734098493
Short name T757
Test name
Test status
Simulation time 252366754 ps
CPU time 4.22 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:09 PM PST 24
Peak memory 209724 kb
Host smart-9f76f806-564e-4984-8a78-1b19acbdd72e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734098493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
priority.2734098493
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.74880380
Short name T779
Test name
Test status
Simulation time 369225669 ps
CPU time 6.04 seconds
Started Jan 10 12:34:33 PM PST 24
Finished Jan 10 12:35:19 PM PST 24
Peak memory 218020 kb
Host smart-5d45bdad-f58c-4823-a81d-095977255451
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74880380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_p
rog_failure.74880380
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2951239638
Short name T364
Test name
Test status
Simulation time 3592204210 ps
CPU time 28.34 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:43 PM PST 24
Peak memory 213992 kb
Host smart-38721fb6-c586-48cf-beab-1d4cedaf02b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951239638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2951239638
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1391839642
Short name T4
Test name
Test status
Simulation time 344161143 ps
CPU time 3.2 seconds
Started Jan 10 12:34:34 PM PST 24
Finished Jan 10 12:35:17 PM PST 24
Peak memory 212944 kb
Host smart-12050b75-3161-4f86-8378-d85c681250f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391839642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1391839642
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.800412693
Short name T442
Test name
Test status
Simulation time 11857957716 ps
CPU time 103.15 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:36:40 PM PST 24
Peak memory 280104 kb
Host smart-a3c459ea-6c6b-419a-9677-baa5d02a07d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800412693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.800412693
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.811127050
Short name T529
Test name
Test status
Simulation time 951747002 ps
CPU time 14.76 seconds
Started Jan 10 12:34:30 PM PST 24
Finished Jan 10 12:35:23 PM PST 24
Peak memory 250256 kb
Host smart-59929a25-fb73-42a0-abdf-b93be6075b15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811127050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.811127050
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2025906992
Short name T929
Test name
Test status
Simulation time 188591862 ps
CPU time 2.65 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 218056 kb
Host smart-31c4e112-4464-4b8f-8dd5-2297753fd0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025906992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2025906992
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2442501912
Short name T363
Test name
Test status
Simulation time 1244398294 ps
CPU time 20.85 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 214096 kb
Host smart-f9da981f-e4b3-47ab-bb85-8d75d363d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442501912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2442501912
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3273871517
Short name T618
Test name
Test status
Simulation time 1048269948 ps
CPU time 15.49 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:18 PM PST 24
Peak memory 218148 kb
Host smart-87a78568-e3d4-4362-9177-6486b10c0906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273871517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3273871517
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.493511502
Short name T415
Test name
Test status
Simulation time 424699224 ps
CPU time 10.87 seconds
Started Jan 10 12:34:20 PM PST 24
Finished Jan 10 12:35:04 PM PST 24
Peak memory 218152 kb
Host smart-10374214-602d-4375-a1cf-564cef5ea467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493511502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.493511502
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2814218002
Short name T365
Test name
Test status
Simulation time 3369763073 ps
CPU time 10.61 seconds
Started Jan 10 12:34:33 PM PST 24
Finished Jan 10 12:35:23 PM PST 24
Peak memory 218400 kb
Host smart-c0a855d6-5f70-4b93-94e1-2056ea3eb966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814218002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
814218002
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1263676591
Short name T717
Test name
Test status
Simulation time 225100996 ps
CPU time 9.98 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 218056 kb
Host smart-407075de-ba60-4b14-bf36-a7e981b8a673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263676591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1263676591
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2771985309
Short name T80
Test name
Test status
Simulation time 138559514 ps
CPU time 1.14 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 213164 kb
Host smart-2c02692e-f6c0-4164-85b7-99bef43cbb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771985309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2771985309
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3980489934
Short name T89
Test name
Test status
Simulation time 2236353687 ps
CPU time 15.92 seconds
Started Jan 10 12:34:19 PM PST 24
Finished Jan 10 12:35:08 PM PST 24
Peak memory 251188 kb
Host smart-9180dfe0-4e68-48a2-be55-2ad3b57a7b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980489934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3980489934
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4047770347
Short name T681
Test name
Test status
Simulation time 76854771 ps
CPU time 7.45 seconds
Started Jan 10 12:34:14 PM PST 24
Finished Jan 10 12:34:52 PM PST 24
Peak memory 247984 kb
Host smart-89b7fe8f-ee79-4173-a0c4-57f6a0f25e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047770347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4047770347
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.455689475
Short name T469
Test name
Test status
Simulation time 2670861719 ps
CPU time 17.56 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:20 PM PST 24
Peak memory 251056 kb
Host smart-7e3caed8-6465-401e-a0c3-6ce09d27d484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455689475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.455689475
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3687714616
Short name T893
Test name
Test status
Simulation time 41306976 ps
CPU time 0.75 seconds
Started Jan 10 12:34:10 PM PST 24
Finished Jan 10 12:34:41 PM PST 24
Peak memory 208304 kb
Host smart-83f70fbd-2a54-46ea-8366-4b39880e1d02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687714616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3687714616
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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