cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | lc_ctrl_smoke | 7.570s | 126.647us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 1.040s | 18.042us | 5 | 5 | 100.00 |
| V1 | csr_rw | lc_ctrl_csr_rw | 1.090s | 17.160us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 1.970s | 54.014us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | lc_ctrl_csr_aliasing | 1.300s | 27.679us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 1.970s | 80.680us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 1.090s | 17.160us | 20 | 20 | 100.00 |
| lc_ctrl_csr_aliasing | 1.300s | 27.679us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | state_post_trans | lc_ctrl_state_post_trans | 10.420s | 304.767us | 50 | 50 | 100.00 |
| V2 | regwen_during_op | lc_ctrl_regwen_during_op | 20.850s | 1.244ms | 10 | 10 | 100.00 |
| V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0.910s | 22.431us | 10 | 10 | 100.00 |
| V2 | lc_prog_failure | lc_ctrl_prog_failure | 5.110s | 508.262us | 50 | 50 | 100.00 |
| V2 | lc_state_failure | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| V2 | lc_errors | lc_ctrl_errors | 24.590s | 647.464us | 49 | 50 | 98.00 |
| V2 | security_escalation | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_prog_failure | 5.110s | 508.262us | 50 | 50 | 100.00 | ||
| lc_ctrl_errors | 24.590s | 647.464us | 49 | 50 | 98.00 | ||
| lc_ctrl_security_escalation | 17.250s | 544.038us | 50 | 50 | 100.00 | ||
| lc_ctrl_jtag_state_failure | 1.904m | 14.676ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_prog_failure | 19.030s | 714.628us | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_errors | 1.621m | 9.471ms | 18 | 20 | 90.00 | ||
| V2 | jtag_access | lc_ctrl_jtag_smoke | 17.030s | 1.359ms | 20 | 20 | 100.00 |
| lc_ctrl_jtag_state_post_trans | 27.930s | 987.700us | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_prog_failure | 19.030s | 714.628us | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_errors | 1.621m | 9.471ms | 18 | 20 | 90.00 | ||
| lc_ctrl_jtag_access | 18.580s | 773.691us | 49 | 50 | 98.00 | ||
| lc_ctrl_jtag_regwen_during_op | 36.990s | 1.318ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_hw_reset | 4.830s | 411.913us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_rw | 2.240s | 298.571us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_bit_bash | 44.110s | 4.140ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_aliasing | 15.610s | 700.675us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_same_csr_outstanding | 1.920s | 46.339us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 1.990s | 155.970us | 9 | 10 | 90.00 | ||
| lc_ctrl_jtag_alert_test | 1.860s | 262.714us | 10 | 10 | 100.00 | ||
| V2 | jtag_priority | lc_ctrl_jtag_priority | 49.830s | 4.471ms | 10 | 10 | 100.00 |
| V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 1.420s | 73.757us | 50 | 50 | 100.00 |
| V2 | stress_all | lc_ctrl_stress_all | 10.727m | 46.319ms | 49 | 50 | 98.00 |
| V2 | alert_test | lc_ctrl_alert_test | 1.270s | 50.113us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 5.440s | 631.688us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 5.440s | 631.688us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 1.040s | 18.042us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.090s | 17.160us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.300s | 27.679us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 1.770s | 156.762us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 1.040s | 18.042us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.090s | 17.160us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.300s | 27.679us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 1.770s | 156.762us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 694 | 700 | 99.14 | |||
| V2S | tl_intg_err | lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 |
| lc_ctrl_tl_intg_err | 4.440s | 112.841us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 4.440s | 112.841us | 20 | 20 | 100.00 |
| V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 20.850s | 1.244ms | 10 | 10 | 100.00 |
| V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 38.940s | 1.478ms | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 35.180s | 417.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 17.250s | 544.038us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 10.420s | 304.767us | 50 | 50 | 100.00 |
| lc_ctrl_jtag_state_post_trans | 27.930s | 987.700us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 21.810s | 699.696us | 50 | 50 | 100.00 |
| V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 21.810s | 699.696us | 50 | 50 | 100.00 |
| V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 23.290s | 4.909ms | 50 | 50 | 100.00 |
| V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 15.910s | 829.126us | 48 | 50 | 96.00 |
| V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 15.910s | 829.126us | 48 | 50 | 96.00 |
| V2S | TOTAL | 173 | 175 | 98.86 | |||
| V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 1.421h | 50.903ms | 7 | 50 | 14.00 |
| V3 | TOTAL | 7 | 50 | 14.00 | |||
| TOTAL | 979 | 1030 | 95.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 27 | 27 | 22 | 81.48 |
| V2S | 5 | 5 | 4 | 80.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.37 | 97.29 | 95.88 | 91.98 | 100.00 | 96.13 | 98.48 | 94.82 |
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 25 failures:
1.lc_ctrl_stress_all_with_rand_reset.70525799835134732720570809936451478189645582035019451719176668548514943863440
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:bf904437-90b0-4580-9382-e9e7d4054b7e
7.lc_ctrl_stress_all_with_rand_reset.103211761449250252084561706356851984820760230060029131012737313444622363302787
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a05d24ea-0a93-4d34-b134-74d7ec5ee09b
... and 23 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
0.lc_ctrl_stress_all_with_rand_reset.82894816276179874823046079589804003434508293189103504797862952013791613694365
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d955a360-4f9d-4916-ba46-7a3ac1e0ae47
2.lc_ctrl_stress_all_with_rand_reset.24499005806271160458560359507267384998432101990318240801222353104364401512836
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9a83fa42-9c21-4f11-9e9c-23343c3509b1
... and 6 more failures.
10.lc_ctrl_sec_token_mux.91445902347783406317538690766994713326841605304680727221120542753000387171582
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_sec_token_mux/latest/run.log
Job ID: smart:bcfc3a37-549a-42db-bbfa-140e4db8decf
Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:
Test lc_ctrl_sec_token_mux has 1 failures.
2.lc_ctrl_sec_token_mux.74182631287863653314921928918446072136905483169807227190225024194250670016074
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_sec_token_mux/latest/run.log
[make]: simulate
cd /workspace/2.lc_ctrl_sec_token_mux/latest && /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842625610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2842625610
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test lc_ctrl_jtag_access has 1 failures.
4.lc_ctrl_jtag_access.78298845478789296965596650338120047148470482736149259371529162071374717632466
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_jtag_access/latest/run.log
[make]: simulate
cd /workspace/4.lc_ctrl_jtag_access/latest && /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040277970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4040277970
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test lc_ctrl_jtag_errors has 2 failures.
5.lc_ctrl_jtag_errors.100658546706697221824678530795350590375142657761902730713064461291503697588826
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_jtag_errors/latest/run.log
[make]: simulate
cd /workspace/5.lc_ctrl_jtag_errors/latest && /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718415962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_errors.1718415962
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
6.lc_ctrl_jtag_errors.84592249934376211294428225985462750197948506529227891252916565339266283667487
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_jtag_errors/latest/run.log
[make]: simulate
cd /workspace/6.lc_ctrl_jtag_errors/latest && /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864381983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_errors.2864381983
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test lc_ctrl_stress_all has 1 failures.
19.lc_ctrl_stress_all.28992919440149094439860091460399171738806032459089086349397345195486275108072
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/19.lc_ctrl_stress_all/latest/run.log
[make]: simulate
cd /workspace/19.lc_ctrl_stress_all/latest && /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585277160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.3585277160
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 5 failures:
3.lc_ctrl_stress_all_with_rand_reset.88560136393336086098923602745964886132501972770748399689473590205224097321739
Line 17420, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 81361890293 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xc4c7b200
UVM_INFO @ 81361890293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.lc_ctrl_stress_all_with_rand_reset.18120593302689088343430289436490390318930411948060505759708619639656163199890
Line 7964, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2827323339 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x1bca3400
UVM_INFO @ 2827323339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
14.lc_ctrl_stress_all_with_rand_reset.57988431148807374086720717997162127215671726609113614532946547685425277840126
Line 10254, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16634684564 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 16634684564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.lc_ctrl_stress_all_with_rand_reset.70934626955566851336003786155038673068888994105000368104374150183960892092117
Line 14028, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 85024727468 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 85024727468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:743) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:
Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
28.lc_ctrl_stress_all_with_rand_reset.36159164590320361949781552633011470512037743837573877480230059595330111025733
Line 18384, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9577900788 ps: (lc_ctrl_errors_vseq.sv:743) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9577900788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test lc_ctrl_errors has 1 failures.
46.lc_ctrl_errors.33191005583589073317986960341803568344216361131459433724469212355237445849155
Line 849, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/46.lc_ctrl_errors/latest/run.log
UVM_ERROR @ 242468339 ps: (lc_ctrl_errors_vseq.sv:743) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 242468339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.80917736052165634180589262267452999736143646148158237583535658264311870294497
Line 334, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 155970370 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
UVM_INFO @ 155970370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * has 1 failures:
9.lc_ctrl_stress_all_with_rand_reset.19475425797944672354669043289237926493806038456737152022455304811477195499447
Line 794, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 738744154 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0
UVM_INFO @ 738744154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'lc_ctrl_pkg::lc_tx_test_false_strict(lc_clk_byp_req_o)' has 1 failures:
18.lc_ctrl_stress_all_with_rand_reset.14603395999794071263944710601667529175282939344703378902393719919527053224811
Line 369, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Offending 'lc_ctrl_pkg::lc_tx_test_false_strict(lc_clk_byp_req_o)'
UVM_ERROR @ 4374194890 ps: (lc_ctrl_fsm.sv:826) [ASSERT FAILED] NoClkBypInProdStates_A
UVM_INFO @ 4374194890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---