Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65441478

1

T1

4011

T90

1162

T91

2301

auto[1]

1263481

1

T1

297

T2

396

T10

10350

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65440075

1

T1

3813

T90

1162

T91

2301

auto[1]

1264884

1

T1

495

T2

693

T10

9812

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5745231	1			T1	786		T90	88		T91	87
auto[IdleSt]	16405003	1			T1	1670		T90	1074		T91	2214
auto[ClkMuxSt]	28598	1			T1	8		T2	68		T3	16
auto[CntIncrSt]	28394	1			T1	8		T2	68		T3	16
auto[CntProgSt]	1408731	1			T1	25		T2	5141		T3	425
auto[TransCheckSt]	22519	1			T2	51		T3	16		T9	1
auto[TokenHashSt]	19264991	1			T2	472		T3	355		T9	64
auto[FlashRmaSt]	21740	1			T2	47		T3	67		T9	1
auto[TokenCheck0St]	9892	1			T2	16		T3	16		T9	1
auto[TokenCheck1St]	7102	1			T2	9		T3	16		T9	1
auto[TransProgSt]	272259	1			T2	1057		T3	523		T9	21
auto[PostTransSt]	9391570	1			T1	696		T2	10573		T3	5773
auto[ScrapSt]	170868	1			T107	125		T108	950		T154	64
auto[EscalateSt]	5471243	1			T1	1115		T2	1501		T10	13631
auto[InvalidSt]	8455337	1			T5	123631		T13	5433		T28	613

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1481	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	8455337	1			T5	123631		T13	5433		T28	613
EscalateSt	5471243	1			T1	1115		T2	1501		T10	13631
ScrapSt	170868	1			T107	125		T108	950		T154	64
PostTransSt	9391570	1			T1	696		T2	10573		T3	5773
TransProgSt	272259	1			T2	1057		T3	523		T9	21
TokenCheck1St	7102	1			T2	9		T3	16		T9	1
TokenCheck0St	9892	1			T2	16		T3	16		T9	1
FlashRmaSt	21740	1			T2	47		T3	67		T9	1
TokenHashSt	19264991	1			T2	472		T3	355		T9	64
TransCheckSt	22519	1			T2	51		T3	16		T9	1
CntProgSt	1408731	1			T1	25		T2	5141		T3	425
CntIncrSt	28394	1			T1	8		T2	68		T3	16
ClkMuxSt	28598	1			T1	8		T2	68		T3	16
IdleSt	16405003	1			T1	1670		T90	1074		T91	2214
ResetSt	5745231	1			T1	786		T90	88		T91	87
arcs[ResetSt=>IdleSt]	43307	1			T1	9		T90	1		T91	1
arcs[IdleSt=>ScrapSt]	221	1			T107	1		T108	2		T154	1
arcs[IdleSt=>ClkMuxSt]	28462	1			T1	8		T2	68		T3	16
arcs[ClkMuxSt=>CntIncrSt]	28394	1			T1	8		T2	68		T3	16
arcs[CntIncrSt=>PostTransSt]	1312	1			T2	6		T36	10		T20	26
arcs[CntIncrSt=>CntProgSt]	27025	1			T1	8		T2	62		T3	16
arcs[CntProgSt=>PostTransSt]	3404	1			T1	8		T2	11		T36	8
arcs[CntProgSt=>TransCheckSt]	22519	1			T2	51		T3	16		T9	1
arcs[TransCheckSt=>PostTransSt]	3224	1			T2	8		T42	44		T44	43
arcs[TransCheckSt=>TokenHashSt]	19190	1			T2	43		T3	16		T9	1
arcs[TokenHashSt=>PostTransSt]	8477	1			T2	27		T42	8		T44	9
arcs[TokenHashSt=>FlashRmaSt]	10001	1			T2	16		T3	16		T9	1
arcs[FlashRmaSt=>TokenCheck0St]	9892	1			T2	16		T3	16		T9	1
arcs[TokenCheck0St=>PostTransSt]	2760	1			T2	7		T42	5		T44	22
arcs[TokenCheck0St=>TokenCheck1St]	7102	1			T2	9		T3	16		T9	1
arcs[TokenCheck1St=>PostTransSt]	645	1			T42	7		T44	13		T36	1
arcs[TransProgSt=>PostTransSt]	5581	1			T2	9		T3	16		T9	1
arcs[IdleSt=>EscalateSt]	224	1			T40	5		T56	6		T57	11
arcs[ClkMuxSt=>EscalateSt]	68	1			T10	2		T12	1		T40	2
arcs[CntIncrSt=>EscalateSt]	57	1			T10	3		T12	1		T56	1
arcs[CntProgSt=>EscalateSt]	1102	1			T10	10		T12	38		T40	6
arcs[TransCheckSt=>EscalateSt]	105	1			T10	6		T40	9		T57	6
arcs[TokenHashSt=>EscalateSt]	702	1			T10	25		T12	9		T40	16
arcs[FlashRmaSt=>EscalateSt]	109	1			T10	5		T40	2		T56	1
arcs[TokenCheck0St=>EscalateSt]	30	1			T40	1		T56	1		T57	3
arcs[TokenCheck1St=>EscalateSt]	139	1			T10	6		T12	2		T40	1
arcs[TransProgSt=>EscalateSt]	737	1			T10	8		T12	20		T40	8
arcs[PostTransSt=>EscalateSt]	3647	1			T1	8		T2	11		T10	12
arcs[InvalidSt=>EscalateSt]	12324	1			T5	69		T13	78		T28	9

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5745055	1			T1	786		T90	88		T91	87
auto[0]	auto[IdleSt]	16404858	1			T1	1670		T90	1074		T91	2214
auto[0]	auto[ClkMuxSt]	28547	1			T1	8		T2	68		T3	16
auto[0]	auto[CntIncrSt]	28357	1			T1	8		T2	68		T3	16
auto[0]	auto[CntProgSt]	1407988	1			T1	25		T2	5141		T3	425
auto[0]	auto[TransCheckSt]	22450	1			T2	51		T3	16		T9	1
auto[0]	auto[TokenHashSt]	19264533	1			T2	472		T3	355		T9	64
auto[0]	auto[FlashRmaSt]	21668	1			T2	47		T3	67		T9	1
auto[0]	auto[TokenCheck0St]	9873	1			T2	16		T3	16		T9	1
auto[0]	auto[TokenCheck1St]	7013	1			T2	9		T3	16		T9	1
auto[0]	auto[TransProgSt]	271761	1			T2	1057		T3	523		T9	21
auto[0]	auto[PostTransSt]	9389749	1			T1	693		T2	10569		T3	5773
auto[0]	auto[ScrapSt]	170828	1			T107	125		T108	950		T154	64
auto[0]	auto[EscalateSt]	4218196	1			T1	821		T2	1109		T10	3343
auto[0]	auto[InvalidSt]	8449121	1			T5	123590		T13	5389		T28	610
auto[1]	auto[ResetSt]	176	1			T10	4		T12	4		T40	4
auto[1]	auto[IdleSt]	145	1			T40	2		T56	4		T57	9
auto[1]	auto[ClkMuxSt]	51	1			T10	1		T12	1		T40	1
auto[1]	auto[CntIncrSt]	37	1			T10	3		T56	1		T181	1
auto[1]	auto[CntProgSt]	743	1			T10	8		T12	25		T40	3
auto[1]	auto[TransCheckSt]	69	1			T10	5		T40	5		T57	2
auto[1]	auto[TokenHashSt]	458	1			T10	17		T12	8		T40	8
auto[1]	auto[FlashRmaSt]	72	1			T10	3		T40	2		T57	2
auto[1]	auto[TokenCheck0St]	19	1			T40	1		T56	1		T57	2
auto[1]	auto[TokenCheck1St]	89	1			T10	5		T12	2		T40	1
auto[1]	auto[TransProgSt]	498	1			T10	6		T12	12		T40	8
auto[1]	auto[PostTransSt]	1821	1			T1	3		T2	4		T10	9
auto[1]	auto[ScrapSt]	40	1			T10	1		T56	1		T57	2
auto[1]	auto[EscalateSt]	1253047	1			T1	294		T2	392		T10	10288
auto[1]	auto[InvalidSt]	6216	1			T5	41		T13	44		T28	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5745033	1			T1	786		T90	88		T91	87
auto[0]	auto[IdleSt]	16404865	1			T1	1670		T90	1074		T91	2214
auto[0]	auto[ClkMuxSt]	28553	1			T1	8		T2	68		T3	16
auto[0]	auto[CntIncrSt]	28356	1			T1	8		T2	68		T3	16
auto[0]	auto[CntProgSt]	1407994	1			T1	25		T2	5141		T3	425
auto[0]	auto[TransCheckSt]	22449	1			T2	51		T3	16		T9	1
auto[0]	auto[TokenHashSt]	19264533	1			T2	472		T3	355		T9	64
auto[0]	auto[FlashRmaSt]	21670	1			T2	47		T3	67		T9	1
auto[0]	auto[TokenCheck0St]	9872	1			T2	16		T3	16		T9	1
auto[0]	auto[TokenCheck1St]	7007	1			T2	9		T3	16		T9	1
auto[0]	auto[TransProgSt]	271769	1			T2	1057		T3	523		T9	21
auto[0]	auto[PostTransSt]	9389661	1			T1	691		T2	10566		T3	5773
auto[0]	auto[ScrapSt]	170836	1			T107	125		T108	950		T154	64
auto[0]	auto[EscalateSt]	4216767	1			T1	625		T2	815		T10	3878
auto[0]	auto[InvalidSt]	8449229	1			T5	123603		T13	5399		T28	607
auto[1]	auto[ResetSt]	198	1			T10	5		T12	3		T40	4
auto[1]	auto[IdleSt]	138	1			T40	4		T56	4		T57	4
auto[1]	auto[ClkMuxSt]	45	1			T10	2		T40	2		T57	1
auto[1]	auto[CntIncrSt]	38	1			T12	1		T56	1		T182	1
auto[1]	auto[CntProgSt]	737	1			T10	8		T12	24		T40	4
auto[1]	auto[TransCheckSt]	70	1			T10	3		T40	5		T57	4
auto[1]	auto[TokenHashSt]	458	1			T10	19		T12	3		T40	13
auto[1]	auto[FlashRmaSt]	70	1			T10	3		T40	1		T56	1
auto[1]	auto[TokenCheck0St]	20	1			T57	2		T182	2		T183	1
auto[1]	auto[TokenCheck1St]	95	1			T10	5		T56	1		T57	2
auto[1]	auto[TransProgSt]	490	1			T10	6		T12	13		T40	3
auto[1]	auto[PostTransSt]	1909	1			T1	5		T2	7		T10	8
auto[1]	auto[ScrapSt]	32	1			T56	1		T57	1		T184	1
auto[1]	auto[EscalateSt]	1254476	1			T1	490		T2	686		T10	9753
auto[1]	auto[InvalidSt]	6108	1			T5	28		T13	34		T28	6