Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	788230	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

974474

1

T1

86

T90

175

T91

103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1475845	1			T1	78		T90	10		T91	22
values[0x0]	143055	1			T1	26		T90	74		T91	36
values[0x1]	143804	1			T1	38		T90	91		T91	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	623694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1139010

1

T1

98

T90

175

T91

117

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4639	1			T1	2		T97	1		T140	2
valid_sources[0x01]	4567	1			T120	7		T140	2		T105	3
valid_sources[0x02]	4397	1			T93	1		T97	2		T106	1
valid_sources[0x03]	4705	1			T1	1		T90	1		T91	1
valid_sources[0x04]	4497	1			T97	2		T140	1		T106	2
valid_sources[0x05]	4652	1			T1	1		T96	3		T97	4
valid_sources[0x06]	4618	1			T1	1		T92	4		T97	1
valid_sources[0x07]	4586	1			T91	1		T97	1		T120	2
valid_sources[0x08]	6592	1			T105	1		T124	7		T108	18
valid_sources[0x09]	8197	1			T90	1		T92	5		T93	1
valid_sources[0x0a]	4876	1			T93	1		T97	5		T105	1
valid_sources[0x0b]	5770	1			T91	1		T93	1		T96	1
valid_sources[0x0c]	6309	1			T92	3		T97	1		T120	4
valid_sources[0x0d]	4482	1			T96	3		T97	1		T120	6
valid_sources[0x0e]	5114	1			T1	2		T90	2		T96	1
valid_sources[0x0f]	5039	1			T91	1		T97	4		T120	2
valid_sources[0x10]	4596	1			T97	4		T140	1		T105	3
valid_sources[0x11]	4843	1			T90	1		T91	1		T97	2
valid_sources[0x12]	9642	1			T1	2		T90	3		T91	1
valid_sources[0x13]	4619	1			T1	1		T93	1		T97	2
valid_sources[0x14]	6127	1			T93	1		T97	2		T105	2
valid_sources[0x15]	4500	1			T90	1		T91	2		T92	4
valid_sources[0x16]	4603	1			T92	13		T93	1		T97	5
valid_sources[0x17]	6375	1			T1	1		T90	1		T140	2
valid_sources[0x18]	7532	1			T1	1		T90	3		T91	1
valid_sources[0x19]	4754	1			T90	2		T93	1		T96	3
valid_sources[0x1a]	4663	1			T93	2		T97	3		T120	4
valid_sources[0x1b]	4626	1			T93	1		T140	1		T105	1
valid_sources[0x1c]	4725	1			T90	2		T91	1		T93	1
valid_sources[0x1d]	5845	1			T96	6		T97	4		T105	4
valid_sources[0x1e]	5011	1			T1	2		T90	8		T97	2
valid_sources[0x1f]	4707	1			T1	1		T91	2		T97	1
valid_sources[0x20]	6137	1			T1	2		T90	3		T91	3
valid_sources[0x21]	4443	1			T1	1		T91	3		T92	19
valid_sources[0x22]	5348	1			T90	5		T91	2		T96	2
valid_sources[0x23]	5335	1			T96	1		T97	4		T121	1
valid_sources[0x24]	7154	1			T90	1		T91	1		T97	4
valid_sources[0x25]	5032	1			T1	1		T96	4		T97	6
valid_sources[0x26]	4648	1			T1	1		T91	2		T96	3
valid_sources[0x27]	4960	1			T1	1		T96	1		T97	3
valid_sources[0x28]	4378	1			T1	1		T90	2		T91	1
valid_sources[0x29]	4755	1			T97	1		T106	1		T124	2
valid_sources[0x2a]	6268	1			T90	1		T105	1		T106	2
valid_sources[0x2b]	4683	1			T90	1		T93	1		T97	4
valid_sources[0x2c]	5650	1			T97	3		T105	1		T106	1
valid_sources[0x2d]	4692	1			T90	1		T91	2		T92	7
valid_sources[0x2e]	6412	1			T90	1		T93	1		T96	2
valid_sources[0x2f]	4858	1			T91	1		T96	1		T97	1
valid_sources[0x30]	4621	1			T1	1		T91	1		T97	1
valid_sources[0x31]	5032	1			T1	1		T90	2		T92	3
valid_sources[0x32]	4865	1			T1	2		T91	2		T97	1
valid_sources[0x33]	4989	1			T1	1		T96	1		T97	3
valid_sources[0x34]	4566	1			T93	1		T97	3		T105	2
valid_sources[0x35]	4726	1			T91	2		T96	1		T97	1
valid_sources[0x36]	4590	1			T96	1		T97	1		T120	6
valid_sources[0x37]	5647	1			T97	2		T120	8		T140	1
valid_sources[0x38]	81589	1			T1	2		T90	1		T91	1
valid_sources[0x39]	5914	1			T91	1		T96	1		T97	1
valid_sources[0x3a]	4608	1			T97	1		T105	3		T153	2
valid_sources[0x3b]	4638	1			T90	2		T93	1		T96	1
valid_sources[0x3c]	5902	1			T96	1		T97	1		T121	1
valid_sources[0x3d]	6300	1			T90	1		T93	1		T96	1
valid_sources[0x3e]	4534	1			T91	1		T120	3		T105	5
valid_sources[0x3f]	4652	1			T90	2		T91	2		T96	1
valid_sources[0x40]	4564	1			T93	1		T97	3		T105	3
valid_sources[0x41]	6353	1			T90	1		T96	1		T97	1
valid_sources[0x42]	4955	1			T90	1		T96	2		T97	1
valid_sources[0x43]	4470	1			T90	1		T97	1		T120	3
valid_sources[0x44]	4737	1			T97	2		T105	1		T106	1
valid_sources[0x45]	4484	1			T96	4		T97	1		T140	1
valid_sources[0x46]	9413	1			T96	3		T105	1		T148	1
valid_sources[0x47]	4883	1			T1	1		T90	2		T97	4
valid_sources[0x48]	4519	1			T97	2		T105	4		T106	3
valid_sources[0x49]	4820	1			T91	1		T97	2		T140	2
valid_sources[0x4a]	6256	1			T96	1		T120	1		T140	4
valid_sources[0x4b]	4650	1			T90	2		T96	4		T97	6
valid_sources[0x4c]	4995	1			T93	2		T96	1		T97	2
valid_sources[0x4d]	7576	1			T90	5		T96	1		T97	2
valid_sources[0x4e]	9400	1			T1	1		T93	1		T97	2
valid_sources[0x4f]	8002	1			T90	1		T91	1		T96	3
valid_sources[0x50]	4600	1			T90	2		T93	1		T96	1
valid_sources[0x51]	4670	1			T93	1		T97	3		T105	1
valid_sources[0x52]	5715	1			T97	4		T140	1		T105	5
valid_sources[0x53]	5334	1			T1	1		T90	3		T91	1
valid_sources[0x54]	4845	1			T1	1		T91	1		T92	2
valid_sources[0x55]	4842	1			T96	3		T120	3		T124	1
valid_sources[0x56]	4665	1			T1	2		T90	1		T96	1
valid_sources[0x57]	7206	1			T92	2		T96	5		T97	1
valid_sources[0x58]	95512	1			T1	1		T92	2		T97	2
valid_sources[0x59]	8347	1			T1	1		T96	2		T97	6
valid_sources[0x5a]	4786	1			T91	1		T97	7		T121	3
valid_sources[0x5b]	4657	1			T1	2		T91	3		T96	2
valid_sources[0x5c]	10629	1			T1	1		T91	1		T97	4
valid_sources[0x5d]	4642	1			T1	1		T91	2		T96	2
valid_sources[0x5e]	4876	1			T90	5		T92	3		T96	5
valid_sources[0x5f]	4666	1			T92	16		T97	2		T140	1
valid_sources[0x60]	4639	1			T1	1		T90	1		T91	1
valid_sources[0x61]	5560	1			T1	1		T90	3		T93	1
valid_sources[0x62]	70741	1			T90	2		T91	1		T93	1
valid_sources[0x63]	4596	1			T1	1		T93	1		T96	5
valid_sources[0x64]	4659	1			T93	1		T97	2		T120	3
valid_sources[0x65]	9046	1			T1	2		T92	3		T96	2
valid_sources[0x66]	4730	1			T96	2		T97	2		T105	1
valid_sources[0x67]	4499	1			T90	4		T96	3		T140	1
valid_sources[0x68]	5973	1			T1	1		T90	1		T91	1
valid_sources[0x69]	35725	1			T91	2		T96	1		T105	2
valid_sources[0x6a]	5055	1			T1	1		T91	2		T124	5
valid_sources[0x6b]	5938	1			T91	1		T93	1		T96	3
valid_sources[0x6c]	5460	1			T1	2		T97	2		T140	1
valid_sources[0x6d]	6745	1			T96	4		T97	1		T105	2
valid_sources[0x6e]	4728	1			T1	2		T93	1		T97	1
valid_sources[0x6f]	5041	1			T1	3		T96	4		T97	3
valid_sources[0x70]	4654	1			T1	1		T91	1		T96	6
valid_sources[0x71]	7514	1			T97	1		T140	3		T105	4
valid_sources[0x72]	4612	1			T1	1		T120	5		T106	1
valid_sources[0x73]	5958	1			T90	1		T93	1		T97	4
valid_sources[0x74]	4492	1			T91	2		T93	1		T96	2
valid_sources[0x75]	4590	1			T1	1		T91	1		T93	1
valid_sources[0x76]	4499	1			T91	2		T92	6		T97	2
valid_sources[0x77]	5214	1			T1	1		T91	3		T105	2
valid_sources[0x78]	78686	1			T1	1		T96	5		T140	1
valid_sources[0x79]	7107	1			T97	4		T105	2		T106	1
valid_sources[0x7a]	4813	1			T1	1		T97	1		T140	2
valid_sources[0x7b]	7257	1			T97	1		T140	8		T105	1
valid_sources[0x7c]	6391	1			T1	1		T93	1		T97	2
valid_sources[0x7d]	4951	1			T1	1		T90	4		T97	2
valid_sources[0x7e]	6983	1			T96	1		T97	4		T140	5
valid_sources[0x7f]	4951	1			T1	1		T90	2		T96	9
valid_sources[0x80]	4531	1			T90	1		T91	2		T93	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

727957

1

T1

35

T90

10

T91

21

values[0x0]

all_enables

biggest_size

123830

1

T1

20

T90

74

T91

36

values[0x1]

all_enables

biggest_size

122687

1

T1

31

T90

91

T91

46