Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	66704676	12270	0	0
claim_transition_if_regwen_rd_A	66704676	1747	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66704676	12270	0	0
T91	2300	288	0	0
T93	5094	250	0	0
T95	3648	3	0	0
T96	1933	121	0	0
T97	11672	902	0	0
T103	1660	237	0	0
T106	1554	68	0	0
T107	3925	4	0	0
T108	9853	7	0	0
T124	12673	582	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66704676	1747	0	0
T92	2584	5	0	0
T93	5094	2	0	0
T119	0	66	0	0
T121	1222	6	0	0
T124	12673	5	0	0
T125	1874	0	0	0
T127	9276	0	0	0
T129	0	7	0	0
T140	2264	13	0	0
T145	4639	30	0	0
T146	1299	0	0	0
T148	1759	0	0	0
T149	0	10	0	0
T150	0	5	0	0