Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.53	98.46	92.81	96.97	78.18	96.40	98.35

Total modules in report: 54

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_mubi4_dec	0.00	0.00
prim_count	4.08			4.08
prim_generic_clock_inv	66.67			66.67
prim_clock_inv	66.67			66.67
prim_clock_mux2	75.00			75.00
tlul_rsp_intg_chk	80.00	100.00	40.00				100.00
prim_generic_clock_mux2	82.64	100.00	55.56	75.00			100.00
lc_ctrl_state_transition	86.27	96.92	70.37			91.53
tlul_adapter_host	87.51	91.30	68.75			90.00	100.00
lc_ctrl_fsm	90.61	97.73	89.13		75.51	97.33	93.33
tlul_rsp_intg_gen	91.67	83.33					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	66.67	66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
lc_ctrl	92.90	100.00	81.94	98.16		100.00	84.38
dmi_jtag_tap	94.12			94.12
dmi_jtag	95.56			95.56
prim_sync_reqack	95.59	94.59	100.00	100.00		83.33	100.00
dmi_cdc	96.36			96.36
lc_ctrl_signal_decode	96.69	98.41				91.67	100.00
prim_fifo_async_simple	96.78			96.78
prim_fifo_async_simple ( parameter Width=34,EnRstChks=0,EnRzHs=1 )	94.67			94.67
prim_fifo_async_simple ( parameter Width=41,EnRstChks=0,EnRzHs=1 )	98.89			98.89
lc_ctrl_fsm_cov_if	96.97	100.00	90.91			100.00
lc_ctrl_state_decode	98.89	100.00	100.00			96.67
tlul_adapter_reg	98.91	100.00	95.65			100.00	100.00
lc_ctrl_reg_top	99.42	100.00	97.70			100.00	100.00
lc_ctrl_csr_assert_fpv	100.00						100.00
prim_lc_sync	100.00	100.00					100.00
prim_lc_sync	100.00						100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=4,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=8,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sender	100.00	100.00
tlul_data_integ_dec	100.00	100.00
prim_sparse_fsm_flop	100.00	100.00					100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
prim_alert_sender	100.00			100.00
tlul_cmd_intg_gen	100.00	100.00					100.00
lc_ctrl_kmac_if	100.00	100.00	100.00		100.00	100.00	100.00
tlul_assert	100.00	100.00				100.00	100.00
prim_onehot_check	100.00			100.00
prim_cdc_rand_delay	100.00			100.00
prim_subreg	100.00	100.00	100.00			100.00
prim_secded_inv_39_32_dec	100.00			100.00
prim_generic_buf	100.00	100.00
prim_subreg_arb	100.00	100.00	100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_esc_receiver	100.00			100.00
prim_secded_inv_64_57_enc	100.00	100.00
prim_secded_inv_64_57_dec	100.00			100.00
prim_flop	100.00			100.00
prim_flop_2sync	100.00			100.00
prim_sync_reqack_data	100.00	100.00	100.00			100.00
prim_generic_flop	100.00	100.00		100.00		100.00
tlul_data_integ_enc
prim_reg_we_check
prim_sec_anchor_flop
prim_buf
tb
prim_sec_anchor_buf