Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.34 97.29 95.52 91.98 100.00 96.13 98.48 95.00


Total test records in report: 986
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T755 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3049321030 Jan 14 12:31:24 PM PST 24 Jan 14 12:31:29 PM PST 24 1473876209 ps
T756 /workspace/coverage/default/39.lc_ctrl_smoke.1789059309 Jan 14 12:32:02 PM PST 24 Jan 14 12:32:07 PM PST 24 95786668 ps
T757 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.219799915 Jan 14 12:30:21 PM PST 24 Jan 14 12:30:27 PM PST 24 1311221179 ps
T758 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1136714739 Jan 14 12:31:59 PM PST 24 Jan 14 12:32:00 PM PST 24 25896950 ps
T759 /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.881680471 Jan 14 12:32:04 PM PST 24 Jan 14 12:38:35 PM PST 24 64684488509 ps
T760 /workspace/coverage/default/17.lc_ctrl_sec_mubi.4134819655 Jan 14 12:31:24 PM PST 24 Jan 14 12:31:39 PM PST 24 2249126793 ps
T761 /workspace/coverage/default/35.lc_ctrl_jtag_access.1889328338 Jan 14 12:31:49 PM PST 24 Jan 14 12:32:00 PM PST 24 381177247 ps
T762 /workspace/coverage/default/32.lc_ctrl_prog_failure.3136967847 Jan 14 12:31:49 PM PST 24 Jan 14 12:31:52 PM PST 24 103274285 ps
T763 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3339800849 Jan 14 12:30:55 PM PST 24 Jan 14 12:31:04 PM PST 24 475853238 ps
T764 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1686830840 Jan 14 12:32:11 PM PST 24 Jan 14 12:32:29 PM PST 24 2958741925 ps
T765 /workspace/coverage/default/18.lc_ctrl_smoke.1625591471 Jan 14 12:31:18 PM PST 24 Jan 14 12:31:19 PM PST 24 17074520 ps
T766 /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1719952668 Jan 14 12:32:00 PM PST 24 Jan 14 12:32:08 PM PST 24 893298507 ps
T767 /workspace/coverage/default/32.lc_ctrl_state_failure.2766871181 Jan 14 12:31:51 PM PST 24 Jan 14 12:32:15 PM PST 24 539091287 ps
T768 /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.4240309012 Jan 14 12:30:03 PM PST 24 Jan 14 12:47:00 PM PST 24 127253322435 ps
T769 /workspace/coverage/default/9.lc_ctrl_jtag_priority.3931060855 Jan 14 12:30:27 PM PST 24 Jan 14 12:30:35 PM PST 24 606304421 ps
T770 /workspace/coverage/default/25.lc_ctrl_stress_all.796593996 Jan 14 12:31:56 PM PST 24 Jan 14 12:33:55 PM PST 24 6465995630 ps
T771 /workspace/coverage/default/32.lc_ctrl_jtag_access.2245231673 Jan 14 12:31:52 PM PST 24 Jan 14 12:31:59 PM PST 24 422784314 ps
T772 /workspace/coverage/default/45.lc_ctrl_prog_failure.4008595963 Jan 14 12:32:02 PM PST 24 Jan 14 12:32:07 PM PST 24 181638869 ps
T773 /workspace/coverage/default/44.lc_ctrl_errors.29884593 Jan 14 12:32:04 PM PST 24 Jan 14 12:32:14 PM PST 24 335806446 ps
T774 /workspace/coverage/default/13.lc_ctrl_sec_mubi.269623107 Jan 14 12:30:47 PM PST 24 Jan 14 12:30:58 PM PST 24 296900917 ps
T775 /workspace/coverage/default/2.lc_ctrl_errors.2755039943 Jan 14 12:30:04 PM PST 24 Jan 14 12:30:22 PM PST 24 1858688261 ps
T776 /workspace/coverage/default/17.lc_ctrl_state_failure.2093670012 Jan 14 12:31:00 PM PST 24 Jan 14 12:31:26 PM PST 24 1377760593 ps
T777 /workspace/coverage/default/38.lc_ctrl_alert_test.3028023872 Jan 14 12:31:59 PM PST 24 Jan 14 12:32:01 PM PST 24 48776526 ps
T778 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2499005098 Jan 14 12:31:22 PM PST 24 Jan 14 12:32:00 PM PST 24 1534006690 ps
T779 /workspace/coverage/default/21.lc_ctrl_errors.4076900727 Jan 14 12:31:50 PM PST 24 Jan 14 12:32:05 PM PST 24 488414110 ps
T780 /workspace/coverage/default/48.lc_ctrl_state_post_trans.3296231680 Jan 14 12:32:12 PM PST 24 Jan 14 12:32:23 PM PST 24 46667425 ps
T781 /workspace/coverage/default/41.lc_ctrl_jtag_access.2304239923 Jan 14 12:32:03 PM PST 24 Jan 14 12:32:11 PM PST 24 1180610660 ps
T782 /workspace/coverage/default/10.lc_ctrl_stress_all.1917703147 Jan 14 12:30:37 PM PST 24 Jan 14 12:31:55 PM PST 24 1983207303 ps
T783 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.4257142682 Jan 14 12:32:02 PM PST 24 Jan 14 12:32:13 PM PST 24 2032493409 ps
T784 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2470911639 Jan 14 12:30:08 PM PST 24 Jan 14 12:30:11 PM PST 24 20119877 ps
T785 /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2887310153 Jan 14 12:31:22 PM PST 24 Jan 14 12:31:29 PM PST 24 392860801 ps
T786 /workspace/coverage/default/8.lc_ctrl_errors.1862088782 Jan 14 12:30:33 PM PST 24 Jan 14 12:30:43 PM PST 24 334006046 ps
T787 /workspace/coverage/default/9.lc_ctrl_state_failure.1980003220 Jan 14 12:30:36 PM PST 24 Jan 14 12:31:04 PM PST 24 307634313 ps
T788 /workspace/coverage/default/10.lc_ctrl_state_failure.649935153 Jan 14 12:30:30 PM PST 24 Jan 14 12:31:04 PM PST 24 656737490 ps
T789 /workspace/coverage/default/4.lc_ctrl_sec_mubi.991435979 Jan 14 12:30:21 PM PST 24 Jan 14 12:30:35 PM PST 24 768374679 ps
T790 /workspace/coverage/default/2.lc_ctrl_smoke.4056253180 Jan 14 12:29:56 PM PST 24 Jan 14 12:30:00 PM PST 24 43293316 ps
T791 /workspace/coverage/default/3.lc_ctrl_sec_mubi.1726130406 Jan 14 12:30:02 PM PST 24 Jan 14 12:30:21 PM PST 24 736839944 ps
T792 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1068742504 Jan 14 12:31:22 PM PST 24 Jan 14 12:31:31 PM PST 24 250881527 ps
T793 /workspace/coverage/default/34.lc_ctrl_security_escalation.541833833 Jan 14 12:31:56 PM PST 24 Jan 14 12:32:04 PM PST 24 817255817 ps
T794 /workspace/coverage/default/34.lc_ctrl_jtag_access.3880248313 Jan 14 12:31:53 PM PST 24 Jan 14 12:32:04 PM PST 24 1272545684 ps
T795 /workspace/coverage/default/17.lc_ctrl_stress_all.2548517675 Jan 14 12:31:23 PM PST 24 Jan 14 12:33:58 PM PST 24 13444060776 ps
T796 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.152705538 Jan 14 12:29:51 PM PST 24 Jan 14 12:30:12 PM PST 24 488522788 ps
T797 /workspace/coverage/default/29.lc_ctrl_errors.2595903456 Jan 14 12:31:58 PM PST 24 Jan 14 12:32:11 PM PST 24 340698777 ps
T798 /workspace/coverage/default/0.lc_ctrl_jtag_access.1672890695 Jan 14 12:29:53 PM PST 24 Jan 14 12:29:59 PM PST 24 430222647 ps
T799 /workspace/coverage/default/15.lc_ctrl_stress_all.3461816578 Jan 14 12:30:51 PM PST 24 Jan 14 12:31:54 PM PST 24 1579891429 ps
T800 /workspace/coverage/default/8.lc_ctrl_prog_failure.3501916037 Jan 14 12:30:16 PM PST 24 Jan 14 12:30:19 PM PST 24 96700813 ps
T801 /workspace/coverage/default/30.lc_ctrl_stress_all.3309968699 Jan 14 12:31:54 PM PST 24 Jan 14 12:38:07 PM PST 24 87932806590 ps
T802 /workspace/coverage/default/24.lc_ctrl_jtag_access.2897796615 Jan 14 12:31:56 PM PST 24 Jan 14 12:32:08 PM PST 24 1090207288 ps
T803 /workspace/coverage/default/39.lc_ctrl_errors.3491331004 Jan 14 12:32:08 PM PST 24 Jan 14 12:32:22 PM PST 24 1476322566 ps
T804 /workspace/coverage/default/34.lc_ctrl_stress_all.141158057 Jan 14 12:31:53 PM PST 24 Jan 14 12:32:33 PM PST 24 10481510712 ps
T805 /workspace/coverage/default/36.lc_ctrl_sec_mubi.2566235904 Jan 14 12:31:55 PM PST 24 Jan 14 12:32:09 PM PST 24 402238890 ps
T806 /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1493498424 Jan 14 12:31:49 PM PST 24 Jan 14 12:31:51 PM PST 24 91836537 ps
T807 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.34073609 Jan 14 12:30:13 PM PST 24 Jan 14 12:30:40 PM PST 24 3735335041 ps
T808 /workspace/coverage/default/2.lc_ctrl_sec_mubi.1700490162 Jan 14 12:30:00 PM PST 24 Jan 14 12:30:16 PM PST 24 2041194451 ps
T809 /workspace/coverage/default/23.lc_ctrl_smoke.2633012996 Jan 14 12:31:46 PM PST 24 Jan 14 12:31:49 PM PST 24 79091388 ps
T810 /workspace/coverage/default/35.lc_ctrl_state_post_trans.1655475970 Jan 14 12:31:49 PM PST 24 Jan 14 12:31:57 PM PST 24 259825778 ps
T811 /workspace/coverage/default/22.lc_ctrl_alert_test.2894063892 Jan 14 12:31:49 PM PST 24 Jan 14 12:31:50 PM PST 24 20609030 ps
T812 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2943709349 Jan 14 12:30:35 PM PST 24 Jan 14 12:30:45 PM PST 24 1917773652 ps
T813 /workspace/coverage/default/16.lc_ctrl_alert_test.186177758 Jan 14 12:30:53 PM PST 24 Jan 14 12:30:55 PM PST 24 46260414 ps
T814 /workspace/coverage/default/1.lc_ctrl_jtag_access.3220175654 Jan 14 12:30:11 PM PST 24 Jan 14 12:30:21 PM PST 24 10400103078 ps
T815 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3205373131 Jan 14 12:30:51 PM PST 24 Jan 14 12:31:03 PM PST 24 1412025607 ps
T816 /workspace/coverage/default/27.lc_ctrl_prog_failure.1496142847 Jan 14 12:31:56 PM PST 24 Jan 14 12:32:01 PM PST 24 226207129 ps
T817 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.934940325 Jan 14 12:32:06 PM PST 24 Jan 14 12:32:16 PM PST 24 1298070367 ps
T818 /workspace/coverage/default/47.lc_ctrl_alert_test.3470179595 Jan 14 12:32:08 PM PST 24 Jan 14 12:32:11 PM PST 24 36386447 ps
T819 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3362232781 Jan 14 12:30:49 PM PST 24 Jan 14 12:30:50 PM PST 24 17327667 ps
T820 /workspace/coverage/default/14.lc_ctrl_prog_failure.2688324120 Jan 14 12:30:45 PM PST 24 Jan 14 12:30:48 PM PST 24 40548081 ps
T821 /workspace/coverage/default/25.lc_ctrl_state_post_trans.3722254670 Jan 14 12:31:50 PM PST 24 Jan 14 12:32:00 PM PST 24 282374008 ps
T822 /workspace/coverage/default/8.lc_ctrl_state_failure.173019865 Jan 14 12:30:21 PM PST 24 Jan 14 12:30:45 PM PST 24 182575093 ps
T823 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1480574078 Jan 14 12:30:40 PM PST 24 Jan 14 12:30:48 PM PST 24 2264652032 ps
T824 /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3004358956 Jan 14 12:31:52 PM PST 24 Jan 14 12:32:00 PM PST 24 229454464 ps
T825 /workspace/coverage/default/21.lc_ctrl_security_escalation.2153113453 Jan 14 12:31:48 PM PST 24 Jan 14 12:31:56 PM PST 24 230242394 ps
T826 /workspace/coverage/default/33.lc_ctrl_security_escalation.2902621039 Jan 14 12:31:56 PM PST 24 Jan 14 12:32:10 PM PST 24 311951235 ps
T827 /workspace/coverage/default/26.lc_ctrl_smoke.737760730 Jan 14 12:31:53 PM PST 24 Jan 14 12:31:57 PM PST 24 156498482 ps
T828 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3227520528 Jan 14 12:30:16 PM PST 24 Jan 14 12:30:24 PM PST 24 966518609 ps
T829 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.717729548 Jan 14 12:30:38 PM PST 24 Jan 14 12:30:49 PM PST 24 8817282397 ps
T830 /workspace/coverage/default/49.lc_ctrl_jtag_access.2200352933 Jan 14 12:32:21 PM PST 24 Jan 14 12:32:32 PM PST 24 285828495 ps
T831 /workspace/coverage/default/47.lc_ctrl_state_failure.3265848266 Jan 14 12:32:05 PM PST 24 Jan 14 12:32:22 PM PST 24 212083278 ps
T832 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.573661209 Jan 14 12:30:51 PM PST 24 Jan 14 12:30:59 PM PST 24 1046044844 ps
T833 /workspace/coverage/default/8.lc_ctrl_state_post_trans.2381499202 Jan 14 12:30:16 PM PST 24 Jan 14 12:30:20 PM PST 24 481704216 ps
T834 /workspace/coverage/default/29.lc_ctrl_security_escalation.1903207942 Jan 14 12:31:55 PM PST 24 Jan 14 12:32:08 PM PST 24 506533895 ps
T835 /workspace/coverage/default/25.lc_ctrl_state_failure.1827376650 Jan 14 12:31:51 PM PST 24 Jan 14 12:32:21 PM PST 24 324943924 ps
T836 /workspace/coverage/default/27.lc_ctrl_state_post_trans.895312296 Jan 14 12:31:55 PM PST 24 Jan 14 12:32:03 PM PST 24 63960186 ps
T837 /workspace/coverage/default/38.lc_ctrl_errors.217122397 Jan 14 12:32:08 PM PST 24 Jan 14 12:32:25 PM PST 24 428817479 ps
T838 /workspace/coverage/default/20.lc_ctrl_errors.1840752572 Jan 14 12:31:26 PM PST 24 Jan 14 12:31:47 PM PST 24 809233486 ps
T839 /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.410506105 Jan 14 12:30:46 PM PST 24 Jan 14 12:31:01 PM PST 24 2594318850 ps
T840 /workspace/coverage/default/20.lc_ctrl_sec_mubi.3106181123 Jan 14 12:31:40 PM PST 24 Jan 14 12:31:55 PM PST 24 1084856427 ps
T841 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1467739022 Jan 14 12:30:05 PM PST 24 Jan 14 12:30:17 PM PST 24 1167608160 ps
T842 /workspace/coverage/default/1.lc_ctrl_jtag_priority.905379899 Jan 14 12:30:06 PM PST 24 Jan 14 12:30:16 PM PST 24 592227822 ps
T843 /workspace/coverage/default/37.lc_ctrl_jtag_access.3858864818 Jan 14 12:31:56 PM PST 24 Jan 14 12:32:01 PM PST 24 231824085 ps
T844 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.824747063 Jan 14 12:31:55 PM PST 24 Jan 14 12:32:04 PM PST 24 292340067 ps
T845 /workspace/coverage/default/40.lc_ctrl_jtag_access.4213724278 Jan 14 12:31:57 PM PST 24 Jan 14 12:32:01 PM PST 24 72606734 ps
T846 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1793465318 Jan 14 12:31:41 PM PST 24 Jan 14 12:31:42 PM PST 24 53890799 ps
T847 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3415610544 Jan 14 12:30:40 PM PST 24 Jan 14 12:30:59 PM PST 24 489358316 ps
T848 /workspace/coverage/default/46.lc_ctrl_state_post_trans.4276442792 Jan 14 12:32:10 PM PST 24 Jan 14 12:32:23 PM PST 24 414936685 ps
T849 /workspace/coverage/default/25.lc_ctrl_alert_test.3273303737 Jan 14 12:31:55 PM PST 24 Jan 14 12:31:58 PM PST 24 18132204 ps
T850 /workspace/coverage/default/46.lc_ctrl_smoke.3441959932 Jan 14 12:32:05 PM PST 24 Jan 14 12:32:08 PM PST 24 242201159 ps
T851 /workspace/coverage/default/26.lc_ctrl_sec_mubi.588713824 Jan 14 12:31:56 PM PST 24 Jan 14 12:32:13 PM PST 24 331624586 ps
T852 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1446365572 Jan 14 12:30:44 PM PST 24 Jan 14 12:30:54 PM PST 24 2006414210 ps
T853 /workspace/coverage/default/41.lc_ctrl_sec_mubi.1371884081 Jan 14 12:32:01 PM PST 24 Jan 14 12:32:12 PM PST 24 762937515 ps
T854 /workspace/coverage/default/23.lc_ctrl_jtag_access.1058628630 Jan 14 12:31:49 PM PST 24 Jan 14 12:31:52 PM PST 24 697109720 ps
T855 /workspace/coverage/default/15.lc_ctrl_jtag_errors.3270153208 Jan 14 12:30:53 PM PST 24 Jan 14 12:31:43 PM PST 24 1828170810 ps
T856 /workspace/coverage/default/3.lc_ctrl_stress_all.2130349247 Jan 14 12:30:07 PM PST 24 Jan 14 12:32:24 PM PST 24 4958935121 ps
T857 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2385919896 Jan 14 12:31:44 PM PST 24 Jan 14 12:31:45 PM PST 24 16294356 ps
T858 /workspace/coverage/default/42.lc_ctrl_errors.2032230484 Jan 14 12:32:06 PM PST 24 Jan 14 12:32:16 PM PST 24 280155418 ps
T859 /workspace/coverage/default/16.lc_ctrl_state_failure.2288517930 Jan 14 12:30:46 PM PST 24 Jan 14 12:31:20 PM PST 24 504579884 ps
T860 /workspace/coverage/default/48.lc_ctrl_sec_mubi.1065669890 Jan 14 12:32:27 PM PST 24 Jan 14 12:32:43 PM PST 24 624272483 ps
T861 /workspace/coverage/default/22.lc_ctrl_smoke.923778168 Jan 14 12:31:47 PM PST 24 Jan 14 12:31:49 PM PST 24 39458248 ps
T862 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.424933885 Jan 14 12:30:40 PM PST 24 Jan 14 12:30:45 PM PST 24 857623973 ps
T863 /workspace/coverage/default/21.lc_ctrl_stress_all.7554767 Jan 14 12:31:45 PM PST 24 Jan 14 12:39:51 PM PST 24 26864105470 ps
T864 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2371838492 Jan 14 12:30:48 PM PST 24 Jan 14 12:31:01 PM PST 24 1166711800 ps
T865 /workspace/coverage/default/16.lc_ctrl_jtag_errors.325488120 Jan 14 12:30:50 PM PST 24 Jan 14 12:31:26 PM PST 24 4554514640 ps
T866 /workspace/coverage/default/12.lc_ctrl_stress_all.763674002 Jan 14 12:30:38 PM PST 24 Jan 14 12:33:15 PM PST 24 8002931253 ps
T867 /workspace/coverage/default/36.lc_ctrl_prog_failure.676508250 Jan 14 12:31:58 PM PST 24 Jan 14 12:32:02 PM PST 24 60459343 ps
T868 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2635490747 Jan 14 12:29:59 PM PST 24 Jan 14 12:30:10 PM PST 24 521332668 ps
T869 /workspace/coverage/default/13.lc_ctrl_security_escalation.3823738624 Jan 14 12:30:47 PM PST 24 Jan 14 12:31:03 PM PST 24 913669977 ps
T870 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1479862497 Jan 14 12:31:56 PM PST 24 Jan 14 12:31:59 PM PST 24 15025050 ps
T871 /workspace/coverage/default/33.lc_ctrl_jtag_access.250165815 Jan 14 12:31:57 PM PST 24 Jan 14 12:32:01 PM PST 24 72341577 ps
T872 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1205372927 Jan 14 12:31:52 PM PST 24 Jan 14 12:31:53 PM PST 24 40900228 ps
T873 /workspace/coverage/default/32.lc_ctrl_sec_mubi.1960938572 Jan 14 12:31:59 PM PST 24 Jan 14 12:32:11 PM PST 24 2369024484 ps
T874 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3468640576 Jan 14 12:31:55 PM PST 24 Jan 14 12:32:05 PM PST 24 297578759 ps
T875 /workspace/coverage/default/1.lc_ctrl_security_escalation.233764801 Jan 14 12:30:06 PM PST 24 Jan 14 12:30:17 PM PST 24 232334781 ps
T876 /workspace/coverage/default/4.lc_ctrl_jtag_priority.3256281363 Jan 14 12:30:05 PM PST 24 Jan 14 12:30:18 PM PST 24 3506045371 ps
T877 /workspace/coverage/default/47.lc_ctrl_sec_mubi.4203010239 Jan 14 12:32:07 PM PST 24 Jan 14 12:32:27 PM PST 24 638345571 ps
T878 /workspace/coverage/default/45.lc_ctrl_smoke.1339259198 Jan 14 12:32:08 PM PST 24 Jan 14 12:32:16 PM PST 24 95201863 ps
T879 /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1905036847 Jan 14 12:31:49 PM PST 24 Jan 14 12:31:50 PM PST 24 12992798 ps
T880 /workspace/coverage/default/11.lc_ctrl_sec_mubi.785065358 Jan 14 12:30:35 PM PST 24 Jan 14 12:30:44 PM PST 24 1372651101 ps
T881 /workspace/coverage/default/16.lc_ctrl_sec_mubi.2052638812 Jan 14 12:30:54 PM PST 24 Jan 14 12:31:08 PM PST 24 2302371112 ps
T882 /workspace/coverage/default/2.lc_ctrl_jtag_access.2891309084 Jan 14 12:30:10 PM PST 24 Jan 14 12:30:21 PM PST 24 1559746178 ps
T883 /workspace/coverage/default/28.lc_ctrl_state_failure.3206326272 Jan 14 12:31:52 PM PST 24 Jan 14 12:32:26 PM PST 24 1124861978 ps
T884 /workspace/coverage/default/13.lc_ctrl_state_post_trans.475239623 Jan 14 12:30:46 PM PST 24 Jan 14 12:30:53 PM PST 24 216026355 ps
T885 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3260589314 Jan 14 12:30:45 PM PST 24 Jan 14 12:30:47 PM PST 24 12143512 ps
T886 /workspace/coverage/default/42.lc_ctrl_alert_test.2983429177 Jan 14 12:32:10 PM PST 24 Jan 14 12:32:18 PM PST 24 44387837 ps
T887 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2831697109 Jan 14 12:30:27 PM PST 24 Jan 14 12:30:45 PM PST 24 420771472 ps
T888 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2858999391 Jan 14 12:30:06 PM PST 24 Jan 14 12:30:29 PM PST 24 3149975443 ps
T889 /workspace/coverage/default/0.lc_ctrl_state_failure.3780621949 Jan 14 12:30:02 PM PST 24 Jan 14 12:30:25 PM PST 24 225783311 ps
T111 /workspace/coverage/default/0.lc_ctrl_sec_cm.3789369463 Jan 14 12:30:01 PM PST 24 Jan 14 12:30:28 PM PST 24 235987841 ps
T890 /workspace/coverage/default/2.lc_ctrl_security_escalation.2963544197 Jan 14 12:30:17 PM PST 24 Jan 14 12:30:28 PM PST 24 225242354 ps
T891 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.801976302 Jan 14 12:31:45 PM PST 24 Jan 14 12:32:09 PM PST 24 2966046695 ps
T892 /workspace/coverage/default/33.lc_ctrl_sec_mubi.2701222893 Jan 14 12:32:07 PM PST 24 Jan 14 12:32:21 PM PST 24 298118543 ps
T893 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3174719540 Jan 14 12:30:22 PM PST 24 Jan 14 12:30:35 PM PST 24 306356387 ps
T894 /workspace/coverage/default/28.lc_ctrl_jtag_access.3680809015 Jan 14 12:31:49 PM PST 24 Jan 14 12:31:53 PM PST 24 240196410 ps
T895 /workspace/coverage/default/4.lc_ctrl_security_escalation.3916197763 Jan 14 12:30:14 PM PST 24 Jan 14 12:30:29 PM PST 24 1146405109 ps
T896 /workspace/coverage/default/49.lc_ctrl_state_post_trans.1368187358 Jan 14 12:32:03 PM PST 24 Jan 14 12:32:10 PM PST 24 316745456 ps
T897 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1816044769 Jan 14 12:30:02 PM PST 24 Jan 14 12:30:13 PM PST 24 1221335910 ps
T60 /workspace/coverage/default/2.lc_ctrl_sec_cm.3055970378 Jan 14 12:30:01 PM PST 24 Jan 14 12:30:33 PM PST 24 1783876397 ps
T898 /workspace/coverage/default/10.lc_ctrl_alert_test.73211093 Jan 14 12:30:36 PM PST 24 Jan 14 12:30:38 PM PST 24 12602525 ps
T899 /workspace/coverage/default/32.lc_ctrl_errors.3349094650 Jan 14 12:31:52 PM PST 24 Jan 14 12:32:07 PM PST 24 1799166727 ps
T900 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4208970606 Jan 14 12:32:05 PM PST 24 Jan 14 12:32:15 PM PST 24 231632301 ps
T901 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1550474576 Jan 14 12:32:12 PM PST 24 Jan 14 12:32:38 PM PST 24 4268056318 ps
T902 /workspace/coverage/default/4.lc_ctrl_state_post_trans.4114091502 Jan 14 12:30:06 PM PST 24 Jan 14 12:30:16 PM PST 24 380194192 ps
T903 /workspace/coverage/default/25.lc_ctrl_security_escalation.128078374 Jan 14 12:31:51 PM PST 24 Jan 14 12:31:59 PM PST 24 215331874 ps
T904 /workspace/coverage/default/6.lc_ctrl_stress_all.3467038168 Jan 14 12:30:15 PM PST 24 Jan 14 12:33:20 PM PST 24 35293150672 ps
T905 /workspace/coverage/default/48.lc_ctrl_prog_failure.4022773051 Jan 14 12:32:00 PM PST 24 Jan 14 12:32:03 PM PST 24 137498722 ps
T906 /workspace/coverage/default/31.lc_ctrl_errors.604407174 Jan 14 12:31:49 PM PST 24 Jan 14 12:32:02 PM PST 24 1418881230 ps
T907 /workspace/coverage/default/3.lc_ctrl_security_escalation.1016687386 Jan 14 12:30:05 PM PST 24 Jan 14 12:30:14 PM PST 24 4164466148 ps
T908 /workspace/coverage/default/20.lc_ctrl_stress_all.1965752514 Jan 14 12:31:45 PM PST 24 Jan 14 12:32:43 PM PST 24 1551595087 ps
T179 /workspace/coverage/default/0.lc_ctrl_claim_transition_if.368511325 Jan 14 12:30:08 PM PST 24 Jan 14 12:30:11 PM PST 24 38962470 ps
T909 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.501561426 Jan 14 12:31:43 PM PST 24 Jan 14 12:31:56 PM PST 24 457443218 ps
T910 /workspace/coverage/default/10.lc_ctrl_prog_failure.2510699656 Jan 14 12:30:33 PM PST 24 Jan 14 12:30:36 PM PST 24 48781814 ps
T911 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3628652928 Jan 14 12:31:54 PM PST 24 Jan 14 12:32:11 PM PST 24 1428775331 ps
T912 /workspace/coverage/default/26.lc_ctrl_errors.2497872904 Jan 14 12:32:01 PM PST 24 Jan 14 12:32:14 PM PST 24 1830402425 ps
T913 /workspace/coverage/default/3.lc_ctrl_errors.3913162414 Jan 14 12:30:12 PM PST 24 Jan 14 12:30:23 PM PST 24 959080410 ps
T914 /workspace/coverage/default/23.lc_ctrl_state_post_trans.2055196968 Jan 14 12:31:49 PM PST 24 Jan 14 12:31:52 PM PST 24 47758175 ps
T915 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.115827077 Jan 14 12:30:00 PM PST 24 Jan 14 12:30:02 PM PST 24 54760658 ps
T916 /workspace/coverage/default/35.lc_ctrl_stress_all.4138821987 Jan 14 12:31:49 PM PST 24 Jan 14 12:36:19 PM PST 24 36375694422 ps
T917 /workspace/coverage/default/9.lc_ctrl_jtag_errors.1905660118 Jan 14 12:30:35 PM PST 24 Jan 14 12:31:34 PM PST 24 30003688493 ps
T918 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.169987486 Jan 14 12:31:52 PM PST 24 Jan 14 12:31:53 PM PST 24 14142250 ps
T919 /workspace/coverage/default/5.lc_ctrl_stress_all.3461143239 Jan 14 12:30:13 PM PST 24 Jan 14 12:34:47 PM PST 24 16454502146 ps
T920 /workspace/coverage/default/45.lc_ctrl_jtag_access.2720236619 Jan 14 12:32:03 PM PST 24 Jan 14 12:32:05 PM PST 24 55730130 ps
T921 /workspace/coverage/default/30.lc_ctrl_prog_failure.2861881418 Jan 14 12:31:56 PM PST 24 Jan 14 12:32:04 PM PST 24 554340022 ps
T922 /workspace/coverage/default/27.lc_ctrl_jtag_access.53741949 Jan 14 12:31:45 PM PST 24 Jan 14 12:31:57 PM PST 24 857365566 ps
T923 /workspace/coverage/default/8.lc_ctrl_smoke.408596582 Jan 14 12:30:22 PM PST 24 Jan 14 12:30:27 PM PST 24 62702452 ps
T924 /workspace/coverage/default/20.lc_ctrl_prog_failure.580835077 Jan 14 12:31:24 PM PST 24 Jan 14 12:31:27 PM PST 24 163030830 ps
T925 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.990470404 Jan 14 12:31:52 PM PST 24 Jan 14 12:32:04 PM PST 24 1083537415 ps
T926 /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.135767605 Jan 14 12:30:18 PM PST 24 Jan 14 12:30:46 PM PST 24 3911182210 ps
T927 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2140206544 Jan 14 12:29:54 PM PST 24 Jan 14 12:30:07 PM PST 24 1794384821 ps
T928 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4021347753 Jan 14 12:30:44 PM PST 24 Jan 14 12:30:56 PM PST 24 851874519 ps
T929 /workspace/coverage/default/31.lc_ctrl_alert_test.2178810852 Jan 14 12:31:51 PM PST 24 Jan 14 12:31:53 PM PST 24 38310119 ps
T930 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3791892758 Jan 14 12:32:13 PM PST 24 Jan 14 12:32:24 PM PST 24 662705481 ps
T76 /workspace/coverage/default/38.lc_ctrl_stress_all.4086337863 Jan 14 12:31:51 PM PST 24 Jan 14 12:33:10 PM PST 24 1815593398 ps
T931 /workspace/coverage/default/49.lc_ctrl_stress_all.3585759739 Jan 14 12:32:26 PM PST 24 Jan 14 12:34:17 PM PST 24 42481129547 ps
T932 /workspace/coverage/default/41.lc_ctrl_smoke.1811204707 Jan 14 12:31:55 PM PST 24 Jan 14 12:31:59 PM PST 24 47742154 ps
T933 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1095119901 Jan 14 12:32:04 PM PST 24 Jan 14 12:32:13 PM PST 24 998026973 ps
T934 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3455866463 Jan 14 12:30:06 PM PST 24 Jan 14 12:30:52 PM PST 24 7617015341 ps
T935 /workspace/coverage/default/6.lc_ctrl_prog_failure.1761677873 Jan 14 12:30:06 PM PST 24 Jan 14 12:30:11 PM PST 24 140216450 ps
T936 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2312643176 Jan 14 12:32:02 PM PST 24 Jan 14 12:32:11 PM PST 24 170164930 ps
T937 /workspace/coverage/default/17.lc_ctrl_prog_failure.2663244284 Jan 14 12:30:51 PM PST 24 Jan 14 12:30:54 PM PST 24 49024751 ps
T938 /workspace/coverage/default/14.lc_ctrl_stress_all.172494329 Jan 14 12:30:47 PM PST 24 Jan 14 12:32:00 PM PST 24 1564156456 ps
T939 /workspace/coverage/default/42.lc_ctrl_sec_mubi.2496999947 Jan 14 12:32:22 PM PST 24 Jan 14 12:32:37 PM PST 24 973205900 ps
T940 /workspace/coverage/default/23.lc_ctrl_security_escalation.2095641095 Jan 14 12:31:52 PM PST 24 Jan 14 12:32:07 PM PST 24 1342479776 ps
T941 /workspace/coverage/default/5.lc_ctrl_state_post_trans.3612381582 Jan 14 12:30:12 PM PST 24 Jan 14 12:30:22 PM PST 24 85358565 ps
T942 /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4051646140 Jan 14 12:31:01 PM PST 24 Jan 14 12:31:03 PM PST 24 11937547 ps
T943 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1438794032 Jan 14 12:30:47 PM PST 24 Jan 14 12:31:24 PM PST 24 5389256669 ps
T944 /workspace/coverage/default/41.lc_ctrl_prog_failure.4010158720 Jan 14 12:32:03 PM PST 24 Jan 14 12:32:09 PM PST 24 529395332 ps
T945 /workspace/coverage/default/40.lc_ctrl_stress_all.2208636084 Jan 14 12:32:08 PM PST 24 Jan 14 12:35:17 PM PST 24 11340687347 ps
T946 /workspace/coverage/default/15.lc_ctrl_state_failure.1853686511 Jan 14 12:30:54 PM PST 24 Jan 14 12:31:11 PM PST 24 320353462 ps
T947 /workspace/coverage/default/4.lc_ctrl_jtag_access.462028234 Jan 14 12:30:12 PM PST 24 Jan 14 12:30:19 PM PST 24 2515473921 ps
T948 /workspace/coverage/default/39.lc_ctrl_state_post_trans.422728808 Jan 14 12:32:08 PM PST 24 Jan 14 12:32:17 PM PST 24 294709865 ps
T949 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1100270674 Jan 14 12:32:01 PM PST 24 Jan 14 12:32:02 PM PST 24 18732561 ps
T950 /workspace/coverage/default/16.lc_ctrl_state_post_trans.1190749188 Jan 14 12:30:54 PM PST 24 Jan 14 12:30:59 PM PST 24 258723559 ps
T951 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1194789665 Jan 14 12:30:54 PM PST 24 Jan 14 12:31:00 PM PST 24 1200252517 ps
T952 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3651244213 Jan 14 12:30:23 PM PST 24 Jan 14 12:31:21 PM PST 24 3297940797 ps
T953 /workspace/coverage/default/49.lc_ctrl_security_escalation.2782588173 Jan 14 12:31:58 PM PST 24 Jan 14 12:32:07 PM PST 24 352236218 ps
T954 /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3891420910 Jan 14 12:31:55 PM PST 24 Jan 14 12:32:11 PM PST 24 668204033 ps
T955 /workspace/coverage/default/42.lc_ctrl_prog_failure.4004751795 Jan 14 12:32:05 PM PST 24 Jan 14 12:32:10 PM PST 24 168783441 ps
T956 /workspace/coverage/default/18.lc_ctrl_jtag_errors.2282348016 Jan 14 12:31:28 PM PST 24 Jan 14 12:32:08 PM PST 24 1677673687 ps
T957 /workspace/coverage/default/44.lc_ctrl_state_post_trans.765496188 Jan 14 12:32:14 PM PST 24 Jan 14 12:32:24 PM PST 24 53564227 ps
T958 /workspace/coverage/default/25.lc_ctrl_smoke.3420623160 Jan 14 12:31:51 PM PST 24 Jan 14 12:31:55 PM PST 24 86102120 ps
T959 /workspace/coverage/default/34.lc_ctrl_smoke.3093615991 Jan 14 12:31:54 PM PST 24 Jan 14 12:31:57 PM PST 24 46519595 ps
T960 /workspace/coverage/default/5.lc_ctrl_state_failure.3310071786 Jan 14 12:30:23 PM PST 24 Jan 14 12:30:59 PM PST 24 539278508 ps
T961 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2119140213 Jan 14 12:30:39 PM PST 24 Jan 14 12:30:46 PM PST 24 460576085 ps
T962 /workspace/coverage/default/23.lc_ctrl_state_failure.4223610310 Jan 14 12:31:50 PM PST 24 Jan 14 12:32:14 PM PST 24 339332392 ps
T963 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1333190718 Jan 14 12:31:46 PM PST 24 Jan 14 12:31:58 PM PST 24 999280350 ps
T964 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3517398365 Jan 14 12:30:25 PM PST 24 Jan 14 12:30:31 PM PST 24 13319882 ps
T965 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3455908192 Jan 14 12:30:16 PM PST 24 Jan 14 12:30:24 PM PST 24 202552806 ps
T966 /workspace/coverage/default/7.lc_ctrl_prog_failure.3293920647 Jan 14 12:30:20 PM PST 24 Jan 14 12:30:25 PM PST 24 116569316 ps
T967 /workspace/coverage/default/18.lc_ctrl_state_failure.899343022 Jan 14 12:31:23 PM PST 24 Jan 14 12:31:47 PM PST 24 941596420 ps
T968 /workspace/coverage/default/37.lc_ctrl_alert_test.602804508 Jan 14 12:32:01 PM PST 24 Jan 14 12:32:04 PM PST 24 32166474 ps
T969 /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4219822362 Jan 14 12:31:55 PM PST 24 Jan 14 12:31:58 PM PST 24 166991261 ps
T970 /workspace/coverage/default/47.lc_ctrl_security_escalation.3784730661 Jan 14 12:32:05 PM PST 24 Jan 14 12:32:14 PM PST 24 1262935093 ps
T971 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4068777593 Jan 14 12:30:24 PM PST 24 Jan 14 12:30:31 PM PST 24 37790923 ps
T972 /workspace/coverage/default/41.lc_ctrl_state_failure.2575242694 Jan 14 12:32:08 PM PST 24 Jan 14 12:32:41 PM PST 24 862477502 ps
T973 /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1370794952 Jan 14 12:32:05 PM PST 24 Jan 14 12:32:18 PM PST 24 279704025 ps
T974 /workspace/coverage/default/7.lc_ctrl_security_escalation.4118024697 Jan 14 12:30:16 PM PST 24 Jan 14 12:30:26 PM PST 24 4388841789 ps
T975 /workspace/coverage/default/5.lc_ctrl_prog_failure.160448529 Jan 14 12:30:19 PM PST 24 Jan 14 12:30:22 PM PST 24 44177954 ps
T976 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.4150295944 Jan 14 12:31:55 PM PST 24 Jan 14 12:32:06 PM PST 24 1391660290 ps
T977 /workspace/coverage/default/34.lc_ctrl_prog_failure.1695714486 Jan 14 12:31:55 PM PST 24 Jan 14 12:31:59 PM PST 24 119884068 ps
T978 /workspace/coverage/default/19.lc_ctrl_sec_token_mux.212139070 Jan 14 12:31:25 PM PST 24 Jan 14 12:31:36 PM PST 24 2291771260 ps
T979 /workspace/coverage/default/11.lc_ctrl_smoke.1805812353 Jan 14 12:30:43 PM PST 24 Jan 14 12:30:46 PM PST 24 31591252 ps
T980 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1417139992 Jan 14 12:30:24 PM PST 24 Jan 14 12:30:43 PM PST 24 2036868453 ps
T981 /workspace/coverage/default/14.lc_ctrl_sec_mubi.2384843834 Jan 14 12:30:53 PM PST 24 Jan 14 12:31:04 PM PST 24 231901998 ps
T982 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.4252619097 Jan 14 12:30:59 PM PST 24 Jan 14 12:33:02 PM PST 24 7206062203 ps
T983 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2508536706 Jan 14 12:30:24 PM PST 24 Jan 14 12:30:30 PM PST 24 194950045 ps
T984 /workspace/coverage/default/22.lc_ctrl_state_post_trans.2333368419 Jan 14 12:31:46 PM PST 24 Jan 14 12:31:54 PM PST 24 252755829 ps
T985 /workspace/coverage/default/28.lc_ctrl_stress_all.3199950943 Jan 14 12:31:52 PM PST 24 Jan 14 12:32:18 PM PST 24 474097305 ps
T986 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.4107346124 Jan 14 12:31:25 PM PST 24 Jan 14 12:31:30 PM PST 24 458336704 ps

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1034121906
Short name T1
Test name
Test status
Simulation time 269354531 ps
CPU time 2.1 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:22 PM PST 24
Peak memory 218168 kb
Host smart-3e980b7a-6d88-439e-8aef-78e2938f1057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034121906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1034121906
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3694411523
Short name T10
Test name
Test status
Simulation time 1351855630 ps
CPU time 8.44 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:58 PM PST 24
Peak memory 218028 kb
Host smart-60e75682-d3bf-4f66-bdac-da6ef1495d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694411523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3694411523
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3420260435
Short name T20
Test name
Test status
Simulation time 15332614495 ps
CPU time 137.74 seconds
Started Jan 14 12:32:15 PM PST 24
Finished Jan 14 12:34:35 PM PST 24
Peak memory 267604 kb
Host smart-b4cf4f80-ea6b-4577-836c-238365673ebd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420260435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3420260435
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1328148354
Short name T94
Test name
Test status
Simulation time 80838498 ps
CPU time 1.52 seconds
Started Jan 14 12:23:55 PM PST 24
Finished Jan 14 12:23:57 PM PST 24
Peak memory 210716 kb
Host smart-98c98088-8bd6-4fc3-a6c0-e8b94c1d7894
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328148354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1328148354
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2911237972
Short name T97
Test name
Test status
Simulation time 686646808 ps
CPU time 3.57 seconds
Started Jan 14 12:24:11 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 217700 kb
Host smart-742b28b8-0069-4fe2-a560-f8088ee4aac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911237972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2911237972
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.595160582
Short name T51
Test name
Test status
Simulation time 773755043 ps
CPU time 17.24 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 218748 kb
Host smart-ee8c2a64-0cc7-42cd-a727-1d5f3236e858
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595160582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.595160582
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3594291124
Short name T108
Test name
Test status
Simulation time 547533285 ps
CPU time 2.96 seconds
Started Jan 14 12:24:30 PM PST 24
Finished Jan 14 12:24:33 PM PST 24
Peak memory 221236 kb
Host smart-d810874c-4a8a-4f89-9534-7471bfb2ce4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594291124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3594291124
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.187936464
Short name T40
Test name
Test status
Simulation time 3062709586 ps
CPU time 8.24 seconds
Started Jan 14 12:30:23 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 218188 kb
Host smart-b8163a96-6a84-4731-ab9f-3ca4d1018142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187936464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.187936464
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2016171878
Short name T48
Test name
Test status
Simulation time 11540284971 ps
CPU time 69.8 seconds
Started Jan 14 12:32:10 PM PST 24
Finished Jan 14 12:33:26 PM PST 24
Peak memory 281532 kb
Host smart-09615865-1afa-48b9-912d-90eb51fd404e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016171878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2016171878
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1865795348
Short name T32
Test name
Test status
Simulation time 11137698 ps
CPU time 0.88 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:18 PM PST 24
Peak memory 208616 kb
Host smart-d496dd25-381d-4778-b14e-50ec1fcebbea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865795348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1865795348
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3143599796
Short name T105
Test name
Test status
Simulation time 39000434 ps
CPU time 1.37 seconds
Started Jan 14 12:24:02 PM PST 24
Finished Jan 14 12:24:05 PM PST 24
Peak memory 211332 kb
Host smart-d321ea70-6f5c-487c-adf6-51a1636b5200
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143599796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3143599796
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3835822494
Short name T4
Test name
Test status
Simulation time 496367563 ps
CPU time 6.16 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 209604 kb
Host smart-6486a0e5-ec97-42d3-a6c8-54c0e3ba2e84
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835822494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.3835822494
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.881680471
Short name T759
Test name
Test status
Simulation time 64684488509 ps
CPU time 390.32 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:38:35 PM PST 24
Peak memory 422304 kb
Host smart-2224e25d-d9a8-4613-a275-f98d1e48a9f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=881680471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.881680471
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3055970378
Short name T60
Test name
Test status
Simulation time 1783876397 ps
CPU time 29.13 seconds
Started Jan 14 12:30:01 PM PST 24
Finished Jan 14 12:30:33 PM PST 24
Peak memory 280820 kb
Host smart-f60327da-af1b-4970-b603-f46fe8311748
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055970378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3055970378
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1166339997
Short name T37
Test name
Test status
Simulation time 951863391 ps
CPU time 10.58 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:16 PM PST 24
Peak memory 218120 kb
Host smart-82785e98-f1bb-4cd3-99f2-6ba2ca73d6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166339997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1166339997
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1318650429
Short name T42
Test name
Test status
Simulation time 996210536 ps
CPU time 7.14 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 218104 kb
Host smart-14cff220-5344-471b-9001-f834f5f4dc64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318650429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1318650429
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4109379235
Short name T153
Test name
Test status
Simulation time 36524271 ps
CPU time 1.3 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 217712 kb
Host smart-81266e4b-a856-42af-8f1c-9f8c3efa7edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109379235 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.4109379235
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3844687484
Short name T150
Test name
Test status
Simulation time 15723957 ps
CPU time 0.9 seconds
Started Jan 14 12:23:46 PM PST 24
Finished Jan 14 12:23:47 PM PST 24
Peak memory 209664 kb
Host smart-915a441c-7e6f-47b6-92ff-c4012c68a54a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844687484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3844687484
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.210912400
Short name T104
Test name
Test status
Simulation time 3043957706 ps
CPU time 82.83 seconds
Started Jan 14 12:30:49 PM PST 24
Finished Jan 14 12:32:12 PM PST 24
Peak memory 273124 kb
Host smart-e41401ec-40db-4f9b-ae88-deaf43edee21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210912400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.210912400
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2243262624
Short name T316
Test name
Test status
Simulation time 1698479542 ps
CPU time 53.94 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:31:45 PM PST 24
Peak memory 267412 kb
Host smart-33b300b4-b55f-4ea4-bd89-9d53767aa03c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243262624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2243262624
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.624995553
Short name T72
Test name
Test status
Simulation time 21936232 ps
CPU time 0.93 seconds
Started Jan 14 12:30:44 PM PST 24
Finished Jan 14 12:30:45 PM PST 24
Peak memory 209568 kb
Host smart-053a25bb-f948-4404-a67f-77c9ae5265a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624995553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.624995553
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2315496508
Short name T126
Test name
Test status
Simulation time 125702439 ps
CPU time 2.85 seconds
Started Jan 14 12:24:17 PM PST 24
Finished Jan 14 12:24:20 PM PST 24
Peak memory 221612 kb
Host smart-eb627f83-1c35-4dbf-8418-443862f4447c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315496508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2315496508
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.27077889
Short name T39
Test name
Test status
Simulation time 432967756 ps
CPU time 6.2 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 217876 kb
Host smart-d006064e-89b4-494d-b809-6563a0d4baa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27077889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.27077889
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.167393494
Short name T62
Test name
Test status
Simulation time 4658440871 ps
CPU time 101.67 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:33:31 PM PST 24
Peak memory 269280 kb
Host smart-f3d5c66f-5b2a-48fe-8f13-ba3a6d2a8c5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167393494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.167393494
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1633641773
Short name T129
Test name
Test status
Simulation time 142744995 ps
CPU time 2.83 seconds
Started Jan 14 12:24:05 PM PST 24
Finished Jan 14 12:24:08 PM PST 24
Peak memory 217676 kb
Host smart-50212f4d-410e-4479-844f-bfabdfb3542e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633641773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1633641773
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1294697075
Short name T46
Test name
Test status
Simulation time 15395473 ps
CPU time 0.77 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 208224 kb
Host smart-56180da8-e917-4cde-9f04-dd9c504cd175
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294697075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1294697075
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.103344491
Short name T55
Test name
Test status
Simulation time 15480641301 ps
CPU time 606.28 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:42:00 PM PST 24
Peak memory 464120 kb
Host smart-51700990-9c3f-4b82-b3fb-dac83dd33c16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=103344491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.103344491
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1454804703
Short name T107
Test name
Test status
Simulation time 157118513 ps
CPU time 1.74 seconds
Started Jan 14 12:24:04 PM PST 24
Finished Jan 14 12:24:06 PM PST 24
Peak memory 221260 kb
Host smart-108f6e37-e2fd-4448-abb6-1b51878ab864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454804703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1454804703
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.238956550
Short name T182
Test name
Test status
Simulation time 635320428 ps
CPU time 11.08 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:30:47 PM PST 24
Peak memory 218080 kb
Host smart-5f293a32-05c1-4f0b-aa86-f714d633ccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238956550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.238956550
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1561661734
Short name T137
Test name
Test status
Simulation time 657225558 ps
CPU time 4.53 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:15 PM PST 24
Peak memory 217652 kb
Host smart-1c48ac9b-08c3-460f-b397-4c80b722fc43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561661734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1561661734
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2441133808
Short name T131
Test name
Test status
Simulation time 59437425 ps
CPU time 2.05 seconds
Started Jan 14 12:23:49 PM PST 24
Finished Jan 14 12:23:57 PM PST 24
Peak memory 221728 kb
Host smart-2a3f5af7-64c6-4e6c-89e5-0fb0e5b044c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441133808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2441133808
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3668406787
Short name T469
Test name
Test status
Simulation time 31050249 ps
CPU time 0.71 seconds
Started Jan 14 12:30:32 PM PST 24
Finished Jan 14 12:30:35 PM PST 24
Peak memory 208112 kb
Host smart-bb69672e-c8b3-48a4-8925-4e2f03dda1e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668406787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3668406787
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3993386706
Short name T139
Test name
Test status
Simulation time 112721071 ps
CPU time 3.09 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 222048 kb
Host smart-b5e55535-3828-4ea7-9540-ca37ed484c0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993386706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3993386706
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.368511325
Short name T179
Test name
Test status
Simulation time 38962470 ps
CPU time 0.81 seconds
Started Jan 14 12:30:08 PM PST 24
Finished Jan 14 12:30:11 PM PST 24
Peak memory 209248 kb
Host smart-bedf1cdc-cf60-4438-88cf-fd3d7a729583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368511325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.368511325
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2271822666
Short name T447
Test name
Test status
Simulation time 633476190 ps
CPU time 7.19 seconds
Started Jan 14 12:30:46 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 218104 kb
Host smart-f4c55253-3c5a-4768-9e95-676a4bce6e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271822666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2271822666
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2362479714
Short name T178
Test name
Test status
Simulation time 11260042 ps
CPU time 0.94 seconds
Started Jan 14 12:30:03 PM PST 24
Finished Jan 14 12:30:06 PM PST 24
Peak memory 208300 kb
Host smart-143aea1b-9381-4458-afa2-9a63f11fbfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362479714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2362479714
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1678553867
Short name T177
Test name
Test status
Simulation time 39134928 ps
CPU time 0.81 seconds
Started Jan 14 12:29:59 PM PST 24
Finished Jan 14 12:30:01 PM PST 24
Peak memory 209292 kb
Host smart-a09ff270-6c48-45f4-a9e0-3147f5072ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678553867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1678553867
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1663242875
Short name T175
Test name
Test status
Simulation time 12427606 ps
CPU time 0.94 seconds
Started Jan 14 12:30:19 PM PST 24
Finished Jan 14 12:30:21 PM PST 24
Peak memory 208292 kb
Host smart-b8992bd7-1e9a-46be-8862-e33bf8a78460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663242875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1663242875
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1149683367
Short name T98
Test name
Test status
Simulation time 781647735 ps
CPU time 17.33 seconds
Started Jan 14 12:23:58 PM PST 24
Finished Jan 14 12:24:15 PM PST 24
Peak memory 209376 kb
Host smart-42e103fd-a35a-4fe3-81fc-57f203a12e6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149683367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1149683367
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1401832771
Short name T191
Test name
Test status
Simulation time 1775600230 ps
CPU time 47.43 seconds
Started Jan 14 12:29:59 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 283772 kb
Host smart-7150a7f7-2226-4fd9-b0f0-a6b9ed55b238
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401832771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1401832771
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2743030365
Short name T130
Test name
Test status
Simulation time 263573933 ps
CPU time 2.56 seconds
Started Jan 14 12:24:18 PM PST 24
Finished Jan 14 12:24:21 PM PST 24
Peak memory 221820 kb
Host smart-68033082-3171-4048-ad40-b959f9c873f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743030365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2743030365
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3887254945
Short name T132
Test name
Test status
Simulation time 141407484 ps
CPU time 3.1 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:18 PM PST 24
Peak memory 217632 kb
Host smart-f5d97e11-4d3e-4ea3-8c9a-fabf43e345bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887254945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3887254945
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2445218384
Short name T122
Test name
Test status
Simulation time 71783648 ps
CPU time 2.71 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:18 PM PST 24
Peak memory 212524 kb
Host smart-eb32c52d-3273-4d1c-b4e6-0b574d1244cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445218384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2445218384
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.770450596
Short name T106
Test name
Test status
Simulation time 16219998 ps
CPU time 1.13 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 219112 kb
Host smart-e2740d40-be9a-414b-ab21-10eacbdfc911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770450596 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.770450596
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.617260612
Short name T171
Test name
Test status
Simulation time 30648511 ps
CPU time 1.18 seconds
Started Jan 14 12:24:05 PM PST 24
Finished Jan 14 12:24:07 PM PST 24
Peak memory 217728 kb
Host smart-06d0d048-0f7b-4285-b3b5-9ac67d1c6cc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617260612 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.617260612
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3579187506
Short name T195
Test name
Test status
Simulation time 102334991 ps
CPU time 1.02 seconds
Started Jan 14 12:23:41 PM PST 24
Finished Jan 14 12:23:43 PM PST 24
Peak memory 211424 kb
Host smart-20905cf8-da33-4547-b8d9-d1a790c2c01c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579187506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3579187506
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4103758524
Short name T161
Test name
Test status
Simulation time 80499409 ps
CPU time 1.79 seconds
Started Jan 14 12:23:57 PM PST 24
Finished Jan 14 12:23:59 PM PST 24
Peak memory 209444 kb
Host smart-a4f250ac-0e36-4517-8dfa-cad5e33db1d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103758524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.4103758524
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1734334611
Short name T156
Test name
Test status
Simulation time 399942844 ps
CPU time 1.42 seconds
Started Jan 14 12:24:03 PM PST 24
Finished Jan 14 12:24:05 PM PST 24
Peak memory 209444 kb
Host smart-a845dfd0-2ea1-4dfb-8e5d-e7841488f51f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734334611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1734334611
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3122172330
Short name T165
Test name
Test status
Simulation time 61181689 ps
CPU time 0.85 seconds
Started Jan 14 12:23:59 PM PST 24
Finished Jan 14 12:24:00 PM PST 24
Peak memory 209560 kb
Host smart-8e91dc23-8853-4354-b801-4a70c9fc3860
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122172330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3122172330
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3584759390
Short name T296
Test name
Test status
Simulation time 15648029 ps
CPU time 0.99 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 217736 kb
Host smart-54d1c6cc-1fc4-4f51-a3a1-c5e92a23ec2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584759390 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3584759390
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2041601727
Short name T121
Test name
Test status
Simulation time 48978625 ps
CPU time 0.88 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:11 PM PST 24
Peak memory 209384 kb
Host smart-0c823ff4-46df-432c-bdfe-6542e958dda0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041601727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2041601727
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3758517269
Short name T262
Test name
Test status
Simulation time 46048808 ps
CPU time 1.1 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:11 PM PST 24
Peak memory 209192 kb
Host smart-e77e5428-bf78-4879-b929-66d1fb74d16e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758517269 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3758517269
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1490842226
Short name T215
Test name
Test status
Simulation time 2866477428 ps
CPU time 28.86 seconds
Started Jan 14 12:23:33 PM PST 24
Finished Jan 14 12:24:03 PM PST 24
Peak memory 208420 kb
Host smart-7d61394f-2697-49c8-a911-d7936590d9a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490842226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1490842226
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1825823272
Short name T235
Test name
Test status
Simulation time 5101130892 ps
CPU time 22.14 seconds
Started Jan 14 12:24:02 PM PST 24
Finished Jan 14 12:24:26 PM PST 24
Peak memory 209424 kb
Host smart-f251775f-27af-44ef-886a-be7fbf3643f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825823272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1825823272
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1450249362
Short name T238
Test name
Test status
Simulation time 166867473 ps
CPU time 1.69 seconds
Started Jan 14 12:24:00 PM PST 24
Finished Jan 14 12:24:02 PM PST 24
Peak memory 210624 kb
Host smart-b472ba40-c00b-437f-91a1-62a8a4d348ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450249362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1450249362
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3173737666
Short name T277
Test name
Test status
Simulation time 64640964 ps
CPU time 1.65 seconds
Started Jan 14 12:23:53 PM PST 24
Finished Jan 14 12:23:55 PM PST 24
Peak memory 218816 kb
Host smart-bb514345-8c6d-41ed-baea-4e9db23d6691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317373
7666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3173737666
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2282106285
Short name T143
Test name
Test status
Simulation time 72365796 ps
CPU time 2.25 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 209408 kb
Host smart-da018eb3-84ca-4698-8b7a-c2ae373f56a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282106285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2282106285
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1318065842
Short name T244
Test name
Test status
Simulation time 411280932 ps
CPU time 1.38 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 209572 kb
Host smart-f5836cd0-fd30-4e5a-a797-002d1556a195
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318065842 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1318065842
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.687625454
Short name T225
Test name
Test status
Simulation time 68724748 ps
CPU time 1.37 seconds
Started Jan 14 12:23:39 PM PST 24
Finished Jan 14 12:23:41 PM PST 24
Peak memory 209432 kb
Host smart-90b65582-9df5-4449-a45f-adf679ffa323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687625454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.687625454
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3175632023
Short name T232
Test name
Test status
Simulation time 75891569 ps
CPU time 2.22 seconds
Started Jan 14 12:24:07 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 217556 kb
Host smart-5d952647-5429-4b30-b4a0-871608e0a17e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175632023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3175632023
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.295505689
Short name T134
Test name
Test status
Simulation time 116253680 ps
CPU time 2.7 seconds
Started Jan 14 12:23:30 PM PST 24
Finished Jan 14 12:23:34 PM PST 24
Peak memory 221888 kb
Host smart-c1441482-cfc8-44e2-af10-ea5d28b89d83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295505689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.295505689
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2144632317
Short name T295
Test name
Test status
Simulation time 14521510 ps
CPU time 0.96 seconds
Started Jan 14 12:23:42 PM PST 24
Finished Jan 14 12:23:44 PM PST 24
Peak memory 208296 kb
Host smart-172b1f0e-f62f-4c6b-a38d-5383db92244a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144632317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2144632317
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3077280037
Short name T208
Test name
Test status
Simulation time 92715741 ps
CPU time 1.88 seconds
Started Jan 14 12:23:43 PM PST 24
Finished Jan 14 12:23:46 PM PST 24
Peak memory 209436 kb
Host smart-28bffa7e-ce4a-47bf-bc91-e20af29ad0a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077280037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3077280037
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2746622273
Short name T197
Test name
Test status
Simulation time 329769337 ps
CPU time 1.36 seconds
Started Jan 14 12:23:44 PM PST 24
Finished Jan 14 12:23:47 PM PST 24
Peak memory 217924 kb
Host smart-868be617-fd2c-497a-968c-f3ea600ae7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746622273 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2746622273
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.920176521
Short name T300
Test name
Test status
Simulation time 57413866 ps
CPU time 1.01 seconds
Started Jan 14 12:24:00 PM PST 24
Finished Jan 14 12:24:01 PM PST 24
Peak memory 209456 kb
Host smart-27f59fa3-b9f3-4307-8763-9f3280b31195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920176521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.920176521
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.991611134
Short name T155
Test name
Test status
Simulation time 146320747 ps
CPU time 1.05 seconds
Started Jan 14 12:23:41 PM PST 24
Finished Jan 14 12:23:43 PM PST 24
Peak memory 209244 kb
Host smart-23516902-54f7-4249-b883-ca8d5a460ed8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991611134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.991611134
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2561529230
Short name T292
Test name
Test status
Simulation time 2620319145 ps
CPU time 6.89 seconds
Started Jan 14 12:23:39 PM PST 24
Finished Jan 14 12:23:46 PM PST 24
Peak memory 209516 kb
Host smart-58ede8ef-d57f-43e0-99b8-d89c5e46f5d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561529230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2561529230
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.22270703
Short name T158
Test name
Test status
Simulation time 9261537262 ps
CPU time 38.94 seconds
Started Jan 14 12:23:44 PM PST 24
Finished Jan 14 12:24:24 PM PST 24
Peak memory 208420 kb
Host smart-3da73507-85ba-45dd-92bd-034a52f70bbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22270703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.22270703
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1064051201
Short name T95
Test name
Test status
Simulation time 37629778 ps
CPU time 1.58 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 209608 kb
Host smart-5c4b0ce4-73e5-4a75-9ae7-b37b3c624298
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106405
1201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1064051201
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.232238522
Short name T147
Test name
Test status
Simulation time 145595129 ps
CPU time 1.08 seconds
Started Jan 14 12:23:53 PM PST 24
Finished Jan 14 12:23:55 PM PST 24
Peak memory 209376 kb
Host smart-3dc2a34e-00a2-43d1-8d8f-91e4873c98dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232238522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.232238522
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3545425233
Short name T245
Test name
Test status
Simulation time 22682662 ps
CPU time 1.32 seconds
Started Jan 14 12:23:54 PM PST 24
Finished Jan 14 12:23:56 PM PST 24
Peak memory 211408 kb
Host smart-f0c72e1b-f036-46c4-88d2-3597d7dfb36c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545425233 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3545425233
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2637404431
Short name T160
Test name
Test status
Simulation time 49356002 ps
CPU time 1.31 seconds
Started Jan 14 12:23:33 PM PST 24
Finished Jan 14 12:23:35 PM PST 24
Peak memory 209400 kb
Host smart-7d77a59c-9559-431c-9730-4ecafc2172f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637404431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2637404431
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3639511226
Short name T198
Test name
Test status
Simulation time 34798334 ps
CPU time 2.3 seconds
Started Jan 14 12:23:30 PM PST 24
Finished Jan 14 12:23:33 PM PST 24
Peak memory 217532 kb
Host smart-7248852c-af69-486f-87a1-655c03de37aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639511226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3639511226
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2877654040
Short name T230
Test name
Test status
Simulation time 64884117 ps
CPU time 1.38 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 218384 kb
Host smart-8c5e1339-9942-4631-b195-a3d69f37a532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877654040 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2877654040
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1050865
Short name T269
Test name
Test status
Simulation time 14898179 ps
CPU time 0.89 seconds
Started Jan 14 12:23:58 PM PST 24
Finished Jan 14 12:24:00 PM PST 24
Peak memory 209408 kb
Host smart-e8358f39-185f-4c30-8ef5-83a677a6b9a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1050865
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4213261728
Short name T219
Test name
Test status
Simulation time 204980328 ps
CPU time 1.26 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 209328 kb
Host smart-42700928-b2e8-4575-b057-55c1eb7ae96f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213261728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.4213261728
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.522141072
Short name T138
Test name
Test status
Simulation time 44324974 ps
CPU time 2.33 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:18 PM PST 24
Peak memory 217776 kb
Host smart-8a37d23d-1719-4b15-a1ab-60d4784a189b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522141072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.522141072
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.907819284
Short name T96
Test name
Test status
Simulation time 19362599 ps
CPU time 1.54 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 217220 kb
Host smart-f1f7b9ac-68d7-45e5-b7aa-2918f5ddc854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907819284 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.907819284
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2247577065
Short name T243
Test name
Test status
Simulation time 18915799 ps
CPU time 0.87 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:09 PM PST 24
Peak memory 209440 kb
Host smart-94264860-2ff6-4502-aede-06d5748affad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247577065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2247577065
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.273290063
Short name T157
Test name
Test status
Simulation time 34621460 ps
CPU time 1.49 seconds
Started Jan 14 12:24:17 PM PST 24
Finished Jan 14 12:24:19 PM PST 24
Peak memory 209412 kb
Host smart-b0889774-4443-4762-a9b8-031a2c365c36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273290063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.273290063
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2369861839
Short name T93
Test name
Test status
Simulation time 196010598 ps
CPU time 2.32 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 217524 kb
Host smart-44a327d8-021a-4ebc-b6d1-2bac961883bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369861839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2369861839
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2873888639
Short name T202
Test name
Test status
Simulation time 16941036 ps
CPU time 0.97 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 217688 kb
Host smart-8758a89d-028e-410a-a4e6-5c4a252e8518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873888639 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2873888639
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3337248016
Short name T247
Test name
Test status
Simulation time 13868362 ps
CPU time 0.82 seconds
Started Jan 14 12:24:07 PM PST 24
Finished Jan 14 12:24:08 PM PST 24
Peak memory 209440 kb
Host smart-883bb0ac-a6ad-4e7b-92bf-856d8f1fc0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337248016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3337248016
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.452068812
Short name T159
Test name
Test status
Simulation time 31390302 ps
CPU time 1.42 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 209380 kb
Host smart-c23ff153-1e07-4a6d-a999-3bd6f957c6b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452068812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.452068812
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2474275620
Short name T233
Test name
Test status
Simulation time 51185706 ps
CPU time 1.75 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 216960 kb
Host smart-5f082615-6e76-4605-9f86-0867cef131a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474275620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2474275620
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4119813302
Short name T267
Test name
Test status
Simulation time 45716793 ps
CPU time 1.45 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:11 PM PST 24
Peak memory 217712 kb
Host smart-65b6a830-8fef-4bc5-b463-f88f41ab3a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119813302 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.4119813302
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.346988490
Short name T169
Test name
Test status
Simulation time 17010483 ps
CPU time 1.08 seconds
Started Jan 14 12:24:07 PM PST 24
Finished Jan 14 12:24:09 PM PST 24
Peak memory 208936 kb
Host smart-22f9d846-9edb-4cbd-808c-73751ea809fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346988490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.346988490
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.290907728
Short name T241
Test name
Test status
Simulation time 80594902 ps
CPU time 0.98 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:15 PM PST 24
Peak memory 209504 kb
Host smart-d51be918-9fff-41eb-8830-aeaca5d7b628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290907728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.290907728
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2399601114
Short name T200
Test name
Test status
Simulation time 69611221 ps
CPU time 2.28 seconds
Started Jan 14 12:24:01 PM PST 24
Finished Jan 14 12:24:04 PM PST 24
Peak memory 218080 kb
Host smart-62aaf33e-f785-4110-b38c-552b42229991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399601114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2399601114
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.349936405
Short name T180
Test name
Test status
Simulation time 337781897 ps
CPU time 1.9 seconds
Started Jan 14 12:24:17 PM PST 24
Finished Jan 14 12:24:19 PM PST 24
Peak memory 221204 kb
Host smart-9ff403c1-0be8-48f7-8472-dd9f0db0c7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349936405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.349936405
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1950744027
Short name T270
Test name
Test status
Simulation time 350554522 ps
CPU time 1.66 seconds
Started Jan 14 12:24:18 PM PST 24
Finished Jan 14 12:24:20 PM PST 24
Peak memory 217644 kb
Host smart-c4fbfbca-21d9-417c-b89e-f3c8099aefbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950744027 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1950744027
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.233285762
Short name T168
Test name
Test status
Simulation time 49828536 ps
CPU time 0.97 seconds
Started Jan 14 12:24:16 PM PST 24
Finished Jan 14 12:24:18 PM PST 24
Peak memory 209460 kb
Host smart-c69473fd-e914-4497-a983-04ff3e689592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233285762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.233285762
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1971718671
Short name T272
Test name
Test status
Simulation time 205169833 ps
CPU time 1.37 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 211196 kb
Host smart-1e479bd7-6a7c-400e-8f84-1787483fa2c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971718671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1971718671
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3572470874
Short name T253
Test name
Test status
Simulation time 130754979 ps
CPU time 2.08 seconds
Started Jan 14 12:24:17 PM PST 24
Finished Jan 14 12:24:25 PM PST 24
Peak memory 218668 kb
Host smart-68621a8a-86fd-42bd-b217-baabf629c46e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572470874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3572470874
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1429190293
Short name T136
Test name
Test status
Simulation time 220397127 ps
CPU time 2.37 seconds
Started Jan 14 12:24:18 PM PST 24
Finished Jan 14 12:24:21 PM PST 24
Peak memory 217700 kb
Host smart-95244540-7755-4cd5-9017-9b48af8b702d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429190293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1429190293
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.689019367
Short name T103
Test name
Test status
Simulation time 207728431 ps
CPU time 1.76 seconds
Started Jan 14 12:24:38 PM PST 24
Finished Jan 14 12:24:40 PM PST 24
Peak memory 219232 kb
Host smart-4d514bcc-6aa8-4a71-a843-64284b420919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689019367 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.689019367
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3753324406
Short name T254
Test name
Test status
Simulation time 28290252 ps
CPU time 0.9 seconds
Started Jan 14 12:24:20 PM PST 24
Finished Jan 14 12:24:22 PM PST 24
Peak memory 208420 kb
Host smart-246edce5-8df2-428c-a58e-3a230b337c02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753324406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3753324406
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3523529673
Short name T92
Test name
Test status
Simulation time 172449901 ps
CPU time 1.03 seconds
Started Jan 14 12:24:19 PM PST 24
Finished Jan 14 12:24:20 PM PST 24
Peak memory 209408 kb
Host smart-6a3d94bf-5c2f-45b3-9ab5-578412c36bc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523529673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3523529673
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2073686867
Short name T276
Test name
Test status
Simulation time 50617910 ps
CPU time 2.83 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 217908 kb
Host smart-022b8246-ae92-4ac8-8d49-cf3098d06410
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073686867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2073686867
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.206195999
Short name T199
Test name
Test status
Simulation time 20969296 ps
CPU time 1.45 seconds
Started Jan 14 12:24:25 PM PST 24
Finished Jan 14 12:24:27 PM PST 24
Peak memory 219560 kb
Host smart-452537f5-3b7a-43bc-a6e9-0faa2dd66e2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206195999 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.206195999
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3878908391
Short name T303
Test name
Test status
Simulation time 14650081 ps
CPU time 0.86 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 209336 kb
Host smart-b86f7a8a-47ef-49ab-a85a-b22c3ec97868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878908391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3878908391
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3229747827
Short name T260
Test name
Test status
Simulation time 45576353 ps
CPU time 1.96 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 211244 kb
Host smart-f5071f50-90b8-41d6-b950-3be9b440ecf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229747827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3229747827
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.451510131
Short name T193
Test name
Test status
Simulation time 46490565 ps
CPU time 3.2 seconds
Started Jan 14 12:24:01 PM PST 24
Finished Jan 14 12:24:04 PM PST 24
Peak memory 217600 kb
Host smart-cbe10f2c-249e-48d5-b280-6319369526d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451510131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.451510131
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1584830031
Short name T305
Test name
Test status
Simulation time 44103993 ps
CPU time 1.15 seconds
Started Jan 14 12:24:18 PM PST 24
Finished Jan 14 12:24:20 PM PST 24
Peak memory 217612 kb
Host smart-ed80201b-0e9b-42cc-b6fb-7eb03b6afdab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584830031 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1584830031
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1550990475
Short name T237
Test name
Test status
Simulation time 15006718 ps
CPU time 1.02 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 208700 kb
Host smart-7410b4d6-6e51-452d-8aa9-cd2f28411088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550990475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1550990475
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2242416712
Short name T297
Test name
Test status
Simulation time 104002858 ps
CPU time 1.14 seconds
Started Jan 14 12:24:18 PM PST 24
Finished Jan 14 12:24:19 PM PST 24
Peak memory 208916 kb
Host smart-b3b50e63-2efb-4f5c-8d2d-a5d654cee830
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242416712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2242416712
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.368877068
Short name T125
Test name
Test status
Simulation time 24059167 ps
CPU time 1.57 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 217988 kb
Host smart-22c7e6c1-8dfc-48e2-a8a2-a1739709c332
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368877068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.368877068
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3247270040
Short name T294
Test name
Test status
Simulation time 32576840 ps
CPU time 1 seconds
Started Jan 14 12:24:17 PM PST 24
Finished Jan 14 12:24:19 PM PST 24
Peak memory 217740 kb
Host smart-8e36ca7b-90a4-4eef-b932-7ced17f4d8c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247270040 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3247270040
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2677596146
Short name T212
Test name
Test status
Simulation time 45061704 ps
CPU time 0.83 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:11 PM PST 24
Peak memory 209196 kb
Host smart-9e8d6cdf-bf6e-435e-9c52-1fb9080f3ca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677596146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2677596146
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1004138586
Short name T298
Test name
Test status
Simulation time 35691070 ps
CPU time 1.36 seconds
Started Jan 14 12:24:23 PM PST 24
Finished Jan 14 12:24:24 PM PST 24
Peak memory 209380 kb
Host smart-a7c16d86-bf1b-411c-be21-680b069cb9dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004138586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1004138586
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4242344430
Short name T124
Test name
Test status
Simulation time 150904677 ps
CPU time 5.11 seconds
Started Jan 14 12:24:29 PM PST 24
Finished Jan 14 12:24:35 PM PST 24
Peak memory 217720 kb
Host smart-fe568b00-d6ff-4b91-8300-ece7d9c26a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242344430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4242344430
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3306502695
Short name T133
Test name
Test status
Simulation time 107597869 ps
CPU time 3.95 seconds
Started Jan 14 12:24:32 PM PST 24
Finished Jan 14 12:24:36 PM PST 24
Peak memory 217728 kb
Host smart-4cb39b76-2c28-4e38-ba7e-355b0550dfe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306502695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3306502695
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1428128157
Short name T173
Test name
Test status
Simulation time 26589128 ps
CPU time 0.99 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 208824 kb
Host smart-1083b543-fcc8-48cc-8049-c3b686ff5239
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428128157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1428128157
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.876906767
Short name T90
Test name
Test status
Simulation time 48481432 ps
CPU time 0.92 seconds
Started Jan 14 12:24:20 PM PST 24
Finished Jan 14 12:24:21 PM PST 24
Peak memory 209392 kb
Host smart-0b22b572-0bd0-47ab-bde3-1c8b3c7b7d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876906767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.876906767
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2759566590
Short name T205
Test name
Test status
Simulation time 118023952 ps
CPU time 2 seconds
Started Jan 14 12:24:38 PM PST 24
Finished Jan 14 12:24:40 PM PST 24
Peak memory 217648 kb
Host smart-89b31536-a757-4b5e-9d8b-3f54299f4963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759566590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2759566590
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2220473523
Short name T288
Test name
Test status
Simulation time 31062697 ps
CPU time 1.12 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:11 PM PST 24
Peak memory 209508 kb
Host smart-e86afaac-8805-4c10-9f8c-999c70bfc8f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220473523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2220473523
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3491074354
Short name T213
Test name
Test status
Simulation time 66764556 ps
CPU time 1.08 seconds
Started Jan 14 12:24:04 PM PST 24
Finished Jan 14 12:24:05 PM PST 24
Peak memory 209440 kb
Host smart-26ae679d-f026-4a5f-8ea7-657a888870d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491074354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3491074354
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3318393245
Short name T146
Test name
Test status
Simulation time 144410490 ps
CPU time 1.03 seconds
Started Jan 14 12:24:07 PM PST 24
Finished Jan 14 12:24:09 PM PST 24
Peak memory 211300 kb
Host smart-9f91c4cc-b2c6-4c03-9667-ebddcfb7fb0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318393245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3318393245
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3924437049
Short name T249
Test name
Test status
Simulation time 17090278 ps
CPU time 0.84 seconds
Started Jan 14 12:24:06 PM PST 24
Finished Jan 14 12:24:07 PM PST 24
Peak memory 208668 kb
Host smart-12a2e564-a61c-47cf-afc8-3ebc3d2f7b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924437049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3924437049
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1419065940
Short name T239
Test name
Test status
Simulation time 107598594 ps
CPU time 1.8 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:15 PM PST 24
Peak memory 209252 kb
Host smart-bc083225-4423-44c9-9c8a-fe1f899b7115
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419065940 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1419065940
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1656360905
Short name T211
Test name
Test status
Simulation time 1278152939 ps
CPU time 26.14 seconds
Started Jan 14 12:23:50 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 208348 kb
Host smart-0126bcfb-0393-4f9c-82b6-9fa9c678b97e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656360905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1656360905
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3827395102
Short name T109
Test name
Test status
Simulation time 1232489895 ps
CPU time 6.55 seconds
Started Jan 14 12:24:05 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 210804 kb
Host smart-2e25b57b-2f47-4bd3-944b-6e10a6510b6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827395102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3827395102
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.677647927
Short name T286
Test name
Test status
Simulation time 52123040 ps
CPU time 1.3 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 219540 kb
Host smart-30e8a6bd-15d3-4849-9bcc-65d623155e37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677647
927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.677647927
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1588782580
Short name T266
Test name
Test status
Simulation time 250297795 ps
CPU time 1.82 seconds
Started Jan 14 12:23:35 PM PST 24
Finished Jan 14 12:23:38 PM PST 24
Peak memory 209300 kb
Host smart-dc2aecfb-040b-4b4d-bc69-808b91e093b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588782580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1588782580
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2538438250
Short name T221
Test name
Test status
Simulation time 14778826 ps
CPU time 0.94 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 209472 kb
Host smart-963e00c9-7350-4a89-94a4-8caed32a9f92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538438250 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2538438250
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1676570179
Short name T301
Test name
Test status
Simulation time 90090774 ps
CPU time 1.41 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 209404 kb
Host smart-ad12c2a6-b0f3-4afb-9373-1d90f74255db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676570179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1676570179
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2964379804
Short name T304
Test name
Test status
Simulation time 43824717 ps
CPU time 1.49 seconds
Started Jan 14 12:23:35 PM PST 24
Finished Jan 14 12:23:40 PM PST 24
Peak memory 217944 kb
Host smart-98bb5aa1-67e3-4a7b-ab9f-04f5d926a134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964379804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2964379804
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.428903569
Short name T229
Test name
Test status
Simulation time 214824516 ps
CPU time 1.97 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 212868 kb
Host smart-996e17ef-276e-4d94-9778-e32bcbd604de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428903569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.428903569
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3032465107
Short name T242
Test name
Test status
Simulation time 70134413 ps
CPU time 1.29 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 208756 kb
Host smart-89cf37be-8efa-4cb0-8ef1-7978f58c72fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032465107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3032465107
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.531420040
Short name T194
Test name
Test status
Simulation time 322910340 ps
CPU time 1.63 seconds
Started Jan 14 12:23:42 PM PST 24
Finished Jan 14 12:23:45 PM PST 24
Peak memory 209376 kb
Host smart-ed2a216b-be1b-4c28-85bc-2db7e465802c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531420040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.531420040
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4064084587
Short name T154
Test name
Test status
Simulation time 46305142 ps
CPU time 1.02 seconds
Started Jan 14 12:24:04 PM PST 24
Finished Jan 14 12:24:06 PM PST 24
Peak memory 210200 kb
Host smart-0428f78f-79b6-4f3e-a48a-fc9fedb0eb62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064084587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.4064084587
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2348281510
Short name T227
Test name
Test status
Simulation time 82242915 ps
CPU time 1.79 seconds
Started Jan 14 12:24:03 PM PST 24
Finished Jan 14 12:24:05 PM PST 24
Peak memory 219676 kb
Host smart-212c8ec7-55bf-4722-91ee-9016618f0801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348281510 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2348281510
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1220720574
Short name T201
Test name
Test status
Simulation time 24276079 ps
CPU time 0.99 seconds
Started Jan 14 12:23:38 PM PST 24
Finished Jan 14 12:23:40 PM PST 24
Peak memory 209384 kb
Host smart-19c28912-ab36-4d1e-9bb2-cc8e742ad76e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220720574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1220720574
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3642379712
Short name T282
Test name
Test status
Simulation time 196250495 ps
CPU time 1.15 seconds
Started Jan 14 12:24:03 PM PST 24
Finished Jan 14 12:24:05 PM PST 24
Peak memory 209236 kb
Host smart-c62ad185-039d-4caa-9b4f-42d5b7366847
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642379712 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3642379712
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1338768484
Short name T203
Test name
Test status
Simulation time 925358010 ps
CPU time 5.27 seconds
Started Jan 14 12:23:42 PM PST 24
Finished Jan 14 12:23:48 PM PST 24
Peak memory 207980 kb
Host smart-f3b9fce7-db69-43fc-84ed-c5f9ffb75abf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338768484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1338768484
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.106878517
Short name T289
Test name
Test status
Simulation time 679640780 ps
CPU time 7.42 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:20 PM PST 24
Peak memory 209428 kb
Host smart-a54177bc-7aad-401c-b70a-0037b8e56376
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106878517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.106878517
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3434396512
Short name T265
Test name
Test status
Simulation time 248710482 ps
CPU time 1.29 seconds
Started Jan 14 12:24:11 PM PST 24
Finished Jan 14 12:24:13 PM PST 24
Peak memory 210480 kb
Host smart-16906466-e9eb-47a5-8e82-1ec3e1f1c40d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434396512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3434396512
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.922594166
Short name T127
Test name
Test status
Simulation time 193286408 ps
CPU time 1.81 seconds
Started Jan 14 12:24:04 PM PST 24
Finished Jan 14 12:24:07 PM PST 24
Peak memory 218656 kb
Host smart-4f9f97a0-d624-4abf-94ec-0e1a728c5d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922594
166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.922594166
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3490856825
Short name T144
Test name
Test status
Simulation time 227918933 ps
CPU time 1.28 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 208160 kb
Host smart-1f5fbc53-cf7b-4c34-ad24-f521adba7293
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490856825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3490856825
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2134694099
Short name T287
Test name
Test status
Simulation time 81900966 ps
CPU time 1.5 seconds
Started Jan 14 12:23:58 PM PST 24
Finished Jan 14 12:24:00 PM PST 24
Peak memory 211452 kb
Host smart-e8691b95-16fe-4edb-bb0b-450127332769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134694099 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2134694099
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.282095479
Short name T248
Test name
Test status
Simulation time 144566626 ps
CPU time 1.12 seconds
Started Jan 14 12:23:59 PM PST 24
Finished Jan 14 12:24:00 PM PST 24
Peak memory 209516 kb
Host smart-260c1e5e-2553-4891-85a5-ab29ef1ee188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282095479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.282095479
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.130707126
Short name T91
Test name
Test status
Simulation time 23025320 ps
CPU time 1.57 seconds
Started Jan 14 12:23:48 PM PST 24
Finished Jan 14 12:23:50 PM PST 24
Peak memory 218600 kb
Host smart-35ca0bf8-14b6-477f-89df-069ba62a9941
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130707126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.130707126
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1487198533
Short name T273
Test name
Test status
Simulation time 35120286 ps
CPU time 1.26 seconds
Started Jan 14 12:23:44 PM PST 24
Finished Jan 14 12:23:51 PM PST 24
Peak memory 209432 kb
Host smart-4eb870ba-106e-43f7-b9b2-97c9666f62ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487198533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1487198533
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3701029504
Short name T148
Test name
Test status
Simulation time 18155447 ps
CPU time 1.15 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 209416 kb
Host smart-06bc2d1c-0968-40eb-927f-2f8a3893214d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701029504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3701029504
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2722935601
Short name T290
Test name
Test status
Simulation time 26438233 ps
CPU time 1.49 seconds
Started Jan 14 12:24:02 PM PST 24
Finished Jan 14 12:24:04 PM PST 24
Peak memory 218420 kb
Host smart-1d79766c-2b27-40fd-aedb-790f30d02d39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722935601 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2722935601
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.343592853
Short name T268
Test name
Test status
Simulation time 13028609 ps
CPU time 1.01 seconds
Started Jan 14 12:24:05 PM PST 24
Finished Jan 14 12:24:06 PM PST 24
Peak memory 208888 kb
Host smart-9f0dfbeb-a3ae-4442-a267-52b2f2732557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343592853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.343592853
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1446808666
Short name T118
Test name
Test status
Simulation time 163332313 ps
CPU time 1.45 seconds
Started Jan 14 12:23:56 PM PST 24
Finished Jan 14 12:23:57 PM PST 24
Peak memory 209260 kb
Host smart-923b593b-2a25-4113-8961-6ceedd935f84
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446808666 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1446808666
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3186295552
Short name T281
Test name
Test status
Simulation time 911810553 ps
CPU time 7.33 seconds
Started Jan 14 12:23:46 PM PST 24
Finished Jan 14 12:23:54 PM PST 24
Peak memory 208392 kb
Host smart-76eb5291-7e7f-470a-93f4-b036dc88ed12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186295552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3186295552
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1474021500
Short name T246
Test name
Test status
Simulation time 540969501 ps
CPU time 12.33 seconds
Started Jan 14 12:23:41 PM PST 24
Finished Jan 14 12:23:54 PM PST 24
Peak memory 209376 kb
Host smart-d5653578-c685-42c9-b4d7-558f42d431b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474021500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1474021500
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2075813435
Short name T209
Test name
Test status
Simulation time 207456162 ps
CPU time 1.83 seconds
Started Jan 14 12:23:46 PM PST 24
Finished Jan 14 12:23:49 PM PST 24
Peak memory 210236 kb
Host smart-a5a1cbf2-dd6e-426f-b0cf-a49552d4ad98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075813435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2075813435
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2646754089
Short name T240
Test name
Test status
Simulation time 60576754 ps
CPU time 1.85 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 218836 kb
Host smart-895022d6-73bf-4487-8a00-d296472e8d9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264675
4089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2646754089
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3292653243
Short name T234
Test name
Test status
Simulation time 334111371 ps
CPU time 2.14 seconds
Started Jan 14 12:23:46 PM PST 24
Finished Jan 14 12:23:49 PM PST 24
Peak memory 209304 kb
Host smart-e278b682-7fa0-4eb7-ae63-40869e69a204
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292653243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3292653243
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.10087543
Short name T145
Test name
Test status
Simulation time 185601553 ps
CPU time 1.97 seconds
Started Jan 14 12:24:04 PM PST 24
Finished Jan 14 12:24:07 PM PST 24
Peak memory 209440 kb
Host smart-4e92994d-f797-4642-945e-02ddbdb369b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087543 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.10087543
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1267830990
Short name T275
Test name
Test status
Simulation time 25115085 ps
CPU time 1.02 seconds
Started Jan 14 12:23:52 PM PST 24
Finished Jan 14 12:23:54 PM PST 24
Peak memory 209464 kb
Host smart-20dadeea-eb8b-4d2d-bdcf-095b12ed001e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267830990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1267830990
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4096115166
Short name T278
Test name
Test status
Simulation time 36013851 ps
CPU time 2.67 seconds
Started Jan 14 12:24:13 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 218480 kb
Host smart-444c8275-0962-405e-a8c6-e42309542ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096115166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.4096115166
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2710160023
Short name T214
Test name
Test status
Simulation time 72313784 ps
CPU time 2.58 seconds
Started Jan 14 12:24:07 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 217680 kb
Host smart-562099b8-9d3b-445b-a90e-e97ceeaa6b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710160023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2710160023
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2198024661
Short name T210
Test name
Test status
Simulation time 206516471 ps
CPU time 1.16 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:09 PM PST 24
Peak memory 219044 kb
Host smart-a2d0c972-8617-47b4-a040-c6e0253ba231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198024661 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2198024661
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2663249631
Short name T167
Test name
Test status
Simulation time 12338712 ps
CPU time 0.83 seconds
Started Jan 14 12:24:16 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 209272 kb
Host smart-d30bbbe5-c3f2-4b68-af1b-b3462435a269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663249631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2663249631
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3818695568
Short name T207
Test name
Test status
Simulation time 39400248 ps
CPU time 1 seconds
Started Jan 14 12:23:50 PM PST 24
Finished Jan 14 12:23:51 PM PST 24
Peak memory 207716 kb
Host smart-b5d1cee0-8c63-4e0c-a229-9bbc204dddac
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818695568 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3818695568
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1079697165
Short name T204
Test name
Test status
Simulation time 1825597331 ps
CPU time 8.02 seconds
Started Jan 14 12:23:56 PM PST 24
Finished Jan 14 12:24:04 PM PST 24
Peak memory 207792 kb
Host smart-9bbc5cce-9643-40a2-831b-a696a219c5c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079697165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1079697165
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4186025763
Short name T142
Test name
Test status
Simulation time 2530708985 ps
CPU time 16.12 seconds
Started Jan 14 12:24:07 PM PST 24
Finished Jan 14 12:24:23 PM PST 24
Peak memory 209436 kb
Host smart-626da55b-5489-41bf-99fd-2b52483e7bc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186025763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4186025763
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3089433747
Short name T206
Test name
Test status
Simulation time 131687072 ps
CPU time 1.24 seconds
Started Jan 14 12:23:47 PM PST 24
Finished Jan 14 12:23:48 PM PST 24
Peak memory 210524 kb
Host smart-8773553f-c234-4886-9552-b51a596ea9a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089433747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3089433747
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3553351073
Short name T226
Test name
Test status
Simulation time 41145294 ps
CPU time 1.25 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:11 PM PST 24
Peak memory 218692 kb
Host smart-0a955511-fc27-46dd-b5c1-3871e9b96b7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355335
1073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3553351073
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1125426759
Short name T220
Test name
Test status
Simulation time 70347632 ps
CPU time 2.21 seconds
Started Jan 14 12:24:02 PM PST 24
Finished Jan 14 12:24:05 PM PST 24
Peak memory 209376 kb
Host smart-06f7440f-399d-4767-bb2d-49a5b5b1a11e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125426759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1125426759
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3009601730
Short name T299
Test name
Test status
Simulation time 146497237 ps
CPU time 1.51 seconds
Started Jan 14 12:23:54 PM PST 24
Finished Jan 14 12:23:57 PM PST 24
Peak memory 211468 kb
Host smart-92ed4eab-073b-4dcf-854f-7910f4617142
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009601730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3009601730
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4107713277
Short name T302
Test name
Test status
Simulation time 176496829 ps
CPU time 2.16 seconds
Started Jan 14 12:23:54 PM PST 24
Finished Jan 14 12:23:57 PM PST 24
Peak memory 218552 kb
Host smart-aea288e5-9207-42dd-b66c-39c1f8f9fea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107713277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.4107713277
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4097996538
Short name T135
Test name
Test status
Simulation time 834073299 ps
CPU time 3.05 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 217612 kb
Host smart-5f5133c0-4126-4608-bbea-ad0bdcf4fe4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097996538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4097996538
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3557921010
Short name T170
Test name
Test status
Simulation time 36184690 ps
CPU time 1.54 seconds
Started Jan 14 12:24:04 PM PST 24
Finished Jan 14 12:24:06 PM PST 24
Peak memory 219560 kb
Host smart-9bff3389-1796-4f2a-894f-708362e56e44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557921010 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3557921010
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1638469232
Short name T149
Test name
Test status
Simulation time 18210431 ps
CPU time 1.11 seconds
Started Jan 14 12:24:19 PM PST 24
Finished Jan 14 12:24:21 PM PST 24
Peak memory 209400 kb
Host smart-7de67ca4-4a27-49d8-9906-f4f9ee667b93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638469232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1638469232
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3983056317
Short name T274
Test name
Test status
Simulation time 49288812 ps
CPU time 1.27 seconds
Started Jan 14 12:23:50 PM PST 24
Finished Jan 14 12:23:52 PM PST 24
Peak memory 209384 kb
Host smart-54d4d12e-9000-4a51-a5c1-7fd3e102c72d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983056317 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3983056317
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3193336156
Short name T223
Test name
Test status
Simulation time 1025523308 ps
CPU time 6.75 seconds
Started Jan 14 12:23:50 PM PST 24
Finished Jan 14 12:23:58 PM PST 24
Peak memory 209488 kb
Host smart-f7044fa0-15eb-4160-bbc9-ae3261b9e848
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193336156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3193336156
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4009328451
Short name T164
Test name
Test status
Simulation time 7628992787 ps
CPU time 17.94 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:29 PM PST 24
Peak memory 209160 kb
Host smart-9b322874-6399-42eb-b5e6-79731b019ea8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009328451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4009328451
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.12831435
Short name T280
Test name
Test status
Simulation time 436042113 ps
CPU time 2.44 seconds
Started Jan 14 12:23:54 PM PST 24
Finished Jan 14 12:23:57 PM PST 24
Peak memory 210796 kb
Host smart-a5210bf2-eb1f-4532-80d4-e9d3e9b97743
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12831435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.12831435
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1469719175
Short name T217
Test name
Test status
Simulation time 74110291 ps
CPU time 2.36 seconds
Started Jan 14 12:24:11 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 218296 kb
Host smart-1e5bbaa1-1cb9-4d94-867a-d86381b7418b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146971
9175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1469719175
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2274368818
Short name T251
Test name
Test status
Simulation time 113970600 ps
CPU time 3.28 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:19 PM PST 24
Peak memory 209324 kb
Host smart-e2aa53c8-ba3e-4e51-b9b5-00ea36394087
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274368818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2274368818
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1793016706
Short name T218
Test name
Test status
Simulation time 38762643 ps
CPU time 1.32 seconds
Started Jan 14 12:23:35 PM PST 24
Finished Jan 14 12:23:37 PM PST 24
Peak memory 209384 kb
Host smart-ccb32507-0a70-4b19-963d-05fca7006f86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793016706 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1793016706
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4096889854
Short name T140
Test name
Test status
Simulation time 151084843 ps
CPU time 1.07 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 209348 kb
Host smart-c497ac3c-0b19-4a9a-8fb2-a5e2a051d3a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096889854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.4096889854
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1450974399
Short name T166
Test name
Test status
Simulation time 98654106 ps
CPU time 3.11 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 217560 kb
Host smart-83dd8b10-a6cf-4206-b3b2-ffba1341d13a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450974399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1450974399
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1922933941
Short name T222
Test name
Test status
Simulation time 25854848 ps
CPU time 1.12 seconds
Started Jan 14 12:24:22 PM PST 24
Finished Jan 14 12:24:29 PM PST 24
Peak memory 217584 kb
Host smart-bd329518-8ee7-4e9f-bad0-d3a51ee18ba6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922933941 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1922933941
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1270820459
Short name T250
Test name
Test status
Simulation time 13253378 ps
CPU time 0.86 seconds
Started Jan 14 12:24:11 PM PST 24
Finished Jan 14 12:24:13 PM PST 24
Peak memory 208988 kb
Host smart-edc1daab-9322-45c0-8723-d10fe30833a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270820459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1270820459
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3116919277
Short name T255
Test name
Test status
Simulation time 85170093 ps
CPU time 1.32 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 207340 kb
Host smart-857165d1-ff90-4dab-81ce-bf50042c9162
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116919277 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3116919277
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1892369592
Short name T252
Test name
Test status
Simulation time 366524453 ps
CPU time 4.82 seconds
Started Jan 14 12:24:13 PM PST 24
Finished Jan 14 12:24:19 PM PST 24
Peak memory 209336 kb
Host smart-ab06cf8e-c306-48a7-8072-b4b093a84eba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892369592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1892369592
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2805158798
Short name T284
Test name
Test status
Simulation time 1483265508 ps
CPU time 4.73 seconds
Started Jan 14 12:24:13 PM PST 24
Finished Jan 14 12:24:19 PM PST 24
Peak memory 209376 kb
Host smart-a6a4d327-484b-4544-b4f0-49301e7225b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805158798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2805158798
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.987926727
Short name T257
Test name
Test status
Simulation time 255044901 ps
CPU time 1.95 seconds
Started Jan 14 12:23:57 PM PST 24
Finished Jan 14 12:24:00 PM PST 24
Peak memory 210580 kb
Host smart-eba426fe-af88-4abd-a942-0d57986a3e31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987926727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.987926727
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1028395539
Short name T231
Test name
Test status
Simulation time 299005672 ps
CPU time 1.54 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 217688 kb
Host smart-775f8e79-530c-4fcb-bc4c-535b62caf2fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102839
5539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1028395539
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2578145013
Short name T141
Test name
Test status
Simulation time 139932316 ps
CPU time 1.81 seconds
Started Jan 14 12:24:04 PM PST 24
Finished Jan 14 12:24:06 PM PST 24
Peak memory 209276 kb
Host smart-2b0ae451-c3a0-42d4-9c94-a212da16beb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578145013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2578145013
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1711938469
Short name T163
Test name
Test status
Simulation time 226513043 ps
CPU time 1.29 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 209420 kb
Host smart-638478e0-1acb-46b8-830b-5e03d0e6f438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711938469 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1711938469
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3938319116
Short name T224
Test name
Test status
Simulation time 247494290 ps
CPU time 1.9 seconds
Started Jan 14 12:24:19 PM PST 24
Finished Jan 14 12:24:21 PM PST 24
Peak memory 217512 kb
Host smart-ef361888-393b-4770-9cae-26f8f1c88a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938319116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3938319116
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2371296456
Short name T119
Test name
Test status
Simulation time 426148748 ps
CPU time 4.12 seconds
Started Jan 14 12:24:07 PM PST 24
Finished Jan 14 12:24:11 PM PST 24
Peak memory 217636 kb
Host smart-8d120f5a-45fd-4d7a-ba83-b719aa57a3bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371296456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2371296456
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3195181236
Short name T196
Test name
Test status
Simulation time 29912041 ps
CPU time 2.21 seconds
Started Jan 14 12:24:19 PM PST 24
Finished Jan 14 12:24:21 PM PST 24
Peak memory 219688 kb
Host smart-c0046144-7d11-4a60-9354-f597b8d399f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195181236 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3195181236
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3398326829
Short name T293
Test name
Test status
Simulation time 85470445 ps
CPU time 0.99 seconds
Started Jan 14 12:24:10 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 209492 kb
Host smart-15533797-ce9f-4a62-947e-e509ae4e34d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398326829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3398326829
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3559695989
Short name T264
Test name
Test status
Simulation time 60407915 ps
CPU time 0.98 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:09 PM PST 24
Peak memory 209364 kb
Host smart-cd09a3c4-a736-40df-a004-eeb71be0432d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559695989 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3559695989
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1297645232
Short name T236
Test name
Test status
Simulation time 225003031 ps
CPU time 5.67 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:22 PM PST 24
Peak memory 209340 kb
Host smart-854a051a-1e8f-4848-8546-dd440788cfa4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297645232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1297645232
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.607812941
Short name T259
Test name
Test status
Simulation time 3501630943 ps
CPU time 19.08 seconds
Started Jan 14 12:24:03 PM PST 24
Finished Jan 14 12:24:23 PM PST 24
Peak memory 209364 kb
Host smart-a7074e2b-549f-45e6-81a9-62138dd66d3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607812941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.607812941
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2768618333
Short name T228
Test name
Test status
Simulation time 146157786 ps
CPU time 3.87 seconds
Started Jan 14 12:24:11 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 211048 kb
Host smart-f6b34934-3df4-404b-b858-ceba98e91c55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768618333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2768618333
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2734378584
Short name T174
Test name
Test status
Simulation time 119506666 ps
CPU time 1.91 seconds
Started Jan 14 12:24:13 PM PST 24
Finished Jan 14 12:24:15 PM PST 24
Peak memory 218620 kb
Host smart-3f120408-1bba-4955-9f77-1f979b370e7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273437
8584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2734378584
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3928907499
Short name T110
Test name
Test status
Simulation time 85066431 ps
CPU time 1.07 seconds
Started Jan 14 12:24:07 PM PST 24
Finished Jan 14 12:24:08 PM PST 24
Peak memory 209536 kb
Host smart-8d536aaf-2df9-47c9-851e-aea0eafa8ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928907499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3928907499
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4002599354
Short name T172
Test name
Test status
Simulation time 73770979 ps
CPU time 1.16 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 209096 kb
Host smart-8fc2f189-4249-4e5e-bf64-e44239941ed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002599354 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4002599354
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3182264806
Short name T120
Test name
Test status
Simulation time 53507207 ps
CPU time 0.93 seconds
Started Jan 14 12:24:12 PM PST 24
Finished Jan 14 12:24:14 PM PST 24
Peak memory 208964 kb
Host smart-e13c3333-c24d-4d80-b076-d953b0e9acef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182264806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3182264806
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1137070053
Short name T283
Test name
Test status
Simulation time 23885926 ps
CPU time 1.49 seconds
Started Jan 14 12:24:28 PM PST 24
Finished Jan 14 12:24:30 PM PST 24
Peak memory 217656 kb
Host smart-46a18075-99e9-456e-a41a-63da664a2935
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137070053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1137070053
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1858883201
Short name T216
Test name
Test status
Simulation time 96338231 ps
CPU time 1.5 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 218956 kb
Host smart-0e70ce8a-5d3f-475c-8dcb-0b54850f81e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858883201 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1858883201
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3748834562
Short name T162
Test name
Test status
Simulation time 24682989 ps
CPU time 0.84 seconds
Started Jan 14 12:23:59 PM PST 24
Finished Jan 14 12:24:01 PM PST 24
Peak memory 209240 kb
Host smart-0820a76b-82ef-47cb-87ad-9993f0feb181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748834562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3748834562
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1934001756
Short name T263
Test name
Test status
Simulation time 286134282 ps
CPU time 2.54 seconds
Started Jan 14 12:24:13 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 207844 kb
Host smart-6d6073af-f5eb-43ef-ae36-8691c5d5608f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934001756 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1934001756
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1679399870
Short name T256
Test name
Test status
Simulation time 916968820 ps
CPU time 10.51 seconds
Started Jan 14 12:24:18 PM PST 24
Finished Jan 14 12:24:29 PM PST 24
Peak memory 208300 kb
Host smart-7a97273c-ece5-452b-b276-cf22d26f4665
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679399870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1679399870
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.382064541
Short name T285
Test name
Test status
Simulation time 815253181 ps
CPU time 6.57 seconds
Started Jan 14 12:24:16 PM PST 24
Finished Jan 14 12:24:23 PM PST 24
Peak memory 209304 kb
Host smart-939d8dce-cc15-44c1-bc84-9218346cfba1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382064541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.382064541
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4078169531
Short name T271
Test name
Test status
Simulation time 552205596 ps
CPU time 3.74 seconds
Started Jan 14 12:24:13 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 210772 kb
Host smart-485efaa6-b515-4134-9802-179a0eb03771
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078169531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.4078169531
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.939835574
Short name T291
Test name
Test status
Simulation time 60517135 ps
CPU time 1.17 seconds
Started Jan 14 12:24:18 PM PST 24
Finished Jan 14 12:24:19 PM PST 24
Peak memory 218172 kb
Host smart-0f8a82f5-fec4-49a5-8751-5bd30a682069
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939835
574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.939835574
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1781756367
Short name T258
Test name
Test status
Simulation time 35287870 ps
CPU time 1.07 seconds
Started Jan 14 12:24:15 PM PST 24
Finished Jan 14 12:24:17 PM PST 24
Peak memory 209092 kb
Host smart-de2921e7-b0fe-4ec5-926c-533072c7c5d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781756367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1781756367
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.623033302
Short name T279
Test name
Test status
Simulation time 77567166 ps
CPU time 1.02 seconds
Started Jan 14 12:24:03 PM PST 24
Finished Jan 14 12:24:05 PM PST 24
Peak memory 209472 kb
Host smart-eef605c6-a7f0-4dde-a759-a80549a90b59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623033302 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.623033302
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2046366228
Short name T261
Test name
Test status
Simulation time 46858283 ps
CPU time 1.26 seconds
Started Jan 14 12:24:14 PM PST 24
Finished Jan 14 12:24:16 PM PST 24
Peak memory 209424 kb
Host smart-84b96cc0-86bd-4027-aa9a-6b50d18eacec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046366228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2046366228
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2477267985
Short name T128
Test name
Test status
Simulation time 379197575 ps
CPU time 3.86 seconds
Started Jan 14 12:24:16 PM PST 24
Finished Jan 14 12:24:20 PM PST 24
Peak memory 217656 kb
Host smart-79d2f1a5-de8a-44bf-bd63-612bbd77914c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477267985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2477267985
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.245859444
Short name T123
Test name
Test status
Simulation time 189741050 ps
CPU time 2.11 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:12 PM PST 24
Peak memory 221300 kb
Host smart-0ab9bf3f-2091-4f71-b320-460209bc006d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245859444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.245859444
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1004952223
Short name T662
Test name
Test status
Simulation time 84642789 ps
CPU time 0.91 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:10 PM PST 24
Peak memory 209568 kb
Host smart-864400c9-7a74-49b4-acf1-3514de4e8a93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004952223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1004952223
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.930360161
Short name T715
Test name
Test status
Simulation time 1625787726 ps
CPU time 12.11 seconds
Started Jan 14 12:29:54 PM PST 24
Finished Jan 14 12:30:09 PM PST 24
Peak memory 218128 kb
Host smart-e2c9b558-461b-4145-9d34-fa6dc61abb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930360161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.930360161
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1672890695
Short name T798
Test name
Test status
Simulation time 430222647 ps
CPU time 2.14 seconds
Started Jan 14 12:29:53 PM PST 24
Finished Jan 14 12:29:59 PM PST 24
Peak memory 209604 kb
Host smart-2abcd407-04e4-4539-92ea-837b647954d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672890695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.1672890695
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.808850329
Short name T685
Test name
Test status
Simulation time 2956664010 ps
CPU time 39.03 seconds
Started Jan 14 12:29:57 PM PST 24
Finished Jan 14 12:30:37 PM PST 24
Peak memory 218128 kb
Host smart-28321ade-57da-438a-84cf-78144db49c96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808850329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.808850329
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1762721335
Short name T669
Test name
Test status
Simulation time 796622480 ps
CPU time 16.79 seconds
Started Jan 14 12:29:58 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 217944 kb
Host smart-e9905247-dcbc-46e8-9c32-44a60bd43f46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762721335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.1762721335
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.414250029
Short name T536
Test name
Test status
Simulation time 236048327 ps
CPU time 2.78 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:10 PM PST 24
Peak memory 218052 kb
Host smart-1be568aa-7a88-4b96-b96e-e9cc35ad51ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414250029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.414250029
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.534247503
Short name T684
Test name
Test status
Simulation time 771120873 ps
CPU time 12.57 seconds
Started Jan 14 12:30:04 PM PST 24
Finished Jan 14 12:30:18 PM PST 24
Peak memory 212904 kb
Host smart-3222a879-f413-4833-8bc0-d53d0f495f8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534247503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.534247503
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2103761974
Short name T677
Test name
Test status
Simulation time 398982054 ps
CPU time 2.31 seconds
Started Jan 14 12:29:59 PM PST 24
Finished Jan 14 12:30:03 PM PST 24
Peak memory 212788 kb
Host smart-01d8320b-fe92-4377-b95f-af7b81095d6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103761974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2103761974
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1983322306
Short name T511
Test name
Test status
Simulation time 1025077963 ps
CPU time 15.87 seconds
Started Jan 14 12:29:55 PM PST 24
Finished Jan 14 12:30:13 PM PST 24
Peak memory 226404 kb
Host smart-531ae7d8-95f2-482c-a163-7914097bf78b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983322306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1983322306
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.953740258
Short name T331
Test name
Test status
Simulation time 22692435 ps
CPU time 1.54 seconds
Started Jan 14 12:29:58 PM PST 24
Finished Jan 14 12:30:01 PM PST 24
Peak memory 218088 kb
Host smart-1f277409-9ba8-4081-8b12-4060b3ca5ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953740258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.953740258
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1776534508
Short name T77
Test name
Test status
Simulation time 424456664 ps
CPU time 12.31 seconds
Started Jan 14 12:29:53 PM PST 24
Finished Jan 14 12:30:09 PM PST 24
Peak memory 213676 kb
Host smart-593c504e-7f15-4dda-8793-7352e3e226c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776534508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1776534508
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3789369463
Short name T111
Test name
Test status
Simulation time 235987841 ps
CPU time 24.96 seconds
Started Jan 14 12:30:01 PM PST 24
Finished Jan 14 12:30:28 PM PST 24
Peak memory 272908 kb
Host smart-324d3181-e114-4417-a3d2-f2b6470aa4c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789369463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3789369463
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.195922793
Short name T353
Test name
Test status
Simulation time 614356219 ps
CPU time 11.83 seconds
Started Jan 14 12:30:11 PM PST 24
Finished Jan 14 12:30:24 PM PST 24
Peak memory 218608 kb
Host smart-427ed7e7-deb9-4f51-81fc-f0d2dfc4f687
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195922793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.195922793
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.152705538
Short name T796
Test name
Test status
Simulation time 488522788 ps
CPU time 16.11 seconds
Started Jan 14 12:29:51 PM PST 24
Finished Jan 14 12:30:12 PM PST 24
Peak memory 218040 kb
Host smart-13764650-098f-4d51-ba2e-006d95cd47d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152705538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.152705538
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2140206544
Short name T927
Test name
Test status
Simulation time 1794384821 ps
CPU time 10.52 seconds
Started Jan 14 12:29:54 PM PST 24
Finished Jan 14 12:30:07 PM PST 24
Peak memory 218084 kb
Host smart-5eb2308d-504d-4eee-89d4-f760a97db208
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140206544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
140206544
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2173630570
Short name T391
Test name
Test status
Simulation time 1984903656 ps
CPU time 10.99 seconds
Started Jan 14 12:29:58 PM PST 24
Finished Jan 14 12:30:11 PM PST 24
Peak memory 218096 kb
Host smart-6af70505-1455-4d04-9aea-2d1f9e281465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173630570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2173630570
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3272569166
Short name T339
Test name
Test status
Simulation time 66495206 ps
CPU time 3.23 seconds
Started Jan 14 12:30:01 PM PST 24
Finished Jan 14 12:30:06 PM PST 24
Peak memory 213916 kb
Host smart-e0c2444f-2a79-48e1-bb85-3a13133bef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272569166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3272569166
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3780621949
Short name T889
Test name
Test status
Simulation time 225783311 ps
CPU time 20.51 seconds
Started Jan 14 12:30:02 PM PST 24
Finished Jan 14 12:30:25 PM PST 24
Peak memory 251024 kb
Host smart-31c3de1f-6342-47a1-b934-aa9c49b5ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780621949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3780621949
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.730697142
Short name T437
Test name
Test status
Simulation time 73803493 ps
CPU time 7.1 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 251012 kb
Host smart-beafd78a-a09b-4b48-b309-2442b20c1fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730697142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.730697142
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2748477751
Short name T414
Test name
Test status
Simulation time 25961753182 ps
CPU time 186 seconds
Started Jan 14 12:30:02 PM PST 24
Finished Jan 14 12:33:10 PM PST 24
Peak memory 268136 kb
Host smart-9184cc27-9918-42b3-863b-6e2340731c62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748477751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2748477751
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1990020247
Short name T35
Test name
Test status
Simulation time 22722518 ps
CPU time 0.76 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:09 PM PST 24
Peak memory 208188 kb
Host smart-46482620-d61b-481b-8fda-00a3a68bddfd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990020247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1990020247
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2215064098
Short name T620
Test name
Test status
Simulation time 14373168 ps
CPU time 1.19 seconds
Started Jan 14 12:30:10 PM PST 24
Finished Jan 14 12:30:12 PM PST 24
Peak memory 209764 kb
Host smart-d8add0db-fa8e-4703-b9ba-a8c523dc49c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215064098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2215064098
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.257085313
Short name T307
Test name
Test status
Simulation time 35232741 ps
CPU time 0.81 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:09 PM PST 24
Peak memory 208016 kb
Host smart-d6e5bd6d-2d1a-4a5a-ac50-2660feeae31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257085313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.257085313
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2882019524
Short name T498
Test name
Test status
Simulation time 1276688200 ps
CPU time 12.09 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:18 PM PST 24
Peak memory 218156 kb
Host smart-90df64aa-50b3-4a9c-8689-fdd25df36afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882019524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2882019524
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3220175654
Short name T814
Test name
Test status
Simulation time 10400103078 ps
CPU time 8.82 seconds
Started Jan 14 12:30:11 PM PST 24
Finished Jan 14 12:30:21 PM PST 24
Peak memory 209664 kb
Host smart-cfbd7a96-50cf-4cf7-ac8e-01ea42830770
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220175654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.3220175654
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1515407511
Short name T601
Test name
Test status
Simulation time 8793511364 ps
CPU time 56.28 seconds
Started Jan 14 12:30:04 PM PST 24
Finished Jan 14 12:31:02 PM PST 24
Peak memory 218520 kb
Host smart-aa2d811c-2195-4112-958d-f46601607de8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515407511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1515407511
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.905379899
Short name T842
Test name
Test status
Simulation time 592227822 ps
CPU time 8.32 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 209688 kb
Host smart-9c6dbfc0-13ce-48cc-81cf-7cf10d755def
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905379899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_p
riority.905379899
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1627209425
Short name T518
Test name
Test status
Simulation time 867077714 ps
CPU time 2.02 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:30:04 PM PST 24
Peak memory 218004 kb
Host smart-ade606e5-3367-4120-9984-eac1d7a4ca06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627209425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1627209425
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2858999391
Short name T888
Test name
Test status
Simulation time 3149975443 ps
CPU time 21.28 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:29 PM PST 24
Peak memory 213400 kb
Host smart-805e9282-bd4b-4ef6-8310-d7cc435aeaea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858999391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2858999391
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.4166851919
Short name T3
Test name
Test status
Simulation time 1037451425 ps
CPU time 13.33 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:30:14 PM PST 24
Peak memory 213568 kb
Host smart-3691d3eb-bed2-4786-8da3-aa87fa7d8935
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166851919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
4166851919
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1300833291
Short name T398
Test name
Test status
Simulation time 5225035040 ps
CPU time 49.56 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 251076 kb
Host smart-019e5277-a067-46b5-8a01-da0e57604f13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300833291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1300833291
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.773170252
Short name T386
Test name
Test status
Simulation time 1945301562 ps
CPU time 31.31 seconds
Started Jan 14 12:30:02 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 250704 kb
Host smart-3e26ff6b-f82b-4fa3-a950-f8a4b53c4fce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773170252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.773170252
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3024042061
Short name T334
Test name
Test status
Simulation time 48453142 ps
CPU time 1.79 seconds
Started Jan 14 12:30:11 PM PST 24
Finished Jan 14 12:30:14 PM PST 24
Peak memory 218136 kb
Host smart-d9372b62-810f-48cb-9636-e9ecd867fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024042061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3024042061
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3682518674
Short name T80
Test name
Test status
Simulation time 411847614 ps
CPU time 8.78 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:30:10 PM PST 24
Peak memory 213636 kb
Host smart-9b860691-ecd8-42be-8920-5eca45c7221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682518674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3682518674
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3331152365
Short name T73
Test name
Test status
Simulation time 549108790 ps
CPU time 19.03 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:30:21 PM PST 24
Peak memory 271876 kb
Host smart-14b04b39-837c-43a2-9561-1603fc27d9e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331152365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3331152365
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2803351763
Short name T653
Test name
Test status
Simulation time 845789887 ps
CPU time 11.66 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 218156 kb
Host smart-5a23823b-a235-493b-be7e-7fff14c2a3dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803351763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2803351763
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3655597526
Short name T401
Test name
Test status
Simulation time 2640627383 ps
CPU time 15.51 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:24 PM PST 24
Peak memory 218156 kb
Host smart-7443f048-8b38-43b5-8f7b-52d97c99676f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655597526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3655597526
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.262572719
Short name T495
Test name
Test status
Simulation time 349295076 ps
CPU time 8.11 seconds
Started Jan 14 12:29:50 PM PST 24
Finished Jan 14 12:30:04 PM PST 24
Peak memory 217972 kb
Host smart-2f5e8db9-c5f4-4bea-b607-00c79ca59707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262572719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.262572719
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.233764801
Short name T875
Test name
Test status
Simulation time 232334781 ps
CPU time 9.24 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:17 PM PST 24
Peak memory 218136 kb
Host smart-1ad1cc47-0969-45a2-b9db-227fe8e31e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233764801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.233764801
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3509085171
Short name T583
Test name
Test status
Simulation time 116535885 ps
CPU time 3.45 seconds
Started Jan 14 12:29:58 PM PST 24
Finished Jan 14 12:30:02 PM PST 24
Peak memory 213320 kb
Host smart-ab28989a-4870-458f-9514-f525324f0c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509085171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3509085171
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1360480341
Short name T675
Test name
Test status
Simulation time 794768623 ps
CPU time 27.38 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:35 PM PST 24
Peak memory 251072 kb
Host smart-300b0f4f-7064-4557-aa91-4a7d6ac085e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360480341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1360480341
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.381659738
Short name T354
Test name
Test status
Simulation time 133720105 ps
CPU time 7.23 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:13 PM PST 24
Peak memory 251136 kb
Host smart-3c1460d4-24a5-4561-85d2-3e6a9ac66005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381659738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.381659738
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.90052150
Short name T582
Test name
Test status
Simulation time 2937634448 ps
CPU time 68.56 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:31:10 PM PST 24
Peak memory 250348 kb
Host smart-73ed336e-1c4a-4102-ba79-e2c1c9562d13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90052150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.lc_ctrl_stress_all.90052150
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.115827077
Short name T915
Test name
Test status
Simulation time 54760658 ps
CPU time 0.77 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:30:02 PM PST 24
Peak memory 208156 kb
Host smart-a9947211-cd73-4f83-b148-c365257e4170
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115827077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.115827077
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.73211093
Short name T898
Test name
Test status
Simulation time 12602525 ps
CPU time 0.84 seconds
Started Jan 14 12:30:36 PM PST 24
Finished Jan 14 12:30:38 PM PST 24
Peak memory 209428 kb
Host smart-49a518ec-4a44-40d7-9368-e04936a3688d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73211093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.73211093
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2245274944
Short name T407
Test name
Test status
Simulation time 1227614258 ps
CPU time 14.35 seconds
Started Jan 14 12:30:33 PM PST 24
Finished Jan 14 12:30:49 PM PST 24
Peak memory 218172 kb
Host smart-0fdc20a9-21bb-4a13-9a4f-ac7293f3e333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245274944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2245274944
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1634210138
Short name T403
Test name
Test status
Simulation time 1696952250 ps
CPU time 6.18 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:30:47 PM PST 24
Peak memory 209632 kb
Host smart-ee67f459-46f7-46f6-a0ca-79d3a5621208
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634210138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.1634210138
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1433482009
Short name T507
Test name
Test status
Simulation time 18493409264 ps
CPU time 48.92 seconds
Started Jan 14 12:30:44 PM PST 24
Finished Jan 14 12:31:34 PM PST 24
Peak memory 219252 kb
Host smart-258c4f75-fc75-4435-b06d-521c87e2e3c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433482009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1433482009
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1294464193
Short name T485
Test name
Test status
Simulation time 8002958498 ps
CPU time 17.06 seconds
Started Jan 14 12:30:39 PM PST 24
Finished Jan 14 12:30:57 PM PST 24
Peak memory 218068 kb
Host smart-93dd1822-97f6-4339-a412-af59890d97eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294464193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1294464193
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1451598152
Short name T539
Test name
Test status
Simulation time 569359822 ps
CPU time 4.19 seconds
Started Jan 14 12:30:43 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 211792 kb
Host smart-42bc0eef-1a45-40dd-823e-888325c1cda3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451598152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1451598152
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3736563370
Short name T706
Test name
Test status
Simulation time 1857749739 ps
CPU time 75.55 seconds
Started Jan 14 12:30:39 PM PST 24
Finished Jan 14 12:31:55 PM PST 24
Peak memory 267372 kb
Host smart-4703f23f-3618-4ddc-aa0b-e4d134b1f8c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736563370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3736563370
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.120033920
Short name T481
Test name
Test status
Simulation time 1442281215 ps
CPU time 19.88 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:31:01 PM PST 24
Peak memory 218068 kb
Host smart-583848b6-af8f-4dcd-9d14-e38d4d7d02d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120033920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.120033920
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2510699656
Short name T910
Test name
Test status
Simulation time 48781814 ps
CPU time 1.65 seconds
Started Jan 14 12:30:33 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 218120 kb
Host smart-fd2fdb11-972a-4f4d-8250-2ebfebf3983f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510699656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2510699656
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3336061428
Short name T736
Test name
Test status
Simulation time 1259026745 ps
CPU time 8.61 seconds
Started Jan 14 12:30:39 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 218188 kb
Host smart-bf7074b1-a15a-4f81-ab15-3d07613a8a43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336061428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3336061428
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1144998274
Short name T667
Test name
Test status
Simulation time 528477398 ps
CPU time 9.87 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:30:46 PM PST 24
Peak memory 218084 kb
Host smart-875b7fa2-03f4-48ec-82b7-5ab90be11810
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144998274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1144998274
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4231966721
Short name T694
Test name
Test status
Simulation time 378806413 ps
CPU time 8.68 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:30:47 PM PST 24
Peak memory 218132 kb
Host smart-17bfff19-3d76-4761-813f-3d382f26b636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231966721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4231966721
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.421216120
Short name T514
Test name
Test status
Simulation time 85383709 ps
CPU time 2.65 seconds
Started Jan 14 12:30:31 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 213916 kb
Host smart-c5df5ae8-a8c9-4e96-92e4-11cd7512a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421216120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.421216120
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.649935153
Short name T788
Test name
Test status
Simulation time 656737490 ps
CPU time 30.94 seconds
Started Jan 14 12:30:30 PM PST 24
Finished Jan 14 12:31:04 PM PST 24
Peak memory 250984 kb
Host smart-76c695fd-8954-4abf-947a-7fcf864b412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649935153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.649935153
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.257845880
Short name T622
Test name
Test status
Simulation time 132684075 ps
CPU time 10.28 seconds
Started Jan 14 12:30:29 PM PST 24
Finished Jan 14 12:30:41 PM PST 24
Peak memory 251108 kb
Host smart-1b52b9c9-b669-4a14-b39c-d46137742966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257845880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.257845880
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1917703147
Short name T782
Test name
Test status
Simulation time 1983207303 ps
CPU time 76.93 seconds
Started Jan 14 12:30:37 PM PST 24
Finished Jan 14 12:31:55 PM PST 24
Peak memory 253868 kb
Host smart-5af591da-2bf1-4808-be85-638b034597e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917703147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1917703147
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1488048677
Short name T705
Test name
Test status
Simulation time 17586243 ps
CPU time 1.02 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:30:42 PM PST 24
Peak memory 209664 kb
Host smart-e7af07b5-f54e-4b33-b37d-4c1ac13a6bc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488048677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1488048677
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1429861351
Short name T36
Test name
Test status
Simulation time 1021793667 ps
CPU time 12.01 seconds
Started Jan 14 12:30:39 PM PST 24
Finished Jan 14 12:30:52 PM PST 24
Peak memory 218108 kb
Host smart-3bd649ce-2f9f-477f-a146-47945370991b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429861351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1429861351
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2443416053
Short name T8
Test name
Test status
Simulation time 546167217 ps
CPU time 6.8 seconds
Started Jan 14 12:30:36 PM PST 24
Finished Jan 14 12:30:44 PM PST 24
Peak memory 209636 kb
Host smart-3bacf422-6519-4f78-bf89-234488b8147b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443416053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.2443416053
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.38294323
Short name T589
Test name
Test status
Simulation time 9226355821 ps
CPU time 38.18 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:31:19 PM PST 24
Peak memory 218544 kb
Host smart-9c718d67-0d90-4bf5-a522-bab85442e7fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38294323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_err
ors.38294323
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.222087026
Short name T467
Test name
Test status
Simulation time 1883981429 ps
CPU time 6.83 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:30:46 PM PST 24
Peak memory 218144 kb
Host smart-e57f0932-5508-4c74-863d-16863cbf3af8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222087026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.222087026
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.424933885
Short name T862
Test name
Test status
Simulation time 857623973 ps
CPU time 4.14 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:30:45 PM PST 24
Peak memory 213168 kb
Host smart-da21a0e0-64d1-4120-8182-894ac6de11d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424933885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
424933885
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3296165158
Short name T634
Test name
Test status
Simulation time 6741753334 ps
CPU time 70.7 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:31:51 PM PST 24
Peak memory 277132 kb
Host smart-9d5601b4-d2ea-460f-8066-36ec7a9512c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296165158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3296165158
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2119140213
Short name T961
Test name
Test status
Simulation time 460576085 ps
CPU time 6.53 seconds
Started Jan 14 12:30:39 PM PST 24
Finished Jan 14 12:30:46 PM PST 24
Peak memory 222468 kb
Host smart-77916a8b-724d-4adc-86dd-6cef793f4b29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119140213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2119140213
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3312320731
Short name T753
Test name
Test status
Simulation time 33407274 ps
CPU time 1.69 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:30:38 PM PST 24
Peak memory 218152 kb
Host smart-19868369-9184-4e11-a8cb-4b9c7bbd1180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312320731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3312320731
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.785065358
Short name T880
Test name
Test status
Simulation time 1372651101 ps
CPU time 7.89 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:30:44 PM PST 24
Peak memory 218096 kb
Host smart-a21836e9-1c84-4781-a2be-955a2611304c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785065358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.785065358
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3415610544
Short name T847
Test name
Test status
Simulation time 489358316 ps
CPU time 18.3 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 218092 kb
Host smart-8bee9429-40c4-4841-b254-316899209055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415610544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3415610544
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3768400964
Short name T351
Test name
Test status
Simulation time 1189275326 ps
CPU time 19.19 seconds
Started Jan 14 12:30:36 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 218028 kb
Host smart-349b074d-2d8f-408d-bb42-8c290c3f6d79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768400964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3768400964
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1805812353
Short name T979
Test name
Test status
Simulation time 31591252 ps
CPU time 2.4 seconds
Started Jan 14 12:30:43 PM PST 24
Finished Jan 14 12:30:46 PM PST 24
Peak memory 213780 kb
Host smart-3ee66b21-6a67-4b3a-ae98-57cbbb970785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805812353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1805812353
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3912483154
Short name T746
Test name
Test status
Simulation time 171945502 ps
CPU time 18.63 seconds
Started Jan 14 12:30:42 PM PST 24
Finished Jan 14 12:31:01 PM PST 24
Peak memory 251148 kb
Host smart-ed98ee5a-f23f-4243-b227-56856e76d08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912483154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3912483154
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3078728387
Short name T393
Test name
Test status
Simulation time 280396955 ps
CPU time 8.3 seconds
Started Jan 14 12:30:34 PM PST 24
Finished Jan 14 12:30:44 PM PST 24
Peak memory 251096 kb
Host smart-4e3a0e72-1dd4-4cae-9a9b-37e0a625dde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078728387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3078728387
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.354963454
Short name T641
Test name
Test status
Simulation time 7615562795 ps
CPU time 91.24 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 272224 kb
Host smart-f8b9efdf-ba81-4991-8dad-683eec682896
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354963454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.354963454
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4249491138
Short name T472
Test name
Test status
Simulation time 13675781 ps
CPU time 0.75 seconds
Started Jan 14 12:30:36 PM PST 24
Finished Jan 14 12:30:37 PM PST 24
Peak memory 208360 kb
Host smart-40bcc7a8-224c-4992-93b2-791f79ef9492
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249491138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4249491138
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.555861803
Short name T657
Test name
Test status
Simulation time 79242214 ps
CPU time 1.21 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:30:49 PM PST 24
Peak memory 209560 kb
Host smart-f62eb665-41f6-424a-b08e-32e884ae6137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555861803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.555861803
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.392422104
Short name T432
Test name
Test status
Simulation time 2276833154 ps
CPU time 12.45 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:30:51 PM PST 24
Peak memory 218164 kb
Host smart-56fa6a47-6c24-42ec-a3b3-e45616664216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392422104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.392422104
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1338223610
Short name T716
Test name
Test status
Simulation time 1684467491 ps
CPU time 10.12 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:30:46 PM PST 24
Peak memory 209536 kb
Host smart-03245d17-7c18-4224-ae0d-698b665686d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338223610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_a
ccess.1338223610
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4233154760
Short name T640
Test name
Test status
Simulation time 2149787518 ps
CPU time 61.54 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:31:40 PM PST 24
Peak memory 218212 kb
Host smart-327ed642-3398-4138-8443-7b9ed85574ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233154760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4233154760
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1446365572
Short name T852
Test name
Test status
Simulation time 2006414210 ps
CPU time 8.49 seconds
Started Jan 14 12:30:44 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 217992 kb
Host smart-0e3e917d-1fc2-428d-b1f1-2a2c4c6fbd6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446365572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1446365572
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1480574078
Short name T823
Test name
Test status
Simulation time 2264652032 ps
CPU time 7.63 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 213668 kb
Host smart-01b3a8e2-ce15-4331-bfcc-da10d3b5f283
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480574078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1480574078
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.409871729
Short name T701
Test name
Test status
Simulation time 5815670751 ps
CPU time 122.22 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:32:41 PM PST 24
Peak memory 283468 kb
Host smart-5cfc1a08-3716-4f4c-8481-d1d12ed28d46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409871729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.409871729
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.717729548
Short name T829
Test name
Test status
Simulation time 8817282397 ps
CPU time 11.1 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:30:49 PM PST 24
Peak memory 246460 kb
Host smart-ca7ba71d-c0f0-4983-bb01-a328c50227c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717729548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.717729548
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.956320681
Short name T702
Test name
Test status
Simulation time 436468315 ps
CPU time 3.23 seconds
Started Jan 14 12:30:43 PM PST 24
Finished Jan 14 12:30:47 PM PST 24
Peak memory 218100 kb
Host smart-4f2be238-652b-4b25-afa7-27f5497b9ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956320681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.956320681
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3842349319
Short name T505
Test name
Test status
Simulation time 311195791 ps
CPU time 11.94 seconds
Started Jan 14 12:30:39 PM PST 24
Finished Jan 14 12:30:52 PM PST 24
Peak memory 219212 kb
Host smart-c2a6d694-6aad-41b2-9fc7-2ab4ef254b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842349319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3842349319
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3779384354
Short name T313
Test name
Test status
Simulation time 222902327 ps
CPU time 6.55 seconds
Started Jan 14 12:30:40 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 218048 kb
Host smart-6068eb55-7092-4c86-a657-553378585e32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779384354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3779384354
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3308948250
Short name T659
Test name
Test status
Simulation time 692602375 ps
CPU time 10.97 seconds
Started Jan 14 12:30:45 PM PST 24
Finished Jan 14 12:30:57 PM PST 24
Peak memory 217996 kb
Host smart-33d050e4-2e84-48b7-96ea-20d38032d856
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308948250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3308948250
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3977464202
Short name T754
Test name
Test status
Simulation time 400859446 ps
CPU time 8.92 seconds
Started Jan 14 12:30:43 PM PST 24
Finished Jan 14 12:30:53 PM PST 24
Peak memory 217072 kb
Host smart-e15feefe-00d9-4dae-a969-aaf5337eace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977464202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3977464202
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2488980931
Short name T550
Test name
Test status
Simulation time 41931613 ps
CPU time 1.53 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:30:41 PM PST 24
Peak memory 213204 kb
Host smart-aac3d7a1-888b-43ea-a897-1824c2da8d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488980931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2488980931
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3546782675
Short name T661
Test name
Test status
Simulation time 226526538 ps
CPU time 24.09 seconds
Started Jan 14 12:30:37 PM PST 24
Finished Jan 14 12:31:01 PM PST 24
Peak memory 251016 kb
Host smart-84d3e126-f046-4ca1-bff9-c2c983291f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546782675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3546782675
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3321605659
Short name T377
Test name
Test status
Simulation time 144676164 ps
CPU time 5.97 seconds
Started Jan 14 12:30:43 PM PST 24
Finished Jan 14 12:30:50 PM PST 24
Peak memory 245996 kb
Host smart-c03141dc-8152-433a-812b-56525546c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321605659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3321605659
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.763674002
Short name T866
Test name
Test status
Simulation time 8002931253 ps
CPU time 155.61 seconds
Started Jan 14 12:30:38 PM PST 24
Finished Jan 14 12:33:15 PM PST 24
Peak memory 275700 kb
Host smart-5afed15b-3fc7-49e7-8be1-08e3277c39ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763674002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.763674002
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3260589314
Short name T885
Test name
Test status
Simulation time 12143512 ps
CPU time 0.93 seconds
Started Jan 14 12:30:45 PM PST 24
Finished Jan 14 12:30:47 PM PST 24
Peak memory 208056 kb
Host smart-e4bd19ea-9688-4b39-b6f7-2d4fbfd606d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260589314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3260589314
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.4216522871
Short name T678
Test name
Test status
Simulation time 448319533 ps
CPU time 18.26 seconds
Started Jan 14 12:30:48 PM PST 24
Finished Jan 14 12:31:07 PM PST 24
Peak memory 218048 kb
Host smart-eb1fc971-1da5-4da8-a324-e074b4642868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216522871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.4216522871
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.773312647
Short name T721
Test name
Test status
Simulation time 1532427053 ps
CPU time 9.58 seconds
Started Jan 14 12:30:45 PM PST 24
Finished Jan 14 12:30:55 PM PST 24
Peak memory 209616 kb
Host smart-3638ea27-c3bd-4254-8cc0-b7c02b40d9cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773312647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ac
cess.773312647
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2914148071
Short name T346
Test name
Test status
Simulation time 6531674280 ps
CPU time 26.36 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:31:15 PM PST 24
Peak memory 218156 kb
Host smart-196bdfa7-3b2b-44cc-8735-1b17662fc9ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914148071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2914148071
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3205373131
Short name T815
Test name
Test status
Simulation time 1412025607 ps
CPU time 10.96 seconds
Started Jan 14 12:30:51 PM PST 24
Finished Jan 14 12:31:03 PM PST 24
Peak memory 218076 kb
Host smart-474de1b6-4294-4f48-b78f-9575433ccd79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205373131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3205373131
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.573661209
Short name T832
Test name
Test status
Simulation time 1046044844 ps
CPU time 6.79 seconds
Started Jan 14 12:30:51 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 213088 kb
Host smart-26237d41-e5d3-4837-a561-739ebbf10d31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573661209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
573661209
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3357496528
Short name T352
Test name
Test status
Simulation time 424641997 ps
CPU time 11.56 seconds
Started Jan 14 12:30:42 PM PST 24
Finished Jan 14 12:30:55 PM PST 24
Peak memory 245876 kb
Host smart-e27550d5-057c-4f87-8fad-5d5fd12dfb78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357496528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3357496528
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3847793205
Short name T645
Test name
Test status
Simulation time 35290442 ps
CPU time 2.26 seconds
Started Jan 14 12:30:53 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 218064 kb
Host smart-b956303a-eca4-4a35-9f6d-30cbabb7c059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847793205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3847793205
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.269623107
Short name T774
Test name
Test status
Simulation time 296900917 ps
CPU time 9.91 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:30:58 PM PST 24
Peak memory 219100 kb
Host smart-6d730233-da36-4717-b25e-caeef12d85de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269623107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.269623107
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4021347753
Short name T928
Test name
Test status
Simulation time 851874519 ps
CPU time 10.9 seconds
Started Jan 14 12:30:44 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 218080 kb
Host smart-dd28dcd8-e39e-4665-a735-ad504593f863
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021347753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4021347753
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1669363791
Short name T453
Test name
Test status
Simulation time 253989871 ps
CPU time 9.71 seconds
Started Jan 14 12:30:49 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 217996 kb
Host smart-60dc121b-bc51-4f29-870a-7a911789d713
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669363791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1669363791
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3823738624
Short name T869
Test name
Test status
Simulation time 913669977 ps
CPU time 14.62 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:31:03 PM PST 24
Peak memory 218116 kb
Host smart-a3be47b1-599e-49cb-b33e-1f708018fdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823738624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3823738624
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3326998779
Short name T568
Test name
Test status
Simulation time 18876012 ps
CPU time 1.09 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:30:51 PM PST 24
Peak memory 213112 kb
Host smart-f50a9a6b-e738-4599-be1c-09713d1085ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326998779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3326998779
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3544207377
Short name T618
Test name
Test status
Simulation time 225605950 ps
CPU time 20.27 seconds
Started Jan 14 12:30:56 PM PST 24
Finished Jan 14 12:31:17 PM PST 24
Peak memory 251100 kb
Host smart-e2aab55c-93b4-4f89-b391-34b145407706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544207377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3544207377
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.475239623
Short name T884
Test name
Test status
Simulation time 216026355 ps
CPU time 6.2 seconds
Started Jan 14 12:30:46 PM PST 24
Finished Jan 14 12:30:53 PM PST 24
Peak memory 242968 kb
Host smart-fc52da7e-cfce-4082-8274-a7920b542c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475239623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.475239623
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3325170701
Short name T464
Test name
Test status
Simulation time 30138350 ps
CPU time 0.69 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:30:51 PM PST 24
Peak memory 206848 kb
Host smart-acd5c616-703b-4aa5-8f2c-2c99b095cb87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325170701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3325170701
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.4276892258
Short name T468
Test name
Test status
Simulation time 63141490 ps
CPU time 1.37 seconds
Started Jan 14 12:30:48 PM PST 24
Finished Jan 14 12:30:50 PM PST 24
Peak memory 208348 kb
Host smart-7eaae574-074d-4260-a6e2-4f078194d46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276892258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4276892258
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1279770719
Short name T330
Test name
Test status
Simulation time 318023477 ps
CPU time 14.76 seconds
Started Jan 14 12:30:49 PM PST 24
Finished Jan 14 12:31:04 PM PST 24
Peak memory 218052 kb
Host smart-a89ea4c4-09e6-4806-86c2-de6fb6ee52e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279770719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1279770719
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.4064607296
Short name T647
Test name
Test status
Simulation time 418073598 ps
CPU time 7.22 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 209548 kb
Host smart-57d7e1bc-016b-4f37-89ca-23ae7f77d54b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064607296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_a
ccess.4064607296
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3023054054
Short name T355
Test name
Test status
Simulation time 3231064795 ps
CPU time 47.44 seconds
Started Jan 14 12:30:45 PM PST 24
Finished Jan 14 12:31:33 PM PST 24
Peak memory 219076 kb
Host smart-706f60b3-d89c-4484-b4e5-7998020cf569
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023054054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3023054054
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1466695436
Short name T424
Test name
Test status
Simulation time 5020672338 ps
CPU time 11.13 seconds
Started Jan 14 12:30:42 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 218124 kb
Host smart-e83a0cf6-4cb3-4eba-a9a2-c93287a8fab8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466695436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1466695436
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2371971216
Short name T670
Test name
Test status
Simulation time 425720747 ps
CPU time 5.79 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 212988 kb
Host smart-f08ef547-06f5-47ad-80dd-61e80293e69b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371971216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2371971216
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2360830570
Short name T500
Test name
Test status
Simulation time 8474055842 ps
CPU time 69.16 seconds
Started Jan 14 12:30:43 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 275704 kb
Host smart-eb97769e-c54f-4493-836a-5bf7edc606f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360830570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2360830570
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.806603333
Short name T592
Test name
Test status
Simulation time 1060429528 ps
CPU time 8.83 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:30:57 PM PST 24
Peak memory 223608 kb
Host smart-3ce492dd-aaed-47f2-bbc2-a9251469231f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806603333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.806603333
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2688324120
Short name T820
Test name
Test status
Simulation time 40548081 ps
CPU time 2.62 seconds
Started Jan 14 12:30:45 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 218104 kb
Host smart-babe83cd-ad39-449f-83ac-b618f9602a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688324120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2688324120
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2384843834
Short name T981
Test name
Test status
Simulation time 231901998 ps
CPU time 10.25 seconds
Started Jan 14 12:30:53 PM PST 24
Finished Jan 14 12:31:04 PM PST 24
Peak memory 219120 kb
Host smart-aea0b34d-eb39-4420-8e6c-065a9618ae07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384843834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2384843834
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3339800849
Short name T763
Test name
Test status
Simulation time 475853238 ps
CPU time 7.74 seconds
Started Jan 14 12:30:55 PM PST 24
Finished Jan 14 12:31:04 PM PST 24
Peak memory 218092 kb
Host smart-6366e2c6-cdf8-4576-b56c-5f64c2b19e70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339800849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3339800849
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.845954406
Short name T743
Test name
Test status
Simulation time 866440567 ps
CPU time 6.45 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:30:57 PM PST 24
Peak memory 218056 kb
Host smart-d167b125-92d0-42c7-ad04-3044909496cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845954406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.845954406
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3122572126
Short name T85
Test name
Test status
Simulation time 92073385 ps
CPU time 3.55 seconds
Started Jan 14 12:30:44 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 213860 kb
Host smart-5a83a476-29a2-4d95-a08e-32f7d09d8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122572126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3122572126
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.997621043
Short name T333
Test name
Test status
Simulation time 631965620 ps
CPU time 20.82 seconds
Started Jan 14 12:30:54 PM PST 24
Finished Jan 14 12:31:16 PM PST 24
Peak memory 251088 kb
Host smart-cbccfca2-6118-4eb2-9107-47b78af79258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997621043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.997621043
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2198290713
Short name T356
Test name
Test status
Simulation time 263093798 ps
CPU time 7.4 seconds
Started Jan 14 12:30:46 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 251072 kb
Host smart-583be996-3f7b-44ec-a82e-94366841fa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198290713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2198290713
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.172494329
Short name T938
Test name
Test status
Simulation time 1564156456 ps
CPU time 72.15 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 267320 kb
Host smart-faf885a3-08ab-4359-a0ef-db9ba542c682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172494329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.172494329
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2266979761
Short name T11
Test name
Test status
Simulation time 157762611 ps
CPU time 0.93 seconds
Started Jan 14 12:30:53 PM PST 24
Finished Jan 14 12:30:55 PM PST 24
Peak memory 211516 kb
Host smart-2f403a41-4405-4725-a198-808209122109
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266979761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2266979761
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.143045196
Short name T461
Test name
Test status
Simulation time 62782531 ps
CPU time 0.99 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:30:52 PM PST 24
Peak memory 209604 kb
Host smart-99b4289e-9461-4bc0-8612-0f91bbb65500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143045196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.143045196
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3346142144
Short name T345
Test name
Test status
Simulation time 1050826011 ps
CPU time 11.26 seconds
Started Jan 14 12:30:57 PM PST 24
Finished Jan 14 12:31:09 PM PST 24
Peak memory 218124 kb
Host smart-5917a568-5647-40a3-8d31-d1b35fa33860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346142144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3346142144
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1534409526
Short name T26
Test name
Test status
Simulation time 1013140250 ps
CPU time 6.49 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 209580 kb
Host smart-bca7066e-a992-40ea-9698-53a46a6d04cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534409526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.1534409526
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3270153208
Short name T855
Test name
Test status
Simulation time 1828170810 ps
CPU time 49.17 seconds
Started Jan 14 12:30:53 PM PST 24
Finished Jan 14 12:31:43 PM PST 24
Peak memory 218004 kb
Host smart-9f0ee8fb-56bf-4621-96ca-583c90116bbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270153208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3270153208
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1279207955
Short name T664
Test name
Test status
Simulation time 2057937945 ps
CPU time 14.08 seconds
Started Jan 14 12:30:52 PM PST 24
Finished Jan 14 12:31:06 PM PST 24
Peak memory 218104 kb
Host smart-c7b1c6f7-dab4-4cb2-91db-19b614fab609
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279207955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1279207955
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3438421934
Short name T320
Test name
Test status
Simulation time 1536819828 ps
CPU time 9.39 seconds
Started Jan 14 12:30:49 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 213332 kb
Host smart-9c84a915-6905-45f4-b212-06a8f9daab0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438421934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3438421934
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1438794032
Short name T943
Test name
Test status
Simulation time 5389256669 ps
CPU time 36.14 seconds
Started Jan 14 12:30:47 PM PST 24
Finished Jan 14 12:31:24 PM PST 24
Peak memory 275788 kb
Host smart-3f6770f3-0baa-40e7-aa4c-f4c82e13a527
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438794032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1438794032
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.410506105
Short name T839
Test name
Test status
Simulation time 2594318850 ps
CPU time 14.27 seconds
Started Jan 14 12:30:46 PM PST 24
Finished Jan 14 12:31:01 PM PST 24
Peak memory 251036 kb
Host smart-cc20c4ed-bbb6-4488-a9c8-667864c61793
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410506105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.410506105
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2780154061
Short name T312
Test name
Test status
Simulation time 232669368 ps
CPU time 2.53 seconds
Started Jan 14 12:30:57 PM PST 24
Finished Jan 14 12:31:00 PM PST 24
Peak memory 218128 kb
Host smart-12cbf8ee-b208-4141-9837-2fa82bd42204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780154061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2780154061
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1890739942
Short name T349
Test name
Test status
Simulation time 1199034213 ps
CPU time 13.69 seconds
Started Jan 14 12:30:52 PM PST 24
Finished Jan 14 12:31:07 PM PST 24
Peak memory 219200 kb
Host smart-7acd5078-0d21-402f-a0dc-3bfca3f9b698
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890739942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1890739942
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.278282998
Short name T703
Test name
Test status
Simulation time 293167385 ps
CPU time 12.56 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:31:03 PM PST 24
Peak memory 218088 kb
Host smart-2197e777-b5d9-4e50-af91-0d52950fdead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278282998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.278282998
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.313910102
Short name T506
Test name
Test status
Simulation time 656526239 ps
CPU time 7.88 seconds
Started Jan 14 12:30:44 PM PST 24
Finished Jan 14 12:30:53 PM PST 24
Peak memory 218144 kb
Host smart-0b7c3475-b5ed-4d43-8989-d66f862866eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313910102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.313910102
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1798579595
Short name T553
Test name
Test status
Simulation time 665754357 ps
CPU time 13.61 seconds
Started Jan 14 12:30:56 PM PST 24
Finished Jan 14 12:31:10 PM PST 24
Peak memory 218188 kb
Host smart-0894da80-80a2-4aec-89da-74671b79da91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798579595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1798579595
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2842067302
Short name T9
Test name
Test status
Simulation time 44590736 ps
CPU time 0.98 seconds
Started Jan 14 12:30:52 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 211296 kb
Host smart-cc050352-84bb-480a-be70-8f34ba473061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842067302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2842067302
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1853686511
Short name T946
Test name
Test status
Simulation time 320353462 ps
CPU time 16.22 seconds
Started Jan 14 12:30:54 PM PST 24
Finished Jan 14 12:31:11 PM PST 24
Peak memory 251068 kb
Host smart-3c68aaa2-3bd9-4e0d-a4dc-41487d09481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853686511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1853686511
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.719740681
Short name T413
Test name
Test status
Simulation time 2502012806 ps
CPU time 7.89 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 246980 kb
Host smart-14ad41c7-b92d-4bce-8cef-fde5b6ff48b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719740681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.719740681
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3461816578
Short name T799
Test name
Test status
Simulation time 1579891429 ps
CPU time 61.67 seconds
Started Jan 14 12:30:51 PM PST 24
Finished Jan 14 12:31:54 PM PST 24
Peak memory 251144 kb
Host smart-6319a356-1b55-47b9-bfcb-519ea7950378
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461816578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3461816578
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3362232781
Short name T819
Test name
Test status
Simulation time 17327667 ps
CPU time 0.84 seconds
Started Jan 14 12:30:49 PM PST 24
Finished Jan 14 12:30:50 PM PST 24
Peak memory 208360 kb
Host smart-31e81c3f-b78b-4ede-b136-239bc2b8e41c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362232781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3362232781
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.186177758
Short name T813
Test name
Test status
Simulation time 46260414 ps
CPU time 0.79 seconds
Started Jan 14 12:30:53 PM PST 24
Finished Jan 14 12:30:55 PM PST 24
Peak memory 209480 kb
Host smart-ee9e6f93-23c9-4a2d-88a9-201f45e3ddd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186177758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.186177758
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2314217098
Short name T152
Test name
Test status
Simulation time 2032137327 ps
CPU time 15.23 seconds
Started Jan 14 12:30:59 PM PST 24
Finished Jan 14 12:31:15 PM PST 24
Peak memory 218264 kb
Host smart-09877f3c-1731-4ea5-995a-bb271b1838fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314217098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2314217098
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3616850931
Short name T704
Test name
Test status
Simulation time 1046316052 ps
CPU time 5.31 seconds
Started Jan 14 12:30:52 PM PST 24
Finished Jan 14 12:30:58 PM PST 24
Peak memory 209560 kb
Host smart-577ab081-8f49-4053-99cc-f2beab5283bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616850931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.3616850931
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.325488120
Short name T865
Test name
Test status
Simulation time 4554514640 ps
CPU time 35.33 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:31:26 PM PST 24
Peak memory 218688 kb
Host smart-0d28b3e3-74e7-444e-9cc8-f50b1c1dbbfa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325488120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.325488120
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1194789665
Short name T951
Test name
Test status
Simulation time 1200252517 ps
CPU time 5.71 seconds
Started Jan 14 12:30:54 PM PST 24
Finished Jan 14 12:31:00 PM PST 24
Peak memory 218192 kb
Host smart-178a0f2d-4c50-4705-abd1-ced24a06b16f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194789665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1194789665
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2371838492
Short name T864
Test name
Test status
Simulation time 1166711800 ps
CPU time 12.12 seconds
Started Jan 14 12:30:48 PM PST 24
Finished Jan 14 12:31:01 PM PST 24
Peak memory 213636 kb
Host smart-1bd8302c-15a0-4c6b-b911-a58aa96cb50d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371838492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2371838492
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2927697585
Short name T745
Test name
Test status
Simulation time 6611672839 ps
CPU time 32.15 seconds
Started Jan 14 12:30:56 PM PST 24
Finished Jan 14 12:31:29 PM PST 24
Peak memory 251136 kb
Host smart-fd2af9a5-9fab-456b-bd10-f39250d1c0bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927697585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2927697585
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.645127643
Short name T450
Test name
Test status
Simulation time 950457964 ps
CPU time 14.53 seconds
Started Jan 14 12:30:57 PM PST 24
Finished Jan 14 12:31:12 PM PST 24
Peak memory 223544 kb
Host smart-f44fa852-6c0b-4989-97e4-549e2caa853c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645127643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.645127643
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2965233739
Short name T66
Test name
Test status
Simulation time 66309291 ps
CPU time 2.81 seconds
Started Jan 14 12:30:53 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 218168 kb
Host smart-f0311a39-9472-4ecd-88b9-ff4650ac99fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965233739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2965233739
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2052638812
Short name T881
Test name
Test status
Simulation time 2302371112 ps
CPU time 13.41 seconds
Started Jan 14 12:30:54 PM PST 24
Finished Jan 14 12:31:08 PM PST 24
Peak memory 218152 kb
Host smart-e5409d3a-f891-452a-8dd1-3fba0229d83a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052638812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2052638812
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.4029384879
Short name T691
Test name
Test status
Simulation time 296929358 ps
CPU time 8.82 seconds
Started Jan 14 12:30:55 PM PST 24
Finished Jan 14 12:31:04 PM PST 24
Peak memory 218012 kb
Host smart-632c4e53-13c3-4708-86e2-02630d792cd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029384879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.4029384879
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1659439425
Short name T433
Test name
Test status
Simulation time 1980207464 ps
CPU time 9.46 seconds
Started Jan 14 12:30:52 PM PST 24
Finished Jan 14 12:31:02 PM PST 24
Peak memory 218080 kb
Host smart-9fe1a2e6-0337-449f-90b8-2b16c17ba9ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659439425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1659439425
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1956245752
Short name T57
Test name
Test status
Simulation time 2842873964 ps
CPU time 9.08 seconds
Started Jan 14 12:30:55 PM PST 24
Finished Jan 14 12:31:05 PM PST 24
Peak memory 218224 kb
Host smart-90d05ffb-3c7a-48fd-bc6d-95852f8a465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956245752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1956245752
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1805163814
Short name T340
Test name
Test status
Simulation time 257804832 ps
CPU time 2.23 seconds
Started Jan 14 12:30:50 PM PST 24
Finished Jan 14 12:30:53 PM PST 24
Peak memory 213860 kb
Host smart-7dc8524e-58fc-48c2-859d-7c4d36d2094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805163814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1805163814
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2288517930
Short name T859
Test name
Test status
Simulation time 504579884 ps
CPU time 34.14 seconds
Started Jan 14 12:30:46 PM PST 24
Finished Jan 14 12:31:20 PM PST 24
Peak memory 246200 kb
Host smart-7fd96622-be9d-4138-bcf4-be34e3728ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288517930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2288517930
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1190749188
Short name T950
Test name
Test status
Simulation time 258723559 ps
CPU time 3.34 seconds
Started Jan 14 12:30:54 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 222116 kb
Host smart-f2924871-c8b8-41de-a79b-fee5900b92b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190749188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1190749188
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2138340825
Short name T482
Test name
Test status
Simulation time 9168942804 ps
CPU time 47.57 seconds
Started Jan 14 12:30:52 PM PST 24
Finished Jan 14 12:31:41 PM PST 24
Peak memory 251040 kb
Host smart-5ea5ad66-e4b7-4421-aa1b-9ab5f9455162
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138340825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2138340825
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3736202470
Short name T628
Test name
Test status
Simulation time 12453547 ps
CPU time 0.91 seconds
Started Jan 14 12:30:54 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 207976 kb
Host smart-77e52b19-c068-444f-8e99-e9a5bbf0a80d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736202470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3736202470
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.285991785
Short name T571
Test name
Test status
Simulation time 39482462 ps
CPU time 0.85 seconds
Started Jan 14 12:31:26 PM PST 24
Finished Jan 14 12:31:27 PM PST 24
Peak memory 208100 kb
Host smart-1a146bc7-c504-42fd-bd3f-afdaaac17f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285991785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.285991785
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3653370653
Short name T427
Test name
Test status
Simulation time 1048598796 ps
CPU time 12.71 seconds
Started Jan 14 12:30:51 PM PST 24
Finished Jan 14 12:31:04 PM PST 24
Peak memory 218144 kb
Host smart-59808b07-c8b2-4251-a96c-15a7738d9c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653370653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3653370653
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3201091828
Short name T711
Test name
Test status
Simulation time 924037122 ps
CPU time 20.5 seconds
Started Jan 14 12:30:59 PM PST 24
Finished Jan 14 12:31:20 PM PST 24
Peak memory 209516 kb
Host smart-79da2c9b-9d08-4c43-a80f-8d3a050bee22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201091828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.3201091828
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1180652608
Short name T740
Test name
Test status
Simulation time 1482130746 ps
CPU time 40.16 seconds
Started Jan 14 12:30:59 PM PST 24
Finished Jan 14 12:31:40 PM PST 24
Peak memory 218016 kb
Host smart-fdc5976b-d019-459d-be92-c719e7aa686f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180652608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1180652608
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3977686633
Short name T546
Test name
Test status
Simulation time 587832703 ps
CPU time 4.31 seconds
Started Jan 14 12:30:59 PM PST 24
Finished Jan 14 12:31:04 PM PST 24
Peak memory 217704 kb
Host smart-13ed33d4-f742-4849-8246-1c3c80edb0fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977686633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3977686633
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.4166501306
Short name T18
Test name
Test status
Simulation time 234058506 ps
CPU time 6.69 seconds
Started Jan 14 12:30:52 PM PST 24
Finished Jan 14 12:31:00 PM PST 24
Peak memory 213412 kb
Host smart-3f624ca5-f02e-4c4a-b540-cee765c66e43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166501306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.4166501306
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.4252619097
Short name T982
Test name
Test status
Simulation time 7206062203 ps
CPU time 122.52 seconds
Started Jan 14 12:30:59 PM PST 24
Finished Jan 14 12:33:02 PM PST 24
Peak memory 283964 kb
Host smart-b3864e49-193e-44d5-a835-2c9eb85ac762
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252619097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.4252619097
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1146470979
Short name T612
Test name
Test status
Simulation time 3062583374 ps
CPU time 18.24 seconds
Started Jan 14 12:30:55 PM PST 24
Finished Jan 14 12:31:14 PM PST 24
Peak memory 251096 kb
Host smart-f1f4cba3-7f46-4ad1-9fea-9fa080880f11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146470979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1146470979
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2663244284
Short name T937
Test name
Test status
Simulation time 49024751 ps
CPU time 2.14 seconds
Started Jan 14 12:30:51 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 218172 kb
Host smart-9e4578aa-f7a9-42b6-8baa-3d3523a27526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663244284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2663244284
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4134819655
Short name T760
Test name
Test status
Simulation time 2249126793 ps
CPU time 14.57 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:39 PM PST 24
Peak memory 217220 kb
Host smart-7e48c0c5-3f26-459e-82f8-f4d046176f22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134819655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4134819655
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1068742504
Short name T792
Test name
Test status
Simulation time 250881527 ps
CPU time 8.57 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:31:31 PM PST 24
Peak memory 218080 kb
Host smart-601f1ca8-870b-45ae-a050-5b0409f8cf94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068742504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1068742504
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3267365224
Short name T67
Test name
Test status
Simulation time 253711099 ps
CPU time 9.91 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:31:33 PM PST 24
Peak memory 218012 kb
Host smart-5dca3a1e-a29e-420b-a650-0e984f8bba3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267365224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3267365224
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.21717434
Short name T718
Test name
Test status
Simulation time 3738458438 ps
CPU time 10.88 seconds
Started Jan 14 12:30:59 PM PST 24
Finished Jan 14 12:31:11 PM PST 24
Peak memory 217892 kb
Host smart-165f3765-0e7d-4d03-8f2d-68e543e7c25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21717434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.21717434
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2598472663
Short name T378
Test name
Test status
Simulation time 40006164 ps
CPU time 2.27 seconds
Started Jan 14 12:30:53 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 213912 kb
Host smart-dbf4a79c-28e6-427e-8da7-f4c51782dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598472663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2598472663
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2093670012
Short name T776
Test name
Test status
Simulation time 1377760593 ps
CPU time 25.53 seconds
Started Jan 14 12:31:00 PM PST 24
Finished Jan 14 12:31:26 PM PST 24
Peak memory 248140 kb
Host smart-40831994-ef96-4cc9-b987-bcb8e0ca8f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093670012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2093670012
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3442759640
Short name T61
Test name
Test status
Simulation time 149673846 ps
CPU time 9.19 seconds
Started Jan 14 12:30:57 PM PST 24
Finished Jan 14 12:31:07 PM PST 24
Peak memory 250516 kb
Host smart-05c1ad0d-389a-45dc-8f94-757a5285a026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442759640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3442759640
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2548517675
Short name T795
Test name
Test status
Simulation time 13444060776 ps
CPU time 154.01 seconds
Started Jan 14 12:31:23 PM PST 24
Finished Jan 14 12:33:58 PM PST 24
Peak memory 283864 kb
Host smart-28a719e9-ec3b-4895-89ab-d60fa76c9b6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548517675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2548517675
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4051646140
Short name T942
Test name
Test status
Simulation time 11937547 ps
CPU time 0.77 seconds
Started Jan 14 12:31:01 PM PST 24
Finished Jan 14 12:31:03 PM PST 24
Peak memory 207980 kb
Host smart-31c1a0b2-4b4d-4d7d-af59-b8dff32fa245
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051646140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4051646140
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3769459284
Short name T101
Test name
Test status
Simulation time 125709787 ps
CPU time 1.08 seconds
Started Jan 14 12:31:26 PM PST 24
Finished Jan 14 12:31:27 PM PST 24
Peak memory 208428 kb
Host smart-ea6ead30-7592-4178-b8e0-b847cd21f6a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769459284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3769459284
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.481077478
Short name T587
Test name
Test status
Simulation time 432069674 ps
CPU time 15.94 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:40 PM PST 24
Peak memory 218160 kb
Host smart-33bef78b-a0a8-4db7-b093-717165112076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481077478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.481077478
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1486273344
Short name T25
Test name
Test status
Simulation time 1986931661 ps
CPU time 12.83 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:37 PM PST 24
Peak memory 208608 kb
Host smart-7fbadafe-c0fa-4ed6-b265-a0bf635ca7d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486273344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.1486273344
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2282348016
Short name T956
Test name
Test status
Simulation time 1677673687 ps
CPU time 39.85 seconds
Started Jan 14 12:31:28 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218092 kb
Host smart-fc36cd5a-b83c-4c92-a56c-385e8657dd9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282348016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2282348016
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3049321030
Short name T755
Test name
Test status
Simulation time 1473876209 ps
CPU time 4.65 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:29 PM PST 24
Peak memory 218196 kb
Host smart-072edfb5-605e-4491-8210-59282bf94dea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049321030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3049321030
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.4107346124
Short name T986
Test name
Test status
Simulation time 458336704 ps
CPU time 4.9 seconds
Started Jan 14 12:31:25 PM PST 24
Finished Jan 14 12:31:30 PM PST 24
Peak memory 213236 kb
Host smart-cf3799e0-7584-4399-bb5d-25f51892f5a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107346124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.4107346124
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3474650849
Short name T17
Test name
Test status
Simulation time 3167040485 ps
CPU time 47.38 seconds
Started Jan 14 12:31:27 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 283864 kb
Host smart-7ac1cc61-70e3-452b-922a-f14c80abd256
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474650849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3474650849
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2847508240
Short name T186
Test name
Test status
Simulation time 440459949 ps
CPU time 18.11 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:43 PM PST 24
Peak memory 251204 kb
Host smart-62f44f31-bcfd-499f-b54b-ee761f565e8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847508240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2847508240
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.4091648086
Short name T308
Test name
Test status
Simulation time 229569961 ps
CPU time 2.72 seconds
Started Jan 14 12:31:19 PM PST 24
Finished Jan 14 12:31:22 PM PST 24
Peak memory 218156 kb
Host smart-89f27ea4-ae28-4c13-931e-00aefc7e0ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091648086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.4091648086
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.973404877
Short name T554
Test name
Test status
Simulation time 5808476759 ps
CPU time 11.67 seconds
Started Jan 14 12:31:21 PM PST 24
Finished Jan 14 12:31:34 PM PST 24
Peak memory 218228 kb
Host smart-689501f2-a917-4da6-8651-1f67ec156016
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973404877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.973404877
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1099119871
Short name T686
Test name
Test status
Simulation time 1319818776 ps
CPU time 9.57 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:34 PM PST 24
Peak memory 218096 kb
Host smart-520937a8-ee73-448f-ba4f-519c63a1b4b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099119871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1099119871
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1044506486
Short name T695
Test name
Test status
Simulation time 377191252 ps
CPU time 8.91 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:33 PM PST 24
Peak memory 218084 kb
Host smart-0554ac10-278f-4d49-bee2-785e29859220
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044506486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1044506486
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3250607890
Short name T596
Test name
Test status
Simulation time 641187651 ps
CPU time 11.7 seconds
Started Jan 14 12:31:26 PM PST 24
Finished Jan 14 12:31:38 PM PST 24
Peak memory 218168 kb
Host smart-1909e677-ca99-4c52-b67a-df4b1778caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250607890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3250607890
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1625591471
Short name T765
Test name
Test status
Simulation time 17074520 ps
CPU time 1.28 seconds
Started Jan 14 12:31:18 PM PST 24
Finished Jan 14 12:31:19 PM PST 24
Peak memory 213060 kb
Host smart-7f099bdb-2e28-4eb0-b603-72111f553d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625591471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1625591471
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.899343022
Short name T967
Test name
Test status
Simulation time 941596420 ps
CPU time 23.58 seconds
Started Jan 14 12:31:23 PM PST 24
Finished Jan 14 12:31:47 PM PST 24
Peak memory 251112 kb
Host smart-a433a819-513a-4eaa-886b-8caf23f566d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899343022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.899343022
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.860107791
Short name T89
Test name
Test status
Simulation time 290917445 ps
CPU time 3.35 seconds
Started Jan 14 12:31:21 PM PST 24
Finished Jan 14 12:31:24 PM PST 24
Peak memory 222324 kb
Host smart-a8597f85-306a-41de-852c-e19a21d729fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860107791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.860107791
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2706108428
Short name T75
Test name
Test status
Simulation time 33788275037 ps
CPU time 120.83 seconds
Started Jan 14 12:31:23 PM PST 24
Finished Jan 14 12:33:24 PM PST 24
Peak memory 267480 kb
Host smart-759af1c6-aa79-4c1c-8f99-5d60e9fe14b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706108428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2706108428
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2301206961
Short name T638
Test name
Test status
Simulation time 61038989 ps
CPU time 0.98 seconds
Started Jan 14 12:31:21 PM PST 24
Finished Jan 14 12:31:22 PM PST 24
Peak memory 208368 kb
Host smart-1ec45b75-57a3-40dc-bb23-1712532d5c51
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301206961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2301206961
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3604650544
Short name T102
Test name
Test status
Simulation time 42696987 ps
CPU time 0.85 seconds
Started Jan 14 12:31:25 PM PST 24
Finished Jan 14 12:31:27 PM PST 24
Peak memory 207832 kb
Host smart-51d49fa4-294c-43b5-9af0-7fe94d1f4113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604650544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3604650544
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3139209284
Short name T344
Test name
Test status
Simulation time 1023119071 ps
CPU time 11.82 seconds
Started Jan 14 12:31:27 PM PST 24
Finished Jan 14 12:31:40 PM PST 24
Peak memory 218148 kb
Host smart-5039849e-f986-489b-b504-a01194f2b1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139209284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3139209284
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2239544859
Short name T7
Test name
Test status
Simulation time 834514958 ps
CPU time 19.54 seconds
Started Jan 14 12:31:28 PM PST 24
Finished Jan 14 12:31:48 PM PST 24
Peak memory 209604 kb
Host smart-d621cc3a-c769-4636-b857-a13a823338dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239544859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.2239544859
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3929801659
Short name T527
Test name
Test status
Simulation time 1587004622 ps
CPU time 27.86 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:31:50 PM PST 24
Peak memory 218012 kb
Host smart-bb4d46ca-3abe-4704-af60-273be6b69af2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929801659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3929801659
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2887310153
Short name T785
Test name
Test status
Simulation time 392860801 ps
CPU time 6.48 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:31:29 PM PST 24
Peak memory 218004 kb
Host smart-50677338-c81f-4583-b643-57b95817a3cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887310153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2887310153
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1725038481
Short name T84
Test name
Test status
Simulation time 104651462 ps
CPU time 2.23 seconds
Started Jan 14 12:31:25 PM PST 24
Finished Jan 14 12:31:27 PM PST 24
Peak memory 212904 kb
Host smart-d271a82c-980e-44a2-bae6-8c5d853a259d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725038481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1725038481
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2499005098
Short name T778
Test name
Test status
Simulation time 1534006690 ps
CPU time 38.38 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 250972 kb
Host smart-39fec505-0a70-46b1-a839-8305cb713d8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499005098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2499005098
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1137316255
Short name T602
Test name
Test status
Simulation time 579522788 ps
CPU time 17.8 seconds
Started Jan 14 12:31:27 PM PST 24
Finished Jan 14 12:31:46 PM PST 24
Peak memory 223880 kb
Host smart-636073fc-ca0a-44ca-b660-c6c31c2b8971
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137316255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1137316255
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3398583283
Short name T317
Test name
Test status
Simulation time 646179478 ps
CPU time 3.42 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:31:26 PM PST 24
Peak memory 218096 kb
Host smart-94a8e653-73fd-490f-a385-08aa4326be9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398583283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3398583283
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.4076281407
Short name T475
Test name
Test status
Simulation time 178937323 ps
CPU time 7.94 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:31:30 PM PST 24
Peak memory 218104 kb
Host smart-3d26acaa-d8af-491e-80b7-2526a08aaf67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076281407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4076281407
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1544122907
Short name T363
Test name
Test status
Simulation time 2208168925 ps
CPU time 12.35 seconds
Started Jan 14 12:31:23 PM PST 24
Finished Jan 14 12:31:36 PM PST 24
Peak memory 218056 kb
Host smart-32a29de0-af07-4355-932f-8a64f18254dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544122907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1544122907
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.212139070
Short name T978
Test name
Test status
Simulation time 2291771260 ps
CPU time 9.77 seconds
Started Jan 14 12:31:25 PM PST 24
Finished Jan 14 12:31:36 PM PST 24
Peak memory 218140 kb
Host smart-5a5a617a-dca5-418c-9fca-8b17b95cabc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212139070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.212139070
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.814506737
Short name T471
Test name
Test status
Simulation time 278304973 ps
CPU time 6.95 seconds
Started Jan 14 12:31:23 PM PST 24
Finished Jan 14 12:31:30 PM PST 24
Peak memory 218072 kb
Host smart-4b3b3830-d2ca-487d-b11e-203d1138c43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814506737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.814506737
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.165773765
Short name T86
Test name
Test status
Simulation time 49248494 ps
CPU time 2.84 seconds
Started Jan 14 12:31:23 PM PST 24
Finished Jan 14 12:31:27 PM PST 24
Peak memory 214252 kb
Host smart-97d25a80-afc1-437c-9eb3-d3be2880de17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165773765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.165773765
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1910061090
Short name T369
Test name
Test status
Simulation time 236190533 ps
CPU time 19.87 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:31:43 PM PST 24
Peak memory 250996 kb
Host smart-96ab5a65-babe-455a-86fe-daee5cf71d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910061090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1910061090
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1828274387
Short name T452
Test name
Test status
Simulation time 345432344 ps
CPU time 7.51 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:32 PM PST 24
Peak memory 251080 kb
Host smart-155fe263-0c07-44b6-b7a6-0f0ea36d1848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828274387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1828274387
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2045221302
Short name T748
Test name
Test status
Simulation time 23540669572 ps
CPU time 221.2 seconds
Started Jan 14 12:31:22 PM PST 24
Finished Jan 14 12:35:04 PM PST 24
Peak memory 284020 kb
Host smart-731f592d-f7cf-4d93-81aa-c936f83499a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045221302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2045221302
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3208228272
Short name T720
Test name
Test status
Simulation time 43182199 ps
CPU time 0.83 seconds
Started Jan 14 12:31:26 PM PST 24
Finished Jan 14 12:31:27 PM PST 24
Peak memory 208328 kb
Host smart-4c63874c-547d-4b34-b4c4-f58332080aaa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208228272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3208228272
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3409855466
Short name T581
Test name
Test status
Simulation time 30512275 ps
CPU time 0.87 seconds
Started Jan 14 12:29:59 PM PST 24
Finished Jan 14 12:30:01 PM PST 24
Peak memory 209636 kb
Host smart-36b63c5a-69a2-4df6-9b60-4fb124524ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409855466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3409855466
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2755039943
Short name T775
Test name
Test status
Simulation time 1858688261 ps
CPU time 17.01 seconds
Started Jan 14 12:30:04 PM PST 24
Finished Jan 14 12:30:22 PM PST 24
Peak memory 218160 kb
Host smart-7ed3255c-8c0b-4cec-a404-3158aa570148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755039943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2755039943
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2891309084
Short name T882
Test name
Test status
Simulation time 1559746178 ps
CPU time 9.2 seconds
Started Jan 14 12:30:10 PM PST 24
Finished Jan 14 12:30:21 PM PST 24
Peak memory 209656 kb
Host smart-fc439192-64a9-4f0b-9f7d-0cffdba50be1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891309084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ac
cess.2891309084
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.681592232
Short name T621
Test name
Test status
Simulation time 1885737916 ps
CPU time 30.1 seconds
Started Jan 14 12:30:03 PM PST 24
Finished Jan 14 12:30:35 PM PST 24
Peak memory 218020 kb
Host smart-9542a0ab-a3e5-4c91-be58-ee5bd9319e53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681592232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.681592232
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.466077303
Short name T338
Test name
Test status
Simulation time 327559624 ps
CPU time 8.46 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:15 PM PST 24
Peak memory 218048 kb
Host smart-abf84c4d-7fab-4db7-8239-1cdd6fccacff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466077303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_p
riority.466077303
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.615482068
Short name T373
Test name
Test status
Simulation time 76125414 ps
CPU time 2.27 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:30:04 PM PST 24
Peak memory 218200 kb
Host smart-32307522-a2f0-41b7-b9b8-c19be51ee35c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615482068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.615482068
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.903728300
Short name T585
Test name
Test status
Simulation time 1101919549 ps
CPU time 31.44 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:38 PM PST 24
Peak memory 213052 kb
Host smart-97ef9e16-34e2-43e9-8e57-c671b10553a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903728300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.903728300
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3086920333
Short name T470
Test name
Test status
Simulation time 1356733296 ps
CPU time 3.75 seconds
Started Jan 14 12:30:03 PM PST 24
Finished Jan 14 12:30:09 PM PST 24
Peak memory 213180 kb
Host smart-cb913270-c2d1-4344-ad54-79894b89926e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086920333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3086920333
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4053900040
Short name T680
Test name
Test status
Simulation time 5109183024 ps
CPU time 36.31 seconds
Started Jan 14 12:30:04 PM PST 24
Finished Jan 14 12:30:42 PM PST 24
Peak memory 283796 kb
Host smart-f3fdfbd3-adfb-4e90-a163-3541e3bb6d96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053900040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4053900040
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3562899936
Short name T342
Test name
Test status
Simulation time 1492066901 ps
CPU time 10.62 seconds
Started Jan 14 12:29:56 PM PST 24
Finished Jan 14 12:30:08 PM PST 24
Peak memory 249980 kb
Host smart-f70ecd2a-3870-417c-a66e-41ee842d2355
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562899936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3562899936
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2147729138
Short name T747
Test name
Test status
Simulation time 390870754 ps
CPU time 1.99 seconds
Started Jan 14 12:30:10 PM PST 24
Finished Jan 14 12:30:14 PM PST 24
Peak memory 218244 kb
Host smart-87bd41fb-b449-4a68-ba36-3e4e059133ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147729138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2147729138
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3521799399
Short name T719
Test name
Test status
Simulation time 821941738 ps
CPU time 5.71 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:15 PM PST 24
Peak memory 213980 kb
Host smart-07380bb7-1946-4f14-91af-8066d479ff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521799399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3521799399
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1700490162
Short name T808
Test name
Test status
Simulation time 2041194451 ps
CPU time 14.12 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 218716 kb
Host smart-35d69c25-bb15-4d99-996d-2da4e4cedf15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700490162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1700490162
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2635490747
Short name T868
Test name
Test status
Simulation time 521332668 ps
CPU time 9.35 seconds
Started Jan 14 12:29:59 PM PST 24
Finished Jan 14 12:30:10 PM PST 24
Peak memory 218156 kb
Host smart-4ffd4453-4d9c-43fa-9b11-987f4fc6e0c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635490747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2635490747
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1816044769
Short name T897
Test name
Test status
Simulation time 1221335910 ps
CPU time 8.74 seconds
Started Jan 14 12:30:02 PM PST 24
Finished Jan 14 12:30:13 PM PST 24
Peak memory 218172 kb
Host smart-06600f2b-23de-46ec-af1a-8e6c95d12260
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816044769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
816044769
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2963544197
Short name T890
Test name
Test status
Simulation time 225242354 ps
CPU time 9.94 seconds
Started Jan 14 12:30:17 PM PST 24
Finished Jan 14 12:30:28 PM PST 24
Peak memory 218056 kb
Host smart-ef3ef20a-d4b8-4836-9562-5081327e4818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963544197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2963544197
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4056253180
Short name T790
Test name
Test status
Simulation time 43293316 ps
CPU time 2.06 seconds
Started Jan 14 12:29:56 PM PST 24
Finished Jan 14 12:30:00 PM PST 24
Peak memory 213796 kb
Host smart-526e9f92-2a7c-44ab-8355-599919a885c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056253180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4056253180
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1068581319
Short name T665
Test name
Test status
Simulation time 1305080221 ps
CPU time 32.6 seconds
Started Jan 14 12:30:01 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 251004 kb
Host smart-e0a8b7a4-cd81-4b34-9470-8ea55865d1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068581319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1068581319
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.4229266761
Short name T529
Test name
Test status
Simulation time 81149256 ps
CPU time 6.8 seconds
Started Jan 14 12:30:01 PM PST 24
Finished Jan 14 12:30:10 PM PST 24
Peak memory 248352 kb
Host smart-c2cce9f1-b1d3-4362-a1f4-44e8e9569f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229266761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.4229266761
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1248534318
Short name T562
Test name
Test status
Simulation time 719546545 ps
CPU time 25.27 seconds
Started Jan 14 12:30:00 PM PST 24
Finished Jan 14 12:30:27 PM PST 24
Peak memory 226232 kb
Host smart-c04f8c28-9737-4842-9ec2-8fd1218038bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248534318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1248534318
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2504886171
Short name T521
Test name
Test status
Simulation time 10997770 ps
CPU time 0.77 seconds
Started Jan 14 12:29:59 PM PST 24
Finished Jan 14 12:30:01 PM PST 24
Peak memory 207988 kb
Host smart-bb16e1d8-131e-468e-a6a7-2c0cf3617056
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504886171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2504886171
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3363197198
Short name T541
Test name
Test status
Simulation time 18574023 ps
CPU time 0.91 seconds
Started Jan 14 12:31:48 PM PST 24
Finished Jan 14 12:31:49 PM PST 24
Peak memory 209656 kb
Host smart-4a2e57aa-d41a-4494-810b-ba5d01e29c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363197198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3363197198
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1840752572
Short name T838
Test name
Test status
Simulation time 809233486 ps
CPU time 20.63 seconds
Started Jan 14 12:31:26 PM PST 24
Finished Jan 14 12:31:47 PM PST 24
Peak memory 218124 kb
Host smart-4a71010f-2cdf-451c-92b3-764150910f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840752572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1840752572
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2867713718
Short name T22
Test name
Test status
Simulation time 371590372 ps
CPU time 1.65 seconds
Started Jan 14 12:31:23 PM PST 24
Finished Jan 14 12:31:25 PM PST 24
Peak memory 209632 kb
Host smart-4d95ef8c-15eb-4519-97cb-5bd39a6cb960
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867713718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.2867713718
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.580835077
Short name T924
Test name
Test status
Simulation time 163030830 ps
CPU time 2.52 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:27 PM PST 24
Peak memory 218084 kb
Host smart-0a0797cc-d851-4a55-ac3e-b5bf054cb3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580835077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.580835077
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3106181123
Short name T840
Test name
Test status
Simulation time 1084856427 ps
CPU time 15.08 seconds
Started Jan 14 12:31:40 PM PST 24
Finished Jan 14 12:31:55 PM PST 24
Peak memory 219180 kb
Host smart-0be7be7c-1467-4d09-b4cf-84893fbb0daa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106181123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3106181123
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2786839716
Short name T735
Test name
Test status
Simulation time 2437443453 ps
CPU time 13.06 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218040 kb
Host smart-f006c47d-a238-4757-8e18-91b7b3661814
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786839716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2786839716
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3349735831
Short name T484
Test name
Test status
Simulation time 224711482 ps
CPU time 9.33 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 217980 kb
Host smart-279117bc-4b45-4c0f-bcbd-5ec656f19185
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349735831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3349735831
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.124458275
Short name T524
Test name
Test status
Simulation time 2211905301 ps
CPU time 15.35 seconds
Started Jan 14 12:31:28 PM PST 24
Finished Jan 14 12:31:44 PM PST 24
Peak memory 218200 kb
Host smart-ae264dc7-b927-4a8d-828c-0472cfaf2a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124458275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.124458275
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3369758689
Short name T82
Test name
Test status
Simulation time 106376954 ps
CPU time 3.14 seconds
Started Jan 14 12:31:24 PM PST 24
Finished Jan 14 12:31:28 PM PST 24
Peak memory 214412 kb
Host smart-b9d59d10-cbe8-4e9d-ab2b-8557968368e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369758689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3369758689
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1049481768
Short name T68
Test name
Test status
Simulation time 252726415 ps
CPU time 30.06 seconds
Started Jan 14 12:31:26 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 251100 kb
Host smart-58986631-2fb2-49c2-b689-9f9b8f633d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049481768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1049481768
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.191763035
Short name T671
Test name
Test status
Simulation time 47356714 ps
CPU time 6.16 seconds
Started Jan 14 12:31:20 PM PST 24
Finished Jan 14 12:31:26 PM PST 24
Peak memory 246284 kb
Host smart-7ca17871-5997-4864-971a-60d161d5dbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191763035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.191763035
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1965752514
Short name T908
Test name
Test status
Simulation time 1551595087 ps
CPU time 57.53 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:32:43 PM PST 24
Peak memory 234868 kb
Host smart-8982a74d-e281-4467-a4ee-98e3f64e3020
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965752514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1965752514
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2959352686
Short name T336
Test name
Test status
Simulation time 18486908 ps
CPU time 0.88 seconds
Started Jan 14 12:31:25 PM PST 24
Finished Jan 14 12:31:27 PM PST 24
Peak memory 207832 kb
Host smart-d06bd836-c581-444c-84ba-8e0a64edb70e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959352686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2959352686
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.10313757
Short name T566
Test name
Test status
Simulation time 19187330 ps
CPU time 1.14 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:31:47 PM PST 24
Peak memory 209668 kb
Host smart-1f2a04f7-7c28-4a38-857a-e3ffc9ae0024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10313757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.10313757
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4076900727
Short name T779
Test name
Test status
Simulation time 488414110 ps
CPU time 14.98 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 218148 kb
Host smart-1179781a-4d68-4507-ad78-224eec2cc083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076900727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4076900727
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.362861289
Short name T21
Test name
Test status
Simulation time 447209317 ps
CPU time 7.45 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 209512 kb
Host smart-e857eef8-9ac1-4620-b0e9-348ba83f6275
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362861289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_ac
cess.362861289
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.420912322
Short name T538
Test name
Test status
Simulation time 433918238 ps
CPU time 2.51 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:52 PM PST 24
Peak memory 217880 kb
Host smart-d638149e-811e-4d99-a6d8-4ebba787db5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420912322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.420912322
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3105996664
Short name T654
Test name
Test status
Simulation time 1419202310 ps
CPU time 10.46 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 218340 kb
Host smart-f2518073-6eac-447b-a770-4138fb5437cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105996664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3105996664
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.501561426
Short name T909
Test name
Test status
Simulation time 457443218 ps
CPU time 12.36 seconds
Started Jan 14 12:31:43 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 218068 kb
Host smart-b8d843af-e585-4f94-ad57-e9984e9c5451
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501561426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.501561426
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2179362345
Short name T579
Test name
Test status
Simulation time 602614300 ps
CPU time 21.05 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218132 kb
Host smart-afce6863-b8a6-479d-b4f9-114c0ff038b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179362345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2179362345
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2153113453
Short name T825
Test name
Test status
Simulation time 230242394 ps
CPU time 7.3 seconds
Started Jan 14 12:31:48 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 218152 kb
Host smart-922e8e06-5b03-41d5-9449-c07fb4b16e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153113453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2153113453
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1904723306
Short name T729
Test name
Test status
Simulation time 78290628 ps
CPU time 3.84 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 214340 kb
Host smart-f58ec946-4534-4d86-8d75-2caebb8de012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904723306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1904723306
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3825271031
Short name T712
Test name
Test status
Simulation time 873791519 ps
CPU time 29.42 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 251024 kb
Host smart-5fba1e2f-e18c-4cf4-a77e-0948726b6b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825271031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3825271031
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1094588789
Short name T392
Test name
Test status
Simulation time 261909660 ps
CPU time 7.96 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 251088 kb
Host smart-79262217-0e4f-4c18-9b73-d77601645f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094588789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1094588789
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.7554767
Short name T863
Test name
Test status
Simulation time 26864105470 ps
CPU time 486.12 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:39:51 PM PST 24
Peak memory 303540 kb
Host smart-267891af-f5d3-4071-83c2-370ed3db88e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7554767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.lc_ctrl_stress_all.7554767
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.522393882
Short name T699
Test name
Test status
Simulation time 31934305 ps
CPU time 0.84 seconds
Started Jan 14 12:31:47 PM PST 24
Finished Jan 14 12:31:48 PM PST 24
Peak memory 208328 kb
Host smart-5ec2aba1-28ec-4983-b912-2405dcb66336
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522393882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.522393882
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2894063892
Short name T811
Test name
Test status
Simulation time 20609030 ps
CPU time 1.13 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:50 PM PST 24
Peak memory 209632 kb
Host smart-d36f9d64-0c11-4145-a5e9-4e4c20ec3108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894063892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2894063892
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2588185807
Short name T681
Test name
Test status
Simulation time 1183865306 ps
CPU time 12.94 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 218140 kb
Host smart-879aa9bb-fd59-4faa-a2d2-837a3e0a41b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588185807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2588185807
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1394694568
Short name T751
Test name
Test status
Simulation time 1035621014 ps
CPU time 14.12 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 209672 kb
Host smart-5ab0a8aa-1380-4ed6-aff2-b9e0a239cb28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394694568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.1394694568
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.431807923
Short name T480
Test name
Test status
Simulation time 22605155 ps
CPU time 1.62 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:51 PM PST 24
Peak memory 217816 kb
Host smart-7408fda2-0a9f-4d8e-8e0d-a2f77e3eadce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431807923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.431807923
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.341615930
Short name T590
Test name
Test status
Simulation time 234444248 ps
CPU time 12.47 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 218240 kb
Host smart-869e99d1-85cf-4300-b94a-71f1da615e6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341615930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.341615930
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4168584518
Short name T734
Test name
Test status
Simulation time 311511200 ps
CPU time 9.72 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 218084 kb
Host smart-7eeab633-f5de-49d2-be6a-97c280cd1333
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168584518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4168584518
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2836762616
Short name T380
Test name
Test status
Simulation time 1315042580 ps
CPU time 9.04 seconds
Started Jan 14 12:31:44 PM PST 24
Finished Jan 14 12:31:54 PM PST 24
Peak memory 218000 kb
Host smart-7e3a07e2-879f-448b-afda-9c8b9cd38404
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836762616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2836762616
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2267268562
Short name T600
Test name
Test status
Simulation time 2057427487 ps
CPU time 11.93 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 218180 kb
Host smart-60156857-e980-4a36-80cd-58df928a2f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267268562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2267268562
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.923778168
Short name T861
Test name
Test status
Simulation time 39458248 ps
CPU time 1.18 seconds
Started Jan 14 12:31:47 PM PST 24
Finished Jan 14 12:31:49 PM PST 24
Peak memory 212988 kb
Host smart-0553a725-6637-4a18-8b59-cef1d0102c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923778168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.923778168
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3248102278
Short name T635
Test name
Test status
Simulation time 277607914 ps
CPU time 28.29 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:32:20 PM PST 24
Peak memory 251088 kb
Host smart-91702118-4ee6-4148-bea4-d1b1d245128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248102278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3248102278
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2333368419
Short name T984
Test name
Test status
Simulation time 252755829 ps
CPU time 7.01 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:31:54 PM PST 24
Peak memory 248044 kb
Host smart-94dafdc6-bcb5-41ab-98a5-440d3d10f944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333368419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2333368419
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2385919896
Short name T857
Test name
Test status
Simulation time 16294356 ps
CPU time 0.84 seconds
Started Jan 14 12:31:44 PM PST 24
Finished Jan 14 12:31:45 PM PST 24
Peak memory 208244 kb
Host smart-8384cb83-d21f-4e97-a0eb-e07c34989321
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385919896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2385919896
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2395856263
Short name T459
Test name
Test status
Simulation time 18136819 ps
CPU time 0.88 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:31:48 PM PST 24
Peak memory 209664 kb
Host smart-a00518fb-262c-4b22-9a48-6df94e372dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395856263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2395856263
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3243583413
Short name T503
Test name
Test status
Simulation time 472189556 ps
CPU time 7.81 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 218136 kb
Host smart-35d9f92e-1b91-4772-bef4-0e86724ceba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243583413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3243583413
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1058628630
Short name T854
Test name
Test status
Simulation time 697109720 ps
CPU time 3.12 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:52 PM PST 24
Peak memory 209532 kb
Host smart-e0a2b907-2317-4805-becc-1905cfd23238
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058628630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.1058628630
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.589150747
Short name T473
Test name
Test status
Simulation time 63773149 ps
CPU time 3.33 seconds
Started Jan 14 12:31:44 PM PST 24
Finished Jan 14 12:31:47 PM PST 24
Peak memory 218068 kb
Host smart-224d5c8a-f1cc-455f-9dc9-cb36283dec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589150747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.589150747
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3295884773
Short name T421
Test name
Test status
Simulation time 227084506 ps
CPU time 9.15 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:31:55 PM PST 24
Peak memory 219096 kb
Host smart-ac2d5cba-ada6-44d0-99a4-90517977ebff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295884773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3295884773
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3004358956
Short name T824
Test name
Test status
Simulation time 229454464 ps
CPU time 7.43 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 218024 kb
Host smart-19fb5480-440c-44ae-9ec0-7fa04558325b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004358956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3004358956
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1333190718
Short name T963
Test name
Test status
Simulation time 999280350 ps
CPU time 11.2 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:31:58 PM PST 24
Peak memory 218132 kb
Host smart-1f5711e0-56a2-4af5-b655-61526e24f3b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333190718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1333190718
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2095641095
Short name T940
Test name
Test status
Simulation time 1342479776 ps
CPU time 14.57 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218092 kb
Host smart-a5077718-6943-44e6-abfb-7bfe792e7ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095641095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2095641095
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2633012996
Short name T809
Test name
Test status
Simulation time 79091388 ps
CPU time 1.9 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:31:49 PM PST 24
Peak memory 213820 kb
Host smart-ad6cdda1-3b10-44b3-b7e8-d5697d34eaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633012996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2633012996
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4223610310
Short name T962
Test name
Test status
Simulation time 339332392 ps
CPU time 22.5 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 250812 kb
Host smart-a924f9af-16a7-4907-b143-22db11742068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223610310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4223610310
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2055196968
Short name T914
Test name
Test status
Simulation time 47758175 ps
CPU time 3 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:52 PM PST 24
Peak memory 222004 kb
Host smart-0bc0cc80-6da5-43cb-bee9-e41240a35a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055196968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2055196968
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2028219932
Short name T649
Test name
Test status
Simulation time 6021003946 ps
CPU time 73.43 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:33:11 PM PST 24
Peak memory 250868 kb
Host smart-e3d5cef3-d66d-4de5-b434-716276b47509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028219932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2028219932
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1793465318
Short name T846
Test name
Test status
Simulation time 53890799 ps
CPU time 0.88 seconds
Started Jan 14 12:31:41 PM PST 24
Finished Jan 14 12:31:42 PM PST 24
Peak memory 211344 kb
Host smart-61c915ab-f585-450e-948c-3a26e2113539
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793465318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1793465318
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2527031261
Short name T551
Test name
Test status
Simulation time 100090017 ps
CPU time 1.27 seconds
Started Jan 14 12:31:47 PM PST 24
Finished Jan 14 12:31:49 PM PST 24
Peak memory 208488 kb
Host smart-771eeaff-dacb-4f1d-bc58-adbbd48f81e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527031261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2527031261
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2704601179
Short name T623
Test name
Test status
Simulation time 494481060 ps
CPU time 11.01 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 218148 kb
Host smart-d966cbf8-203d-48f8-8d37-ae48ff14e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704601179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2704601179
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2897796615
Short name T802
Test name
Test status
Simulation time 1090207288 ps
CPU time 10.08 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 209436 kb
Host smart-671e1f19-3e5a-47d7-b712-1469b145eaa6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897796615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_a
ccess.2897796615
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1718311950
Short name T381
Test name
Test status
Simulation time 70059729 ps
CPU time 3.14 seconds
Started Jan 14 12:31:47 PM PST 24
Finished Jan 14 12:31:51 PM PST 24
Peak memory 218144 kb
Host smart-7ddc9459-b79c-4d47-a450-12909de995df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718311950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1718311950
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.4227137541
Short name T438
Test name
Test status
Simulation time 855703758 ps
CPU time 14.67 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 218164 kb
Host smart-687d6fae-e911-4afb-85fa-0a6bd46e6803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227137541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4227137541
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1325858062
Short name T185
Test name
Test status
Simulation time 1874771594 ps
CPU time 17.51 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 218016 kb
Host smart-9cbad4ae-ee54-4cc9-951d-2c08187303dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325858062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1325858062
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2147527990
Short name T624
Test name
Test status
Simulation time 190706119 ps
CPU time 7.84 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 218036 kb
Host smart-8ca44244-fde7-45f8-b609-9b474ddd87f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147527990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2147527990
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.565352080
Short name T12
Test name
Test status
Simulation time 921844167 ps
CPU time 9.7 seconds
Started Jan 14 12:31:43 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 218076 kb
Host smart-6ae24d19-e50e-4f1d-a423-d540a91d2c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565352080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.565352080
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2764907063
Short name T516
Test name
Test status
Simulation time 531660935 ps
CPU time 3.65 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 217668 kb
Host smart-bc0f6ce5-11e1-4653-b524-4f464ed5e5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764907063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2764907063
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.882759258
Short name T692
Test name
Test status
Simulation time 505930856 ps
CPU time 22.26 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 251068 kb
Host smart-1fdd517d-5afc-4dc0-97e5-7cb2bc6246a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882759258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.882759258
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2074487236
Short name T457
Test name
Test status
Simulation time 154450111 ps
CPU time 8.7 seconds
Started Jan 14 12:31:47 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 251092 kb
Host smart-0d60d3a7-c5e9-4178-975d-0953d6cc5c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074487236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2074487236
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2485726252
Short name T542
Test name
Test status
Simulation time 9607932029 ps
CPU time 68.78 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:33:05 PM PST 24
Peak memory 250468 kb
Host smart-9130638b-ef97-4de5-be30-08ffbaf05a48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485726252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2485726252
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1905036847
Short name T879
Test name
Test status
Simulation time 12992798 ps
CPU time 0.99 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:50 PM PST 24
Peak memory 211376 kb
Host smart-09f4245f-04b6-4a12-9874-4ab2cdb8ed6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905036847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1905036847
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3273303737
Short name T849
Test name
Test status
Simulation time 18132204 ps
CPU time 1.14 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:31:58 PM PST 24
Peak memory 209584 kb
Host smart-dc87ea5f-745c-400e-aefb-2a7327ed98f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273303737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3273303737
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3411534858
Short name T593
Test name
Test status
Simulation time 1432460198 ps
CPU time 16.44 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218136 kb
Host smart-2e455118-4b44-4b75-9963-0d9b5c4b0c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411534858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3411534858
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1138585811
Short name T580
Test name
Test status
Simulation time 253478052 ps
CPU time 3.18 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 209560 kb
Host smart-35505845-03d3-4c89-981f-0f69dbc6de04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138585811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_a
ccess.1138585811
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3501812496
Short name T360
Test name
Test status
Simulation time 271408177 ps
CPU time 3.24 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:31:54 PM PST 24
Peak memory 218176 kb
Host smart-3d504b9a-1f6d-443c-af37-56f17a7dbbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501812496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3501812496
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.312595063
Short name T648
Test name
Test status
Simulation time 4844288928 ps
CPU time 13.37 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 219168 kb
Host smart-85d9306b-53c2-4ab4-8384-1b8276755d63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312595063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.312595063
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2840397674
Short name T479
Test name
Test status
Simulation time 2112019168 ps
CPU time 27.65 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:26 PM PST 24
Peak memory 218192 kb
Host smart-7ad33964-34cc-4283-85c7-0f2fbef40a16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840397674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2840397674
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3891420910
Short name T954
Test name
Test status
Simulation time 668204033 ps
CPU time 14 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 217956 kb
Host smart-5426a128-f89c-4286-aef5-09022e0f268c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891420910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3891420910
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.128078374
Short name T903
Test name
Test status
Simulation time 215331874 ps
CPU time 7.3 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 218140 kb
Host smart-fb2eae8b-3a9f-41ce-92b7-86178921400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128078374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.128078374
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3420623160
Short name T958
Test name
Test status
Simulation time 86102120 ps
CPU time 2.52 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:31:55 PM PST 24
Peak memory 214032 kb
Host smart-3c4eba79-6ced-478e-9a9e-346ee6a03fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420623160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3420623160
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1827376650
Short name T835
Test name
Test status
Simulation time 324943924 ps
CPU time 29.88 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:32:21 PM PST 24
Peak memory 251132 kb
Host smart-fab4fca7-324b-421d-ae43-adb78f75e198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827376650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1827376650
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3722254670
Short name T821
Test name
Test status
Simulation time 282374008 ps
CPU time 9.19 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 251180 kb
Host smart-b141df72-4cf0-4ba0-9c94-6dbf972ecf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722254670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3722254670
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.796593996
Short name T770
Test name
Test status
Simulation time 6465995630 ps
CPU time 116.82 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:33:55 PM PST 24
Peak memory 275408 kb
Host smart-ef594753-1197-48c1-b1e0-23c514180837
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796593996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.796593996
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.443796752
Short name T723
Test name
Test status
Simulation time 13726601 ps
CPU time 0.86 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:31:58 PM PST 24
Peak memory 208008 kb
Host smart-77a78207-0938-40a7-95d8-d7e817052006
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443796752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.443796752
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3597601688
Short name T463
Test name
Test status
Simulation time 35321849 ps
CPU time 0.81 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:31:58 PM PST 24
Peak memory 209392 kb
Host smart-f1c23fa9-2468-4ddb-97b2-b7d8fbbc8d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597601688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3597601688
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2497872904
Short name T912
Test name
Test status
Simulation time 1830402425 ps
CPU time 12.64 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 218132 kb
Host smart-f7f4eab3-6fd5-4460-aab3-e95403a6adc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497872904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2497872904
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2913303508
Short name T652
Test name
Test status
Simulation time 3586503655 ps
CPU time 7.51 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 209740 kb
Host smart-b80dcb7f-cabe-4d1c-8f86-dd88a7d301b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913303508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.2913303508
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.200922987
Short name T449
Test name
Test status
Simulation time 366936756 ps
CPU time 2.74 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 218204 kb
Host smart-44eeaad5-94cf-423c-8bf8-528606f4a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200922987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.200922987
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.588713824
Short name T851
Test name
Test status
Simulation time 331624586 ps
CPU time 14.99 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 219228 kb
Host smart-dffb13e9-97ed-4612-aecb-a172331c4219
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588713824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.588713824
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1287063466
Short name T679
Test name
Test status
Simulation time 417596807 ps
CPU time 14.05 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:16 PM PST 24
Peak memory 217988 kb
Host smart-82e2c191-5b19-4648-8969-97d952edf549
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287063466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1287063466
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.934940325
Short name T817
Test name
Test status
Simulation time 1298070367 ps
CPU time 9.57 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:16 PM PST 24
Peak memory 218036 kb
Host smart-f066d50f-a948-4b15-bac9-848f8cdd5b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934940325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.934940325
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3703678315
Short name T63
Test name
Test status
Simulation time 630298747 ps
CPU time 7.58 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 218132 kb
Host smart-b6f7dee2-cab4-4eee-8eec-680992345ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703678315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3703678315
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.737760730
Short name T827
Test name
Test status
Simulation time 156498482 ps
CPU time 2.67 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 214076 kb
Host smart-12d1bb1b-3c44-4d12-bd02-58ff809f9fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737760730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.737760730
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2541319234
Short name T563
Test name
Test status
Simulation time 1333958678 ps
CPU time 35.72 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:35 PM PST 24
Peak memory 251020 kb
Host smart-0a3ae0ed-ce2c-4efb-88fe-c6623b941b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541319234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2541319234
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.162411991
Short name T315
Test name
Test status
Simulation time 120744007 ps
CPU time 7.49 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 251092 kb
Host smart-da8f3c6e-d9ea-4e14-ba42-437b59890351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162411991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.162411991
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.714889178
Short name T693
Test name
Test status
Simulation time 25348562256 ps
CPU time 52.46 seconds
Started Jan 14 12:31:47 PM PST 24
Finished Jan 14 12:32:40 PM PST 24
Peak memory 226400 kb
Host smart-21913559-9b34-42bc-bc68-460e8a1ecb0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714889178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.714889178
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1136714739
Short name T758
Test name
Test status
Simulation time 25896950 ps
CPU time 0.8 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 208072 kb
Host smart-74be573a-5ec1-4e6f-af58-f90eadd237c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136714739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1136714739
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4025030801
Short name T642
Test name
Test status
Simulation time 79369716 ps
CPU time 0.93 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 209680 kb
Host smart-f3c011d2-d918-4f7b-ae80-4a64f89b5708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025030801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4025030801
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2867538608
Short name T52
Test name
Test status
Simulation time 1190357986 ps
CPU time 9.97 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 218104 kb
Host smart-bd8d9a31-7a55-4516-b67c-6769d605e387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867538608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2867538608
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.53741949
Short name T922
Test name
Test status
Simulation time 857365566 ps
CPU time 11.71 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 209636 kb
Host smart-02bfae32-3cf5-436d-a26d-4e80f2196b0b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53741949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_acc
ess.53741949
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1496142847
Short name T816
Test name
Test status
Simulation time 226207129 ps
CPU time 2.79 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 218176 kb
Host smart-2d2c8dac-e01e-4315-a366-502908568ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496142847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1496142847
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2144905120
Short name T526
Test name
Test status
Simulation time 782143679 ps
CPU time 12.78 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 218464 kb
Host smart-61b68d9f-0729-4690-acf2-41ab84096568
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144905120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2144905120
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3347866398
Short name T548
Test name
Test status
Simulation time 567815027 ps
CPU time 8.09 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 217552 kb
Host smart-e981bade-6e87-47bd-b5a8-fbc6ba939672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347866398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3347866398
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4004919672
Short name T615
Test name
Test status
Simulation time 785372086 ps
CPU time 8.61 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 218040 kb
Host smart-52dc8894-511f-4326-a95b-700d8624c3d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004919672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4004919672
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2033225973
Short name T512
Test name
Test status
Simulation time 1337876455 ps
CPU time 8.55 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 218168 kb
Host smart-15b2d543-af3f-46a5-b218-ab30808806c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033225973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2033225973
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2869172169
Short name T639
Test name
Test status
Simulation time 48689090 ps
CPU time 2.95 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:31:58 PM PST 24
Peak memory 214068 kb
Host smart-e2cb761a-393e-46d9-89a8-2832fe6055d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869172169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2869172169
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3321382857
Short name T646
Test name
Test status
Simulation time 321872941 ps
CPU time 36.48 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:32:31 PM PST 24
Peak memory 251008 kb
Host smart-48934d3a-4061-47e7-babf-1d62b77cd242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321382857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3321382857
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.895312296
Short name T836
Test name
Test status
Simulation time 63960186 ps
CPU time 5.94 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 246176 kb
Host smart-1b4960e8-81c3-4164-8e31-960b2e2f2721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895312296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.895312296
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3498508247
Short name T714
Test name
Test status
Simulation time 124894787129 ps
CPU time 314.98 seconds
Started Jan 14 12:31:48 PM PST 24
Finished Jan 14 12:37:03 PM PST 24
Peak memory 258588 kb
Host smart-b62813d0-bf8f-4770-bc98-838a04de0b4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498508247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3498508247
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3600803879
Short name T619
Test name
Test status
Simulation time 38360147 ps
CPU time 1.14 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:31:52 PM PST 24
Peak memory 209692 kb
Host smart-5e32b904-6da6-4526-a24f-3763de1190d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600803879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3600803879
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2305153714
Short name T368
Test name
Test status
Simulation time 587283510 ps
CPU time 22.14 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 218032 kb
Host smart-853cc7b8-a96a-4a3e-acc0-96495acf0934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305153714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2305153714
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3680809015
Short name T894
Test name
Test status
Simulation time 240196410 ps
CPU time 3.42 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 209500 kb
Host smart-5822d879-34f2-4847-bd3e-15e9213fc896
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680809015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.3680809015
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2190910470
Short name T696
Test name
Test status
Simulation time 282023633 ps
CPU time 2.06 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 218168 kb
Host smart-72a0216d-5869-4dc3-8420-fb5c8db73f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190910470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2190910470
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2641048871
Short name T687
Test name
Test status
Simulation time 467234527 ps
CPU time 20.09 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 219164 kb
Host smart-23005d40-7652-4013-a893-9ce1d2c725aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641048871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2641048871
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2543551091
Short name T448
Test name
Test status
Simulation time 1910557288 ps
CPU time 12.76 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 218016 kb
Host smart-0c8a80c8-3b51-4571-b713-122e0b396ee5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543551091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2543551091
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.4150295944
Short name T976
Test name
Test status
Simulation time 1391660290 ps
CPU time 9.3 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 218032 kb
Host smart-dc6d4657-5b6f-4c05-b26a-e14527b45241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150295944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
4150295944
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1655351990
Short name T613
Test name
Test status
Simulation time 1757512520 ps
CPU time 16.27 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 218032 kb
Host smart-433dda68-a715-4649-b815-6ddae6467b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655351990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1655351990
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.272449812
Short name T489
Test name
Test status
Simulation time 58457766 ps
CPU time 3.22 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:31:49 PM PST 24
Peak memory 214160 kb
Host smart-322d723d-df0e-4764-abd7-31d8595aff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272449812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.272449812
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3206326272
Short name T883
Test name
Test status
Simulation time 1124861978 ps
CPU time 32.36 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:26 PM PST 24
Peak memory 250876 kb
Host smart-cdd75f1a-23c8-4641-8216-6bc24a640116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206326272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3206326272
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.467839988
Short name T725
Test name
Test status
Simulation time 157070077 ps
CPU time 9.7 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 251104 kb
Host smart-fc9651ab-bd96-4593-a567-4d9646f1f89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467839988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.467839988
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3199950943
Short name T985
Test name
Test status
Simulation time 474097305 ps
CPU time 24.87 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 223856 kb
Host smart-0090b74d-0b71-42e3-ad0e-276787085903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199950943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3199950943
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1493498424
Short name T806
Test name
Test status
Simulation time 91836537 ps
CPU time 0.82 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:51 PM PST 24
Peak memory 208232 kb
Host smart-f37fdb81-b015-407a-9d22-1eb8f1743148
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493498424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1493498424
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1079338892
Short name T382
Test name
Test status
Simulation time 18848363 ps
CPU time 0.95 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 208304 kb
Host smart-3dfeb3bc-896a-4025-91f3-363ca32b3994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079338892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1079338892
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2595903456
Short name T797
Test name
Test status
Simulation time 340698777 ps
CPU time 11.51 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 218132 kb
Host smart-8a3306a0-8cd1-42a1-be45-3acf935fc009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595903456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2595903456
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2615952806
Short name T666
Test name
Test status
Simulation time 1897207126 ps
CPU time 6.53 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 209540 kb
Host smart-74dd2382-eb6b-435b-a188-391153d23a98
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615952806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.2615952806
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2414503827
Short name T406
Test name
Test status
Simulation time 878268122 ps
CPU time 2.73 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 218092 kb
Host smart-3ec35a7b-fcc1-4557-b116-ece0979f49e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414503827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2414503827
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1118654014
Short name T50
Test name
Test status
Simulation time 516505652 ps
CPU time 15.81 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 219084 kb
Host smart-9efefa37-e4f5-4487-9170-86f59dae45d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118654014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1118654014
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3628652928
Short name T911
Test name
Test status
Simulation time 1428775331 ps
CPU time 15.46 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 218000 kb
Host smart-62aa7cf2-92d1-48e8-b227-ee20ed36929b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628652928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3628652928
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.824747063
Short name T844
Test name
Test status
Simulation time 292340067 ps
CPU time 7.35 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 218004 kb
Host smart-2d2b2311-babc-4476-ab9b-d360977dec2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824747063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.824747063
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1903207942
Short name T834
Test name
Test status
Simulation time 506533895 ps
CPU time 11.61 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218016 kb
Host smart-261ad252-790c-4f51-93f9-e9557c7dff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903207942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1903207942
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2787521972
Short name T14
Test name
Test status
Simulation time 41277789 ps
CPU time 1.44 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 212824 kb
Host smart-dc86850c-00aa-4ae3-8262-6ae7d6895766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787521972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2787521972
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1680950970
Short name T309
Test name
Test status
Simulation time 210930032 ps
CPU time 17.62 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 251060 kb
Host smart-f989fe02-4eea-43d3-a476-20625aa1c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680950970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1680950970
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2386908745
Short name T364
Test name
Test status
Simulation time 165553696 ps
CPU time 8.17 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 251028 kb
Host smart-ba47189a-c8ea-49e5-a788-97c50f7ce6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386908745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2386908745
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2579377073
Short name T547
Test name
Test status
Simulation time 8463315843 ps
CPU time 69.54 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:33:07 PM PST 24
Peak memory 221268 kb
Host smart-e6d23eba-339c-4e9b-8e6f-6afeaa8de95d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579377073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2579377073
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3407463621
Short name T34
Test name
Test status
Simulation time 14600260 ps
CPU time 0.92 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:31:51 PM PST 24
Peak memory 208164 kb
Host smart-e7bbe5e2-c29e-4d42-a750-69630f4ace48
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407463621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3407463621
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3257071142
Short name T418
Test name
Test status
Simulation time 42070199 ps
CPU time 0.86 seconds
Started Jan 14 12:30:15 PM PST 24
Finished Jan 14 12:30:17 PM PST 24
Peak memory 208252 kb
Host smart-e78ecb1a-8cf5-4a65-9e58-6aaaff26cc59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257071142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3257071142
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3913162414
Short name T913
Test name
Test status
Simulation time 959080410 ps
CPU time 10.17 seconds
Started Jan 14 12:30:12 PM PST 24
Finished Jan 14 12:30:23 PM PST 24
Peak memory 218056 kb
Host smart-4cd89e82-a6b0-4081-b47d-3e13a8801bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913162414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3913162414
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1604007684
Short name T6
Test name
Test status
Simulation time 161095493 ps
CPU time 2 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:19 PM PST 24
Peak memory 209524 kb
Host smart-5266a9f6-6f2a-4d46-a90b-eba73e3b302b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604007684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.1604007684
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1029498519
Short name T429
Test name
Test status
Simulation time 3737306523 ps
CPU time 42.88 seconds
Started Jan 14 12:30:04 PM PST 24
Finished Jan 14 12:30:49 PM PST 24
Peak memory 219112 kb
Host smart-53e51e2e-342e-44b6-adf8-fa724aa1f834
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029498519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1029498519
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3443945973
Short name T431
Test name
Test status
Simulation time 209315941 ps
CPU time 1.76 seconds
Started Jan 14 12:30:01 PM PST 24
Finished Jan 14 12:30:05 PM PST 24
Peak memory 209580 kb
Host smart-9689ea61-fc74-4b07-9816-4b29cbcb0ab6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443945973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.3443945973
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.595047363
Short name T357
Test name
Test status
Simulation time 95143117 ps
CPU time 2.31 seconds
Started Jan 14 12:30:10 PM PST 24
Finished Jan 14 12:30:14 PM PST 24
Peak memory 218008 kb
Host smart-67c58fb1-6efd-4d63-ac42-ab69c533183d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595047363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.595047363
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1414857770
Short name T81
Test name
Test status
Simulation time 4531123839 ps
CPU time 13.39 seconds
Started Jan 14 12:30:17 PM PST 24
Finished Jan 14 12:30:31 PM PST 24
Peak memory 213572 kb
Host smart-c8b59044-4ddd-49a9-8d6c-ccf627cd6a3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414857770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1414857770
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.184203604
Short name T15
Test name
Test status
Simulation time 2348906232 ps
CPU time 7.89 seconds
Started Jan 14 12:30:11 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 213756 kb
Host smart-380ffbdd-ff4b-4e84-8251-3d3af2f77bfa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184203604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.184203604
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3455866463
Short name T934
Test name
Test status
Simulation time 7617015341 ps
CPU time 45.18 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:52 PM PST 24
Peak memory 277100 kb
Host smart-e209ac7c-0967-4182-8694-765941c3bee9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455866463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3455866463
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2897415484
Short name T187
Test name
Test status
Simulation time 1876750630 ps
CPU time 8.93 seconds
Started Jan 14 12:30:04 PM PST 24
Finished Jan 14 12:30:15 PM PST 24
Peak memory 222792 kb
Host smart-d44fe508-b43d-4d5e-a46f-e8861b053920
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897415484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2897415484
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.445659473
Short name T367
Test name
Test status
Simulation time 61514116 ps
CPU time 2.31 seconds
Started Jan 14 12:30:01 PM PST 24
Finished Jan 14 12:30:06 PM PST 24
Peak memory 218060 kb
Host smart-3d1926b9-4f48-4d37-8863-08d3f75d364e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445659473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.445659473
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.313187610
Short name T690
Test name
Test status
Simulation time 557250251 ps
CPU time 10.97 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:17 PM PST 24
Peak memory 214128 kb
Host smart-bd956c9b-0008-4d53-be45-038ad49f2848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313187610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.313187610
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3592994053
Short name T59
Test name
Test status
Simulation time 533312996 ps
CPU time 36.97 seconds
Started Jan 14 12:30:17 PM PST 24
Finished Jan 14 12:30:55 PM PST 24
Peak memory 268316 kb
Host smart-666b92fd-06ba-4fd4-b922-52297eed1817
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592994053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3592994053
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1726130406
Short name T791
Test name
Test status
Simulation time 736839944 ps
CPU time 17.07 seconds
Started Jan 14 12:30:02 PM PST 24
Finished Jan 14 12:30:21 PM PST 24
Peak memory 219072 kb
Host smart-0b5363ea-1b8a-494e-866c-ea571dac398f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726130406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1726130406
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1254883309
Short name T633
Test name
Test status
Simulation time 265998217 ps
CPU time 11.32 seconds
Started Jan 14 12:30:08 PM PST 24
Finished Jan 14 12:30:21 PM PST 24
Peak memory 218060 kb
Host smart-872310fe-f50a-400c-88fb-dceeb110e388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254883309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1254883309
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1417139992
Short name T980
Test name
Test status
Simulation time 2036868453 ps
CPU time 12.32 seconds
Started Jan 14 12:30:24 PM PST 24
Finished Jan 14 12:30:43 PM PST 24
Peak memory 218092 kb
Host smart-15aec4a0-9f8c-4b73-9aa0-c3684f70dc4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417139992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
417139992
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1016687386
Short name T907
Test name
Test status
Simulation time 4164466148 ps
CPU time 8.2 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:14 PM PST 24
Peak memory 218188 kb
Host smart-5a5e288e-657f-411d-982b-4fe39aa22d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016687386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1016687386
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1073785374
Short name T663
Test name
Test status
Simulation time 23687873 ps
CPU time 1.06 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:11 PM PST 24
Peak memory 213036 kb
Host smart-36f45d13-60f0-4563-8a56-f89b1a3034ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073785374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1073785374
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1792936864
Short name T384
Test name
Test status
Simulation time 639017713 ps
CPU time 27.69 seconds
Started Jan 14 12:30:03 PM PST 24
Finished Jan 14 12:30:33 PM PST 24
Peak memory 251040 kb
Host smart-49306e49-4b23-4ea8-bac8-7b91a1ed7c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792936864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1792936864
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2208399080
Short name T390
Test name
Test status
Simulation time 89916964 ps
CPU time 8.11 seconds
Started Jan 14 12:30:10 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 251052 kb
Host smart-daf33a85-4299-4d6f-aa9c-04801907612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208399080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2208399080
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2130349247
Short name T856
Test name
Test status
Simulation time 4958935121 ps
CPU time 134.44 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:32:24 PM PST 24
Peak memory 251248 kb
Host smart-271d2659-6dbf-44b9-b91a-4207ac4441ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130349247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2130349247
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2824538965
Short name T531
Test name
Test status
Simulation time 24048202 ps
CPU time 0.74 seconds
Started Jan 14 12:30:12 PM PST 24
Finished Jan 14 12:30:14 PM PST 24
Peak memory 208008 kb
Host smart-d37dde36-5183-4fee-b48e-7360d80468a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824538965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2824538965
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.4168460828
Short name T520
Test name
Test status
Simulation time 20333451 ps
CPU time 1.13 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 209572 kb
Host smart-ed71ae65-81e7-4af9-ab8f-f33658608052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168460828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.4168460828
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3174896409
Short name T53
Test name
Test status
Simulation time 181048824 ps
CPU time 7.03 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 218096 kb
Host smart-c83fb880-7a10-4972-8d95-c3b0fb51b627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174896409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3174896409
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2353111637
Short name T27
Test name
Test status
Simulation time 461655285 ps
CPU time 5.79 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 209584 kb
Host smart-0b048930-21c1-4ae9-88b2-a3ac4cd61d49
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353111637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.2353111637
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2861881418
Short name T921
Test name
Test status
Simulation time 554340022 ps
CPU time 5.61 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 218040 kb
Host smart-bab3de30-0d3e-4d88-81b6-9d8915627c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861881418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2861881418
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3945173257
Short name T496
Test name
Test status
Simulation time 959373404 ps
CPU time 10.63 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218032 kb
Host smart-28a851dc-aa45-48b4-b0f0-87c4e79b6dea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945173257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3945173257
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1576697331
Short name T724
Test name
Test status
Simulation time 2749452847 ps
CPU time 16.09 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 217836 kb
Host smart-6a24b0ea-cce4-4a31-b08b-a785c9af0013
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576697331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1576697331
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2893350154
Short name T739
Test name
Test status
Simulation time 1819227996 ps
CPU time 8.39 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 218032 kb
Host smart-f744214b-d9b3-4e52-9bcb-c8c2395bcd88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893350154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2893350154
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.184258007
Short name T151
Test name
Test status
Simulation time 655709158 ps
CPU time 6.51 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 218168 kb
Host smart-ab35bf6c-3f78-45d8-999e-316b68d9955d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184258007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.184258007
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2028063566
Short name T325
Test name
Test status
Simulation time 485905927 ps
CPU time 1.66 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 213260 kb
Host smart-c19c9d00-1179-4701-8600-aefd1a0ca4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028063566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2028063566
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3485028229
Short name T545
Test name
Test status
Simulation time 1048118971 ps
CPU time 32.94 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:34 PM PST 24
Peak memory 251036 kb
Host smart-78e48e93-5ddf-435b-aaa5-2755c6b84beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485028229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3485028229
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1132124676
Short name T519
Test name
Test status
Simulation time 608876244 ps
CPU time 3.35 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 221932 kb
Host smart-97be5591-25be-41dc-b596-c02153e882c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132124676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1132124676
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3309968699
Short name T801
Test name
Test status
Simulation time 87932806590 ps
CPU time 372.17 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:38:07 PM PST 24
Peak memory 250624 kb
Host smart-76545827-9d72-4767-8700-63a98bb2be04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309968699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3309968699
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2136462028
Short name T45
Test name
Test status
Simulation time 17043958 ps
CPU time 0.99 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 212548 kb
Host smart-56ee283c-2c29-47d7-bd19-4d74bf8e0a17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136462028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2136462028
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2178810852
Short name T929
Test name
Test status
Simulation time 38310119 ps
CPU time 1.01 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 208424 kb
Host smart-437b1888-2e54-4495-9dc5-cec0168e6582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178810852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2178810852
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.604407174
Short name T906
Test name
Test status
Simulation time 1418881230 ps
CPU time 12.12 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 218064 kb
Host smart-947ac5c4-dec2-4f8f-b522-c3cce584ff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604407174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.604407174
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.4137175632
Short name T347
Test name
Test status
Simulation time 326550789 ps
CPU time 5.44 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 209656 kb
Host smart-1619b3ee-e408-4019-9621-623e9df3cea6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137175632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.4137175632
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1614713273
Short name T460
Test name
Test status
Simulation time 49171767 ps
CPU time 2.51 seconds
Started Jan 14 12:31:47 PM PST 24
Finished Jan 14 12:31:50 PM PST 24
Peak memory 218104 kb
Host smart-d8a63c52-0899-4baa-a947-61cf255133ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614713273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1614713273
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.688570787
Short name T549
Test name
Test status
Simulation time 448315113 ps
CPU time 12.74 seconds
Started Jan 14 12:31:44 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 218232 kb
Host smart-7d235aad-47e1-4a84-a3e9-4657954ea323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688570787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.688570787
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3468640576
Short name T874
Test name
Test status
Simulation time 297578759 ps
CPU time 8.66 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 217992 kb
Host smart-7b89c76b-7ec1-4820-8ff1-67dc06274ad2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468640576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3468640576
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2511727338
Short name T656
Test name
Test status
Simulation time 2035856541 ps
CPU time 12 seconds
Started Jan 14 12:31:43 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 218044 kb
Host smart-2274b4d6-6a52-49a2-8956-21321efb5cef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511727338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2511727338
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1470467873
Short name T742
Test name
Test status
Simulation time 493856587 ps
CPU time 10.98 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 218040 kb
Host smart-ea16ec86-89d9-4c15-9e38-022680beddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470467873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1470467873
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.330650433
Short name T78
Test name
Test status
Simulation time 63927804 ps
CPU time 3.41 seconds
Started Jan 14 12:31:48 PM PST 24
Finished Jan 14 12:31:52 PM PST 24
Peak memory 214432 kb
Host smart-525ea7e1-5afc-42b4-a446-3c2a512f1f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330650433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.330650433
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1098891444
Short name T428
Test name
Test status
Simulation time 900175579 ps
CPU time 18.44 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:16 PM PST 24
Peak memory 251004 kb
Host smart-6c6728af-325b-41ce-b806-0bb7c300da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098891444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1098891444
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3515003136
Short name T455
Test name
Test status
Simulation time 52367835 ps
CPU time 5.75 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 245936 kb
Host smart-7b50150a-e05e-4206-bf33-d684413667f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515003136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3515003136
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.522425101
Short name T700
Test name
Test status
Simulation time 157763499136 ps
CPU time 310.47 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:37:01 PM PST 24
Peak memory 251100 kb
Host smart-8537db8d-aa38-4855-8876-d1a24965f718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522425101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.522425101
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1931458526
Short name T698
Test name
Test status
Simulation time 38169425 ps
CPU time 1.01 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 211044 kb
Host smart-be875add-a8a4-42bc-8f85-a8f015592743
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931458526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1931458526
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2257907460
Short name T444
Test name
Test status
Simulation time 19241065 ps
CPU time 0.98 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 209556 kb
Host smart-07ab53f7-1f41-412a-b572-5b01e1698442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257907460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2257907460
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3349094650
Short name T899
Test name
Test status
Simulation time 1799166727 ps
CPU time 13.89 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218164 kb
Host smart-96066b60-4feb-4cea-a2c9-bc25bc4cdaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349094650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3349094650
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2245231673
Short name T771
Test name
Test status
Simulation time 422784314 ps
CPU time 5.02 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 209648 kb
Host smart-78299220-b1f9-4a64-9560-5b5639b4237e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245231673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.2245231673
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3136967847
Short name T762
Test name
Test status
Simulation time 103274285 ps
CPU time 2.3 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:52 PM PST 24
Peak memory 218144 kb
Host smart-d7075ccd-2f41-4739-869a-568131539772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136967847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3136967847
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1960938572
Short name T873
Test name
Test status
Simulation time 2369024484 ps
CPU time 11.47 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 217868 kb
Host smart-73b9ba32-f1bc-4d88-9b29-4ad614accd6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960938572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1960938572
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.216725278
Short name T610
Test name
Test status
Simulation time 314188643 ps
CPU time 9.09 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218072 kb
Host smart-d04526c9-5182-4f00-be94-6a746850381b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216725278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.216725278
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.801976302
Short name T891
Test name
Test status
Simulation time 2966046695 ps
CPU time 23.53 seconds
Started Jan 14 12:31:45 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 218080 kb
Host smart-ba25e828-28e7-4007-9004-554f94aa4f66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801976302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.801976302
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4241613657
Short name T752
Test name
Test status
Simulation time 2534909960 ps
CPU time 12.53 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 218220 kb
Host smart-96a149dc-ab83-4197-9334-df1e870e504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241613657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4241613657
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4148816060
Short name T523
Test name
Test status
Simulation time 286580386 ps
CPU time 2.09 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 213848 kb
Host smart-40dafea4-efbe-46ee-a7b2-a65a5c966947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148816060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4148816060
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2766871181
Short name T767
Test name
Test status
Simulation time 539091287 ps
CPU time 23.63 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 251240 kb
Host smart-9ffb23d1-4e14-49c3-9b1d-1c767af8b879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766871181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2766871181
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.680012605
Short name T324
Test name
Test status
Simulation time 291637741 ps
CPU time 4.32 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 218100 kb
Host smart-e7e43323-cd1e-4958-9e9f-898dc7c7091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680012605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.680012605
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1830051332
Short name T688
Test name
Test status
Simulation time 12400835961 ps
CPU time 115.33 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:33:52 PM PST 24
Peak memory 272328 kb
Host smart-f1004fd0-c894-4289-b40d-9a21c4e202a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830051332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1830051332
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4219822362
Short name T969
Test name
Test status
Simulation time 166991261 ps
CPU time 1.02 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:31:58 PM PST 24
Peak memory 212532 kb
Host smart-ef17f322-3ce0-4282-a236-b2d04a768618
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219822362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.4219822362
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.377561555
Short name T430
Test name
Test status
Simulation time 80537306 ps
CPU time 0.91 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 209552 kb
Host smart-c57cd5c5-f416-4c65-a9c5-4e550362dc29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377561555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.377561555
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2060900047
Short name T749
Test name
Test status
Simulation time 1339178464 ps
CPU time 15.42 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 218044 kb
Host smart-1fd62fb6-e06c-4084-ad7b-9d5933bba94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060900047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2060900047
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.250165815
Short name T871
Test name
Test status
Simulation time 72341577 ps
CPU time 2.52 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 209556 kb
Host smart-b9f24615-3e09-4f7a-af19-d518dfbed338
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250165815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_ac
cess.250165815
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.692124216
Short name T737
Test name
Test status
Simulation time 686784234 ps
CPU time 6.81 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 218092 kb
Host smart-24ad3f40-f651-430f-9448-0fdca2fad295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692124216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.692124216
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2701222893
Short name T892
Test name
Test status
Simulation time 298118543 ps
CPU time 11.86 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:21 PM PST 24
Peak memory 218192 kb
Host smart-5e58038d-e928-416b-8221-b00fc4f38d3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701222893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2701222893
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.645828272
Short name T555
Test name
Test status
Simulation time 734241841 ps
CPU time 8.75 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 218148 kb
Host smart-24e2a250-4624-4b94-ab33-ef7ca5eb1ad2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645828272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.645828272
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3497764096
Short name T114
Test name
Test status
Simulation time 1410382412 ps
CPU time 11.89 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 218032 kb
Host smart-a394d8ff-dd5a-440c-8799-ebbaf0ffa4db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497764096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3497764096
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2902621039
Short name T826
Test name
Test status
Simulation time 311951235 ps
CPU time 11.61 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 218124 kb
Host smart-89ff5e92-1006-47b0-ba09-9287bbc31575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902621039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2902621039
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4253177086
Short name T43
Test name
Test status
Simulation time 72463641 ps
CPU time 1.72 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 213620 kb
Host smart-180fae57-a279-41d4-b2e3-da5f4a070878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253177086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4253177086
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2325347592
Short name T741
Test name
Test status
Simulation time 824030769 ps
CPU time 39.15 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:36 PM PST 24
Peak memory 251000 kb
Host smart-50bc8cf3-22c6-41a1-b15c-16be91d30eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325347592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2325347592
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1248181149
Short name T426
Test name
Test status
Simulation time 282790695 ps
CPU time 7.57 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 250652 kb
Host smart-d022ada1-f511-4235-b44c-05d65614f530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248181149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1248181149
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1863476676
Short name T332
Test name
Test status
Simulation time 1013865537 ps
CPU time 26.87 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:36 PM PST 24
Peak memory 251092 kb
Host smart-1c9c2d49-7464-484c-a8e3-3b39506f9396
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863476676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1863476676
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.485782132
Short name T717
Test name
Test status
Simulation time 36954584 ps
CPU time 0.83 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 207812 kb
Host smart-6edecd3c-37b4-4a25-a02c-8a9095fe94de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485782132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.485782132
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1489343833
Short name T487
Test name
Test status
Simulation time 35831480 ps
CPU time 0.77 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:51 PM PST 24
Peak memory 209400 kb
Host smart-15a30216-0c87-47d2-ab2e-2b606d5d6387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489343833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1489343833
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.4179198520
Short name T2
Test name
Test status
Simulation time 342010446 ps
CPU time 13.69 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218068 kb
Host smart-58c7bb40-3565-43f3-a801-bd936de8f0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179198520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.4179198520
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3880248313
Short name T794
Test name
Test status
Simulation time 1272545684 ps
CPU time 10.36 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 209544 kb
Host smart-4a036638-a260-4915-a64d-96ff6d17fde1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880248313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.3880248313
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1695714486
Short name T977
Test name
Test status
Simulation time 119884068 ps
CPU time 2.44 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 218156 kb
Host smart-0ebc18e5-d818-4491-bc0b-4bcf206682ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695714486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1695714486
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.173173912
Short name T557
Test name
Test status
Simulation time 1496323585 ps
CPU time 18.69 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:12 PM PST 24
Peak memory 219156 kb
Host smart-c85b3368-ef0b-4519-9a8a-ec5aef542992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173173912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.173173912
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.138342046
Short name T335
Test name
Test status
Simulation time 550231421 ps
CPU time 11.13 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 217988 kb
Host smart-c101c0cd-f321-4d86-ac6c-685006750936
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138342046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.138342046
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2365289147
Short name T597
Test name
Test status
Simulation time 537652343 ps
CPU time 16.62 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218060 kb
Host smart-ee4a9542-0ac5-41ce-93e4-6639c280f566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365289147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2365289147
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.541833833
Short name T793
Test name
Test status
Simulation time 817255817 ps
CPU time 6.34 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 218092 kb
Host smart-996e8486-2a73-4130-963c-8b3ec52a39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541833833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.541833833
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3093615991
Short name T959
Test name
Test status
Simulation time 46519595 ps
CPU time 1.62 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 213548 kb
Host smart-a0e951db-942a-4e7e-879c-8680cdcb802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093615991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3093615991
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.714416219
Short name T611
Test name
Test status
Simulation time 1295694098 ps
CPU time 29.12 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:25 PM PST 24
Peak memory 250976 kb
Host smart-5ce4e539-a68d-49c4-b8e6-1ffa953d24fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714416219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.714416219
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2877906852
Short name T29
Test name
Test status
Simulation time 127315058 ps
CPU time 6.26 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 246260 kb
Host smart-23523a81-25c8-49c6-8879-6c82cbb7e5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877906852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2877906852
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.141158057
Short name T804
Test name
Test status
Simulation time 10481510712 ps
CPU time 39.68 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:33 PM PST 24
Peak memory 251192 kb
Host smart-2eb80a3a-52f6-4c3a-94ca-23a2d0de5204
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141158057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.141158057
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1479862497
Short name T870
Test name
Test status
Simulation time 15025050 ps
CPU time 0.81 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 208444 kb
Host smart-df9fe744-eec1-45ed-8cc2-a0abf14171d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479862497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1479862497
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.315716896
Short name T400
Test name
Test status
Simulation time 45335475 ps
CPU time 0.81 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 209216 kb
Host smart-2f55c550-664e-4b6f-a3a9-e5d1c77f2531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315716896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.315716896
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1595279427
Short name T630
Test name
Test status
Simulation time 560645787 ps
CPU time 8.65 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 217936 kb
Host smart-bba2df0c-1f43-4cb2-96f4-1e8943d176da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595279427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1595279427
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1889328338
Short name T761
Test name
Test status
Simulation time 381177247 ps
CPU time 10.44 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 209500 kb
Host smart-593b066b-53f8-4f26-a722-9a016e0fff4f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889328338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.1889328338
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1859697498
Short name T341
Test name
Test status
Simulation time 618356223 ps
CPU time 3.17 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:31:56 PM PST 24
Peak memory 218096 kb
Host smart-746f185f-2d92-4a28-a60f-5100b5104b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859697498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1859697498
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.914706865
Short name T561
Test name
Test status
Simulation time 1937616975 ps
CPU time 13.1 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 218744 kb
Host smart-c99169a3-a894-46a1-9cfc-1213a586fc30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914706865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.914706865
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1089711053
Short name T388
Test name
Test status
Simulation time 7569812168 ps
CPU time 18.89 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:12 PM PST 24
Peak memory 218192 kb
Host smart-f27f5e85-02b7-4048-b074-bc7145fce138
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089711053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1089711053
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1204618423
Short name T606
Test name
Test status
Simulation time 780445191 ps
CPU time 8.04 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 218128 kb
Host smart-3bb3970a-dc31-4a15-8378-21433377572f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204618423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1204618423
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.61111494
Short name T730
Test name
Test status
Simulation time 64402552 ps
CPU time 2.67 seconds
Started Jan 14 12:31:46 PM PST 24
Finished Jan 14 12:31:50 PM PST 24
Peak memory 214384 kb
Host smart-a445f05c-bbca-4f2a-b238-4b91d8f6347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61111494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.61111494
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.790483024
Short name T88
Test name
Test status
Simulation time 268900579 ps
CPU time 27.72 seconds
Started Jan 14 12:31:43 PM PST 24
Finished Jan 14 12:32:12 PM PST 24
Peak memory 250992 kb
Host smart-2691ed3a-ce82-4593-9870-019e27500db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790483024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.790483024
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1655475970
Short name T810
Test name
Test status
Simulation time 259825778 ps
CPU time 6.92 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 250464 kb
Host smart-a0c35f4f-b4d9-4205-9d62-b48c4f572d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655475970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1655475970
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.4138821987
Short name T916
Test name
Test status
Simulation time 36375694422 ps
CPU time 269.55 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:36:19 PM PST 24
Peak memory 266748 kb
Host smart-10ec193c-0087-45c8-8038-2bffd0a8781f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138821987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.4138821987
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3863649505
Short name T499
Test name
Test status
Simulation time 13640499 ps
CPU time 0.83 seconds
Started Jan 14 12:31:49 PM PST 24
Finished Jan 14 12:31:51 PM PST 24
Peak memory 208268 kb
Host smart-e82dab52-60f1-4641-94ec-4bfc3adfc161
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863649505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3863649505
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.25557995
Short name T710
Test name
Test status
Simulation time 95356500 ps
CPU time 0.91 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 208268 kb
Host smart-10893854-1cdf-422a-b1a1-9caf4fb1b9c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25557995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.25557995
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2316385432
Short name T575
Test name
Test status
Simulation time 543369130 ps
CPU time 15.8 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 217868 kb
Host smart-10227f3c-c147-497c-9ce5-b50b7d45bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316385432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2316385432
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3559556632
Short name T588
Test name
Test status
Simulation time 1584039933 ps
CPU time 7.77 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 209732 kb
Host smart-51f7bfc1-4e6c-4901-a2cf-4e60d4055d4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559556632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.3559556632
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.676508250
Short name T867
Test name
Test status
Simulation time 60459343 ps
CPU time 2.81 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 218120 kb
Host smart-ebacb144-1cc7-4938-b37e-ec7d454e534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676508250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.676508250
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2566235904
Short name T805
Test name
Test status
Simulation time 402238890 ps
CPU time 13.31 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 219036 kb
Host smart-86bff95b-26d1-4a17-9b0d-b77f781dc868
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566235904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2566235904
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1891916912
Short name T310
Test name
Test status
Simulation time 231207971 ps
CPU time 8.49 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218076 kb
Host smart-bf9fc2fc-1e75-471d-8b06-6b6ce12e9fb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891916912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1891916912
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3239528305
Short name T44
Test name
Test status
Simulation time 378303299 ps
CPU time 8.99 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218176 kb
Host smart-6d99a50e-ccdd-4920-9e4e-109cca10c447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239528305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3239528305
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1667235333
Short name T454
Test name
Test status
Simulation time 2362604910 ps
CPU time 12.75 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 218072 kb
Host smart-a75a57e2-d723-41ad-ad81-c8de28069cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667235333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1667235333
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.932461978
Short name T322
Test name
Test status
Simulation time 22153608 ps
CPU time 1.61 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 213332 kb
Host smart-1f7983f8-9883-47c2-b746-d9d063aeb1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932461978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.932461978
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.402529577
Short name T87
Test name
Test status
Simulation time 165360865 ps
CPU time 17.82 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 251076 kb
Host smart-34d1cb07-fb3d-4024-953a-0ec7448adf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402529577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.402529577
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3235986341
Short name T697
Test name
Test status
Simulation time 366129368 ps
CPU time 6.65 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 250544 kb
Host smart-06e029ae-5b12-4ff7-9446-8d23ae78449a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235986341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3235986341
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2615350346
Short name T559
Test name
Test status
Simulation time 36294771386 ps
CPU time 137.33 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:34:16 PM PST 24
Peak memory 283944 kb
Host smart-6259270f-78d4-4ec8-864b-285f7b4d1608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615350346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2615350346
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.169987486
Short name T918
Test name
Test status
Simulation time 14142250 ps
CPU time 0.77 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 208288 kb
Host smart-74d5b89b-30bb-4efd-87b5-e14ff31a3032
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169987486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.169987486
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.602804508
Short name T968
Test name
Test status
Simulation time 32166474 ps
CPU time 0.96 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 209620 kb
Host smart-87ee502b-1ba5-42c2-8500-f6ac6791f1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602804508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.602804508
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2364723815
Short name T727
Test name
Test status
Simulation time 1412028871 ps
CPU time 16.1 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 218064 kb
Host smart-4f46473a-5207-4167-a5d8-bdf2bfa60b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364723815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2364723815
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3858864818
Short name T843
Test name
Test status
Simulation time 231824085 ps
CPU time 2.44 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 209700 kb
Host smart-8ab53574-39dd-4560-8ea7-ee65d318dd78
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858864818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.3858864818
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3821507335
Short name T415
Test name
Test status
Simulation time 281717102 ps
CPU time 4.42 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:12 PM PST 24
Peak memory 218120 kb
Host smart-7ce6aa0e-0a41-4858-be57-4b7f85a38927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821507335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3821507335
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1469364750
Short name T534
Test name
Test status
Simulation time 264081162 ps
CPU time 8.69 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 218348 kb
Host smart-0e36c996-e036-450f-b986-b787a19437cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469364750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1469364750
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.609871161
Short name T423
Test name
Test status
Simulation time 5983093613 ps
CPU time 20.29 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 218168 kb
Host smart-1b6567ea-cfa4-4384-94c1-c2c44b9bd984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609871161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.609871161
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.804541919
Short name T713
Test name
Test status
Simulation time 328908407 ps
CPU time 11.05 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 218032 kb
Host smart-9bc186c1-b86a-4dee-95fd-435b3475621b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804541919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.804541919
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1838677155
Short name T183
Test name
Test status
Simulation time 1413431455 ps
CPU time 12.04 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:19 PM PST 24
Peak memory 218096 kb
Host smart-955a883e-4f22-4b44-ba49-4c82f246dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838677155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1838677155
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3795202316
Short name T544
Test name
Test status
Simulation time 25642460 ps
CPU time 1.64 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 213312 kb
Host smart-38ca250d-53fd-4411-a031-a4dae790f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795202316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3795202316
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.968931992
Short name T337
Test name
Test status
Simulation time 313826377 ps
CPU time 26.9 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:24 PM PST 24
Peak memory 251048 kb
Host smart-abe254c7-42a2-44b3-a270-907be0b0268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968931992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.968931992
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.31499868
Short name T632
Test name
Test status
Simulation time 187391027 ps
CPU time 3.11 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 226412 kb
Host smart-9e049715-3e1d-416d-957d-924ad4b80226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31499868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.31499868
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3215358966
Short name T497
Test name
Test status
Simulation time 8905702331 ps
CPU time 169.96 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:34:50 PM PST 24
Peak memory 283240 kb
Host smart-55360b40-c62d-466b-872c-5e25366fbf11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215358966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3215358966
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3943130026
Short name T30
Test name
Test status
Simulation time 12896816 ps
CPU time 0.77 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 208032 kb
Host smart-5735fe89-6eb9-424a-981a-c96a38a99987
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943130026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3943130026
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3028023872
Short name T777
Test name
Test status
Simulation time 48776526 ps
CPU time 1.03 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 209552 kb
Host smart-b9414187-8f8f-4073-9204-3071de41d2b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028023872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3028023872
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.217122397
Short name T837
Test name
Test status
Simulation time 428817479 ps
CPU time 15.24 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:25 PM PST 24
Peak memory 217224 kb
Host smart-9155d074-de80-4367-9080-ec1b31c98e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217122397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.217122397
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3814370067
Short name T441
Test name
Test status
Simulation time 800944810 ps
CPU time 5.98 seconds
Started Jan 14 12:31:50 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 209624 kb
Host smart-927f17ab-0551-425d-81c7-27e19dc2aa72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814370067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.3814370067
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.871521468
Short name T722
Test name
Test status
Simulation time 40857577 ps
CPU time 1.97 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 218240 kb
Host smart-53bf35b6-07d2-456d-b10b-d403217c8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871521468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.871521468
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1685782159
Short name T625
Test name
Test status
Simulation time 845432874 ps
CPU time 9.61 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 218100 kb
Host smart-c0bf74c9-c0ca-4c8b-9fee-2bc39e8963f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685782159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1685782159
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1552669599
Short name T532
Test name
Test status
Simulation time 1012607265 ps
CPU time 9.42 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 218052 kb
Host smart-277a0824-291c-4bc1-8ae8-fd4b494a1b1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552669599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1552669599
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.990470404
Short name T925
Test name
Test status
Simulation time 1083537415 ps
CPU time 10.72 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 218096 kb
Host smart-0781ccf8-2bb2-4ad0-bc4b-d0823e64b98b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990470404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.990470404
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3082627390
Short name T674
Test name
Test status
Simulation time 234035360 ps
CPU time 7.54 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 218100 kb
Host smart-19f3fb63-5bea-45bf-b0e4-cf8a5adcb6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082627390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3082627390
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1306995347
Short name T112
Test name
Test status
Simulation time 418306324 ps
CPU time 25.35 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:30 PM PST 24
Peak memory 251016 kb
Host smart-ec4aad1f-f5ba-4351-9705-8b2a8a119530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306995347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1306995347
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2097029077
Short name T643
Test name
Test status
Simulation time 101069289 ps
CPU time 6.56 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:16 PM PST 24
Peak memory 246116 kb
Host smart-e591c228-ca5d-4388-9f29-07c68b9029df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097029077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2097029077
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.4086337863
Short name T76
Test name
Test status
Simulation time 1815593398 ps
CPU time 77.93 seconds
Started Jan 14 12:31:51 PM PST 24
Finished Jan 14 12:33:10 PM PST 24
Peak memory 275992 kb
Host smart-c7ad0cb4-5d23-4b85-a77d-df8719e0e2e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086337863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.4086337863
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1205372927
Short name T872
Test name
Test status
Simulation time 40900228 ps
CPU time 0.79 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:31:53 PM PST 24
Peak memory 208312 kb
Host smart-1027b654-a7f0-48ff-8270-a4ea267f6d5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205372927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1205372927
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2145544001
Short name T616
Test name
Test status
Simulation time 23955894 ps
CPU time 1.25 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 209640 kb
Host smart-38ed7f99-6984-4001-801e-c0bc5e99a1ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145544001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2145544001
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3491331004
Short name T803
Test name
Test status
Simulation time 1476322566 ps
CPU time 12.36 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:22 PM PST 24
Peak memory 218040 kb
Host smart-dcac0c40-b3e7-4a99-bfed-d1690a05b6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491331004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3491331004
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1541206741
Short name T502
Test name
Test status
Simulation time 420134078 ps
CPU time 1.94 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:00 PM PST 24
Peak memory 209548 kb
Host smart-c257c848-8a3a-4f8d-af35-2975e383c671
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541206741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.1541206741
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2283805169
Short name T323
Test name
Test status
Simulation time 48171397 ps
CPU time 2.29 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 218136 kb
Host smart-ef6b8646-10c6-4b21-9b85-04ddaf31297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283805169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2283805169
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1688164480
Short name T451
Test name
Test status
Simulation time 368843874 ps
CPU time 15.44 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:20 PM PST 24
Peak memory 218116 kb
Host smart-aee52ec5-1af5-49f4-b6ea-837ab4d6e754
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688164480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1688164480
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2800848205
Short name T486
Test name
Test status
Simulation time 1575445030 ps
CPU time 10.69 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:16 PM PST 24
Peak memory 217976 kb
Host smart-692f963e-5d23-44db-9817-562d6bbf6eb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800848205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2800848205
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2711871159
Short name T689
Test name
Test status
Simulation time 7386151083 ps
CPU time 11.26 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:21 PM PST 24
Peak memory 217620 kb
Host smart-65abdf6d-6309-49d5-8cec-f16f5aac0633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711871159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2711871159
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1789059309
Short name T756
Test name
Test status
Simulation time 95786668 ps
CPU time 2.66 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 214028 kb
Host smart-32247ac7-4ba7-473e-af63-c6a016dd2bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789059309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1789059309
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.704245530
Short name T572
Test name
Test status
Simulation time 905730889 ps
CPU time 31.62 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:28 PM PST 24
Peak memory 250276 kb
Host smart-9e2ff837-eee0-4e51-9cc7-f9b8a27b3ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704245530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.704245530
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.422728808
Short name T948
Test name
Test status
Simulation time 294709865 ps
CPU time 7.6 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:17 PM PST 24
Peak memory 251024 kb
Host smart-3a79f4b7-c5e2-4a96-be30-08992d09698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422728808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.422728808
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2327526963
Short name T99
Test name
Test status
Simulation time 8139366009 ps
CPU time 271.55 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:36:41 PM PST 24
Peak memory 267380 kb
Host smart-48fd94b4-ff28-4cbe-a4f2-ba2fdecb53d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327526963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2327526963
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1143583364
Short name T33
Test name
Test status
Simulation time 13106448 ps
CPU time 0.92 seconds
Started Jan 14 12:31:52 PM PST 24
Finished Jan 14 12:31:54 PM PST 24
Peak memory 208556 kb
Host smart-615aa9aa-6a57-428a-bc54-c61c2f698d85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143583364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1143583364
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2425118039
Short name T726
Test name
Test status
Simulation time 23008371 ps
CPU time 0.94 seconds
Started Jan 14 12:30:10 PM PST 24
Finished Jan 14 12:30:13 PM PST 24
Peak memory 208384 kb
Host smart-40f1b951-2182-43c0-884e-9a9b5918d065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425118039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2425118039
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1708397283
Short name T366
Test name
Test status
Simulation time 1186783286 ps
CPU time 14 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:30:29 PM PST 24
Peak memory 218044 kb
Host smart-501fcc50-b2e3-43a6-831a-2606d4f0615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708397283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1708397283
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.462028234
Short name T947
Test name
Test status
Simulation time 2515473921 ps
CPU time 4.99 seconds
Started Jan 14 12:30:12 PM PST 24
Finished Jan 14 12:30:19 PM PST 24
Peak memory 209684 kb
Host smart-f438c572-5384-457f-b515-5673f98aaa5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462028234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_acc
ess.462028234
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1368290948
Short name T458
Test name
Test status
Simulation time 1247989690 ps
CPU time 18.16 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:28 PM PST 24
Peak memory 218180 kb
Host smart-2b648ec3-7a99-4fff-b31b-dcaad40bee85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368290948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1368290948
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3256281363
Short name T876
Test name
Test status
Simulation time 3506045371 ps
CPU time 11.19 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:18 PM PST 24
Peak memory 217944 kb
Host smart-34341938-fe5f-44fb-b88a-0c1fc9b5cd52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256281363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.3256281363
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3624652419
Short name T540
Test name
Test status
Simulation time 282204005 ps
CPU time 1.98 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:30:17 PM PST 24
Peak memory 217980 kb
Host smart-4c8afebd-a643-4e32-9775-abd687efc074
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624652419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3624652419
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.46756140
Short name T192
Test name
Test status
Simulation time 1872301761 ps
CPU time 27.27 seconds
Started Jan 14 12:30:15 PM PST 24
Finished Jan 14 12:30:44 PM PST 24
Peak memory 213072 kb
Host smart-115f74cd-ebd1-4507-b379-993a2bcbdf40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46756140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt
ag_regwen_during_op.46756140
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3526927641
Short name T348
Test name
Test status
Simulation time 295852086 ps
CPU time 4.34 seconds
Started Jan 14 12:30:10 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 213324 kb
Host smart-803d3534-2768-47e4-92f8-3427df19c1d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526927641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3526927641
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3651244213
Short name T952
Test name
Test status
Simulation time 3297940797 ps
CPU time 52.39 seconds
Started Jan 14 12:30:23 PM PST 24
Finished Jan 14 12:31:21 PM PST 24
Peak memory 252756 kb
Host smart-e4c18546-7d0f-4e6a-9c94-09544c08ee4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651244213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3651244213
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3087972637
Short name T478
Test name
Test status
Simulation time 1681126261 ps
CPU time 12.55 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:32 PM PST 24
Peak memory 251092 kb
Host smart-bb071b9b-fdee-4bb3-b0e0-321b6cb29e50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087972637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3087972637
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2023885975
Short name T476
Test name
Test status
Simulation time 727097148 ps
CPU time 13.48 seconds
Started Jan 14 12:30:13 PM PST 24
Finished Jan 14 12:30:28 PM PST 24
Peak memory 214288 kb
Host smart-20801ae7-c743-44ff-8219-96b91f2d1ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023885975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2023885975
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.262077956
Short name T58
Test name
Test status
Simulation time 354615285 ps
CPU time 34.46 seconds
Started Jan 14 12:30:20 PM PST 24
Finished Jan 14 12:30:56 PM PST 24
Peak memory 269164 kb
Host smart-989ab8c6-36c2-47c5-88d1-f4603e00acb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262077956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.262077956
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.991435979
Short name T789
Test name
Test status
Simulation time 768374679 ps
CPU time 12.14 seconds
Started Jan 14 12:30:21 PM PST 24
Finished Jan 14 12:30:35 PM PST 24
Peak memory 218120 kb
Host smart-3ea8512c-c54c-4020-b7ad-228eb494ff43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991435979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.991435979
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.42786008
Short name T528
Test name
Test status
Simulation time 254898970 ps
CPU time 8.51 seconds
Started Jan 14 12:30:13 PM PST 24
Finished Jan 14 12:30:23 PM PST 24
Peak memory 217992 kb
Host smart-3aeef07f-f7a4-47c5-bbdc-ce4b1783cc1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42786008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dige
st.42786008
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3451825763
Short name T435
Test name
Test status
Simulation time 1460631381 ps
CPU time 9.74 seconds
Started Jan 14 12:30:13 PM PST 24
Finished Jan 14 12:30:24 PM PST 24
Peak memory 217964 kb
Host smart-a0605d50-517a-48c9-8424-63612ffa1282
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451825763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
451825763
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3916197763
Short name T895
Test name
Test status
Simulation time 1146405109 ps
CPU time 13.62 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:30:29 PM PST 24
Peak memory 218072 kb
Host smart-814bc320-5c20-4520-90ea-6e268e88af41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916197763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3916197763
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1602766333
Short name T64
Test name
Test status
Simulation time 209229405 ps
CPU time 4.09 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:30:19 PM PST 24
Peak memory 213936 kb
Host smart-34881be6-54e2-4aa5-8953-f9556596cd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602766333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1602766333
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2810058033
Short name T509
Test name
Test status
Simulation time 545281693 ps
CPU time 22.9 seconds
Started Jan 14 12:30:12 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 251036 kb
Host smart-4dfcbb1a-a369-410d-beba-f09c059c8d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810058033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2810058033
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.4114091502
Short name T902
Test name
Test status
Simulation time 380194192 ps
CPU time 7.89 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 250512 kb
Host smart-a68ad8da-aa64-4e55-8ac3-ce7140e8383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114091502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.4114091502
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3505009918
Short name T513
Test name
Test status
Simulation time 2670834064 ps
CPU time 79.39 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:31:29 PM PST 24
Peak memory 276004 kb
Host smart-d0a27ac6-efb8-4e43-a493-8a7fc1d11d0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505009918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3505009918
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.4240309012
Short name T768
Test name
Test status
Simulation time 127253322435 ps
CPU time 1014.77 seconds
Started Jan 14 12:30:03 PM PST 24
Finished Jan 14 12:47:00 PM PST 24
Peak memory 274080 kb
Host smart-e1a02261-05c5-4d31-9328-ea82b249b255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4240309012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.4240309012
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2690965828
Short name T564
Test name
Test status
Simulation time 47960140 ps
CPU time 0.85 seconds
Started Jan 14 12:30:11 PM PST 24
Finished Jan 14 12:30:14 PM PST 24
Peak memory 211428 kb
Host smart-e1bb848c-2d42-4c7f-95ee-19d22d9baba1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690965828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2690965828
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3675552416
Short name T556
Test name
Test status
Simulation time 20946752 ps
CPU time 1.2 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 208212 kb
Host smart-881dd46d-d39a-4dab-bd09-0dc92d6bc750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675552416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3675552416
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2888772460
Short name T389
Test name
Test status
Simulation time 2355756637 ps
CPU time 13.95 seconds
Started Jan 14 12:32:00 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 218164 kb
Host smart-4a8af5a2-ee93-470e-85f7-8cbc5ef455c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888772460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2888772460
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.4213724278
Short name T845
Test name
Test status
Simulation time 72606734 ps
CPU time 1.61 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 209560 kb
Host smart-645ad4ff-feb4-470f-bb84-7527d9c2cf44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213724278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.4213724278
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.312026804
Short name T676
Test name
Test status
Simulation time 74128738 ps
CPU time 2.41 seconds
Started Jan 14 12:31:59 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 218140 kb
Host smart-145f3753-8a1d-4b3d-a39e-c89fd96d9aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312026804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.312026804
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1010587972
Short name T604
Test name
Test status
Simulation time 1510649188 ps
CPU time 14.49 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 218568 kb
Host smart-c09cb600-f81f-43ce-a701-42842612b090
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010587972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1010587972
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1825170265
Short name T374
Test name
Test status
Simulation time 899122876 ps
CPU time 13.07 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:12 PM PST 24
Peak memory 218068 kb
Host smart-d3e5b9e8-2c30-479e-88c6-8d1921729695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825170265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1825170265
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2086838162
Short name T577
Test name
Test status
Simulation time 309152854 ps
CPU time 10.8 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 218068 kb
Host smart-b3f7bdb0-168a-405b-9608-3ea8dcc7c565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086838162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2086838162
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2531204593
Short name T184
Test name
Test status
Simulation time 450727564 ps
CPU time 8.43 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 217936 kb
Host smart-78acf0e1-2527-4bdc-90f4-a32d28fb73ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531204593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2531204593
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3510943850
Short name T74
Test name
Test status
Simulation time 33699579 ps
CPU time 2.43 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 213992 kb
Host smart-47bac4b0-fab8-40bc-958c-64a118c4e5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510943850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3510943850
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3262587943
Short name T501
Test name
Test status
Simulation time 964892981 ps
CPU time 32.93 seconds
Started Jan 14 12:31:56 PM PST 24
Finished Jan 14 12:32:31 PM PST 24
Peak memory 250944 kb
Host smart-add790c3-de27-43ee-8a74-66f984791149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262587943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3262587943
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2316794512
Short name T379
Test name
Test status
Simulation time 160907038 ps
CPU time 5.91 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 249828 kb
Host smart-d5a77243-c3b8-4454-913d-fe9cdce54536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316794512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2316794512
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2208636084
Short name T945
Test name
Test status
Simulation time 11340687347 ps
CPU time 187.34 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:35:17 PM PST 24
Peak memory 316100 kb
Host smart-b899d1e6-b156-492d-88e4-eea899a588ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208636084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2208636084
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.4009983518
Short name T117
Test name
Test status
Simulation time 13356980321 ps
CPU time 420.62 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:39:06 PM PST 24
Peak memory 528868 kb
Host smart-169805f3-7851-4f46-a1f5-7a70f6c40fa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4009983518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.4009983518
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1100270674
Short name T949
Test name
Test status
Simulation time 18732561 ps
CPU time 0.72 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:02 PM PST 24
Peak memory 207864 kb
Host smart-286284f5-e20d-4a57-818c-8317733950b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100270674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1100270674
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3185894963
Short name T100
Test name
Test status
Simulation time 29191874 ps
CPU time 1.06 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 208440 kb
Host smart-2d107b85-0965-49cd-b3aa-10d737828c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185894963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3185894963
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3495082996
Short name T416
Test name
Test status
Simulation time 238340507 ps
CPU time 10.68 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:20 PM PST 24
Peak memory 218080 kb
Host smart-40b77ed1-9d66-4910-b087-9571790d4c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495082996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3495082996
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2304239923
Short name T781
Test name
Test status
Simulation time 1180610660 ps
CPU time 6.77 seconds
Started Jan 14 12:32:03 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 209548 kb
Host smart-69aaa3b5-b236-4469-8e26-ee8b5190ced5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304239923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.2304239923
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4010158720
Short name T944
Test name
Test status
Simulation time 529395332 ps
CPU time 4.76 seconds
Started Jan 14 12:32:03 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 218120 kb
Host smart-9386ecb2-a444-42f7-8232-59b10e44355e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010158720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4010158720
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1371884081
Short name T853
Test name
Test status
Simulation time 762937515 ps
CPU time 9.47 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:12 PM PST 24
Peak memory 219136 kb
Host smart-7ccd5fa1-e11c-450d-bce4-9039ff77b9b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371884081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1371884081
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.4257142682
Short name T783
Test name
Test status
Simulation time 2032493409 ps
CPU time 8.84 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 218052 kb
Host smart-7f3d4212-b53b-4f57-9a38-989ca8e76f50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257142682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.4257142682
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4208970606
Short name T900
Test name
Test status
Simulation time 231632301 ps
CPU time 9.06 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:15 PM PST 24
Peak memory 218104 kb
Host smart-312ed49b-5d6e-4db8-8033-fc638870c040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208970606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4208970606
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2443803278
Short name T387
Test name
Test status
Simulation time 283543339 ps
CPU time 10.74 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 218124 kb
Host smart-7a97f1a5-b5f4-451b-b04c-7999ea0f5a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443803278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2443803278
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1811204707
Short name T932
Test name
Test status
Simulation time 47742154 ps
CPU time 2.13 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:31:59 PM PST 24
Peak memory 213492 kb
Host smart-ba24b39f-5324-4f28-a229-ca6b70c3a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811204707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1811204707
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2575242694
Short name T972
Test name
Test status
Simulation time 862477502 ps
CPU time 30.81 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:41 PM PST 24
Peak memory 250336 kb
Host smart-593793df-59d8-4d04-9178-a1fbd4163345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575242694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2575242694
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3952772620
Short name T567
Test name
Test status
Simulation time 70191478 ps
CPU time 7.71 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 251112 kb
Host smart-b8fd8ff2-2002-492b-af27-44433f3cf9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952772620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3952772620
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.937891593
Short name T375
Test name
Test status
Simulation time 1789662886 ps
CPU time 77.64 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:33:14 PM PST 24
Peak memory 267524 kb
Host smart-d327e56f-1dc1-4b40-8bc6-b8ecc9c0abff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937891593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.937891593
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1314623579
Short name T383
Test name
Test status
Simulation time 24663960 ps
CPU time 0.85 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 207836 kb
Host smart-42615188-eae6-43cb-8533-dad57ce2d4e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314623579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1314623579
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2983429177
Short name T886
Test name
Test status
Simulation time 44387837 ps
CPU time 0.86 seconds
Started Jan 14 12:32:10 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 209560 kb
Host smart-65cc72bb-215a-4cee-8523-b7978fedc657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983429177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2983429177
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2032230484
Short name T858
Test name
Test status
Simulation time 280155418 ps
CPU time 8.78 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:16 PM PST 24
Peak memory 218168 kb
Host smart-9319bb80-1093-4757-881f-da4aa11521ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032230484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2032230484
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1819209036
Short name T402
Test name
Test status
Simulation time 1400113256 ps
CPU time 4.84 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 209548 kb
Host smart-1e0cd85b-ff42-4f57-9b56-01f4f6c6c6bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819209036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.1819209036
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.4004751795
Short name T955
Test name
Test status
Simulation time 168783441 ps
CPU time 3.93 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 218252 kb
Host smart-b902779b-6aca-4503-9ecc-52c42d62f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004751795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.4004751795
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2496999947
Short name T939
Test name
Test status
Simulation time 973205900 ps
CPU time 12.86 seconds
Started Jan 14 12:32:22 PM PST 24
Finished Jan 14 12:32:37 PM PST 24
Peak memory 219168 kb
Host smart-9169cf62-672b-48f5-821c-9ce2c7f35455
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496999947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2496999947
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1686830840
Short name T764
Test name
Test status
Simulation time 2958741925 ps
CPU time 11.7 seconds
Started Jan 14 12:32:11 PM PST 24
Finished Jan 14 12:32:29 PM PST 24
Peak memory 217312 kb
Host smart-b4669e08-40a3-447c-b8e3-f1feb95edb4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686830840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1686830840
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3667075878
Short name T493
Test name
Test status
Simulation time 565606178 ps
CPU time 11.51 seconds
Started Jan 14 12:32:11 PM PST 24
Finished Jan 14 12:32:28 PM PST 24
Peak memory 217632 kb
Host smart-9e0f782f-1b1e-421a-8f9e-a14d90e2f162
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667075878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3667075878
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3026355562
Short name T515
Test name
Test status
Simulation time 636786166 ps
CPU time 7.65 seconds
Started Jan 14 12:32:10 PM PST 24
Finished Jan 14 12:32:25 PM PST 24
Peak memory 218132 kb
Host smart-6ca19134-914c-4457-9e38-a9944be60c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026355562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3026355562
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1489521420
Short name T65
Test name
Test status
Simulation time 34248518 ps
CPU time 2.46 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:31:57 PM PST 24
Peak memory 214048 kb
Host smart-a2809bcd-c575-47db-8a57-150373f5b4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489521420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1489521420
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3557951565
Short name T13
Test name
Test status
Simulation time 477485547 ps
CPU time 25.91 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:25 PM PST 24
Peak memory 251040 kb
Host smart-7162f951-8747-4739-875e-c1a942fefefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557951565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3557951565
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1349571558
Short name T434
Test name
Test status
Simulation time 338682618 ps
CPU time 6.32 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 245852 kb
Host smart-d359e664-c68c-46af-bcf9-b0354b1e2ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349571558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1349571558
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3758922422
Short name T574
Test name
Test status
Simulation time 36417750 ps
CPU time 0.98 seconds
Started Jan 14 12:31:53 PM PST 24
Finished Jan 14 12:31:55 PM PST 24
Peak memory 211360 kb
Host smart-2070e44b-aa2e-4c7b-9e7e-a860f62e6344
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758922422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3758922422
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3713560667
Short name T595
Test name
Test status
Simulation time 18928975 ps
CPU time 1.12 seconds
Started Jan 14 12:32:14 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 209632 kb
Host smart-b43cffef-a91d-4104-98b8-d7f0fd931765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713560667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3713560667
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.275299480
Short name T445
Test name
Test status
Simulation time 311643363 ps
CPU time 8.66 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:17 PM PST 24
Peak memory 218152 kb
Host smart-d70cee0d-72e5-44dd-bed6-a6171e37ae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275299480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.275299480
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1118418379
Short name T492
Test name
Test status
Simulation time 690225612 ps
CPU time 16.34 seconds
Started Jan 14 12:32:23 PM PST 24
Finished Jan 14 12:32:42 PM PST 24
Peak memory 209624 kb
Host smart-239dcfd8-80b2-4bc8-8e6e-03b29a2f0480
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118418379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.1118418379
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2065986442
Short name T314
Test name
Test status
Simulation time 82870571 ps
CPU time 2.96 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 218244 kb
Host smart-cab6ae05-068f-44a4-949f-f9c1c629f043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065986442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2065986442
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2662477697
Short name T465
Test name
Test status
Simulation time 755776036 ps
CPU time 10.87 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 219168 kb
Host smart-1e8ff832-739c-4563-bb72-f104ebc60572
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662477697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2662477697
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2451336799
Short name T732
Test name
Test status
Simulation time 608605212 ps
CPU time 15.83 seconds
Started Jan 14 12:32:15 PM PST 24
Finished Jan 14 12:32:33 PM PST 24
Peak memory 217952 kb
Host smart-bd6ade51-8dce-4be9-ad4a-72d8ea8cb00a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451336799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2451336799
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1550474576
Short name T901
Test name
Test status
Simulation time 4268056318 ps
CPU time 15.05 seconds
Started Jan 14 12:32:12 PM PST 24
Finished Jan 14 12:32:38 PM PST 24
Peak memory 218140 kb
Host smart-9f007765-d843-47d9-987a-a4f8aed48728
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550474576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1550474576
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.319248327
Short name T709
Test name
Test status
Simulation time 1260623337 ps
CPU time 11.89 seconds
Started Jan 14 12:32:15 PM PST 24
Finished Jan 14 12:32:29 PM PST 24
Peak memory 217752 kb
Host smart-41453580-55da-4dc2-be23-d28b868b9500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319248327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.319248327
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1289356105
Short name T405
Test name
Test status
Simulation time 88609072 ps
CPU time 1.58 seconds
Started Jan 14 12:32:15 PM PST 24
Finished Jan 14 12:32:19 PM PST 24
Peak memory 213368 kb
Host smart-8a767dbf-843e-44f3-b16a-5a6ddace9cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289356105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1289356105
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4049771495
Short name T321
Test name
Test status
Simulation time 332471638 ps
CPU time 31.3 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:32:27 PM PST 24
Peak memory 251184 kb
Host smart-64eb84c1-6201-4032-b2f5-60988a4582a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049771495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4049771495
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3885724167
Short name T28
Test name
Test status
Simulation time 245258710 ps
CPU time 7.65 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:04 PM PST 24
Peak memory 251028 kb
Host smart-8307500b-f0e8-4c4c-a4af-7aa0e0e14d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885724167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3885724167
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.183285461
Short name T358
Test name
Test status
Simulation time 2630767417 ps
CPU time 78.36 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:33:25 PM PST 24
Peak memory 251268 kb
Host smart-8aca0aed-9e90-4e9c-8e59-01a590a1af14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183285461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.183285461
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1979770649
Short name T599
Test name
Test status
Simulation time 14165242 ps
CPU time 0.85 seconds
Started Jan 14 12:32:15 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 207976 kb
Host smart-1f9ba9fc-ec80-47e6-b8e5-66227ca1b946
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979770649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1979770649
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2447233147
Short name T306
Test name
Test status
Simulation time 71114734 ps
CPU time 0.97 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 209572 kb
Host smart-7d8071dc-677e-40f4-b3c0-8ebf13a5dd31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447233147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2447233147
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.29884593
Short name T773
Test name
Test status
Simulation time 335806446 ps
CPU time 8.69 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 218212 kb
Host smart-91808f51-b60d-4f70-9137-e48b6005b29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29884593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.29884593
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.4232647309
Short name T728
Test name
Test status
Simulation time 206567095 ps
CPU time 2.71 seconds
Started Jan 14 12:32:13 PM PST 24
Finished Jan 14 12:32:20 PM PST 24
Peak memory 218080 kb
Host smart-9fde4655-8173-421a-bdad-7b52d3d0d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232647309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4232647309
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.120485524
Short name T594
Test name
Test status
Simulation time 404839457 ps
CPU time 9.32 seconds
Started Jan 14 12:32:13 PM PST 24
Finished Jan 14 12:32:26 PM PST 24
Peak memory 218104 kb
Host smart-1a962eab-7b89-4ba2-a2bb-c6fea2133997
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120485524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.120485524
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2558849783
Short name T365
Test name
Test status
Simulation time 1481774674 ps
CPU time 9.16 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 218100 kb
Host smart-3a0672f2-688b-4000-8c6a-c2d4e80c825a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558849783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2558849783
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1811140059
Short name T650
Test name
Test status
Simulation time 396625390 ps
CPU time 9.84 seconds
Started Jan 14 12:31:55 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 218032 kb
Host smart-2e6ec4a3-f157-4d1d-a67c-bd51f0ebfd8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811140059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1811140059
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2538553083
Short name T576
Test name
Test status
Simulation time 248726311 ps
CPU time 6.77 seconds
Started Jan 14 12:32:12 PM PST 24
Finished Jan 14 12:32:24 PM PST 24
Peak memory 218104 kb
Host smart-1cc8d901-cfd5-438e-9d9b-28536a9946ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538553083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2538553083
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1115937406
Short name T637
Test name
Test status
Simulation time 45702504 ps
CPU time 1.79 seconds
Started Jan 14 12:32:03 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 213236 kb
Host smart-ab69be4f-b47d-4d4d-8a97-b57b90d1bb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115937406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1115937406
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3576865224
Short name T543
Test name
Test status
Simulation time 268024929 ps
CPU time 29.49 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:34 PM PST 24
Peak memory 251144 kb
Host smart-14230611-a919-4c81-8d5d-02842147a29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576865224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3576865224
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.765496188
Short name T957
Test name
Test status
Simulation time 53564227 ps
CPU time 7.16 seconds
Started Jan 14 12:32:14 PM PST 24
Finished Jan 14 12:32:24 PM PST 24
Peak memory 251128 kb
Host smart-f39c8818-1893-418b-8dbe-34d770125f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765496188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.765496188
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2900369465
Short name T79
Test name
Test status
Simulation time 639640395 ps
CPU time 10.53 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:20 PM PST 24
Peak memory 226176 kb
Host smart-e48d132b-9cc6-4d98-8ad3-85a9b5afb54a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900369465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2900369465
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3652052246
Short name T54
Test name
Test status
Simulation time 117742938392 ps
CPU time 1193.04 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:51:57 PM PST 24
Peak memory 546200 kb
Host smart-2143b44e-f1ff-4404-950e-c3026f63499c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3652052246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3652052246
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2228828656
Short name T371
Test name
Test status
Simulation time 12983669 ps
CPU time 0.98 seconds
Started Jan 14 12:32:11 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 211484 kb
Host smart-46ced2d4-3bea-4364-a7ec-072bf386dfe4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228828656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2228828656
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1751204248
Short name T517
Test name
Test status
Simulation time 49439377 ps
CPU time 1.23 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 209592 kb
Host smart-6dcc14f7-2d17-42ba-a33d-d6e8b152895d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751204248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1751204248
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3111155246
Short name T490
Test name
Test status
Simulation time 997659267 ps
CPU time 16.38 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:26 PM PST 24
Peak memory 218072 kb
Host smart-f151776d-0e0a-4dce-8a00-ed52f4fcf4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111155246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3111155246
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2720236619
Short name T920
Test name
Test status
Simulation time 55730130 ps
CPU time 1.09 seconds
Started Jan 14 12:32:03 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 209588 kb
Host smart-2dd00cda-8c54-4249-9634-cd91f6fbb619
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720236619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.2720236619
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.4008595963
Short name T772
Test name
Test status
Simulation time 181638869 ps
CPU time 2.84 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218104 kb
Host smart-9a6c073c-67e8-4c8a-869c-f491482f0b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008595963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.4008595963
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2433510264
Short name T49
Test name
Test status
Simulation time 467453401 ps
CPU time 19.15 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:26 PM PST 24
Peak memory 218240 kb
Host smart-2c88e0fd-ce98-4cc4-8ddb-6e40c7a6b756
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433510264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2433510264
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1370794952
Short name T973
Test name
Test status
Simulation time 279704025 ps
CPU time 11.86 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 218100 kb
Host smart-c975d7be-5c50-4fc6-a6d4-4a42fb1e5231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370794952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1370794952
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2312643176
Short name T936
Test name
Test status
Simulation time 170164930 ps
CPU time 7.27 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 218012 kb
Host smart-5e24cf0f-2239-40b7-a23b-59e46642aae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312643176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2312643176
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.783044764
Short name T655
Test name
Test status
Simulation time 1019578617 ps
CPU time 9.97 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 218116 kb
Host smart-0d557f58-51a0-4a48-8a82-adb21b0b1363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783044764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.783044764
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1339259198
Short name T878
Test name
Test status
Simulation time 95201863 ps
CPU time 6.41 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:16 PM PST 24
Peak memory 214288 kb
Host smart-aea41bfa-9b75-4480-9716-f52dfebdd374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339259198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1339259198
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2796923865
Short name T494
Test name
Test status
Simulation time 540782954 ps
CPU time 26.88 seconds
Started Jan 14 12:32:01 PM PST 24
Finished Jan 14 12:32:29 PM PST 24
Peak memory 251008 kb
Host smart-31fad2bc-85fd-4d66-88ca-2a57cf41c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796923865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2796923865
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2185740574
Short name T537
Test name
Test status
Simulation time 492811997 ps
CPU time 8 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:17 PM PST 24
Peak memory 251060 kb
Host smart-3b1a6cf9-6e70-4ec0-b2f8-7080f909ae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185740574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2185740574
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1149852910
Short name T608
Test name
Test status
Simulation time 13882059574 ps
CPU time 142.93 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:34:30 PM PST 24
Peak memory 283268 kb
Host smart-3cbc7581-ce5a-472b-b298-be309de7d83f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149852910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1149852910
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1997508282
Short name T409
Test name
Test status
Simulation time 73627933 ps
CPU time 0.8 seconds
Started Jan 14 12:32:03 PM PST 24
Finished Jan 14 12:32:05 PM PST 24
Peak memory 208332 kb
Host smart-138d282a-053b-41b3-a22d-a5e4e3bd8cdc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997508282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1997508282
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2829424865
Short name T311
Test name
Test status
Simulation time 32347808 ps
CPU time 1.14 seconds
Started Jan 14 12:32:15 PM PST 24
Finished Jan 14 12:32:19 PM PST 24
Peak memory 208372 kb
Host smart-8376c3e0-eaba-4ce1-adeb-cc2d229a10c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829424865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2829424865
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.409626093
Short name T47
Test name
Test status
Simulation time 270675582 ps
CPU time 11.91 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218168 kb
Host smart-4a74b985-fd50-435b-9cee-b64b44eefbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409626093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.409626093
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.582346319
Short name T404
Test name
Test status
Simulation time 671955047 ps
CPU time 16.26 seconds
Started Jan 14 12:32:10 PM PST 24
Finished Jan 14 12:32:33 PM PST 24
Peak memory 209532 kb
Host smart-c2df406b-283a-4abc-804c-6362f6fa4276
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582346319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_ac
cess.582346319
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2017209533
Short name T535
Test name
Test status
Simulation time 24370731 ps
CPU time 1.79 seconds
Started Jan 14 12:32:10 PM PST 24
Finished Jan 14 12:32:19 PM PST 24
Peak memory 218252 kb
Host smart-32c9ea49-6a69-4967-94f4-0f65a822db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017209533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2017209533
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3185267882
Short name T343
Test name
Test status
Simulation time 577185379 ps
CPU time 14.51 seconds
Started Jan 14 12:32:15 PM PST 24
Finished Jan 14 12:32:32 PM PST 24
Peak memory 218428 kb
Host smart-80ffaae9-7757-48c9-b53f-6326305859d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185267882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3185267882
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.4003768451
Short name T617
Test name
Test status
Simulation time 599152851 ps
CPU time 12.74 seconds
Started Jan 14 12:31:54 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218012 kb
Host smart-eb4f675c-1737-4530-9d2c-f3bb9f2bcca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003768451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.4003768451
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.570559625
Short name T41
Test name
Test status
Simulation time 1383721978 ps
CPU time 13.79 seconds
Started Jan 14 12:32:22 PM PST 24
Finished Jan 14 12:32:38 PM PST 24
Peak memory 218088 kb
Host smart-c664d2ef-e969-4205-bdd6-f17931e10cb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570559625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.570559625
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1470440583
Short name T181
Test name
Test status
Simulation time 823730985 ps
CPU time 14.31 seconds
Started Jan 14 12:32:11 PM PST 24
Finished Jan 14 12:32:31 PM PST 24
Peak memory 217836 kb
Host smart-843efe4b-de81-4513-90f2-361fd217a798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470440583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1470440583
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3441959932
Short name T850
Test name
Test status
Simulation time 242201159 ps
CPU time 2.42 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 214000 kb
Host smart-92075b91-db80-43a3-8eb9-1ed8cca7919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441959932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3441959932
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1952955442
Short name T683
Test name
Test status
Simulation time 436920997 ps
CPU time 26.55 seconds
Started Jan 14 12:32:03 PM PST 24
Finished Jan 14 12:32:31 PM PST 24
Peak memory 251008 kb
Host smart-198b10bc-fb04-4839-b513-29293a8f1056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952955442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1952955442
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4276442792
Short name T848
Test name
Test status
Simulation time 414936685 ps
CPU time 6.28 seconds
Started Jan 14 12:32:10 PM PST 24
Finished Jan 14 12:32:23 PM PST 24
Peak memory 248052 kb
Host smart-2405db25-b299-4b5b-a292-3c019854189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276442792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4276442792
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2690747448
Short name T668
Test name
Test status
Simulation time 87031847 ps
CPU time 0.77 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 208108 kb
Host smart-0c1e28fc-bd5c-458e-9bd6-a3951bf18f1c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690747448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2690747448
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3470179595
Short name T818
Test name
Test status
Simulation time 36386447 ps
CPU time 1.08 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:11 PM PST 24
Peak memory 209708 kb
Host smart-c0718b84-05fb-41e6-93ee-b4dc1ff91228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470179595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3470179595
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.781372625
Short name T359
Test name
Test status
Simulation time 128994938 ps
CPU time 3.71 seconds
Started Jan 14 12:31:57 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 209512 kb
Host smart-b1888f2e-1426-432b-90d6-e47bc83c4be0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781372625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_ac
cess.781372625
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2953005936
Short name T329
Test name
Test status
Simulation time 33212101 ps
CPU time 1.9 seconds
Started Jan 14 12:32:08 PM PST 24
Finished Jan 14 12:32:12 PM PST 24
Peak memory 218208 kb
Host smart-47d058d6-6442-43f7-b31a-99767ddea652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953005936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2953005936
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.4203010239
Short name T877
Test name
Test status
Simulation time 638345571 ps
CPU time 18.01 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:27 PM PST 24
Peak memory 219020 kb
Host smart-cb668b10-701c-4879-a36c-7c09a1e479c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203010239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.4203010239
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1095119901
Short name T933
Test name
Test status
Simulation time 998026973 ps
CPU time 7.98 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 218080 kb
Host smart-478b82c6-bf4f-47bb-b1bc-37167e457a51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095119901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1095119901
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2417691367
Short name T443
Test name
Test status
Simulation time 999863133 ps
CPU time 10.27 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:19 PM PST 24
Peak memory 218144 kb
Host smart-65c67c56-d6ff-4dd5-94ba-7d5bbf1d15a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417691367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2417691367
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3784730661
Short name T970
Test name
Test status
Simulation time 1262935093 ps
CPU time 7.96 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:14 PM PST 24
Peak memory 218196 kb
Host smart-bbfd8b57-d819-45bf-8402-f3593ccc63dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784730661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3784730661
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3735984621
Short name T71
Test name
Test status
Simulation time 256816506 ps
CPU time 2.63 seconds
Started Jan 14 12:32:21 PM PST 24
Finished Jan 14 12:32:27 PM PST 24
Peak memory 214180 kb
Host smart-3f95f86d-4b39-4d1e-bd1f-f6604f3bb6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735984621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3735984621
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3265848266
Short name T831
Test name
Test status
Simulation time 212083278 ps
CPU time 15.6 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:22 PM PST 24
Peak memory 251088 kb
Host smart-90950f6c-ffd5-4b5b-ad81-3970a359a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265848266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3265848266
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3760608212
Short name T417
Test name
Test status
Simulation time 413896788 ps
CPU time 8.64 seconds
Started Jan 14 12:32:03 PM PST 24
Finished Jan 14 12:32:13 PM PST 24
Peak memory 251168 kb
Host smart-19a3f031-9e1f-4134-be9d-ed4640fcb06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760608212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3760608212
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3606051268
Short name T488
Test name
Test status
Simulation time 17891182584 ps
CPU time 231.3 seconds
Started Jan 14 12:32:28 PM PST 24
Finished Jan 14 12:36:20 PM PST 24
Peak memory 280116 kb
Host smart-fcbb8b55-ebef-4faf-88b1-43ae3aeb3398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606051268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3606051268
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.912568764
Short name T411
Test name
Test status
Simulation time 23256951 ps
CPU time 0.9 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 208348 kb
Host smart-1e592df6-c7e0-4299-bab2-91c9805b138d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912568764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.912568764
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2749189312
Short name T399
Test name
Test status
Simulation time 19662828 ps
CPU time 0.95 seconds
Started Jan 14 12:32:05 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 209656 kb
Host smart-01ba8d9f-26a5-4935-9d71-c572de73e2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749189312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2749189312
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1904597511
Short name T395
Test name
Test status
Simulation time 1092881972 ps
CPU time 12.61 seconds
Started Jan 14 12:32:13 PM PST 24
Finished Jan 14 12:32:30 PM PST 24
Peak memory 218200 kb
Host smart-d837129a-1452-40a6-a305-59e1d4f2f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904597511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1904597511
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3990848958
Short name T504
Test name
Test status
Simulation time 69969864 ps
CPU time 1.78 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:01 PM PST 24
Peak memory 209744 kb
Host smart-8d4edfd5-72b3-421b-a98a-7e8469d6b215
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990848958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.3990848958
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.4022773051
Short name T905
Test name
Test status
Simulation time 137498722 ps
CPU time 1.79 seconds
Started Jan 14 12:32:00 PM PST 24
Finished Jan 14 12:32:03 PM PST 24
Peak memory 218124 kb
Host smart-45ca7168-5093-40a2-949f-e2b275f1fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022773051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.4022773051
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1065669890
Short name T860
Test name
Test status
Simulation time 624272483 ps
CPU time 14.96 seconds
Started Jan 14 12:32:27 PM PST 24
Finished Jan 14 12:32:43 PM PST 24
Peak memory 218200 kb
Host smart-596c45e2-09eb-4419-bdd6-29767db49769
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065669890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1065669890
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4047256915
Short name T707
Test name
Test status
Simulation time 264600175 ps
CPU time 10.76 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:19 PM PST 24
Peak memory 218136 kb
Host smart-dd5aa6c0-4d4c-4dab-aa09-cc2a513340ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047256915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4047256915
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1719952668
Short name T766
Test name
Test status
Simulation time 893298507 ps
CPU time 7.29 seconds
Started Jan 14 12:32:00 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 218104 kb
Host smart-1e282fea-83c6-4b2d-b626-e6f2b8fd28ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719952668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1719952668
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1721222000
Short name T708
Test name
Test status
Simulation time 1329288124 ps
CPU time 9.29 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 218284 kb
Host smart-a66d2249-6dbe-4638-9297-4f05e790ccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721222000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1721222000
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2988641778
Short name T436
Test name
Test status
Simulation time 197072743 ps
CPU time 2.33 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:08 PM PST 24
Peak memory 214124 kb
Host smart-cc7f3885-7e37-429d-bbe0-86ae7b662d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988641778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2988641778
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4058538568
Short name T318
Test name
Test status
Simulation time 972273807 ps
CPU time 17.34 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:25 PM PST 24
Peak memory 251108 kb
Host smart-f677595d-a9b6-462a-b8d3-0fc2c2eb53c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058538568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4058538568
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3296231680
Short name T780
Test name
Test status
Simulation time 46667425 ps
CPU time 6.5 seconds
Started Jan 14 12:32:12 PM PST 24
Finished Jan 14 12:32:23 PM PST 24
Peak memory 249908 kb
Host smart-09818b2b-25eb-4fe4-b2df-dd46b4009530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296231680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3296231680
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3110330637
Short name T425
Test name
Test status
Simulation time 9932235180 ps
CPU time 83.56 seconds
Started Jan 14 12:32:07 PM PST 24
Finished Jan 14 12:33:32 PM PST 24
Peak memory 275736 kb
Host smart-ac7bb5f5-1d42-4c6b-85bd-3c6702cf38fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110330637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3110330637
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.4094457618
Short name T319
Test name
Test status
Simulation time 44441516 ps
CPU time 0.71 seconds
Started Jan 14 12:32:14 PM PST 24
Finished Jan 14 12:32:18 PM PST 24
Peak memory 207864 kb
Host smart-4de25e99-172e-48ae-9307-bf1ca5a43058
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094457618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.4094457618
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2426064601
Short name T446
Test name
Test status
Simulation time 38995619 ps
CPU time 0.81 seconds
Started Jan 14 12:32:20 PM PST 24
Finished Jan 14 12:32:25 PM PST 24
Peak memory 209484 kb
Host smart-ad9a22dd-7c4d-4a00-aabf-5683d13fa5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426064601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2426064601
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1064684390
Short name T442
Test name
Test status
Simulation time 774105954 ps
CPU time 16.19 seconds
Started Jan 14 12:32:14 PM PST 24
Finished Jan 14 12:32:33 PM PST 24
Peak memory 218128 kb
Host smart-13cae848-8e4b-427d-863e-a56eb041fcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064684390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1064684390
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2200352933
Short name T830
Test name
Test status
Simulation time 285828495 ps
CPU time 7.89 seconds
Started Jan 14 12:32:21 PM PST 24
Finished Jan 14 12:32:32 PM PST 24
Peak memory 209548 kb
Host smart-f4045044-f8c2-4fe6-b586-6af9a9eb463b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200352933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_a
ccess.2200352933
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.939666045
Short name T189
Test name
Test status
Simulation time 102522819 ps
CPU time 2.65 seconds
Started Jan 14 12:32:14 PM PST 24
Finished Jan 14 12:32:20 PM PST 24
Peak memory 218096 kb
Host smart-ace9e4f6-8f66-41c3-b217-4d170bf6fd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939666045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.939666045
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.938291409
Short name T491
Test name
Test status
Simulation time 288463834 ps
CPU time 9.72 seconds
Started Jan 14 12:32:06 PM PST 24
Finished Jan 14 12:32:17 PM PST 24
Peak memory 218236 kb
Host smart-b854ce6a-afc6-4c8e-ba84-60279c552207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938291409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.938291409
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.215499701
Short name T385
Test name
Test status
Simulation time 437720373 ps
CPU time 10.58 seconds
Started Jan 14 12:32:22 PM PST 24
Finished Jan 14 12:32:35 PM PST 24
Peak memory 218032 kb
Host smart-02c11ccd-d472-4f4b-9e21-a3b4b958b009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215499701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.215499701
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3791892758
Short name T930
Test name
Test status
Simulation time 662705481 ps
CPU time 7.31 seconds
Started Jan 14 12:32:13 PM PST 24
Finished Jan 14 12:32:24 PM PST 24
Peak memory 218072 kb
Host smart-ee9a4afb-3336-403e-9dad-009cfe819200
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791892758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3791892758
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2782588173
Short name T953
Test name
Test status
Simulation time 352236218 ps
CPU time 7.39 seconds
Started Jan 14 12:31:58 PM PST 24
Finished Jan 14 12:32:07 PM PST 24
Peak memory 218100 kb
Host smart-1cc094f8-a59a-4e61-bcad-e8bf6e6cf2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782588173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2782588173
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.723303239
Short name T522
Test name
Test status
Simulation time 167643424 ps
CPU time 5.25 seconds
Started Jan 14 12:32:02 PM PST 24
Finished Jan 14 12:32:09 PM PST 24
Peak memory 213768 kb
Host smart-db1a27cf-6eb5-4da5-9ace-0e175c5792d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723303239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.723303239
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.895450043
Short name T533
Test name
Test status
Simulation time 185878357 ps
CPU time 25.08 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:31 PM PST 24
Peak memory 251100 kb
Host smart-6f42aba4-c687-4d30-9f40-918089fd73b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895450043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.895450043
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1368187358
Short name T896
Test name
Test status
Simulation time 316745456 ps
CPU time 6.17 seconds
Started Jan 14 12:32:03 PM PST 24
Finished Jan 14 12:32:10 PM PST 24
Peak memory 250704 kb
Host smart-b235b859-50b2-4cc3-9f1f-9a8a8e8a455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368187358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1368187358
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3585759739
Short name T931
Test name
Test status
Simulation time 42481129547 ps
CPU time 109.46 seconds
Started Jan 14 12:32:26 PM PST 24
Finished Jan 14 12:34:17 PM PST 24
Peak memory 283824 kb
Host smart-6309a815-534c-4a32-be9a-8271b5ae52fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585759739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3585759739
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1131277396
Short name T31
Test name
Test status
Simulation time 20396631 ps
CPU time 0.78 seconds
Started Jan 14 12:32:04 PM PST 24
Finished Jan 14 12:32:06 PM PST 24
Peak memory 207972 kb
Host smart-3995b717-418b-4d0e-b83f-5af9321641ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131277396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1131277396
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.4257193326
Short name T660
Test name
Test status
Simulation time 44638550 ps
CPU time 0.96 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:19 PM PST 24
Peak memory 208292 kb
Host smart-8f6e4bf1-e73a-42e7-bc4e-cab3ee89ccad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257193326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.4257193326
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2470911639
Short name T784
Test name
Test status
Simulation time 20119877 ps
CPU time 0.85 seconds
Started Jan 14 12:30:08 PM PST 24
Finished Jan 14 12:30:11 PM PST 24
Peak memory 209292 kb
Host smart-79e5c72a-d6a6-4f4e-a085-53e67876b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470911639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2470911639
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3739911711
Short name T629
Test name
Test status
Simulation time 6104271033 ps
CPU time 10.16 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:30 PM PST 24
Peak memory 218284 kb
Host smart-f46a1aff-e040-4b75-afe8-f1e1e4b782ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739911711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3739911711
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2339873328
Short name T651
Test name
Test status
Simulation time 171098220 ps
CPU time 3.96 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:13 PM PST 24
Peak memory 209640 kb
Host smart-74dfbe27-b813-4083-a7f7-847368df1709
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339873328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ac
cess.2339873328
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3270775662
Short name T682
Test name
Test status
Simulation time 1133467766 ps
CPU time 20.74 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 218116 kb
Host smart-ee193614-3919-4ce0-b3ef-9e71afa49e6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270775662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3270775662
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.4168468150
Short name T419
Test name
Test status
Simulation time 336653128 ps
CPU time 8.57 seconds
Started Jan 14 12:30:08 PM PST 24
Finished Jan 14 12:30:19 PM PST 24
Peak memory 217824 kb
Host smart-a5648709-f6db-4fde-a05e-2a2dcd35da6d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168468150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.4168468150
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2427166080
Short name T19
Test name
Test status
Simulation time 844335575 ps
CPU time 20.77 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:30 PM PST 24
Peak memory 218108 kb
Host smart-2c4f1774-2bde-4749-8393-9b21e7bfd26a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427166080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2427166080
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.34073609
Short name T807
Test name
Test status
Simulation time 3735335041 ps
CPU time 25.08 seconds
Started Jan 14 12:30:13 PM PST 24
Finished Jan 14 12:30:40 PM PST 24
Peak memory 213620 kb
Host smart-65d0826f-b290-4ecd-a22b-378080a5ead3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34073609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt
ag_regwen_during_op.34073609
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1236392144
Short name T16
Test name
Test status
Simulation time 1360315119 ps
CPU time 7.59 seconds
Started Jan 14 12:30:09 PM PST 24
Finished Jan 14 12:30:18 PM PST 24
Peak memory 213004 kb
Host smart-7fabc005-6b3f-4dc4-a5b0-4ad6d298b675
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236392144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1236392144
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3635845755
Short name T5
Test name
Test status
Simulation time 4246471226 ps
CPU time 66.78 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:31:24 PM PST 24
Peak memory 283744 kb
Host smart-028b256f-a1d6-4210-b629-3c4aad986122
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635845755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3635845755
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1467739022
Short name T841
Test name
Test status
Simulation time 1167608160 ps
CPU time 11.1 seconds
Started Jan 14 12:30:05 PM PST 24
Finished Jan 14 12:30:17 PM PST 24
Peak memory 247060 kb
Host smart-d7f9539d-cff3-4e7d-ac4e-f0d8e6de2e7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467739022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1467739022
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.160448529
Short name T975
Test name
Test status
Simulation time 44177954 ps
CPU time 2.18 seconds
Started Jan 14 12:30:19 PM PST 24
Finished Jan 14 12:30:22 PM PST 24
Peak memory 218176 kb
Host smart-fef8cf09-5c28-4a66-b0d0-b3e475db4b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160448529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.160448529
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1140936466
Short name T70
Test name
Test status
Simulation time 410286521 ps
CPU time 13.34 seconds
Started Jan 14 12:30:29 PM PST 24
Finished Jan 14 12:30:44 PM PST 24
Peak memory 214072 kb
Host smart-950b90a1-e5f4-4daa-b911-a5eb10808937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140936466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1140936466
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.4056176603
Short name T462
Test name
Test status
Simulation time 458588418 ps
CPU time 20.59 seconds
Started Jan 14 12:30:19 PM PST 24
Finished Jan 14 12:30:41 PM PST 24
Peak memory 219108 kb
Host smart-93dc2157-7051-45ee-9f90-cbb957489008
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056176603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4056176603
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.809321953
Short name T113
Test name
Test status
Simulation time 636243065 ps
CPU time 15.76 seconds
Started Jan 14 12:30:07 PM PST 24
Finished Jan 14 12:30:25 PM PST 24
Peak memory 218068 kb
Host smart-f9f826a7-7663-4def-b098-b5aa2eeac392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809321953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.809321953
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3099346475
Short name T609
Test name
Test status
Simulation time 229904263 ps
CPU time 7.58 seconds
Started Jan 14 12:30:03 PM PST 24
Finished Jan 14 12:30:12 PM PST 24
Peak memory 218008 kb
Host smart-5b561c01-2fc2-4f28-88e2-962e398272b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099346475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
099346475
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4027188933
Short name T744
Test name
Test status
Simulation time 315508889 ps
CPU time 3.02 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 214584 kb
Host smart-768b3329-79b3-409d-95ba-8835a4289357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027188933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4027188933
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3310071786
Short name T960
Test name
Test status
Simulation time 539278508 ps
CPU time 31.65 seconds
Started Jan 14 12:30:23 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 247456 kb
Host smart-2af63adc-6505-4e1b-b41e-2ed51ed77e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310071786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3310071786
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3612381582
Short name T941
Test name
Test status
Simulation time 85358565 ps
CPU time 8.26 seconds
Started Jan 14 12:30:12 PM PST 24
Finished Jan 14 12:30:22 PM PST 24
Peak memory 251104 kb
Host smart-8294426f-c806-49ec-9082-f58aa0439c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612381582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3612381582
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3461143239
Short name T919
Test name
Test status
Simulation time 16454502146 ps
CPU time 272.54 seconds
Started Jan 14 12:30:13 PM PST 24
Finished Jan 14 12:34:47 PM PST 24
Peak memory 278424 kb
Host smart-de4c50f6-d628-4142-8adc-c09a9977ce94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461143239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3461143239
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1906258784
Short name T733
Test name
Test status
Simulation time 62676214 ps
CPU time 1.04 seconds
Started Jan 14 12:30:31 PM PST 24
Finished Jan 14 12:30:35 PM PST 24
Peak memory 208396 kb
Host smart-d448287c-4d59-4bd1-b9c5-c2bc66c79c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906258784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1906258784
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2285872421
Short name T439
Test name
Test status
Simulation time 105870919 ps
CPU time 0.77 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 209260 kb
Host smart-828c6ade-64dd-40c0-b457-8ec6df5f90fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285872421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2285872421
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2666218600
Short name T394
Test name
Test status
Simulation time 660857804 ps
CPU time 15.89 seconds
Started Jan 14 12:30:20 PM PST 24
Finished Jan 14 12:30:37 PM PST 24
Peak memory 218128 kb
Host smart-e2bfc9f7-896a-4d29-8a18-f4d9f8080baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666218600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2666218600
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2902575024
Short name T24
Test name
Test status
Simulation time 174180173 ps
CPU time 2.27 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:30:38 PM PST 24
Peak memory 209528 kb
Host smart-47168c94-701d-410b-a785-422cb0df07a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902575024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.2902575024
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3316360414
Short name T376
Test name
Test status
Simulation time 6393746212 ps
CPU time 44.13 seconds
Started Jan 14 12:30:24 PM PST 24
Finished Jan 14 12:31:14 PM PST 24
Peak memory 219432 kb
Host smart-29c0cb96-9b87-4b02-a913-5cc626acaf35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316360414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3316360414
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.731138285
Short name T361
Test name
Test status
Simulation time 634701621 ps
CPU time 6.1 seconds
Started Jan 14 12:30:22 PM PST 24
Finished Jan 14 12:30:29 PM PST 24
Peak memory 209680 kb
Host smart-3480d0d0-2d0e-49d3-9539-3eb642e68d5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731138285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_p
riority.731138285
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3227520528
Short name T828
Test name
Test status
Simulation time 966518609 ps
CPU time 7.22 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:24 PM PST 24
Peak memory 218012 kb
Host smart-598f5c08-2517-44c8-ba55-b106758c0b03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227520528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3227520528
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2983608969
Short name T644
Test name
Test status
Simulation time 1445527959 ps
CPU time 12.6 seconds
Started Jan 14 12:30:25 PM PST 24
Finished Jan 14 12:30:43 PM PST 24
Peak memory 212924 kb
Host smart-a267659d-b2a0-4a67-9fd3-bb25319ac36a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983608969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2983608969
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4202889657
Short name T508
Test name
Test status
Simulation time 1457157173 ps
CPU time 2.95 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 212816 kb
Host smart-cc2facc3-9594-48d9-8e4a-8c18e0981fbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202889657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
4202889657
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.646616382
Short name T412
Test name
Test status
Simulation time 1930898710 ps
CPU time 70.16 seconds
Started Jan 14 12:30:09 PM PST 24
Finished Jan 14 12:31:21 PM PST 24
Peak memory 267428 kb
Host smart-ac1a0e09-2fa8-427f-948d-91475e511243
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646616382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.646616382
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.452986038
Short name T440
Test name
Test status
Simulation time 317948723 ps
CPU time 15.14 seconds
Started Jan 14 12:30:17 PM PST 24
Finished Jan 14 12:30:34 PM PST 24
Peak memory 251052 kb
Host smart-2be779bc-581d-495b-b541-6323054034a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452986038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.452986038
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1761677873
Short name T935
Test name
Test status
Simulation time 140216450 ps
CPU time 3.66 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:11 PM PST 24
Peak memory 218112 kb
Host smart-23e2f3c4-768f-4749-9ca3-3fec4642c360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761677873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1761677873
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.641063239
Short name T614
Test name
Test status
Simulation time 164491980 ps
CPU time 8.41 seconds
Started Jan 14 12:30:06 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 213840 kb
Host smart-4213b70d-7450-43c2-a76e-b6d8efb80d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641063239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.641063239
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.380929274
Short name T362
Test name
Test status
Simulation time 1767806863 ps
CPU time 10.63 seconds
Started Jan 14 12:30:15 PM PST 24
Finished Jan 14 12:30:26 PM PST 24
Peak memory 218192 kb
Host smart-b852afdf-726d-4fa0-ba2c-37f95983ded1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380929274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.380929274
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2414642489
Short name T350
Test name
Test status
Simulation time 574668071 ps
CPU time 23.19 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:42 PM PST 24
Peak memory 218052 kb
Host smart-02f9429e-28a9-4c5e-8709-9dc78114958c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414642489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2414642489
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3455908192
Short name T965
Test name
Test status
Simulation time 202552806 ps
CPU time 6.66 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:24 PM PST 24
Peak memory 218032 kb
Host smart-dacb0030-3a24-4b5f-a827-9a75fa3f7cc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455908192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
455908192
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.658090935
Short name T56
Test name
Test status
Simulation time 1866124330 ps
CPU time 12.64 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:30 PM PST 24
Peak memory 218156 kb
Host smart-cbf9f313-19a0-44e7-a4e3-098a71d50294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658090935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.658090935
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.718877429
Short name T396
Test name
Test status
Simulation time 36871988 ps
CPU time 1.67 seconds
Started Jan 14 12:30:32 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 213192 kb
Host smart-243573ab-2138-4791-acbd-9498380ffbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718877429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.718877429
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.307425398
Short name T477
Test name
Test status
Simulation time 254099318 ps
CPU time 22.75 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:30:38 PM PST 24
Peak memory 251024 kb
Host smart-7deb6cf0-6471-4344-a598-9232f33c9859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307425398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.307425398
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2600228441
Short name T188
Test name
Test status
Simulation time 355590363 ps
CPU time 6.98 seconds
Started Jan 14 12:30:31 PM PST 24
Finished Jan 14 12:30:40 PM PST 24
Peak memory 251144 kb
Host smart-a410a6ee-e62d-4635-8aee-b270b353f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600228441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2600228441
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3467038168
Short name T904
Test name
Test status
Simulation time 35293150672 ps
CPU time 183.96 seconds
Started Jan 14 12:30:15 PM PST 24
Finished Jan 14 12:33:20 PM PST 24
Peak memory 247376 kb
Host smart-66d698bd-8ba9-4828-8cc2-e9ef5a28e6af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467038168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3467038168
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.80618262
Short name T116
Test name
Test status
Simulation time 17730323285 ps
CPU time 343.66 seconds
Started Jan 14 12:30:19 PM PST 24
Finished Jan 14 12:36:05 PM PST 24
Peak memory 284216 kb
Host smart-662c3bdc-13bd-40a1-8ed0-bcec53245a51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=80618262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.80618262
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4035271333
Short name T552
Test name
Test status
Simulation time 13535859 ps
CPU time 0.78 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 208228 kb
Host smart-5183cc14-01a1-4ab1-81fe-fd538a0217db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035271333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4035271333
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1393635812
Short name T326
Test name
Test status
Simulation time 14535973 ps
CPU time 0.99 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 208348 kb
Host smart-c3815bae-0790-46ce-9d53-fcf9402f430a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393635812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1393635812
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3517398365
Short name T964
Test name
Test status
Simulation time 13319882 ps
CPU time 0.83 seconds
Started Jan 14 12:30:25 PM PST 24
Finished Jan 14 12:30:31 PM PST 24
Peak memory 209336 kb
Host smart-c116a5a1-cfb8-4299-a06a-3b3af01d0145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517398365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3517398365
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2271189127
Short name T570
Test name
Test status
Simulation time 322206696 ps
CPU time 13.84 seconds
Started Jan 14 12:30:12 PM PST 24
Finished Jan 14 12:30:27 PM PST 24
Peak memory 218208 kb
Host smart-e668b7a2-9c2a-45dd-a524-065f54ef8933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271189127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2271189127
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3992290676
Short name T530
Test name
Test status
Simulation time 2469513355 ps
CPU time 3.26 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 209612 kb
Host smart-8440bce6-7620-454d-adc3-2a185e25bcf3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992290676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.3992290676
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1292402264
Short name T397
Test name
Test status
Simulation time 15550765263 ps
CPU time 51.59 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:31:11 PM PST 24
Peak memory 219172 kb
Host smart-20786ebd-97a3-4774-81d9-57e29c989dc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292402264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1292402264
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.4007100782
Short name T627
Test name
Test status
Simulation time 131188127 ps
CPU time 2.2 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:19 PM PST 24
Peak memory 208944 kb
Host smart-c10495e8-42db-4778-a6b4-f964fbc6fd41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007100782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.4007100782
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2759656195
Short name T422
Test name
Test status
Simulation time 75707148 ps
CPU time 2.43 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:22 PM PST 24
Peak memory 218028 kb
Host smart-bb9ae7d3-b96a-40ee-902e-b781a676f8d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759656195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2759656195
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.135767605
Short name T926
Test name
Test status
Simulation time 3911182210 ps
CPU time 27 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:46 PM PST 24
Peak memory 213692 kb
Host smart-84f5e9ba-f601-4a0b-a76e-a0944286a323
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135767605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.135767605
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1305059061
Short name T586
Test name
Test status
Simulation time 556694930 ps
CPU time 8.32 seconds
Started Jan 14 12:30:09 PM PST 24
Finished Jan 14 12:30:19 PM PST 24
Peak memory 213660 kb
Host smart-5a1dc84d-51d4-40e0-a369-02bc695b0fbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305059061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1305059061
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1149787994
Short name T631
Test name
Test status
Simulation time 2068485537 ps
CPU time 56.05 seconds
Started Jan 14 12:30:17 PM PST 24
Finished Jan 14 12:31:15 PM PST 24
Peak memory 267460 kb
Host smart-28eb475b-5175-4593-8fa7-0b19f7f371b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149787994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1149787994
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2719032571
Short name T672
Test name
Test status
Simulation time 701296242 ps
CPU time 17.44 seconds
Started Jan 14 12:30:24 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 251024 kb
Host smart-a03b7a21-9798-45b3-9009-c4ceb930f92a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719032571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2719032571
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3293920647
Short name T966
Test name
Test status
Simulation time 116569316 ps
CPU time 3.47 seconds
Started Jan 14 12:30:20 PM PST 24
Finished Jan 14 12:30:25 PM PST 24
Peak memory 218092 kb
Host smart-bf4d3b48-4b40-4645-88a0-7de27cfd2951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293920647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3293920647
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3174719540
Short name T893
Test name
Test status
Simulation time 306356387 ps
CPU time 11.83 seconds
Started Jan 14 12:30:22 PM PST 24
Finished Jan 14 12:30:35 PM PST 24
Peak memory 213572 kb
Host smart-3af75b13-4989-4c94-a859-9e9e35f90c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174719540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3174719540
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1508539884
Short name T558
Test name
Test status
Simulation time 801649075 ps
CPU time 12.56 seconds
Started Jan 14 12:30:12 PM PST 24
Finished Jan 14 12:30:26 PM PST 24
Peak memory 219148 kb
Host smart-37c107a9-7b85-45ec-96c9-6ad3aba21ee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508539884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1508539884
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3428783710
Short name T560
Test name
Test status
Simulation time 1239106792 ps
CPU time 10.05 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:30:46 PM PST 24
Peak memory 218036 kb
Host smart-8a1112f5-69f8-412e-ac6e-c9cf3c6ee06b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428783710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3428783710
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.95904409
Short name T420
Test name
Test status
Simulation time 2054774364 ps
CPU time 11.41 seconds
Started Jan 14 12:30:30 PM PST 24
Finished Jan 14 12:30:43 PM PST 24
Peak memory 218004 kb
Host smart-c691f21e-3dd1-4adc-9d89-2cd1bdff887c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95904409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.95904409
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.4118024697
Short name T974
Test name
Test status
Simulation time 4388841789 ps
CPU time 9.13 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:26 PM PST 24
Peak memory 218256 kb
Host smart-26eb4f1a-416e-47f3-b34e-980f6e875842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118024697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.4118024697
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.334217805
Short name T603
Test name
Test status
Simulation time 25471368 ps
CPU time 2.05 seconds
Started Jan 14 12:30:29 PM PST 24
Finished Jan 14 12:30:33 PM PST 24
Peak memory 213472 kb
Host smart-9ffe5c5a-3cf3-4230-847c-3109ce158793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334217805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.334217805
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.144763769
Short name T115
Test name
Test status
Simulation time 492874684 ps
CPU time 24.93 seconds
Started Jan 14 12:30:23 PM PST 24
Finished Jan 14 12:30:49 PM PST 24
Peak memory 251108 kb
Host smart-f5f76fac-6d1d-446e-8c67-95071d1b91fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144763769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.144763769
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1282524932
Short name T607
Test name
Test status
Simulation time 256523680 ps
CPU time 3.41 seconds
Started Jan 14 12:30:30 PM PST 24
Finished Jan 14 12:30:37 PM PST 24
Peak memory 222000 kb
Host smart-3f2b6ab5-8273-40e8-9a60-aa5de181a39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282524932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1282524932
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3251374340
Short name T738
Test name
Test status
Simulation time 3215578878 ps
CPU time 58.47 seconds
Started Jan 14 12:30:19 PM PST 24
Finished Jan 14 12:31:19 PM PST 24
Peak memory 251208 kb
Host smart-6ed3e375-cab5-4d91-9ee8-9d3437099a8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251374340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3251374340
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2508536706
Short name T983
Test name
Test status
Simulation time 194950045 ps
CPU time 0.86 seconds
Started Jan 14 12:30:24 PM PST 24
Finished Jan 14 12:30:30 PM PST 24
Peak memory 211376 kb
Host smart-a2109a7c-e1c1-45e7-a23e-27929dc022e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508536706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2508536706
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1560873557
Short name T474
Test name
Test status
Simulation time 101931483 ps
CPU time 0.93 seconds
Started Jan 14 12:30:34 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 208432 kb
Host smart-1c150c2b-b4ff-42af-aaee-f5552d00e0a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560873557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1560873557
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.199361934
Short name T176
Test name
Test status
Simulation time 37517167 ps
CPU time 0.9 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:30:16 PM PST 24
Peak memory 208224 kb
Host smart-f57e946e-780d-473b-bf11-fb28d5ffe660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199361934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.199361934
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1862088782
Short name T786
Test name
Test status
Simulation time 334006046 ps
CPU time 8.56 seconds
Started Jan 14 12:30:33 PM PST 24
Finished Jan 14 12:30:43 PM PST 24
Peak memory 218124 kb
Host smart-44aafc32-b02b-49ca-94e7-6dae67c9caa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862088782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1862088782
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.982796052
Short name T23
Test name
Test status
Simulation time 727076879 ps
CPU time 17.11 seconds
Started Jan 14 12:30:22 PM PST 24
Finished Jan 14 12:30:41 PM PST 24
Peak memory 209596 kb
Host smart-2af93c2b-435e-4732-a7b2-4bff2454414b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982796052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_acc
ess.982796052
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.495381704
Short name T456
Test name
Test status
Simulation time 3303578347 ps
CPU time 29.13 seconds
Started Jan 14 12:30:21 PM PST 24
Finished Jan 14 12:30:52 PM PST 24
Peak memory 218384 kb
Host smart-cb10359c-baa2-43bd-b50e-42512d275662
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495381704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.495381704
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3600396809
Short name T525
Test name
Test status
Simulation time 1345026582 ps
CPU time 29.91 seconds
Started Jan 14 12:30:22 PM PST 24
Finished Jan 14 12:30:54 PM PST 24
Peak memory 217852 kb
Host smart-8e06d9a4-3986-4764-967a-3b186fd7caaf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600396809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.3600396809
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1998399252
Short name T190
Test name
Test status
Simulation time 2227738835 ps
CPU time 28.33 seconds
Started Jan 14 12:30:28 PM PST 24
Finished Jan 14 12:30:59 PM PST 24
Peak memory 218120 kb
Host smart-031851e7-408d-46f9-9490-3687b3fa41c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998399252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1998399252
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2114795017
Short name T626
Test name
Test status
Simulation time 3209544523 ps
CPU time 19.65 seconds
Started Jan 14 12:30:24 PM PST 24
Finished Jan 14 12:30:50 PM PST 24
Peak memory 213232 kb
Host smart-c39c69cc-3768-4bc3-9c4b-8f44a6cca367
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114795017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2114795017
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2236351287
Short name T605
Test name
Test status
Simulation time 380863611 ps
CPU time 10.09 seconds
Started Jan 14 12:30:18 PM PST 24
Finished Jan 14 12:30:30 PM PST 24
Peak memory 213512 kb
Host smart-5a0a3f25-4cba-4659-bcec-6e5f8e92bc53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236351287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2236351287
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3000707741
Short name T510
Test name
Test status
Simulation time 4139911201 ps
CPU time 140.85 seconds
Started Jan 14 12:30:14 PM PST 24
Finished Jan 14 12:32:36 PM PST 24
Peak memory 283732 kb
Host smart-07119f71-116a-4649-8028-13ff705d6b44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000707741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3000707741
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2943709349
Short name T812
Test name
Test status
Simulation time 1917773652 ps
CPU time 8.46 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:30:45 PM PST 24
Peak memory 222580 kb
Host smart-34a30b9f-fcee-4ec7-ac9b-616c45909bd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943709349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2943709349
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3501916037
Short name T800
Test name
Test status
Simulation time 96700813 ps
CPU time 1.7 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:19 PM PST 24
Peak memory 218080 kb
Host smart-cfa23e61-c8eb-436e-95d0-6bd1a65bc18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501916037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3501916037
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.987431656
Short name T83
Test name
Test status
Simulation time 4029652975 ps
CPU time 9.19 seconds
Started Jan 14 12:30:17 PM PST 24
Finished Jan 14 12:30:27 PM PST 24
Peak memory 214224 kb
Host smart-0b3ff197-a722-400a-a927-72ca1d96b682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987431656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.987431656
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.234226668
Short name T569
Test name
Test status
Simulation time 414926141 ps
CPU time 13.18 seconds
Started Jan 14 12:30:19 PM PST 24
Finished Jan 14 12:30:33 PM PST 24
Peak memory 218556 kb
Host smart-40eab4c8-15cd-4073-981b-10c5243fc401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234226668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.234226668
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2831697109
Short name T887
Test name
Test status
Simulation time 420771472 ps
CPU time 14.25 seconds
Started Jan 14 12:30:27 PM PST 24
Finished Jan 14 12:30:45 PM PST 24
Peak memory 218112 kb
Host smart-4a8980d3-9b13-4c9f-824e-23a3622c08c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831697109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2831697109
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.609015574
Short name T328
Test name
Test status
Simulation time 579466361 ps
CPU time 11.29 seconds
Started Jan 14 12:30:21 PM PST 24
Finished Jan 14 12:30:34 PM PST 24
Peak memory 218056 kb
Host smart-4840a10b-d9e2-4ae0-a948-556b19872a5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609015574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.609015574
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2016616717
Short name T483
Test name
Test status
Simulation time 958926525 ps
CPU time 9.96 seconds
Started Jan 14 12:30:23 PM PST 24
Finished Jan 14 12:30:34 PM PST 24
Peak memory 218216 kb
Host smart-0274683d-b184-45fd-ad32-37efc3348110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016616717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2016616717
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.408596582
Short name T923
Test name
Test status
Simulation time 62702452 ps
CPU time 3.26 seconds
Started Jan 14 12:30:22 PM PST 24
Finished Jan 14 12:30:27 PM PST 24
Peak memory 214120 kb
Host smart-bb7ad23c-ec52-410c-934b-dff9f63567cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408596582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.408596582
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.173019865
Short name T822
Test name
Test status
Simulation time 182575093 ps
CPU time 21.41 seconds
Started Jan 14 12:30:21 PM PST 24
Finished Jan 14 12:30:45 PM PST 24
Peak memory 251068 kb
Host smart-d09bf7e7-b534-48ff-8406-8204be665f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173019865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.173019865
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2381499202
Short name T833
Test name
Test status
Simulation time 481704216 ps
CPU time 3.24 seconds
Started Jan 14 12:30:16 PM PST 24
Finished Jan 14 12:30:20 PM PST 24
Peak memory 221024 kb
Host smart-187ba0b0-4ca2-4ebe-9139-4c23185ecc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381499202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2381499202
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.4029453023
Short name T636
Test name
Test status
Simulation time 7831374876 ps
CPU time 141.76 seconds
Started Jan 14 12:30:37 PM PST 24
Finished Jan 14 12:32:59 PM PST 24
Peak memory 253676 kb
Host smart-0ff4a3cb-14cb-4820-8b6b-f02ac12cf79a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029453023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.4029453023
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2197266552
Short name T410
Test name
Test status
Simulation time 33614700 ps
CPU time 0.86 seconds
Started Jan 14 12:30:19 PM PST 24
Finished Jan 14 12:30:22 PM PST 24
Peak memory 208532 kb
Host smart-ca202466-83ae-4907-b0ee-4ccb7c1d3433
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197266552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2197266552
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3551231275
Short name T372
Test name
Test status
Simulation time 111519612 ps
CPU time 1.26 seconds
Started Jan 14 12:30:30 PM PST 24
Finished Jan 14 12:30:33 PM PST 24
Peak memory 208376 kb
Host smart-b28d6002-e6bc-4291-8906-ebba49ad9fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551231275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3551231275
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3062174174
Short name T591
Test name
Test status
Simulation time 12817392 ps
CPU time 0.93 seconds
Started Jan 14 12:30:32 PM PST 24
Finished Jan 14 12:30:35 PM PST 24
Peak memory 208360 kb
Host smart-714c2a87-fbe4-4aab-bc7e-50239cdd75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062174174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3062174174
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3271528777
Short name T38
Test name
Test status
Simulation time 1318666920 ps
CPU time 15.31 seconds
Started Jan 14 12:30:20 PM PST 24
Finished Jan 14 12:30:37 PM PST 24
Peak memory 218088 kb
Host smart-c2b74472-e1a0-41a4-bb51-e6b6157eb796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271528777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3271528777
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.355847772
Short name T466
Test name
Test status
Simulation time 866034218 ps
CPU time 2.8 seconds
Started Jan 14 12:30:31 PM PST 24
Finished Jan 14 12:30:36 PM PST 24
Peak memory 209716 kb
Host smart-a0dfecda-cbbd-4627-ba96-e7ef82c49e9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355847772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_acc
ess.355847772
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1905660118
Short name T917
Test name
Test status
Simulation time 30003688493 ps
CPU time 57.34 seconds
Started Jan 14 12:30:35 PM PST 24
Finished Jan 14 12:31:34 PM PST 24
Peak memory 219108 kb
Host smart-d1ec76d4-57ac-41e0-b275-f91b4b8b65fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905660118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1905660118
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3931060855
Short name T769
Test name
Test status
Simulation time 606304421 ps
CPU time 4.25 seconds
Started Jan 14 12:30:27 PM PST 24
Finished Jan 14 12:30:35 PM PST 24
Peak memory 217880 kb
Host smart-1f38021c-a698-4ea0-82c1-8dea9a0ba0f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931060855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
priority.3931060855
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2269012687
Short name T658
Test name
Test status
Simulation time 1206920064 ps
CPU time 5.95 seconds
Started Jan 14 12:30:36 PM PST 24
Finished Jan 14 12:30:43 PM PST 24
Peak memory 218028 kb
Host smart-7d732847-39f6-4c95-b88f-adb0d5bbf1a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269012687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2269012687
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.36109332
Short name T69
Test name
Test status
Simulation time 15872230520 ps
CPU time 13.88 seconds
Started Jan 14 12:30:32 PM PST 24
Finished Jan 14 12:30:48 PM PST 24
Peak memory 213776 kb
Host smart-0aeefa48-c5d5-4b50-87a1-97c2b214d83b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt
ag_regwen_during_op.36109332
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.219799915
Short name T757
Test name
Test status
Simulation time 1311221179 ps
CPU time 4.57 seconds
Started Jan 14 12:30:21 PM PST 24
Finished Jan 14 12:30:27 PM PST 24
Peak memory 213072 kb
Host smart-a8ba873d-93a7-495f-9016-d2d5be84d0d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219799915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.219799915
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.210100297
Short name T598
Test name
Test status
Simulation time 11968215234 ps
CPU time 55.12 seconds
Started Jan 14 12:30:36 PM PST 24
Finished Jan 14 12:31:32 PM PST 24
Peak memory 283468 kb
Host smart-074fc749-29a3-4db2-987e-370845d9e336
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210100297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.210100297
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.252218734
Short name T584
Test name
Test status
Simulation time 1803220877 ps
CPU time 16.34 seconds
Started Jan 14 12:30:34 PM PST 24
Finished Jan 14 12:30:51 PM PST 24
Peak memory 250780 kb
Host smart-38793ab1-2325-4d89-8278-a93d9f933330
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252218734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.252218734
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.369012352
Short name T673
Test name
Test status
Simulation time 17622228 ps
CPU time 1.69 seconds
Started Jan 14 12:30:36 PM PST 24
Finished Jan 14 12:30:38 PM PST 24
Peak memory 218104 kb
Host smart-1f4defe4-f504-428f-b1b9-f2dbf79ea61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369012352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.369012352
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3628361682
Short name T731
Test name
Test status
Simulation time 271482670 ps
CPU time 8.46 seconds
Started Jan 14 12:30:24 PM PST 24
Finished Jan 14 12:30:38 PM PST 24
Peak memory 214064 kb
Host smart-39416581-b251-4122-80a5-21bcfe54e472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628361682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3628361682
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1257520066
Short name T370
Test name
Test status
Simulation time 468976975 ps
CPU time 11.04 seconds
Started Jan 14 12:30:19 PM PST 24
Finished Jan 14 12:30:32 PM PST 24
Peak memory 219116 kb
Host smart-7ec7ba21-23dd-47dd-9489-12a2c27bf381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257520066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1257520066
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1318211875
Short name T750
Test name
Test status
Simulation time 440943099 ps
CPU time 9.88 seconds
Started Jan 14 12:30:32 PM PST 24
Finished Jan 14 12:30:44 PM PST 24
Peak memory 218144 kb
Host smart-4b8e76a6-7881-4987-a0fe-cfe193c9edb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318211875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1318211875
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1308171579
Short name T408
Test name
Test status
Simulation time 1165630784 ps
CPU time 10.05 seconds
Started Jan 14 12:30:29 PM PST 24
Finished Jan 14 12:30:41 PM PST 24
Peak memory 218028 kb
Host smart-e671ce22-a4f5-43fc-bd96-f8b0e25a1b1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308171579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
308171579
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4034107263
Short name T573
Test name
Test status
Simulation time 438740254 ps
CPU time 12.95 seconds
Started Jan 14 12:30:20 PM PST 24
Finished Jan 14 12:30:34 PM PST 24
Peak memory 218080 kb
Host smart-ad2a9709-865c-4bef-a5a5-63400ceee910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034107263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4034107263
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1721540804
Short name T565
Test name
Test status
Simulation time 60874810 ps
CPU time 2.04 seconds
Started Jan 14 12:30:23 PM PST 24
Finished Jan 14 12:30:31 PM PST 24
Peak memory 213536 kb
Host smart-7b1f4a7a-83ea-40ae-bf01-00bf1c5c061a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721540804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1721540804
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1980003220
Short name T787
Test name
Test status
Simulation time 307634313 ps
CPU time 27.66 seconds
Started Jan 14 12:30:36 PM PST 24
Finished Jan 14 12:31:04 PM PST 24
Peak memory 251024 kb
Host smart-4ee9e15b-270c-481b-a5e7-a9fa92a8fd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980003220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1980003220
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3820466571
Short name T327
Test name
Test status
Simulation time 69429678 ps
CPU time 6.59 seconds
Started Jan 14 12:30:27 PM PST 24
Finished Jan 14 12:30:37 PM PST 24
Peak memory 250712 kb
Host smart-b7b30c4b-731f-45b1-94d8-d9dffec3a256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820466571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3820466571
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3684748608
Short name T578
Test name
Test status
Simulation time 2379538705 ps
CPU time 70.53 seconds
Started Jan 14 12:30:32 PM PST 24
Finished Jan 14 12:31:45 PM PST 24
Peak memory 251208 kb
Host smart-023ae784-4b92-4d38-916b-794b2544025e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684748608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3684748608
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4068777593
Short name T971
Test name
Test status
Simulation time 37790923 ps
CPU time 0.86 seconds
Started Jan 14 12:30:24 PM PST 24
Finished Jan 14 12:30:31 PM PST 24
Peak memory 211372 kb
Host smart-d746536d-1f98-4bb2-bb63-bb36e931f4a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068777593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.4068777593
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%