LC_CTRL Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.410s	95.202us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.030s	144.410us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	18.210us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.880s	92.716us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.790s	80.499us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.210s	29.912us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	18.210us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	80.499us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.280s	132.684us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	13.480s	727.097us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	11.260us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.810s	686.784us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.140s	587.284us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_prog_failure	6.810s	686.784us	50	50	100.00
		lc_ctrl_errors	22.140s	587.284us	50	50	100.00
		lc_ctrl_security_escalation	16.270s	1.758ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.347m	4.140ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.330s	2.228ms	20	20	100.00
		lc_ctrl_jtag_errors	1.026m	2.150ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.330s	1.037ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.310s	1.945ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.330s	2.228ms	20	20	100.00
		lc_ctrl_jtag_errors	1.026m	2.150ms	20	20	100.00
		lc_ctrl_jtag_access	20.500s	924.037us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.440s	1.102ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.550s	1.232ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.280s	113.971us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	38.940s	9.262ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.860s	2.866ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.970s	185.602us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.360s	74.110us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.540s	286.134us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.910s	1.345ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.020s	166.991us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.102m	26.864ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	63.141us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.110s	150.905us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.110s	150.905us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.030s	144.410us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	18.210us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	80.499us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	45.576us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.030s	144.410us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	18.210us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	80.499us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	45.576us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
		lc_ctrl_tl_intg_err	4.530s	657.226us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.530s	657.226us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	13.480s	727.097us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.150s	824.031us	50	50	100.00
		lc_ctrl_sec_cm	36.970s	533.313us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.270s	1.758ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.280s	132.684us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.310s	1.945ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.590s	458.588us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.590s	458.588us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.650s	2.112ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.530s	2.966ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.530s	2.966ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	19.884m	117.743ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			986	1030	95.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.34	97.29	95.52	91.98	100.00	96.13	98.48	95.00

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.29541003430494778689588133139549491933380808011210903797645688217516006735230
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d7cf2ffd-e4dc-4e43-894e-78196f70bc3a
      

    • 3.lc_ctrl_stress_all_with_rand_reset.33092860914406960986543419049477429502150092529456394250791425364507654428945
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:419ebe73-9d1e-4060-baad-10c6365117f2
      

    • ... and 22 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 8 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.81323869483586533731743540941462317211161771249800037617235175172256955039113
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:56abdec7-9abc-4e8e-b55a-28394b2ac823
      

    • 8.lc_ctrl_stress_all_with_rand_reset.86588896297272620783667318803409886128890114410189583697499245074740135019852
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a76d9da2-3774-4a55-b43d-3ccfcd721e7a
      

    • ... and 6 more failures.

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 6 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 6 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.25108034950752326832588545014045560467849808139079055642425879210324212649297
      Line 28178, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 7973963911 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x40938c00
        UVM_INFO @ 7973963911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.lc_ctrl_stress_all_with_rand_reset.233664959572892297454544041381483882362384627591189505465962259954715278267
      Line 17017, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 83598655549 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xd0c3e200
        UVM_INFO @ 83598655549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.33404772539823773220891017041126056061134923517801118007092972382771399384025
      Line 36414, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31976858174 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 31976858174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 31.lc_ctrl_stress_all_with_rand_reset.115160196996319003278924714262837470885865797830642248055991589162241294194511
      Line 3064, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25789718516 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 25789718516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.15205198628977275562355666645863525441900487643120474015347534953317047627847
      Line 8377, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6190740090 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked0
        UVM_INFO @ 6190740090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.80900558914937013739151922925274085419768171914169689607198380409801538729635
      Line 8178, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24392095785 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked3
        UVM_INFO @ 24392095785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStRma has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.53841930994262046917723813099305347245785552724608546482896352227063075744060
      Line 13840, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6572515603 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStRma
        UVM_INFO @ 6572515603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:236) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_hw_debug_en_o == exp_o.lc_hw_debug_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStDev has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.1212638504403561605844558216033874549835811925596959440470656305043809742822
      Line 1655, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4620848361 ps: (lc_ctrl_scoreboard.sv:236) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_hw_debug_en_o == exp_o.lc_hw_debug_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStDev
        UVM_INFO @ 4620848361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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