Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62659497

1

T65

8237

T96

4553

T97

1435

auto[1]

1160784

1

T1

396

T2

2653

T3

1881

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62673348

1

T65

8237

T96

4553

T97

1435

auto[1]

1146933

1

T1

396

T2

2947

T3

3267

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	4985680	1			T65	2029		T96	111		T97	114
auto[IdleSt]	14727677	1			T65	5855		T96	4442		T97	1321
auto[ClkMuxSt]	27684	1			T1	4		T4	10		T5	18
auto[CntIncrSt]	27499	1			T1	4		T4	10		T5	18
auto[CntProgSt]	1580081	1			T1	1257		T4	395		T5	36
auto[TransCheckSt]	21708	1			T1	4		T4	10		T5	9
auto[TokenHashSt]	22672000	1			T1	75		T4	2766		T5	759
auto[FlashRmaSt]	21681	1			T1	17		T4	23		T5	31
auto[TokenCheck0St]	9553	1			T1	4		T4	10		T5	9
auto[TokenCheck1St]	6889	1			T1	4		T4	10		T5	9
auto[TransProgSt]	339876	1			T1	1252		T4	470		T5	18
auto[PostTransSt]	8542586	1			T1	1262		T4	57792		T5	38585
auto[ScrapSt]	88378	1			T65	353		T100	8729		T104	333
auto[EscalateSt]	4714341	1			T1	2216		T2	28699		T3	7017
auto[InvalidSt]	6053387	1			T1	1502		T2	86189		T3	6323

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1261	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6053387	1			T1	1502		T2	86189		T3	6323
EscalateSt	4714341	1			T1	2216		T2	28699		T3	7017
ScrapSt	88378	1			T65	353		T100	8729		T104	333
PostTransSt	8542586	1			T1	1262		T4	57792		T5	38585
TransProgSt	339876	1			T1	1252		T4	470		T5	18
TokenCheck1St	6889	1			T1	4		T4	10		T5	9
TokenCheck0St	9553	1			T1	4		T4	10		T5	9
FlashRmaSt	21681	1			T1	17		T4	23		T5	31
TokenHashSt	22672000	1			T1	75		T4	2766		T5	759
TransCheckSt	21708	1			T1	4		T4	10		T5	9
CntProgSt	1580081	1			T1	1257		T4	395		T5	36
CntIncrSt	27499	1			T1	4		T4	10		T5	18
ClkMuxSt	27684	1			T1	4		T4	10		T5	18
IdleSt	14727677	1			T65	5855		T96	4442		T97	1321
ResetSt	4985680	1			T65	2029		T96	111		T97	114
arcs[ResetSt=>IdleSt]	40530	1			T65	21		T96	2		T97	1
arcs[IdleSt=>ScrapSt]	227	1			T65	1		T100	1		T104	1
arcs[IdleSt=>ClkMuxSt]	27554	1			T1	4		T4	10		T5	18
arcs[ClkMuxSt=>CntIncrSt]	27499	1			T1	4		T4	10		T5	18
arcs[CntIncrSt=>PostTransSt]	1272	1			T44	15		T45	14		T29	9
arcs[CntIncrSt=>CntProgSt]	26159	1			T1	4		T4	10		T5	18
arcs[CntProgSt=>PostTransSt]	3405	1			T5	9		T15	13		T44	12
arcs[CntProgSt=>TransCheckSt]	21708	1			T1	4		T4	10		T5	9
arcs[TransCheckSt=>PostTransSt]	3087	1			T10	42		T44	14		T45	7
arcs[TransCheckSt=>TokenHashSt]	18503	1			T1	4		T4	10		T5	9
arcs[TokenHashSt=>PostTransSt]	8232	1			T10	11		T12	81		T44	35
arcs[TokenHashSt=>FlashRmaSt]	9650	1			T1	4		T4	10		T5	9
arcs[FlashRmaSt=>TokenCheck0St]	9553	1			T1	4		T4	10		T5	9
arcs[TokenCheck0St=>PostTransSt]	2630	1			T10	13		T44	11		T45	13
arcs[TokenCheck0St=>TokenCheck1St]	6889	1			T1	4		T4	10		T5	9
arcs[TokenCheck1St=>PostTransSt]	655	1			T10	12		T44	1		T45	1
arcs[TransProgSt=>PostTransSt]	5401	1			T1	4		T4	10		T5	9
arcs[IdleSt=>EscalateSt]	204	1			T34	14		T36	4		T92	9
arcs[ClkMuxSt=>EscalateSt]	55	1			T34	1		T36	1		T92	1
arcs[CntIncrSt=>EscalateSt]	68	1			T34	2		T36	1		T92	2
arcs[CntProgSt=>EscalateSt]	1046	1			T34	32		T36	5		T92	28
arcs[TransCheckSt=>EscalateSt]	118	1			T36	5		T180	1		T181	2
arcs[TokenHashSt=>EscalateSt]	611	1			T34	6		T36	13		T66	1
arcs[FlashRmaSt=>EscalateSt]	97	1			T36	2		T92	4		T94	3
arcs[TokenCheck0St=>EscalateSt]	34	1			T34	1		T36	1		T93	1
arcs[TokenCheck1St=>EscalateSt]	149	1			T34	2		T36	3		T92	5
arcs[TransProgSt=>EscalateSt]	683	1			T34	23		T36	6		T92	21
arcs[PostTransSt=>EscalateSt]	3651	1			T5	9		T15	13		T44	12
arcs[InvalidSt=>EscalateSt]	10472	1			T1	8		T2	57		T3	52

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	4985516	1			T65	2029		T96	111		T97	114
auto[0]	auto[IdleSt]	14727531	1			T65	5855		T96	4442		T97	1321
auto[0]	auto[ClkMuxSt]	27650	1			T1	4		T4	10		T5	18
auto[0]	auto[CntIncrSt]	27453	1			T1	4		T4	10		T5	18
auto[0]	auto[CntProgSt]	1579393	1			T1	1257		T4	395		T5	36
auto[0]	auto[TransCheckSt]	21630	1			T1	4		T4	10		T5	9
auto[0]	auto[TokenHashSt]	22671581	1			T1	75		T4	2766		T5	759
auto[0]	auto[FlashRmaSt]	21605	1			T1	17		T4	23		T5	31
auto[0]	auto[TokenCheck0St]	9529	1			T1	4		T4	10		T5	9
auto[0]	auto[TokenCheck1St]	6786	1			T1	4		T4	10		T5	9
auto[0]	auto[TransProgSt]	339431	1			T1	1252		T4	470		T5	18
auto[0]	auto[PostTransSt]	8540746	1			T1	1262		T4	57792		T5	38579
auto[0]	auto[ScrapSt]	88334	1			T65	353		T100	8729		T104	333
auto[0]	auto[EscalateSt]	3562987	1			T1	1824		T2	26073		T3	5155
auto[0]	auto[InvalidSt]	6048064	1			T1	1498		T2	86162		T3	6304
auto[1]	auto[ResetSt]	164	1			T34	4		T92	3		T93	6
auto[1]	auto[IdleSt]	146	1			T34	10		T92	4		T93	2
auto[1]	auto[ClkMuxSt]	34	1			T34	1		T94	1		T180	1
auto[1]	auto[CntIncrSt]	46	1			T34	2		T92	2		T182	1
auto[1]	auto[CntProgSt]	688	1			T34	22		T36	4		T92	20
auto[1]	auto[TransCheckSt]	78	1			T36	2		T180	1		T181	1
auto[1]	auto[TokenHashSt]	419	1			T34	6		T36	6		T92	6
auto[1]	auto[FlashRmaSt]	76	1			T36	2		T92	2		T94	2
auto[1]	auto[TokenCheck0St]	24	1			T36	1		T93	1		T183	3
auto[1]	auto[TokenCheck1St]	103	1			T34	2		T36	2		T92	5
auto[1]	auto[TransProgSt]	445	1			T34	16		T36	4		T92	12
auto[1]	auto[PostTransSt]	1840	1			T5	6		T15	7		T44	4
auto[1]	auto[ScrapSt]	44	1			T34	1		T92	1		T94	3
auto[1]	auto[EscalateSt]	1151354	1			T1	392		T2	2626		T3	1862
auto[1]	auto[InvalidSt]	5323	1			T1	4		T2	27		T3	19

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	4985496	1			T65	2029		T96	111		T97	114
auto[0]	auto[IdleSt]	14727538	1			T65	5855		T96	4442		T97	1321
auto[0]	auto[ClkMuxSt]	27648	1			T1	4		T4	10		T5	18
auto[0]	auto[CntIncrSt]	27454	1			T1	4		T4	10		T5	18
auto[0]	auto[CntProgSt]	1579359	1			T1	1257		T4	395		T5	36
auto[0]	auto[TransCheckSt]	21626	1			T1	4		T4	10		T5	9
auto[0]	auto[TokenHashSt]	22671611	1			T1	75		T4	2766		T5	759
auto[0]	auto[FlashRmaSt]	21628	1			T1	17		T4	23		T5	31
auto[0]	auto[TokenCheck0St]	9532	1			T1	4		T4	10		T5	9
auto[0]	auto[TokenCheck1St]	6796	1			T1	4		T4	10		T5	9
auto[0]	auto[TransProgSt]	339416	1			T1	1252		T4	470		T5	18
auto[0]	auto[PostTransSt]	8540699	1			T1	1262		T4	57792		T5	38582
auto[0]	auto[ScrapSt]	88328	1			T65	353		T100	8729		T104	333
auto[0]	auto[EscalateSt]	3576718	1			T1	1824		T2	25782		T3	3783
auto[0]	auto[InvalidSt]	6048238	1			T1	1498		T2	86159		T3	6290
auto[1]	auto[ResetSt]	184	1			T34	4		T36	3		T92	4
auto[1]	auto[IdleSt]	139	1			T34	10		T36	4		T92	8
auto[1]	auto[ClkMuxSt]	36	1			T36	1		T92	1		T182	1
auto[1]	auto[CntIncrSt]	45	1			T34	2		T36	1		T92	1
auto[1]	auto[CntProgSt]	722	1			T34	21		T36	3		T92	19
auto[1]	auto[TransCheckSt]	82	1			T36	3		T180	1		T181	2
auto[1]	auto[TokenHashSt]	389	1			T34	3		T36	9		T66	1
auto[1]	auto[FlashRmaSt]	53	1			T36	2		T92	4		T94	3
auto[1]	auto[TokenCheck0St]	21	1			T34	1		T36	1		T93	1
auto[1]	auto[TokenCheck1St]	93	1			T36	1		T92	3		T93	3
auto[1]	auto[TransProgSt]	460	1			T34	16		T36	3		T92	14
auto[1]	auto[PostTransSt]	1887	1			T5	3		T15	6		T44	8
auto[1]	auto[ScrapSt]	50	1			T34	2		T36	1		T92	1
auto[1]	auto[EscalateSt]	1137623	1			T1	392		T2	2917		T3	3234
auto[1]	auto[InvalidSt]	5149	1			T1	4		T2	30		T3	33