Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

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Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_q	8	0	8	100.00	100	1	1	0

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_states[ClkMuxSt]	457	1			T10	14		T30	6		T46	14
fsm_states[CntIncrSt]	432	1			T10	9		T30	4		T46	8
fsm_states[CntProgSt]	460	1			T10	13		T30	7		T46	12
fsm_states[TransCheckSt]	474	1			T10	6		T30	12		T46	16
fsm_states[FlashRmaSt]	473	1			T10	7		T30	5		T46	11
fsm_states[TokenHashSt]	450	1			T10	11		T30	5		T46	6
fsm_states[TokenCheck0St]	434	1			T10	6		T30	5		T46	9
fsm_states[TokenCheck1St]	509	1			T10	12		T30	6		T46	13