Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	966261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1149652

1

T65

610

T96

11

T97

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1831523	1			T65	91		T96	3		T97	6
values[0x0]	141587	1			T65	317		T96	3		T97	31
values[0x1]	142803	1			T65	329		T96	5		T97	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	765831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1350082

1

T65

648

T96

11

T97

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25681	1			T65	4		T101	1		T104	2
valid_sources[0x01]	5628	1			T65	7		T101	1		T102	8
valid_sources[0x02]	5965	1			T65	1		T101	1		T110	1
valid_sources[0x03]	6013	1			T65	2		T101	1		T110	2
valid_sources[0x04]	8422	1			T65	1		T110	5		T114	1
valid_sources[0x05]	5585	1			T65	6		T104	4		T110	1
valid_sources[0x06]	5966	1			T65	2		T104	9		T110	2
valid_sources[0x07]	7714	1			T65	2		T99	17		T104	4
valid_sources[0x08]	5769	1			T65	3		T98	11		T113	30
valid_sources[0x09]	5921	1			T65	3		T99	2		T110	5
valid_sources[0x0a]	7339	1			T65	2		T98	3		T127	2
valid_sources[0x0b]	44591	1			T65	3		T99	3		T159	1
valid_sources[0x0c]	6159	1			T65	2		T97	8		T98	17
valid_sources[0x0d]	6085	1			T65	3		T99	4		T104	9
valid_sources[0x0e]	5765	1			T65	4		T114	1		T159	7
valid_sources[0x0f]	5894	1			T104	14		T128	3		T161	3
valid_sources[0x10]	6026	1			T65	3		T104	3		T128	2
valid_sources[0x11]	7353	1			T65	2		T97	6		T110	3
valid_sources[0x12]	5691	1			T65	3		T97	17		T110	3
valid_sources[0x13]	5573	1			T65	1		T98	16		T99	5
valid_sources[0x14]	7179	1			T65	8		T97	2		T110	1
valid_sources[0x15]	6250	1			T65	3		T97	1		T128	5
valid_sources[0x16]	5795	1			T65	4		T98	2		T104	5
valid_sources[0x17]	5902	1			T65	3		T104	1		T110	3
valid_sources[0x18]	9851	1			T65	5		T104	4		T113	2
valid_sources[0x19]	5853	1			T98	4		T110	1		T113	12
valid_sources[0x1a]	6481	1			T65	1		T128	5		T159	1
valid_sources[0x1b]	5564	1			T65	1		T128	2		T114	2
valid_sources[0x1c]	5805	1			T65	4		T101	1		T102	6
valid_sources[0x1d]	13292	1			T65	2		T101	1		T104	3
valid_sources[0x1e]	5814	1			T65	2		T101	1		T128	2
valid_sources[0x1f]	5351	1			T65	3		T104	7		T110	1
valid_sources[0x20]	5765	1			T65	3		T110	2		T114	3
valid_sources[0x21]	6021	1			T65	2		T110	2		T115	155
valid_sources[0x22]	6342	1			T65	6		T104	2		T110	2
valid_sources[0x23]	5374	1			T65	1		T110	2		T128	3
valid_sources[0x24]	7245	1			T65	4		T98	9		T104	10
valid_sources[0x25]	6046	1			T65	2		T101	1		T104	6
valid_sources[0x26]	5895	1			T65	4		T96	1		T104	13
valid_sources[0x27]	6133	1			T65	2		T102	8		T104	2
valid_sources[0x28]	7931	1			T65	3		T104	2		T110	2
valid_sources[0x29]	6253	1			T65	7		T104	2		T110	2
valid_sources[0x2a]	6315	1			T65	2		T110	1		T128	1
valid_sources[0x2b]	6143	1			T65	4		T110	2		T153	3
valid_sources[0x2c]	7285	1			T65	7		T97	8		T104	25
valid_sources[0x2d]	5579	1			T65	8		T104	4		T161	1
valid_sources[0x2e]	5358	1			T65	2		T101	1		T110	4
valid_sources[0x2f]	6632	1			T65	2		T104	4		T110	2
valid_sources[0x30]	5516	1			T65	1		T101	1		T110	4
valid_sources[0x31]	7259	1			T65	1		T104	4		T127	1
valid_sources[0x32]	5632	1			T104	4		T110	5		T128	6
valid_sources[0x33]	5661	1			T65	2		T104	9		T128	3
valid_sources[0x34]	5671	1			T65	1		T104	20		T113	7
valid_sources[0x35]	8358	1			T65	2		T104	3		T110	1
valid_sources[0x36]	42681	1			T65	3		T114	1		T123	1
valid_sources[0x37]	5945	1			T65	1		T98	4		T110	1
valid_sources[0x38]	5788	1			T65	3		T99	4		T128	3
valid_sources[0x39]	5792	1			T65	2		T104	4		T110	3
valid_sources[0x3a]	7541	1			T65	4		T101	1		T104	8
valid_sources[0x3b]	6173	1			T65	1		T113	6		T127	1
valid_sources[0x3c]	35894	1			T65	1		T96	1		T110	2
valid_sources[0x3d]	5699	1			T65	1		T101	1		T104	4
valid_sources[0x3e]	9471	1			T65	2		T104	1		T110	2
valid_sources[0x3f]	5504	1			T65	2		T110	2		T113	4
valid_sources[0x40]	6438	1			T65	3		T104	16		T110	2
valid_sources[0x41]	6166	1			T65	1		T104	6		T114	1
valid_sources[0x42]	5897	1			T65	3		T104	3		T110	1
valid_sources[0x43]	6217	1			T65	1		T104	1		T114	1
valid_sources[0x44]	6128	1			T65	3		T104	12		T113	1
valid_sources[0x45]	7572	1			T65	2		T123	1		T153	6
valid_sources[0x46]	5707	1			T65	2		T99	6		T123	1
valid_sources[0x47]	5858	1			T65	2		T101	1		T104	4
valid_sources[0x48]	5766	1			T65	2		T104	3		T110	2
valid_sources[0x49]	6343	1			T65	10		T96	1		T110	2
valid_sources[0x4a]	6615	1			T65	3		T104	8		T110	1
valid_sources[0x4b]	5934	1			T65	5		T110	2		T114	3
valid_sources[0x4c]	7784	1			T96	1		T101	1		T102	3
valid_sources[0x4d]	6103	1			T65	1		T101	1		T110	5
valid_sources[0x4e]	6195	1			T65	1		T99	7		T110	2
valid_sources[0x4f]	8781	1			T65	5		T114	2		T127	1
valid_sources[0x50]	6335	1			T65	3		T98	25		T99	2
valid_sources[0x51]	5579	1			T104	7		T110	2		T161	4
valid_sources[0x52]	6660	1			T65	1		T113	7		T128	2
valid_sources[0x53]	5644	1			T65	2		T98	11		T99	25
valid_sources[0x54]	5406	1			T65	6		T101	1		T110	1
valid_sources[0x55]	43013	1			T65	2		T96	1		T98	14
valid_sources[0x56]	5599	1			T65	1		T104	2		T110	2
valid_sources[0x57]	7043	1			T65	3		T98	2		T123	2
valid_sources[0x58]	10512	1			T65	3		T101	1		T102	3
valid_sources[0x59]	6854	1			T65	4		T110	1		T128	6
valid_sources[0x5a]	5702	1			T65	2		T97	6		T104	6
valid_sources[0x5b]	9501	1			T114	3		T123	1		T127	1
valid_sources[0x5c]	7282	1			T65	3		T104	10		T159	2
valid_sources[0x5d]	5437	1			T65	2		T97	3		T110	5
valid_sources[0x5e]	6145	1			T65	3		T101	1		T102	12
valid_sources[0x5f]	5552	1			T65	6		T110	2		T128	2
valid_sources[0x60]	7312	1			T65	4		T98	1		T104	25
valid_sources[0x61]	6024	1			T65	5		T110	1		T127	1
valid_sources[0x62]	7928	1			T65	6		T101	1		T110	1
valid_sources[0x63]	5715	1			T65	4		T110	3		T114	1
valid_sources[0x64]	5671	1			T65	2		T113	3		T128	2
valid_sources[0x65]	128150	1			T65	2		T110	1		T113	13
valid_sources[0x66]	6874	1			T65	2		T101	1		T110	1
valid_sources[0x67]	48814	1			T65	5		T110	2		T128	1
valid_sources[0x68]	7234	1			T65	1		T104	6		T110	4
valid_sources[0x69]	6278	1			T65	6		T110	1		T114	1
valid_sources[0x6a]	6907	1			T65	3		T110	1		T114	4
valid_sources[0x6b]	6107	1			T65	6		T101	1		T104	8
valid_sources[0x6c]	5576	1			T65	1		T98	1		T110	1
valid_sources[0x6d]	6001	1			T65	6		T99	3		T101	1
valid_sources[0x6e]	7250	1			T65	1		T104	11		T114	1
valid_sources[0x6f]	5935	1			T65	4		T97	10		T104	6
valid_sources[0x70]	7153	1			T65	2		T110	2		T128	2
valid_sources[0x71]	10419	1			T65	6		T110	2		T123	2
valid_sources[0x72]	5986	1			T65	4		T98	2		T110	1
valid_sources[0x73]	5792	1			T65	1		T104	4		T113	9
valid_sources[0x74]	5533	1			T65	2		T101	1		T104	3
valid_sources[0x75]	7517	1			T65	5		T101	1		T110	1
valid_sources[0x76]	8017	1			T65	4		T104	1		T114	2
valid_sources[0x77]	6482	1			T65	2		T110	1		T128	1
valid_sources[0x78]	5680	1			T65	4		T110	1		T114	2
valid_sources[0x79]	7380	1			T65	4		T102	2		T104	2
valid_sources[0x7a]	9253	1			T65	5		T102	1		T110	2
valid_sources[0x7b]	5797	1			T65	3		T96	1		T101	1
valid_sources[0x7c]	7033	1			T65	5		T110	3		T161	1
valid_sources[0x7d]	6201	1			T65	1		T102	8		T110	3
valid_sources[0x7e]	5698	1			T65	1		T98	2		T104	3
valid_sources[0x7f]	5778	1			T65	2		T110	3		T114	1
valid_sources[0x80]	5683	1			T65	3		T104	4		T110	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

904886

1

T65

26

T96

3

T97

2

values[0x0]

all_enables

biggest_size

122612

1

T65

289

T96

3

T97

25

values[0x1]

all_enables

biggest_size

122154

1

T65

295

T96

5

T97

31