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 LINE       1290
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T65,T97,T98
1	0	1	Covered	T65,T97,T98
1	1	0	Covered	T128,T143,T142
1	1	1	Covered	T1,T3,T5

 LINE       1291
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T65,T97,T98
1	0	1	Covered	T65,T97,T98
1	1	0	Covered	T137
1	1	1	Covered	T1,T3,T5

 LINE       1292
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T65,T97,T98
1	0	1	Covered	T65,T96,T97
1	1	0	Covered	T104,T144,T136
1	1	1	Covered	T1,T3,T5

 LINE       1293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T65,T97,T98
1	0	1	Covered	T65,T97,T98
1	1	0	Covered	T65,T143,T132
1	1	1	Covered	T1,T3,T5

 LINE       1294
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T65,T97,T98
1	0	1	Covered	T65,T97,T98
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5