Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	63820019	15314	0	0
claim_transition_if_regwen_rd_A	63820019	1669	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63820019	15314	0	0
T65	8237	5	0	0
T96	4553	2	0	0
T97	1435	0	0	0
T98	1565	0	0	0
T99	2427	0	0	0
T100	8817	0	0	0
T101	1438	0	0	0
T102	884	0	0	0
T103	7147	0	0	0
T104	10843	8	0	0
T110	0	5	0	0
T111	0	10	0	0
T114	0	62	0	0
T115	0	140	0	0
T123	0	109	0	0
T128	0	5	0	0
T153	0	39	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63820019	1669	0	0
T104	10843	42	0	0
T109	1252	0	0	0
T110	6439	45	0	0
T113	4621	46	0	0
T114	2671	24	0	0
T115	6227	0	0	0
T122	86853	0	0	0
T128	4226	0	0	0
T145	3760	0	0	0
T153	0	10	0	0
T154	0	131	0	0
T155	0	9	0	0
T156	0	27	0	0
T157	0	8	0	0
T158	0	154	0	0
T159	4013	0	0	0