Unified Coverage Report :: Module :: lc_ctrl_fsm

Module : lc_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	97.73	89.13		75.51	97.33	93.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm	96.32	97.73	93.18		100.00	97.33	93.33

---

Module Instance : tb.dut.u_lc_ctrl_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	97.73	93.18		100.00	97.33	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.58	98.86	90.77		100.00	96.12	97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt_regs	100.00	100.00				100.00	100.00
u_fsm_state_regs	100.00	100.00				100.00	100.00
u_lc_ctrl_fsm_cov_if	96.97	100.00	90.91			100.00
u_lc_ctrl_signal_decode	98.86	99.21				97.37	100.00
u_lc_ctrl_state_decode	98.89	100.00	100.00			96.67
u_lc_ctrl_state_transition	89.21	96.92	79.17			91.53
u_prim_lc_sender_check_byp_en	100.00	100.00				100.00
u_prim_lc_sender_clk_byp_req	100.00	100.00				100.00
u_prim_lc_sender_flash_rma_req	100.00	100.00				100.00
u_prim_lc_sync_clk_byp_ack	100.00	100.00				100.00	100.00
u_prim_lc_sync_flash_rma_ack	100.00	100.00				100.00	100.00
u_prim_lc_sync_rma_token_valid	100.00	100.00					100.00
u_prim_lc_sync_test_token_valid	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		176	172	97.73
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	176	114	110	96.49
ALWAYS	556	3	3	100.00
ALWAYS	557	3	3	100.00
ALWAYS	558	3	3	100.00
ALWAYS	561	3	3	100.00
ALWAYS	580	5	5	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	649	15	15	100.00
ALWAYS	684	14	14	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
ALWAYS	852	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
125	1	1
143	1	1
150	1	1
151	1	1
176	1	1
177	1	1
178	1	1
181	1	1
182	1	1
185	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
195	1	1
196	1	1
203	1	1
204	1	1
210	1	1
211	1	1
212	1	1
214	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
			MISSING_ELSE
235	1	1
245	1	1
249	1	1
250	1	1
			MISSING_ELSE
256	1	1
257	1	1
265	1	1
267	1	1
271	1	1
273	1	1
277	1	1
281	1	1
284	1	1
286	1	1
288	0	1
289	0	1
293	1	1
298	1	1
299	1	1
			MISSING_ELSE
305	1	1
322	1	1
323	1	1
			MISSING_ELSE
			MISSING_ELSE
336	1	1
337	1	1
354	1	1
355	1	1
356	1	1
357	1	1
			MISSING_ELSE
360	1	1
363	1	1
370	1	1
371	1	1
373	1	1
379	1	1
383	1	1
384	1	1
385	1	1
			MISSING_ELSE
390	1	1
391	1	1
392	1	1
393	1	1
395	1	1
			MISSING_ELSE
403	1	1
404	1	1
406	1	1
417	1	1
418	1	1
424	1	1
427	1	1
429	1	1
430	1	1
			MISSING_ELSE
438	1	1
439	1	1
440	1	1
441	1	1
			MISSING_ELSE
444	1	1
454	1	1
455	1	1
459	1	1
465	1	1
468	1	1
471	1	1
473	1	1
476	0	1
477	0	1
481	1	1
482	1	1
492	1	1
496	1	1
497	1	1
498	1	1
501	1	1
505	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
			MISSING_ELSE
516	1	1
521	1	1
526	1	1
527	1	1
539	1	1
540	1	1
546	1	1
547	1	1
548	1	1
			MISSING_ELSE
556	3	3
557	3	3
558	3	3
561	1	1
562	1	1
564	1	1
580	1	1
581	1	1
582	1	1
584	1	1
587	1	1
591	1	1
638	1	1
639	1	1
640	1	1
649	1	1
651	1	1
653	1	1
656	1	1
657	1	1
			MISSING_ELSE
659	1	1
660	1	1
			MISSING_ELSE
663	1	1
664	1	1
			MISSING_ELSE
666	1	1
667	1	1
			MISSING_ELSE
670	1	1
671	1	1
			MISSING_ELSE
673	1	1
674	1	1
			MISSING_ELSE
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
690	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
697	1	1
698	1	1
704	1	1
708	1	1
712	1	1
714	1	1
721	1	1
852	3	3

---

Cond Coverage for Module : lc_ctrl_fsm

	Total	Covered	Percent
Conditions	92	82	89.13
Logical	92	82	89.13
Non-Logical	0	0
Event	0	0

 LINE       223
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       256
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T14

 LINE       265
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i)
             -----------1----------    ----------2----------    -----3-----

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T4,T5
-	1	0	Covered	T37,T6,T38
-	1	1	Covered	T37,T38,T39

 LINE       267
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T39,T40,T41

 LINE       267
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Covered	T39,T40,T43
1	Covered	T37,T38,T39

 LINE       267
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T37,T38,T39
1	Covered	T39,T40,T41

 LINE       271
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T39,T40,T41

 LINE       277
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T53

 LINE       277
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T53

 LINE       383
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T44,T45,T29

 LINE       424
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T44
1	0	1	Covered	T44,T45,T29
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       424
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T10,T12,T44
1	Covered	T1,T4,T5

 LINE       438
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       465
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       465
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       468
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       496
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T54,T55,T56

 LINE       501
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T57,T58,T59
1	0	Covered	T60,T61,T62

 LINE       501
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off)))
                 -----------------------------------1----------------------------------    ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T60,T61,T62

 LINE       501
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))
                 -------------1-------------    --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T60,T61,T62
1	0	Not Covered

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_ack[1] != Off)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On)))
                 -----------------------------------1----------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T57,T58,T59

 LINE       501
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T57,T58,T59
1	0	Covered	T63

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_ack[1] != On)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       539
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       546
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       546
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       546
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       584
 SUB-EXPRESSION (set_strap_en_override || gen_strap_delay_regs.strap_en_override_q[0])
                 ----------1----------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41

 LINE       704
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       704
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T6,T38,T64
1	1	Covered	T1,T2,T3

 LINE       708
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       708
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T6,T38,T64
1	1	Covered	T1,T2,T3

 LINE       721
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T30,T46
1	0	Covered	T44,T37,T45

 LINE       721
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T30,T46

---

FSM Coverage for Module : lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	47	35	74.47
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	299	Covered	T65
CntIncrSt	357	Covered	T65
CntProgSt	373	Covered	T65
EscalateSt	540	Covered	T65
FlashRmaSt	427	Covered	T65
IdleSt	224	Covered	T65
InvalidSt	547	Covered	T65
PostTransSt	289	Covered	T65
ResetSt	218	Covered	T65
ScrapSt	257	Covered	T65
TokenCheck0St	441	Covered	T65
TokenCheck1St	473	Covered	T65
TokenHashSt	406	Covered	T65
TransCheckSt	395	Covered	T65
TransProgSt	471	Covered	T65

transitions	Line No.	Covered	Tests
ClkMuxSt->CntIncrSt	357	Covered	T65
ClkMuxSt->EscalateSt	540	Covered	T65
ClkMuxSt->InvalidSt	547	Not Covered
CntIncrSt->CntProgSt	373	Covered	T65
CntIncrSt->EscalateSt	540	Covered	T65
CntIncrSt->InvalidSt	547	Not Covered
CntIncrSt->PostTransSt	371	Covered	T65
CntProgSt->EscalateSt	540	Covered	T65
CntProgSt->InvalidSt	547	Not Covered
CntProgSt->PostTransSt	384	Covered	T65
CntProgSt->TransCheckSt	395	Covered	T65
EscalateSt->InvalidSt	547	Not Covered
FlashRmaSt->EscalateSt	540	Covered	T65
FlashRmaSt->InvalidSt	547	Not Covered
FlashRmaSt->TokenCheck0St	441	Covered	T65
IdleSt->ClkMuxSt	299	Covered	T65
IdleSt->EscalateSt	540	Covered	T65
IdleSt->InvalidSt	547	Covered	T65
IdleSt->PostTransSt	289	Covered	T65
IdleSt->ScrapSt	257	Covered	T65
InvalidSt->EscalateSt	540	Covered	T65
PostTransSt->EscalateSt	540	Covered	T65
PostTransSt->InvalidSt	547	Not Covered
ResetSt->EscalateSt	540	Covered	T65
ResetSt->IdleSt	224	Covered	T65
ResetSt->InvalidSt	547	Not Covered
ScrapSt->EscalateSt	540	Covered	T65
ScrapSt->InvalidSt	547	Covered	T65
TokenCheck0St->EscalateSt	540	Covered	T65
TokenCheck0St->InvalidSt	547	Not Covered
TokenCheck0St->PostTransSt	455	Covered	T65
TokenCheck0St->TokenCheck1St	473	Covered	T65
TokenCheck1St->EscalateSt	540	Covered	T65
TokenCheck1St->InvalidSt	547	Not Covered
TokenCheck1St->PostTransSt	455	Covered	T65
TokenCheck1St->TransProgSt	471	Covered	T65
TokenHashSt->EscalateSt	540	Covered	T65
TokenHashSt->FlashRmaSt	427	Covered	T65
TokenHashSt->InvalidSt	547	Not Covered
TokenHashSt->PostTransSt	429	Covered	T65
TransCheckSt->EscalateSt	540	Covered	T65
TransCheckSt->InvalidSt	547	Not Covered
TransCheckSt->PostTransSt	404	Covered	T65
TransCheckSt->TokenHashSt	406	Covered	T65
TransProgSt->EscalateSt	540	Covered	T65
TransProgSt->InvalidSt	547	Not Covered
TransProgSt->PostTransSt	497	Covered	T65

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	12	57.14	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Not Covered
LcStProd	93	Not Covered
LcStProdEnd	94	Not Covered
LcStRaw	267	Covered	T65
LcStRma	305	Not Covered
LcStScrap	256	Not Covered
LcStTestLocked0	305	Covered	T65
LcStTestLocked1	305	Covered	T65
LcStTestLocked2	305	Covered	T65
LcStTestLocked3	305	Covered	T65
LcStTestLocked4	305	Covered	T65
LcStTestLocked5	305	Not Covered
LcStTestLocked6	305	Not Covered
LcStTestUnlocked0	273	Covered	T65
LcStTestUnlocked1	305	Covered	T65
LcStTestUnlocked2	305	Covered	T65
LcStTestUnlocked3	305	Covered	T65
LcStTestUnlocked4	305	Covered	T65
LcStTestUnlocked5	305	Covered	T65
LcStTestUnlocked6	305	Not Covered
LcStTestUnlocked7	305	Not Covered

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	273	Covered	T65

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	6	24.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	277	Covered	T65
LcCnt1	277	Covered	T65
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Covered	T65
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Covered	T65
LcCnt4	106	Covered	T65
LcCnt5	107	Covered	T65
LcCnt6	108	Not Covered
LcCnt7	109	Not Covered
LcCnt8	110	Not Covered
LcCnt9	111	Not Covered

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	277	Covered	T65

---

Branch Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		75	73	97.33
TERNARY	704	1	1	100.00
TERNARY	708	1	1	100.00
CASE	214	46	44	95.65
IF	539	3	3	100.00
IF	556	2	2	100.00
IF	557	2	2	100.00
IF	558	2	2	100.00
IF	561	2	2	100.00
IF	656	2	2	100.00
IF	659	2	2	100.00
IF	663	2	2	100.00
IF	666	2	2	100.00
IF	670	2	2	100.00
IF	673	2	2	100.00
IF	852	2	2	100.00
IF	580	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	704	(((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	708	(((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	214	case (fsm_state_q)
-2-:	223	if ((init_req_i && lc_state_valid_q))
-3-:	245	if (((!((SecVolatileRawUnlockEn && (lc_state_q == LcStTestUnlocked0)) && (lc_cnt_q != LcCnt0))) || prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)))
-4-:	256	if ((lc_state_q == LcStScrap))
-5-:	265	if (((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i))
-6-:	267	if ((((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})) && (!trans_invalid_error_o)))
-7-:	271	if ((unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed))
-8-:	277	((lc_cnt_q == LcCnt0)) ? 
-9-:	298	if (trans_cmd_i)
-10-:	305	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-11-:	322	if (use_ext_clock_i)
-12-:	337	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-13-:	354	if (use_ext_clock_i)
-14-:	356	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_ack[0]))
-15-:	370	if (trans_cnt_oflw_error_o)
-16-:	383	if ((lc_clk_byp_req_o != lc_clk_byp_ack[1]))
-17-:	390	if (otp_prog_ack_i)
-18-:	391	if (otp_prog_err_i)
-19-:	403	if (trans_invalid_error_o)
-20-:	418	if (token_hash_ack_i)
-21-:	424	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-22-:	438	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}))
-23-:	440	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack[0]))
-24-:	454	if (trans_invalid_error_o)
-25-:	459	if (((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_ack[1])) || (((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack[1]))))
-26-:	465	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-27-:	468	if ((fsm_state_q == TokenCheck1St))
-28-:	496	if ((lc_clk_byp_req_o != lc_clk_byp_ack[2]))
-29-:	501	if ((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))) || ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On)))))
-30-:	507	if (otp_prog_ack_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T41
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T53
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T41
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T37,T38,T39
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T52,T16,T6
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T52,T16,T66
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T61,T67,T68
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T45,T29
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T45,T29
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T69
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T44,T45
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T44
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T30,T46
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T1,T4,T5
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T1,T4,T5
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T44,T45,T29
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T54,T55,T56
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T57,T58,T59
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T1,T4,T5
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T1,T4,T5
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	539	if ((esc_scrap_state0_i || esc_scrap_state1_i))
-2-:	546	if ((((|state_invalid_error) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	656	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	659	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	663	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[2]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	666	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[3]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	670	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	673	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	852	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	580	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClkBypStaysOnOnceAsserted_A	61658664	2756846	0	67
EscStaysOnOnceAsserted_A	61658664	10773452	0	4
FlashRmaStaysOnOnceAsserted_A	61658664	441203	0	15
FsmStateKnown_A	61658664	58550652	0	0
LcCntKnown_A	61658664	58550652	0	0
LcStateKnown_A	61658664	58550652	0	0
NoClkBypInProdStates_A	61658664	8246081	0	0
SecCmCFILinear_A	61658664	0	0	1906
SecCmCFITerminal0_A	61658664	8521474	0	0
SecCmCFITerminal1_A	61658664	36378	0	0
SecCmCFITerminal2_A	61658664	4696810	0	0
SecCmCFITerminal3_A	61658664	6053078	0	0
u_cnt_regs_A	57363526	54535074	0	0
u_fsm_state_regs_A	60312565	57292466	0	0
u_state_regs_A	58283628	55445214	0	0

ClkBypStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	2756846	0	67
T6	22176	20929	0	1
T9	0	0	0	1
T16	78692	25082	0	1
T17	41682	0	0	0
T29	24876	0	0	0
T30	21410	0	0	0
T37	773	0	0	0
T44	40535	0	0	0
T52	4491	250	0	0
T53	0	0	0	1
T61	0	23953	0	0
T66	0	3863	0	0
T67	0	0	0	1
T70	0	34056	0	0
T71	0	629	0	0
T72	0	25844	0	0
T73	0	370	0	0
T74	0	476	0	0
T75	6770	0	0	0
T76	1325	0	0	0
T77	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1
T81	0	0	0	1

EscStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	10773452	0	4
T1	10393	3706	0	0
T2	149453	114802	0	0
T3	20388	13262	0	0
T4	124915	23234	0	0
T5	127471	35581	0	0
T10	31440	0	0	0
T11	31887	22410	0	0
T12	53800	0	0	0
T13	1641	194	0	0
T14	19946	4735	0	0
T15	0	6979	0	0
T21	0	1166	0	0
T82	0	0	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1

FlashRmaStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	441203	0	15
T1	10393	766	0	0
T2	149453	0	0	0
T3	20388	0	0	0
T4	124915	12165	0	0
T5	127471	3689	0	0
T10	31440	147	0	0
T11	31887	0	0	0
T12	53800	0	0	0
T13	1641	0	0	0
T14	19946	0	0	0
T18	0	966	0	0
T20	0	0	0	1
T21	0	205	0	0
T44	0	354	0	0
T45	0	1010	0	0
T52	0	20	0	0
T73	0	0	0	1
T74	0	0	0	1
T75	0	677	0	0
T78	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1
T88	0	0	0	1
T89	0	0	0	1
T90	0	0	0	1
T91	0	0	0	1

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	58550652	0	0
T1	10393	9356	0	0
T2	149453	144296	0	0
T3	20388	16037	0	0
T4	124915	123830	0	0
T5	127471	120422	0	0
T10	31440	25281	0	0
T11	31887	25819	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	19946	10691	0	0

LcCntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	58550652	0	0
T1	10393	9356	0	0
T2	149453	144296	0	0
T3	20388	16037	0	0
T4	124915	123830	0	0
T5	127471	120422	0	0
T10	31440	25281	0	0
T11	31887	25819	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	19946	10691	0	0

LcStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	58550652	0	0
T1	10393	9356	0	0
T2	149453	144296	0	0
T3	20388	16037	0	0
T4	124915	123830	0	0
T5	127471	120422	0	0
T10	31440	25281	0	0
T11	31887	25819	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	19946	10691	0	0

NoClkBypInProdStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	8246081	0	0
T1	10393	2319	0	0
T2	149453	15598	0	0
T3	20388	1983	0	0
T4	124915	9324	0	0
T5	127471	14380	0	0
T10	31440	2940	0	0
T11	31887	3154	0	0
T12	53800	6120	0	0
T13	1641	170	0	0
T14	19946	1373	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	0	0	1906

SecCmCFITerminal0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	8521474	0	0
T1	10393	1258	0	0
T2	149453	0	0	0
T3	20388	0	0	0
T4	124915	57782	0	0
T5	127471	38576	0	0
T10	31440	12122	0	0
T11	31887	0	0	0
T12	53800	15229	0	0
T13	1641	14	0	0
T14	19946	0	0	0
T15	0	9589	0	0
T21	0	910	0	0
T51	0	1587	0	0
T52	0	1329	0	0

SecCmCFITerminal1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	36378	0	0
T5	127471	7	0	0
T10	31440	0	0	0
T11	31887	0	0	0
T12	53800	0	0	0
T13	1641	194	0	0
T14	19946	6	0	0
T15	40753	0	0	0
T21	4397	0	0	0
T34	0	6	0	0
T36	0	3	0	0
T51	6906	0	0	0
T52	4491	0	0	0
T70	0	3352	0	0
T92	0	3	0	0
T93	0	6	0	0
T94	0	9	0	0
T95	0	7	0	0

SecCmCFITerminal2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	4696810	0	0
T1	10393	2208	0	0
T2	149453	28642	0	0
T3	20388	6965	0	0
T4	124915	9367	0	0
T5	127471	21968	0	0
T10	31440	0	0	0
T11	31887	10416	0	0
T12	53800	0	0	0
T13	1641	0	0	0
T14	19946	0	0	0
T15	0	6992	0	0
T21	0	852	0	0
T44	0	1650	0	0
T51	0	810	0	0

SecCmCFITerminal3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	6053078	0	0
T1	10393	1502	0	0
T2	149453	86189	0	0
T3	20388	6323	0	0
T4	124915	13868	0	0
T5	127471	13640	0	0
T10	31440	0	0	0
T11	31887	12030	0	0
T12	53800	0	0	0
T13	1641	0	0	0
T14	19946	4766	0	0
T21	0	318	0	0
T51	0	717	0	0
T75	0	842	0	0

u_cnt_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57363526	54535074	0	0
T1	7910	7148	0	0
T2	109137	105334	0	0
T3	12087	9407	0	0
T4	115429	114423	0	0
T5	111732	106038	0	0
T10	31440	25281	0	0
T11	20071	16104	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	14874	5619	0	0

u_fsm_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60312565	57292466	0	0
T1	9793	8831	0	0
T2	136574	131895	0	0
T3	17710	13926	0	0
T4	116741	115728	0	0
T5	125726	119097	0	0
T10	31440	25281	0	0
T11	28189	22839	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	14874	5619	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58283628	55445214	0	0
T1	8985	8187	0	0
T2	106581	102975	0	0
T3	14574	11645	0	0
T4	118933	117916	0	0
T5	110986	106435	0	0
T10	31440	25281	0	0
T11	21203	17238	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	14874	5619	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		176	172	97.73
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	176	114	110	96.49
ALWAYS	556	3	3	100.00
ALWAYS	557	3	3	100.00
ALWAYS	558	3	3	100.00
ALWAYS	561	3	3	100.00
ALWAYS	580	5	5	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	649	15	15	100.00
ALWAYS	684	14	14	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
ALWAYS	852	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
125	1	1
143	1	1
150	1	1
151	1	1
176	1	1
177	1	1
178	1	1
181	1	1
182	1	1
185	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
195	1	1
196	1	1
203	1	1
204	1	1
210	1	1
211	1	1
212	1	1
214	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
			MISSING_ELSE
235	1	1
245	1	1
249	1	1
250	1	1
			MISSING_ELSE
256	1	1
257	1	1
265	1	1
267	1	1
271	1	1
273	1	1
277	1	1
281	1	1
284	1	1
286	1	1
288	0	1
289	0	1
293	1	1
298	1	1
299	1	1
			MISSING_ELSE
305	1	1
322	1	1
323	1	1
			MISSING_ELSE
			MISSING_ELSE
336	1	1
337	1	1
354	1	1
355	1	1
356	1	1
357	1	1
			MISSING_ELSE
360	1	1
363	1	1
370	1	1
371	1	1
373	1	1
379	1	1
383	1	1
384	1	1
385	1	1
			MISSING_ELSE
390	1	1
391	1	1
392	1	1
393	1	1
395	1	1
			MISSING_ELSE
403	1	1
404	1	1
406	1	1
417	1	1
418	1	1
424	1	1
427	1	1
429	1	1
430	1	1
			MISSING_ELSE
438	1	1
439	1	1
440	1	1
441	1	1
			MISSING_ELSE
444	1	1
454	1	1
455	1	1
459	1	1
465	1	1
468	1	1
471	1	1
473	1	1
476	0	1
477	0	1
481	1	1
482	1	1
492	1	1
496	1	1
497	1	1
498	1	1
501	1	1
505	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
			MISSING_ELSE
516	1	1
521	1	1
526	1	1
527	1	1
539	1	1
540	1	1
546	1	1
547	1	1
548	1	1
			MISSING_ELSE
556	3	3
557	3	3
558	3	3
561	1	1
562	1	1
564	1	1
580	1	1
581	1	1
582	1	1
584	1	1
587	1	1
591	1	1
638	1	1
639	1	1
640	1	1
649	1	1
651	1	1
653	1	1
656	1	1
657	1	1
			MISSING_ELSE
659	1	1
660	1	1
			MISSING_ELSE
663	1	1
664	1	1
			MISSING_ELSE
666	1	1
667	1	1
			MISSING_ELSE
670	1	1
671	1	1
			MISSING_ELSE
673	1	1
674	1	1
			MISSING_ELSE
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
690	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
697	1	1
698	1	1
704	1	1
708	1	1
712	1	1
714	1	1
721	1	1
852	3	3

---

Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Covered	Percent
Conditions	88	82	93.18
Logical	88	82	93.18
Non-Logical	0	0
Event	0	0

 LINE       223
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       256
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T14

 LINE       265
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i)
             -----------1----------    ----------2----------    -----3-----

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T4,T5
-	1	0	Covered	T37,T6,T38
-	1	1	Covered	T37,T38,T39

 LINE       267
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T39,T40,T41

 LINE       267
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Covered	T39,T40,T43
1	Covered	T37,T38,T39

 LINE       267
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T37,T38,T39
1	Covered	T39,T40,T41

 LINE       271
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T39,T40,T41

 LINE       277
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T53

 LINE       277
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T53

 LINE       383
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T44,T45,T29

 LINE       424
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T44
1	0	1	Covered	T44,T45,T29
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       424
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T10,T12,T44
1	Covered	T1,T4,T5

 LINE       438
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       465
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       465
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       468
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       496
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T54,T55,T56

 LINE       501
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T57,T58,T59
1	0	Covered	T60,T61,T62

 LINE       501
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off)))
                 -----------------------------------1----------------------------------    ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T60,T61,T62

 LINE       501
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))
                 -------------1-------------    --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T60,T61,T62
1	0	Not Covered

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_ack[1] != Off)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On)))
                 -----------------------------------1----------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T57,T58,T59

 LINE       501
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T57,T58,T59
1	0	Covered	T63

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_ack[1] != On)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       539
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       546
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       546
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       546
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       584
 SUB-EXPRESSION (set_strap_en_override || gen_strap_delay_regs.strap_en_override_q[0])
                 ----------1----------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41

 LINE       704
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       704
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T6,T38,T64
1	1	Covered	T1,T2,T3

 LINE       708
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       708
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T6,T38,T64
1	1	Covered	T1,T2,T3

 LINE       721
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T30,T46
1	0	Covered	T44,T37,T45

 LINE       721
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T30,T46

---

FSM Coverage for Instance : tb.dut.u_lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	35	35	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	299	Covered	T65
CntIncrSt	357	Covered	T65
CntProgSt	373	Covered	T65
EscalateSt	540	Covered	T65
FlashRmaSt	427	Covered	T65
IdleSt	224	Covered	T65
InvalidSt	547	Covered	T65
PostTransSt	289	Covered	T65
ResetSt	218	Covered	T65
ScrapSt	257	Covered	T65
TokenCheck0St	441	Covered	T65
TokenCheck1St	473	Covered	T65
TokenHashSt	406	Covered	T65
TransCheckSt	395	Covered	T65
TransProgSt	471	Covered	T65

transitions	Line No.	Covered	Tests	Exclude Annotation
ClkMuxSt->CntIncrSt	357	Covered	T65
ClkMuxSt->EscalateSt	540	Covered	T65
ClkMuxSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->CntProgSt	373	Covered	T65
CntIncrSt->EscalateSt	540	Covered	T65
CntIncrSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->PostTransSt	371	Covered	T65
CntProgSt->EscalateSt	540	Covered	T65
CntProgSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntProgSt->PostTransSt	384	Covered	T65
CntProgSt->TransCheckSt	395	Covered	T65
EscalateSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
FlashRmaSt->EscalateSt	540	Covered	T65
FlashRmaSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
FlashRmaSt->TokenCheck0St	441	Covered	T65
IdleSt->ClkMuxSt	299	Covered	T65
IdleSt->EscalateSt	540	Covered	T65
IdleSt->InvalidSt	547	Covered	T65
IdleSt->PostTransSt	289	Covered	T65
IdleSt->ScrapSt	257	Covered	T65
InvalidSt->EscalateSt	540	Covered	T65
PostTransSt->EscalateSt	540	Covered	T65
PostTransSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ResetSt->EscalateSt	540	Covered	T65
ResetSt->IdleSt	224	Covered	T65
ResetSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ScrapSt->EscalateSt	540	Covered	T65
ScrapSt->InvalidSt	547	Covered	T65
TokenCheck0St->EscalateSt	540	Covered	T65
TokenCheck0St->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck0St->PostTransSt	455	Covered	T65
TokenCheck0St->TokenCheck1St	473	Covered	T65
TokenCheck1St->EscalateSt	540	Covered	T65
TokenCheck1St->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck1St->PostTransSt	455	Covered	T65
TokenCheck1St->TransProgSt	471	Covered	T65
TokenHashSt->EscalateSt	540	Covered	T65
TokenHashSt->FlashRmaSt	427	Covered	T65
TokenHashSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenHashSt->PostTransSt	429	Covered	T65
TransCheckSt->EscalateSt	540	Covered	T65
TransCheckSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransCheckSt->PostTransSt	404	Covered	T65
TransCheckSt->TokenHashSt	406	Covered	T65
TransProgSt->EscalateSt	540	Covered	T65
TransProgSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransProgSt->PostTransSt	497	Covered	T65

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	12	57.14	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Not Covered
LcStProd	93	Not Covered
LcStProdEnd	94	Not Covered
LcStRaw	267	Covered	T65
LcStRma	305	Not Covered
LcStScrap	256	Not Covered
LcStTestLocked0	305	Covered	T65
LcStTestLocked1	305	Covered	T65
LcStTestLocked2	305	Covered	T65
LcStTestLocked3	305	Covered	T65
LcStTestLocked4	305	Covered	T65
LcStTestLocked5	305	Not Covered
LcStTestLocked6	305	Not Covered
LcStTestUnlocked0	273	Covered	T65
LcStTestUnlocked1	305	Covered	T65
LcStTestUnlocked2	305	Covered	T65
LcStTestUnlocked3	305	Covered	T65
LcStTestUnlocked4	305	Covered	T65
LcStTestUnlocked5	305	Covered	T65
LcStTestUnlocked6	305	Not Covered
LcStTestUnlocked7	305	Not Covered

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	273	Covered	T65

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	6	24.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	277	Covered	T65
LcCnt1	277	Covered	T65
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Covered	T65
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Covered	T65
LcCnt4	106	Covered	T65
LcCnt5	107	Covered	T65
LcCnt6	108	Not Covered
LcCnt7	109	Not Covered
LcCnt8	110	Not Covered
LcCnt9	111	Not Covered

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	277	Covered	T65

---

Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		75	73	97.33
TERNARY	704	1	1	100.00
TERNARY	708	1	1	100.00
CASE	214	46	44	95.65
IF	539	3	3	100.00
IF	556	2	2	100.00
IF	557	2	2	100.00
IF	558	2	2	100.00
IF	561	2	2	100.00
IF	656	2	2	100.00
IF	659	2	2	100.00
IF	663	2	2	100.00
IF	666	2	2	100.00
IF	670	2	2	100.00
IF	673	2	2	100.00
IF	852	2	2	100.00
IF	580	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	704	(((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	708	(((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	214	case (fsm_state_q)
-2-:	223	if ((init_req_i && lc_state_valid_q))
-3-:	245	if (((!((SecVolatileRawUnlockEn && (lc_state_q == LcStTestUnlocked0)) && (lc_cnt_q != LcCnt0))) || prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)))
-4-:	256	if ((lc_state_q == LcStScrap))
-5-:	265	if (((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i))
-6-:	267	if ((((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})) && (!trans_invalid_error_o)))
-7-:	271	if ((unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed))
-8-:	277	((lc_cnt_q == LcCnt0)) ? 
-9-:	298	if (trans_cmd_i)
-10-:	305	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-11-:	322	if (use_ext_clock_i)
-12-:	337	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-13-:	354	if (use_ext_clock_i)
-14-:	356	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_ack[0]))
-15-:	370	if (trans_cnt_oflw_error_o)
-16-:	383	if ((lc_clk_byp_req_o != lc_clk_byp_ack[1]))
-17-:	390	if (otp_prog_ack_i)
-18-:	391	if (otp_prog_err_i)
-19-:	403	if (trans_invalid_error_o)
-20-:	418	if (token_hash_ack_i)
-21-:	424	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-22-:	438	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}))
-23-:	440	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack[0]))
-24-:	454	if (trans_invalid_error_o)
-25-:	459	if (((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_ack[1])) || (((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack[1]))))
-26-:	465	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-27-:	468	if ((fsm_state_q == TokenCheck1St))
-28-:	496	if ((lc_clk_byp_req_o != lc_clk_byp_ack[2]))
-29-:	501	if ((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))) || ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On)))))
-30-:	507	if (otp_prog_ack_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T41
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T53
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T41
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T37,T38,T39
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T52,T16,T6
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T52,T16,T66
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T61,T67,T68
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T45,T29
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T45,T29
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T69
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T44,T45
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T44
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T30,T46
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T1,T4,T5
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T1,T4,T5
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T44,T45,T29
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T54,T55,T56
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T57,T58,T59
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T1,T4,T5
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T1,T4,T5
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	539	if ((esc_scrap_state0_i || esc_scrap_state1_i))
-2-:	546	if ((((|state_invalid_error) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	656	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	659	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	663	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[2]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	666	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[3]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	670	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	673	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T33,T57,T49

	LineNo.	Expression
-1-:	852	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	580	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClkBypStaysOnOnceAsserted_A	61658664	2756846	0	67
EscStaysOnOnceAsserted_A	61658664	10773452	0	4
FlashRmaStaysOnOnceAsserted_A	61658664	441203	0	15
FsmStateKnown_A	61658664	58550652	0	0
LcCntKnown_A	61658664	58550652	0	0
LcStateKnown_A	61658664	58550652	0	0
NoClkBypInProdStates_A	61658664	8246081	0	0
SecCmCFILinear_A	61658664	0	0	1906
SecCmCFITerminal0_A	61658664	8521474	0	0
SecCmCFITerminal1_A	61658664	36378	0	0
SecCmCFITerminal2_A	61658664	4696810	0	0
SecCmCFITerminal3_A	61658664	6053078	0	0
u_cnt_regs_A	57363526	54535074	0	0
u_fsm_state_regs_A	60312565	57292466	0	0
u_state_regs_A	58283628	55445214	0	0

ClkBypStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	2756846	0	67
T6	22176	20929	0	1
T9	0	0	0	1
T16	78692	25082	0	1
T17	41682	0	0	0
T29	24876	0	0	0
T30	21410	0	0	0
T37	773	0	0	0
T44	40535	0	0	0
T52	4491	250	0	0
T53	0	0	0	1
T61	0	23953	0	0
T66	0	3863	0	0
T67	0	0	0	1
T70	0	34056	0	0
T71	0	629	0	0
T72	0	25844	0	0
T73	0	370	0	0
T74	0	476	0	0
T75	6770	0	0	0
T76	1325	0	0	0
T77	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1
T81	0	0	0	1

EscStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	10773452	0	4
T1	10393	3706	0	0
T2	149453	114802	0	0
T3	20388	13262	0	0
T4	124915	23234	0	0
T5	127471	35581	0	0
T10	31440	0	0	0
T11	31887	22410	0	0
T12	53800	0	0	0
T13	1641	194	0	0
T14	19946	4735	0	0
T15	0	6979	0	0
T21	0	1166	0	0
T82	0	0	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1

FlashRmaStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	441203	0	15
T1	10393	766	0	0
T2	149453	0	0	0
T3	20388	0	0	0
T4	124915	12165	0	0
T5	127471	3689	0	0
T10	31440	147	0	0
T11	31887	0	0	0
T12	53800	0	0	0
T13	1641	0	0	0
T14	19946	0	0	0
T18	0	966	0	0
T20	0	0	0	1
T21	0	205	0	0
T44	0	354	0	0
T45	0	1010	0	0
T52	0	20	0	0
T73	0	0	0	1
T74	0	0	0	1
T75	0	677	0	0
T78	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1
T88	0	0	0	1
T89	0	0	0	1
T90	0	0	0	1
T91	0	0	0	1

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	58550652	0	0
T1	10393	9356	0	0
T2	149453	144296	0	0
T3	20388	16037	0	0
T4	124915	123830	0	0
T5	127471	120422	0	0
T10	31440	25281	0	0
T11	31887	25819	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	19946	10691	0	0

LcCntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	58550652	0	0
T1	10393	9356	0	0
T2	149453	144296	0	0
T3	20388	16037	0	0
T4	124915	123830	0	0
T5	127471	120422	0	0
T10	31440	25281	0	0
T11	31887	25819	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	19946	10691	0	0

LcStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	58550652	0	0
T1	10393	9356	0	0
T2	149453	144296	0	0
T3	20388	16037	0	0
T4	124915	123830	0	0
T5	127471	120422	0	0
T10	31440	25281	0	0
T11	31887	25819	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	19946	10691	0	0

NoClkBypInProdStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	8246081	0	0
T1	10393	2319	0	0
T2	149453	15598	0	0
T3	20388	1983	0	0
T4	124915	9324	0	0
T5	127471	14380	0	0
T10	31440	2940	0	0
T11	31887	3154	0	0
T12	53800	6120	0	0
T13	1641	170	0	0
T14	19946	1373	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	0	0	1906

SecCmCFITerminal0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	8521474	0	0
T1	10393	1258	0	0
T2	149453	0	0	0
T3	20388	0	0	0
T4	124915	57782	0	0
T5	127471	38576	0	0
T10	31440	12122	0	0
T11	31887	0	0	0
T12	53800	15229	0	0
T13	1641	14	0	0
T14	19946	0	0	0
T15	0	9589	0	0
T21	0	910	0	0
T51	0	1587	0	0
T52	0	1329	0	0

SecCmCFITerminal1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	36378	0	0
T5	127471	7	0	0
T10	31440	0	0	0
T11	31887	0	0	0
T12	53800	0	0	0
T13	1641	194	0	0
T14	19946	6	0	0
T15	40753	0	0	0
T21	4397	0	0	0
T34	0	6	0	0
T36	0	3	0	0
T51	6906	0	0	0
T52	4491	0	0	0
T70	0	3352	0	0
T92	0	3	0	0
T93	0	6	0	0
T94	0	9	0	0
T95	0	7	0	0

SecCmCFITerminal2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	4696810	0	0
T1	10393	2208	0	0
T2	149453	28642	0	0
T3	20388	6965	0	0
T4	124915	9367	0	0
T5	127471	21968	0	0
T10	31440	0	0	0
T11	31887	10416	0	0
T12	53800	0	0	0
T13	1641	0	0	0
T14	19946	0	0	0
T15	0	6992	0	0
T21	0	852	0	0
T44	0	1650	0	0
T51	0	810	0	0

SecCmCFITerminal3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61658664	6053078	0	0
T1	10393	1502	0	0
T2	149453	86189	0	0
T3	20388	6323	0	0
T4	124915	13868	0	0
T5	127471	13640	0	0
T10	31440	0	0	0
T11	31887	12030	0	0
T12	53800	0	0	0
T13	1641	0	0	0
T14	19946	4766	0	0
T21	0	318	0	0
T51	0	717	0	0
T75	0	842	0	0

u_cnt_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57363526	54535074	0	0
T1	7910	7148	0	0
T2	109137	105334	0	0
T3	12087	9407	0	0
T4	115429	114423	0	0
T5	111732	106038	0	0
T10	31440	25281	0	0
T11	20071	16104	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	14874	5619	0	0

u_fsm_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60312565	57292466	0	0
T1	9793	8831	0	0
T2	136574	131895	0	0
T3	17710	13926	0	0
T4	116741	115728	0	0
T5	125726	119097	0	0
T10	31440	25281	0	0
T11	28189	22839	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	14874	5619	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58283628	55445214	0	0
T1	8985	8187	0	0
T2	106581	102975	0	0
T3	14574	11645	0	0
T4	118933	117916	0	0
T5	110986	106435	0	0
T10	31440	25281	0	0
T11	21203	17238	0	0
T12	53800	47776	0	0
T13	1641	1404	0	0
T14	14874	5619	0	0