Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 97.29 95.43 91.98 97.67 96.13 98.48 94.64


Total test records in report: 984
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T758 /workspace/coverage/default/18.lc_ctrl_alert_test.4237282283 Jan 17 12:48:45 PM PST 24 Jan 17 12:48:49 PM PST 24 20782469 ps
T116 /workspace/coverage/default/3.lc_ctrl_sec_cm.2719817012 Jan 17 12:47:55 PM PST 24 Jan 17 12:48:20 PM PST 24 111913355 ps
T759 /workspace/coverage/default/43.lc_ctrl_state_post_trans.1609697462 Jan 17 12:49:47 PM PST 24 Jan 17 12:50:09 PM PST 24 115293746 ps
T760 /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.752516261 Jan 17 12:47:42 PM PST 24 Jan 17 12:47:50 PM PST 24 40330537 ps
T761 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3907602014 Jan 17 12:48:42 PM PST 24 Jan 17 12:50:07 PM PST 24 3496367829 ps
T762 /workspace/coverage/default/39.lc_ctrl_security_escalation.1856158046 Jan 17 12:49:22 PM PST 24 Jan 17 12:49:32 PM PST 24 1043156660 ps
T90 /workspace/coverage/default/26.lc_ctrl_smoke.3435980482 Jan 17 12:48:54 PM PST 24 Jan 17 12:49:13 PM PST 24 47332790 ps
T763 /workspace/coverage/default/40.lc_ctrl_stress_all.4147058345 Jan 17 12:49:30 PM PST 24 Jan 17 12:50:25 PM PST 24 13627811860 ps
T764 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2455369197 Jan 17 12:48:10 PM PST 24 Jan 17 12:48:51 PM PST 24 7541348698 ps
T765 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.737115824 Jan 17 12:48:48 PM PST 24 Jan 17 12:50:26 PM PST 24 23371897460 ps
T766 /workspace/coverage/default/27.lc_ctrl_alert_test.1571640804 Jan 17 12:49:02 PM PST 24 Jan 17 12:49:12 PM PST 24 83482623 ps
T767 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3123119613 Jan 17 12:48:24 PM PST 24 Jan 17 12:48:25 PM PST 24 21647398 ps
T768 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1547034015 Jan 17 12:49:31 PM PST 24 Jan 17 12:49:40 PM PST 24 34979820 ps
T769 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1845792559 Jan 17 12:49:50 PM PST 24 Jan 17 12:49:59 PM PST 24 11992598 ps
T770 /workspace/coverage/default/0.lc_ctrl_sec_mubi.2127949460 Jan 17 12:47:58 PM PST 24 Jan 17 12:48:12 PM PST 24 350989152 ps
T771 /workspace/coverage/default/13.lc_ctrl_prog_failure.1667023884 Jan 17 12:48:28 PM PST 24 Jan 17 12:48:31 PM PST 24 14262143 ps
T772 /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3807999385 Jan 17 12:47:54 PM PST 24 Jan 17 12:48:13 PM PST 24 1819086059 ps
T773 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2902041005 Jan 17 12:48:56 PM PST 24 Jan 17 12:49:18 PM PST 24 219289086 ps
T774 /workspace/coverage/default/16.lc_ctrl_alert_test.3143111492 Jan 17 12:48:40 PM PST 24 Jan 17 12:48:46 PM PST 24 118925076 ps
T775 /workspace/coverage/default/25.lc_ctrl_smoke.2284568564 Jan 17 12:48:55 PM PST 24 Jan 17 12:49:13 PM PST 24 28541248 ps
T176 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1507407915 Jan 17 12:47:48 PM PST 24 Jan 17 12:47:53 PM PST 24 83082286 ps
T776 /workspace/coverage/default/25.lc_ctrl_prog_failure.237501523 Jan 17 12:48:56 PM PST 24 Jan 17 12:49:13 PM PST 24 440441293 ps
T777 /workspace/coverage/default/43.lc_ctrl_prog_failure.59854816 Jan 17 12:49:45 PM PST 24 Jan 17 12:50:01 PM PST 24 807664313 ps
T778 /workspace/coverage/default/0.lc_ctrl_state_post_trans.3709094643 Jan 17 12:47:41 PM PST 24 Jan 17 12:47:55 PM PST 24 365888300 ps
T779 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.974914554 Jan 17 12:48:02 PM PST 24 Jan 17 12:48:07 PM PST 24 31412764 ps
T780 /workspace/coverage/default/25.lc_ctrl_sec_mubi.2690369424 Jan 17 12:48:57 PM PST 24 Jan 17 12:49:27 PM PST 24 1704849945 ps
T781 /workspace/coverage/default/27.lc_ctrl_security_escalation.1603020235 Jan 17 12:48:56 PM PST 24 Jan 17 12:49:19 PM PST 24 1939959948 ps
T782 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2631094068 Jan 17 12:49:02 PM PST 24 Jan 17 12:49:11 PM PST 24 53365950 ps
T783 /workspace/coverage/default/34.lc_ctrl_alert_test.2051437188 Jan 17 12:49:24 PM PST 24 Jan 17 12:49:26 PM PST 24 39091153 ps
T784 /workspace/coverage/default/49.lc_ctrl_sec_mubi.121933723 Jan 17 12:50:06 PM PST 24 Jan 17 12:50:22 PM PST 24 906294275 ps
T785 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3234224867 Jan 17 12:48:27 PM PST 24 Jan 17 12:48:28 PM PST 24 34802721 ps
T786 /workspace/coverage/default/11.lc_ctrl_state_failure.3102047359 Jan 17 12:48:21 PM PST 24 Jan 17 12:48:54 PM PST 24 256185635 ps
T787 /workspace/coverage/default/33.lc_ctrl_state_post_trans.535163809 Jan 17 12:49:18 PM PST 24 Jan 17 12:49:29 PM PST 24 225460207 ps
T788 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3494608973 Jan 17 12:49:31 PM PST 24 Jan 17 12:49:51 PM PST 24 368339139 ps
T789 /workspace/coverage/default/38.lc_ctrl_state_post_trans.2440983548 Jan 17 12:49:29 PM PST 24 Jan 17 12:49:46 PM PST 24 931777650 ps
T91 /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.939567424 Jan 17 12:48:13 PM PST 24 Jan 17 12:48:19 PM PST 24 39301657 ps
T790 /workspace/coverage/default/41.lc_ctrl_security_escalation.3212136785 Jan 17 12:49:26 PM PST 24 Jan 17 12:49:39 PM PST 24 380460961 ps
T791 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1530710218 Jan 17 12:48:17 PM PST 24 Jan 17 12:48:33 PM PST 24 698832820 ps
T792 /workspace/coverage/default/14.lc_ctrl_jtag_errors.1385030456 Jan 17 12:48:23 PM PST 24 Jan 17 12:48:46 PM PST 24 1039252854 ps
T793 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1758024977 Jan 17 12:48:06 PM PST 24 Jan 17 12:48:25 PM PST 24 1082960343 ps
T794 /workspace/coverage/default/31.lc_ctrl_sec_mubi.4279598024 Jan 17 12:49:17 PM PST 24 Jan 17 12:49:34 PM PST 24 804501860 ps
T795 /workspace/coverage/default/40.lc_ctrl_prog_failure.2950428743 Jan 17 12:49:42 PM PST 24 Jan 17 12:50:01 PM PST 24 114555062 ps
T796 /workspace/coverage/default/0.lc_ctrl_smoke.471597656 Jan 17 12:47:41 PM PST 24 Jan 17 12:47:51 PM PST 24 57591688 ps
T797 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2473802074 Jan 17 12:49:22 PM PST 24 Jan 17 12:49:37 PM PST 24 556115783 ps
T117 /workspace/coverage/default/2.lc_ctrl_sec_cm.1019705188 Jan 17 12:47:59 PM PST 24 Jan 17 12:48:36 PM PST 24 2122737416 ps
T177 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3923579990 Jan 17 12:48:17 PM PST 24 Jan 17 12:48:21 PM PST 24 12899752 ps
T798 /workspace/coverage/default/29.lc_ctrl_smoke.3579050259 Jan 17 12:49:01 PM PST 24 Jan 17 12:49:12 PM PST 24 43803966 ps
T799 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4108909889 Jan 17 12:49:20 PM PST 24 Jan 17 12:49:38 PM PST 24 1508615744 ps
T800 /workspace/coverage/default/5.lc_ctrl_prog_failure.2817510134 Jan 17 12:48:10 PM PST 24 Jan 17 12:48:14 PM PST 24 412763778 ps
T801 /workspace/coverage/default/7.lc_ctrl_stress_all.3392006013 Jan 17 12:48:12 PM PST 24 Jan 17 12:52:31 PM PST 24 13825455630 ps
T802 /workspace/coverage/default/16.lc_ctrl_sec_mubi.1455879046 Jan 17 12:48:39 PM PST 24 Jan 17 12:48:59 PM PST 24 3498899903 ps
T803 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1586501029 Jan 17 12:48:46 PM PST 24 Jan 17 12:49:46 PM PST 24 2894395943 ps
T804 /workspace/coverage/default/4.lc_ctrl_state_failure.2060757179 Jan 17 12:48:00 PM PST 24 Jan 17 12:48:30 PM PST 24 2075948213 ps
T805 /workspace/coverage/default/43.lc_ctrl_jtag_access.473943707 Jan 17 12:49:51 PM PST 24 Jan 17 12:50:02 PM PST 24 804439441 ps
T806 /workspace/coverage/default/14.lc_ctrl_prog_failure.562968493 Jan 17 12:48:22 PM PST 24 Jan 17 12:48:26 PM PST 24 80773615 ps
T807 /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2891777149 Jan 17 12:50:09 PM PST 24 Jan 17 12:50:13 PM PST 24 29297866 ps
T808 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1816765048 Jan 17 12:49:02 PM PST 24 Jan 17 12:49:32 PM PST 24 625275683 ps
T809 /workspace/coverage/default/30.lc_ctrl_smoke.2181408478 Jan 17 12:49:08 PM PST 24 Jan 17 12:49:14 PM PST 24 241840529 ps
T810 /workspace/coverage/default/1.lc_ctrl_prog_failure.1864214984 Jan 17 12:47:52 PM PST 24 Jan 17 12:47:56 PM PST 24 21103342 ps
T811 /workspace/coverage/default/27.lc_ctrl_sec_mubi.2510106222 Jan 17 12:48:57 PM PST 24 Jan 17 12:49:20 PM PST 24 828862392 ps
T812 /workspace/coverage/default/19.lc_ctrl_state_post_trans.3952386110 Jan 17 12:48:50 PM PST 24 Jan 17 12:49:17 PM PST 24 311095945 ps
T813 /workspace/coverage/default/33.lc_ctrl_jtag_access.3482644573 Jan 17 12:49:15 PM PST 24 Jan 17 12:49:18 PM PST 24 561705757 ps
T814 /workspace/coverage/default/2.lc_ctrl_jtag_access.2402746968 Jan 17 12:47:57 PM PST 24 Jan 17 12:48:11 PM PST 24 531448129 ps
T815 /workspace/coverage/default/14.lc_ctrl_state_post_trans.1940867899 Jan 17 12:48:28 PM PST 24 Jan 17 12:48:37 PM PST 24 252912102 ps
T816 /workspace/coverage/default/23.lc_ctrl_sec_mubi.2806648640 Jan 17 12:48:57 PM PST 24 Jan 17 12:49:24 PM PST 24 1246069461 ps
T817 /workspace/coverage/default/26.lc_ctrl_state_failure.1141205007 Jan 17 12:48:55 PM PST 24 Jan 17 12:49:33 PM PST 24 1831042118 ps
T818 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3963378308 Jan 17 12:48:44 PM PST 24 Jan 17 12:49:07 PM PST 24 2422060693 ps
T819 /workspace/coverage/default/9.lc_ctrl_security_escalation.1324422330 Jan 17 12:48:18 PM PST 24 Jan 17 12:48:34 PM PST 24 235182682 ps
T820 /workspace/coverage/default/5.lc_ctrl_state_post_trans.3641803988 Jan 17 12:48:14 PM PST 24 Jan 17 12:48:25 PM PST 24 46192081 ps
T821 /workspace/coverage/default/32.lc_ctrl_state_failure.278829964 Jan 17 12:49:15 PM PST 24 Jan 17 12:49:32 PM PST 24 933250037 ps
T822 /workspace/coverage/default/32.lc_ctrl_errors.2410517152 Jan 17 12:49:14 PM PST 24 Jan 17 12:49:28 PM PST 24 253130175 ps
T823 /workspace/coverage/default/31.lc_ctrl_jtag_access.1551337428 Jan 17 12:49:20 PM PST 24 Jan 17 12:49:46 PM PST 24 3834724750 ps
T824 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.573311458 Jan 17 12:47:52 PM PST 24 Jan 17 12:48:11 PM PST 24 248148522 ps
T825 /workspace/coverage/default/47.lc_ctrl_prog_failure.26076218 Jan 17 01:42:11 PM PST 24 Jan 17 01:42:16 PM PST 24 101865942 ps
T826 /workspace/coverage/default/42.lc_ctrl_alert_test.242266326 Jan 17 12:49:50 PM PST 24 Jan 17 12:50:00 PM PST 24 17470251 ps
T827 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1559365880 Jan 17 12:47:54 PM PST 24 Jan 17 12:48:17 PM PST 24 2066674652 ps
T828 /workspace/coverage/default/23.lc_ctrl_alert_test.4278832256 Jan 17 12:48:58 PM PST 24 Jan 17 12:49:12 PM PST 24 15365880 ps
T829 /workspace/coverage/default/22.lc_ctrl_security_escalation.582388077 Jan 17 12:48:51 PM PST 24 Jan 17 12:49:25 PM PST 24 790855144 ps
T830 /workspace/coverage/default/20.lc_ctrl_errors.3533047132 Jan 17 12:48:57 PM PST 24 Jan 17 12:49:22 PM PST 24 382508120 ps
T831 /workspace/coverage/default/5.lc_ctrl_jtag_errors.1184645732 Jan 17 12:48:10 PM PST 24 Jan 17 12:48:36 PM PST 24 1731296071 ps
T832 /workspace/coverage/default/46.lc_ctrl_smoke.2934947708 Jan 17 12:50:10 PM PST 24 Jan 17 12:50:25 PM PST 24 58947600 ps
T833 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1831919738 Jan 17 12:49:24 PM PST 24 Jan 17 12:49:26 PM PST 24 13948145 ps
T834 /workspace/coverage/default/32.lc_ctrl_prog_failure.2988007174 Jan 17 12:49:19 PM PST 24 Jan 17 12:49:26 PM PST 24 290741400 ps
T835 /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2137644723 Jan 17 12:49:18 PM PST 24 Jan 17 01:01:19 PM PST 24 178955776794 ps
T836 /workspace/coverage/default/18.lc_ctrl_jtag_access.1501364189 Jan 17 12:48:50 PM PST 24 Jan 17 12:49:17 PM PST 24 1052765570 ps
T837 /workspace/coverage/default/6.lc_ctrl_jtag_errors.2775894522 Jan 17 12:48:01 PM PST 24 Jan 17 12:48:49 PM PST 24 3152326006 ps
T838 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3914058858 Jan 17 12:48:28 PM PST 24 Jan 17 12:48:38 PM PST 24 1414207188 ps
T839 /workspace/coverage/default/35.lc_ctrl_state_failure.390415982 Jan 17 12:49:19 PM PST 24 Jan 17 12:49:48 PM PST 24 1859518625 ps
T840 /workspace/coverage/default/24.lc_ctrl_stress_all.1441024458 Jan 17 12:48:55 PM PST 24 Jan 17 12:50:32 PM PST 24 5911204689 ps
T841 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.207990722 Jan 17 12:49:29 PM PST 24 Jan 17 12:49:49 PM PST 24 327932749 ps
T842 /workspace/coverage/default/47.lc_ctrl_jtag_access.4105425492 Jan 17 12:50:01 PM PST 24 Jan 17 12:50:05 PM PST 24 229948880 ps
T843 /workspace/coverage/default/46.lc_ctrl_prog_failure.1531249998 Jan 17 12:59:13 PM PST 24 Jan 17 12:59:19 PM PST 24 98951758 ps
T844 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.927659145 Jan 17 12:48:00 PM PST 24 Jan 17 12:48:15 PM PST 24 464144671 ps
T845 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.539382893 Jan 17 12:49:43 PM PST 24 Jan 17 12:50:08 PM PST 24 577771011 ps
T846 /workspace/coverage/default/8.lc_ctrl_jtag_access.756076318 Jan 17 12:48:16 PM PST 24 Jan 17 12:48:22 PM PST 24 645301808 ps
T847 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2360664412 Jan 17 12:47:47 PM PST 24 Jan 17 12:47:58 PM PST 24 357152434 ps
T848 /workspace/coverage/default/28.lc_ctrl_sec_mubi.3082773026 Jan 17 12:49:05 PM PST 24 Jan 17 12:49:23 PM PST 24 336732253 ps
T849 /workspace/coverage/default/27.lc_ctrl_jtag_access.1301259379 Jan 17 12:48:55 PM PST 24 Jan 17 12:49:15 PM PST 24 431635421 ps
T850 /workspace/coverage/default/34.lc_ctrl_state_failure.3273804608 Jan 17 12:49:22 PM PST 24 Jan 17 12:49:54 PM PST 24 1591828894 ps
T851 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1912450406 Jan 17 12:47:54 PM PST 24 Jan 17 12:47:58 PM PST 24 94031131 ps
T852 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.394851951 Jan 17 12:48:40 PM PST 24 Jan 17 12:48:50 PM PST 24 286755955 ps
T853 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2354300259 Jan 17 12:48:29 PM PST 24 Jan 17 12:48:43 PM PST 24 293378396 ps
T854 /workspace/coverage/default/4.lc_ctrl_prog_failure.3121003596 Jan 17 12:48:01 PM PST 24 Jan 17 12:48:05 PM PST 24 35941293 ps
T855 /workspace/coverage/default/9.lc_ctrl_state_failure.1374389766 Jan 17 12:48:19 PM PST 24 Jan 17 12:48:48 PM PST 24 901624671 ps
T856 /workspace/coverage/default/3.lc_ctrl_prog_failure.2133259776 Jan 17 12:48:14 PM PST 24 Jan 17 12:48:22 PM PST 24 82483430 ps
T857 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3204353716 Jan 17 12:48:21 PM PST 24 Jan 17 12:48:23 PM PST 24 14123656 ps
T858 /workspace/coverage/default/16.lc_ctrl_security_escalation.3284101389 Jan 17 12:48:41 PM PST 24 Jan 17 12:48:55 PM PST 24 607066347 ps
T859 /workspace/coverage/default/2.lc_ctrl_security_escalation.2425444347 Jan 17 12:47:40 PM PST 24 Jan 17 12:48:00 PM PST 24 331197021 ps
T860 /workspace/coverage/default/44.lc_ctrl_state_failure.3377192266 Jan 17 12:49:40 PM PST 24 Jan 17 12:50:30 PM PST 24 224506800 ps
T861 /workspace/coverage/default/9.lc_ctrl_errors.1183963787 Jan 17 12:48:15 PM PST 24 Jan 17 12:48:34 PM PST 24 4406113176 ps
T862 /workspace/coverage/default/42.lc_ctrl_state_post_trans.1495693509 Jan 17 12:49:40 PM PST 24 Jan 17 12:50:06 PM PST 24 78805489 ps
T863 /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3979475036 Jan 17 12:48:38 PM PST 24 Jan 17 12:48:40 PM PST 24 27531174 ps
T864 /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3484229017 Jan 17 12:47:44 PM PST 24 Jan 17 12:47:50 PM PST 24 24571075 ps
T865 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4285832531 Jan 17 12:49:20 PM PST 24 Jan 17 12:49:24 PM PST 24 14218090 ps
T866 /workspace/coverage/default/29.lc_ctrl_prog_failure.3232298887 Jan 17 12:49:03 PM PST 24 Jan 17 12:49:13 PM PST 24 184648195 ps
T867 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1140046251 Jan 17 12:48:17 PM PST 24 Jan 17 12:48:31 PM PST 24 371720465 ps
T868 /workspace/coverage/default/5.lc_ctrl_sec_mubi.1934962678 Jan 17 12:48:14 PM PST 24 Jan 17 12:48:30 PM PST 24 318385761 ps
T869 /workspace/coverage/default/1.lc_ctrl_jtag_access.4174297104 Jan 17 12:47:44 PM PST 24 Jan 17 12:47:55 PM PST 24 6998193678 ps
T870 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.976217638 Jan 17 12:48:09 PM PST 24 Jan 17 12:48:37 PM PST 24 3852532836 ps
T871 /workspace/coverage/default/27.lc_ctrl_state_post_trans.1695626510 Jan 17 12:48:58 PM PST 24 Jan 17 12:49:16 PM PST 24 75571973 ps
T872 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.526734708 Jan 17 12:48:14 PM PST 24 Jan 17 12:48:31 PM PST 24 563684437 ps
T873 /workspace/coverage/default/44.lc_ctrl_security_escalation.3760417624 Jan 17 12:50:04 PM PST 24 Jan 17 12:50:19 PM PST 24 753707654 ps
T874 /workspace/coverage/default/23.lc_ctrl_errors.2086781585 Jan 17 12:48:57 PM PST 24 Jan 17 12:49:27 PM PST 24 348546829 ps
T875 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3934896323 Jan 17 12:48:15 PM PST 24 Jan 17 12:48:27 PM PST 24 829055867 ps
T876 /workspace/coverage/default/32.lc_ctrl_smoke.2236681274 Jan 17 12:49:14 PM PST 24 Jan 17 12:49:16 PM PST 24 84118134 ps
T877 /workspace/coverage/default/24.lc_ctrl_state_post_trans.877621899 Jan 17 12:48:56 PM PST 24 Jan 17 12:49:18 PM PST 24 136146584 ps
T878 /workspace/coverage/default/17.lc_ctrl_security_escalation.3376696515 Jan 17 12:48:41 PM PST 24 Jan 17 12:48:53 PM PST 24 894943122 ps
T879 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1533171764 Jan 17 12:49:42 PM PST 24 Jan 17 12:50:07 PM PST 24 1652032417 ps
T880 /workspace/coverage/default/47.lc_ctrl_smoke.302111320 Jan 17 12:57:11 PM PST 24 Jan 17 12:57:18 PM PST 24 65672762 ps
T881 /workspace/coverage/default/29.lc_ctrl_state_failure.868416493 Jan 17 12:49:02 PM PST 24 Jan 17 12:49:40 PM PST 24 247866789 ps
T882 /workspace/coverage/default/35.lc_ctrl_prog_failure.842099224 Jan 17 12:49:17 PM PST 24 Jan 17 12:49:22 PM PST 24 99615077 ps
T883 /workspace/coverage/default/13.lc_ctrl_sec_mubi.1298070723 Jan 17 12:48:28 PM PST 24 Jan 17 12:48:41 PM PST 24 696008242 ps
T884 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.729231106 Jan 17 12:48:41 PM PST 24 Jan 17 12:48:57 PM PST 24 1948594946 ps
T885 /workspace/coverage/default/29.lc_ctrl_sec_mubi.2023394672 Jan 17 12:49:22 PM PST 24 Jan 17 12:49:33 PM PST 24 308693709 ps
T886 /workspace/coverage/default/48.lc_ctrl_prog_failure.80580304 Jan 17 12:50:04 PM PST 24 Jan 17 12:50:12 PM PST 24 369249816 ps
T887 /workspace/coverage/default/3.lc_ctrl_jtag_access.861515493 Jan 17 12:47:55 PM PST 24 Jan 17 12:48:00 PM PST 24 514965138 ps
T888 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2439518883 Jan 17 12:48:53 PM PST 24 Jan 17 12:49:11 PM PST 24 11875013 ps
T889 /workspace/coverage/default/32.lc_ctrl_sec_mubi.482619467 Jan 17 12:49:21 PM PST 24 Jan 17 12:49:37 PM PST 24 388482190 ps
T890 /workspace/coverage/default/9.lc_ctrl_jtag_access.603168634 Jan 17 12:48:16 PM PST 24 Jan 17 12:48:24 PM PST 24 1874116848 ps
T891 /workspace/coverage/default/41.lc_ctrl_alert_test.3183067678 Jan 17 12:49:29 PM PST 24 Jan 17 12:49:40 PM PST 24 73606139 ps
T892 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.992340147 Jan 17 12:47:53 PM PST 24 Jan 17 12:48:08 PM PST 24 641799436 ps
T893 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2698998334 Jan 17 12:48:18 PM PST 24 Jan 17 12:48:29 PM PST 24 288398215 ps
T894 /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1416076890 Jan 17 01:22:35 PM PST 24 Jan 17 01:22:38 PM PST 24 13747872 ps
T895 /workspace/coverage/default/40.lc_ctrl_alert_test.2698680016 Jan 17 12:49:28 PM PST 24 Jan 17 12:49:30 PM PST 24 38507406 ps
T896 /workspace/coverage/default/30.lc_ctrl_security_escalation.2649861644 Jan 17 12:49:23 PM PST 24 Jan 17 12:49:36 PM PST 24 5011206634 ps
T897 /workspace/coverage/default/41.lc_ctrl_errors.254020214 Jan 17 12:49:41 PM PST 24 Jan 17 12:50:10 PM PST 24 7674546607 ps
T898 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3722588218 Jan 17 12:50:07 PM PST 24 Jan 17 12:50:19 PM PST 24 411815955 ps
T899 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1801617858 Jan 17 12:48:09 PM PST 24 Jan 17 12:48:25 PM PST 24 1719505026 ps
T900 /workspace/coverage/default/1.lc_ctrl_smoke.2484428868 Jan 17 12:48:00 PM PST 24 Jan 17 12:48:03 PM PST 24 170075217 ps
T901 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3093727007 Jan 17 12:49:17 PM PST 24 Jan 17 12:49:28 PM PST 24 934418109 ps
T902 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1775411352 Jan 17 12:49:40 PM PST 24 Jan 17 12:50:07 PM PST 24 182802905 ps
T903 /workspace/coverage/default/29.lc_ctrl_stress_all.3913789648 Jan 17 12:49:05 PM PST 24 Jan 17 12:49:50 PM PST 24 2991908673 ps
T904 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4097951200 Jan 17 12:50:07 PM PST 24 Jan 17 12:50:22 PM PST 24 736596811 ps
T905 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1853778725 Jan 17 12:49:29 PM PST 24 Jan 17 12:49:39 PM PST 24 85382236 ps
T906 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2145690434 Jan 17 12:48:45 PM PST 24 Jan 17 12:49:00 PM PST 24 2231047504 ps
T907 /workspace/coverage/default/28.lc_ctrl_state_post_trans.2832193276 Jan 17 12:49:19 PM PST 24 Jan 17 12:49:30 PM PST 24 337316280 ps
T908 /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2034104482 Jan 17 12:49:31 PM PST 24 Jan 17 12:49:52 PM PST 24 703586462 ps
T909 /workspace/coverage/default/44.lc_ctrl_smoke.546520164 Jan 17 12:49:51 PM PST 24 Jan 17 12:50:02 PM PST 24 90728533 ps
T910 /workspace/coverage/default/13.lc_ctrl_security_escalation.2346362609 Jan 17 12:48:22 PM PST 24 Jan 17 12:48:32 PM PST 24 409619743 ps
T911 /workspace/coverage/default/37.lc_ctrl_stress_all.791617533 Jan 17 12:49:25 PM PST 24 Jan 17 12:49:56 PM PST 24 764475716 ps
T912 /workspace/coverage/default/11.lc_ctrl_smoke.2014342224 Jan 17 12:48:41 PM PST 24 Jan 17 12:48:48 PM PST 24 86470295 ps
T913 /workspace/coverage/default/28.lc_ctrl_stress_all.687041079 Jan 17 12:49:01 PM PST 24 Jan 17 12:49:30 PM PST 24 1515352158 ps
T914 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1211165484 Jan 17 12:50:05 PM PST 24 Jan 17 12:50:23 PM PST 24 318486094 ps
T915 /workspace/coverage/default/10.lc_ctrl_sec_mubi.1726784422 Jan 17 12:48:15 PM PST 24 Jan 17 12:48:29 PM PST 24 276320132 ps
T916 /workspace/coverage/default/4.lc_ctrl_stress_all.529634096 Jan 17 12:48:00 PM PST 24 Jan 17 12:49:00 PM PST 24 2271192831 ps
T917 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1955447852 Jan 17 12:48:10 PM PST 24 Jan 17 12:48:45 PM PST 24 2396111061 ps
T918 /workspace/coverage/default/21.lc_ctrl_security_escalation.2638192149 Jan 17 12:48:47 PM PST 24 Jan 17 12:49:15 PM PST 24 1092770506 ps
T919 /workspace/coverage/default/24.lc_ctrl_prog_failure.436742881 Jan 17 12:48:55 PM PST 24 Jan 17 12:49:13 PM PST 24 104290367 ps
T920 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2598594624 Jan 17 12:48:14 PM PST 24 Jan 17 12:48:35 PM PST 24 2507899966 ps
T921 /workspace/coverage/default/13.lc_ctrl_stress_all.2722484298 Jan 17 12:48:29 PM PST 24 Jan 17 12:48:58 PM PST 24 8595857769 ps
T922 /workspace/coverage/default/38.lc_ctrl_prog_failure.2002223541 Jan 17 12:49:18 PM PST 24 Jan 17 12:49:25 PM PST 24 53405579 ps
T923 /workspace/coverage/default/7.lc_ctrl_errors.3284682959 Jan 17 12:48:04 PM PST 24 Jan 17 12:48:19 PM PST 24 505095868 ps
T924 /workspace/coverage/default/19.lc_ctrl_state_failure.3217337636 Jan 17 12:48:51 PM PST 24 Jan 17 12:49:40 PM PST 24 4259011622 ps
T925 /workspace/coverage/default/24.lc_ctrl_sec_mubi.1337040814 Jan 17 12:50:34 PM PST 24 Jan 17 12:50:48 PM PST 24 363944473 ps
T926 /workspace/coverage/default/1.lc_ctrl_state_failure.4013758322 Jan 17 12:47:53 PM PST 24 Jan 17 12:48:17 PM PST 24 541153337 ps
T927 /workspace/coverage/default/18.lc_ctrl_sec_mubi.3439250175 Jan 17 12:48:50 PM PST 24 Jan 17 12:49:22 PM PST 24 588234259 ps
T928 /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3513139674 Jan 17 12:48:12 PM PST 24 Jan 17 12:48:25 PM PST 24 645017561 ps
T929 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.565092201 Jan 17 12:48:03 PM PST 24 Jan 17 12:48:26 PM PST 24 3579958854 ps
T930 /workspace/coverage/default/37.lc_ctrl_smoke.4010441469 Jan 17 12:49:21 PM PST 24 Jan 17 12:49:32 PM PST 24 147178463 ps
T121 /workspace/coverage/default/18.lc_ctrl_stress_all.1322408374 Jan 17 12:48:37 PM PST 24 Jan 17 12:51:09 PM PST 24 4193011778 ps
T931 /workspace/coverage/default/20.lc_ctrl_stress_all.2301678481 Jan 17 12:48:56 PM PST 24 Jan 17 12:49:35 PM PST 24 932354667 ps
T932 /workspace/coverage/default/15.lc_ctrl_smoke.2631498785 Jan 17 12:48:42 PM PST 24 Jan 17 12:48:52 PM PST 24 376088153 ps
T933 /workspace/coverage/default/12.lc_ctrl_sec_mubi.4244180398 Jan 17 12:48:35 PM PST 24 Jan 17 12:48:51 PM PST 24 384475937 ps
T934 /workspace/coverage/default/39.lc_ctrl_stress_all.3812323419 Jan 17 12:49:21 PM PST 24 Jan 17 12:50:03 PM PST 24 2457027040 ps
T935 /workspace/coverage/default/46.lc_ctrl_jtag_access.2424054559 Jan 17 12:50:15 PM PST 24 Jan 17 12:50:29 PM PST 24 357431222 ps
T936 /workspace/coverage/default/34.lc_ctrl_jtag_access.4051910661 Jan 17 12:49:16 PM PST 24 Jan 17 12:49:21 PM PST 24 2588200577 ps
T937 /workspace/coverage/default/40.lc_ctrl_state_failure.3106701419 Jan 17 12:49:28 PM PST 24 Jan 17 12:49:53 PM PST 24 1166121329 ps
T938 /workspace/coverage/default/46.lc_ctrl_state_post_trans.1291871901 Jan 17 12:50:09 PM PST 24 Jan 17 12:50:18 PM PST 24 60259310 ps
T939 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2361424989 Jan 17 12:49:51 PM PST 24 Jan 17 12:50:13 PM PST 24 1232008168 ps
T940 /workspace/coverage/default/2.lc_ctrl_jtag_errors.4146629534 Jan 17 12:48:10 PM PST 24 Jan 17 12:48:52 PM PST 24 1583623733 ps
T941 /workspace/coverage/default/6.lc_ctrl_security_escalation.1142245510 Jan 17 12:47:51 PM PST 24 Jan 17 12:48:08 PM PST 24 697996922 ps
T942 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4112193894 Jan 17 12:48:09 PM PST 24 Jan 17 12:48:22 PM PST 24 706495859 ps
T943 /workspace/coverage/default/8.lc_ctrl_alert_test.1650495831 Jan 17 12:48:01 PM PST 24 Jan 17 12:48:05 PM PST 24 21219083 ps
T944 /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2842710426 Jan 17 12:48:52 PM PST 24 Jan 17 12:49:24 PM PST 24 895963415 ps
T945 /workspace/coverage/default/18.lc_ctrl_errors.3040276757 Jan 17 12:48:48 PM PST 24 Jan 17 12:49:21 PM PST 24 344811221 ps
T946 /workspace/coverage/default/10.lc_ctrl_alert_test.3572141039 Jan 17 12:48:19 PM PST 24 Jan 17 12:48:22 PM PST 24 21831151 ps
T947 /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.634634967 Jan 17 12:48:27 PM PST 24 Jan 17 12:48:46 PM PST 24 1199519422 ps
T948 /workspace/coverage/default/47.lc_ctrl_sec_mubi.3418818962 Jan 17 12:50:07 PM PST 24 Jan 17 12:50:28 PM PST 24 1861532690 ps
T949 /workspace/coverage/default/49.lc_ctrl_smoke.3593705421 Jan 17 01:34:59 PM PST 24 Jan 17 01:35:06 PM PST 24 1083465055 ps
T950 /workspace/coverage/default/8.lc_ctrl_jtag_priority.1936193938 Jan 17 12:48:13 PM PST 24 Jan 17 12:48:23 PM PST 24 665254413 ps
T951 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.880910364 Jan 17 12:49:19 PM PST 24 Jan 17 12:49:38 PM PST 24 791796801 ps
T952 /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1741604752 Jan 17 12:48:39 PM PST 24 Jan 17 12:48:42 PM PST 24 51124700 ps
T953 /workspace/coverage/default/35.lc_ctrl_sec_mubi.1526661808 Jan 17 12:49:20 PM PST 24 Jan 17 12:49:33 PM PST 24 740551153 ps
T954 /workspace/coverage/default/10.lc_ctrl_jtag_access.3505057992 Jan 17 12:48:19 PM PST 24 Jan 17 12:48:26 PM PST 24 748321755 ps
T955 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3366026608 Jan 17 12:49:31 PM PST 24 Jan 17 12:49:40 PM PST 24 46672067 ps
T956 /workspace/coverage/default/18.lc_ctrl_security_escalation.1160958867 Jan 17 12:48:43 PM PST 24 Jan 17 12:48:55 PM PST 24 1668590172 ps
T957 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2305666548 Jan 17 12:49:58 PM PST 24 Jan 17 12:50:10 PM PST 24 1437973080 ps
T958 /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1895360655 Jan 17 12:47:54 PM PST 24 Jan 17 12:48:00 PM PST 24 577409898 ps
T959 /workspace/coverage/default/48.lc_ctrl_state_failure.902869515 Jan 17 12:50:05 PM PST 24 Jan 17 12:50:34 PM PST 24 183221927 ps
T960 /workspace/coverage/default/13.lc_ctrl_state_post_trans.2088484375 Jan 17 12:48:29 PM PST 24 Jan 17 12:48:34 PM PST 24 63154580 ps
T961 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2422159757 Jan 17 12:48:00 PM PST 24 Jan 17 12:48:19 PM PST 24 652379720 ps
T962 /workspace/coverage/default/4.lc_ctrl_smoke.3207859393 Jan 17 12:47:55 PM PST 24 Jan 17 12:47:57 PM PST 24 15869359 ps
T963 /workspace/coverage/default/28.lc_ctrl_alert_test.2691851819 Jan 17 12:49:01 PM PST 24 Jan 17 12:49:11 PM PST 24 82512014 ps
T964 /workspace/coverage/default/23.lc_ctrl_state_failure.4159107885 Jan 17 12:48:58 PM PST 24 Jan 17 12:49:35 PM PST 24 287855407 ps
T965 /workspace/coverage/default/13.lc_ctrl_jtag_access.3345707622 Jan 17 12:48:35 PM PST 24 Jan 17 12:48:43 PM PST 24 2100820184 ps
T966 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2660550504 Jan 17 12:48:20 PM PST 24 Jan 17 12:48:31 PM PST 24 788013500 ps
T967 /workspace/coverage/default/23.lc_ctrl_stress_all.3678754867 Jan 17 12:48:58 PM PST 24 Jan 17 12:52:31 PM PST 24 37963047384 ps
T968 /workspace/coverage/default/45.lc_ctrl_sec_token_digest.948738807 Jan 17 12:50:04 PM PST 24 Jan 17 12:50:23 PM PST 24 2530081899 ps
T969 /workspace/coverage/default/28.lc_ctrl_errors.607786334 Jan 17 12:49:00 PM PST 24 Jan 17 12:49:23 PM PST 24 282030808 ps
T970 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.486515659 Jan 17 12:48:35 PM PST 24 Jan 17 12:48:37 PM PST 24 11024619 ps
T971 /workspace/coverage/default/6.lc_ctrl_prog_failure.2447373627 Jan 17 12:48:10 PM PST 24 Jan 17 12:48:14 PM PST 24 47404397 ps
T972 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.374284654 Jan 17 12:47:53 PM PST 24 Jan 17 12:48:08 PM PST 24 1880926510 ps
T973 /workspace/coverage/default/18.lc_ctrl_state_post_trans.2792773904 Jan 17 12:48:48 PM PST 24 Jan 17 12:49:19 PM PST 24 190898021 ps
T974 /workspace/coverage/default/48.lc_ctrl_stress_all.2379400878 Jan 17 12:50:11 PM PST 24 Jan 17 12:51:43 PM PST 24 3790977334 ps
T975 /workspace/coverage/default/44.lc_ctrl_prog_failure.932288662 Jan 17 12:50:07 PM PST 24 Jan 17 12:50:13 PM PST 24 77773174 ps
T976 /workspace/coverage/default/32.lc_ctrl_state_post_trans.3006402811 Jan 17 12:49:16 PM PST 24 Jan 17 12:49:27 PM PST 24 64022136 ps
T977 /workspace/coverage/default/30.lc_ctrl_state_post_trans.2640011670 Jan 17 12:49:04 PM PST 24 Jan 17 12:49:13 PM PST 24 410344749 ps
T978 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.903130979 Jan 17 12:49:05 PM PST 24 Jan 17 12:49:11 PM PST 24 36757894 ps
T979 /workspace/coverage/default/5.lc_ctrl_smoke.4170845893 Jan 17 12:48:09 PM PST 24 Jan 17 12:48:12 PM PST 24 103285240 ps
T980 /workspace/coverage/default/42.lc_ctrl_stress_all.1248569717 Jan 17 12:49:40 PM PST 24 Jan 17 12:50:14 PM PST 24 739830524 ps
T981 /workspace/coverage/default/18.lc_ctrl_jtag_errors.1762057 Jan 17 12:48:40 PM PST 24 Jan 17 12:49:11 PM PST 24 7133659127 ps
T982 /workspace/coverage/default/1.lc_ctrl_alert_test.1706825032 Jan 17 12:47:54 PM PST 24 Jan 17 12:47:56 PM PST 24 16079497 ps
T983 /workspace/coverage/default/42.lc_ctrl_errors.1544990985 Jan 17 12:49:30 PM PST 24 Jan 17 12:49:49 PM PST 24 907828698 ps
T984 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.642323477 Jan 17 12:54:11 PM PST 24 Jan 17 12:54:14 PM PST 24 38906113 ps

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.911189691
Short name T65
Test name
Test status
Simulation time 86727631 ps
CPU time 3.79 seconds
Started Jan 17 12:54:42 PM PST 24
Finished Jan 17 12:54:48 PM PST 24
Peak memory 217660 kb
Host smart-f1958b50-83e6-4c06-a02c-221f8d2cb784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911189691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.911189691
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3784677601
Short name T5
Test name
Test status
Simulation time 2089659218 ps
CPU time 42.4 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:49:05 PM PST 24
Peak memory 251456 kb
Host smart-d6c603de-46ff-4c61-ac9b-b17fe18fa416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784677601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3784677601
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4256026043
Short name T115
Test name
Test status
Simulation time 259574976 ps
CPU time 2.52 seconds
Started Jan 17 12:54:36 PM PST 24
Finished Jan 17 12:54:39 PM PST 24
Peak memory 217908 kb
Host smart-4b02cb62-19ea-4b5c-95c0-0f3b6e4e66fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425602
6043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4256026043
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2768323678
Short name T33
Test name
Test status
Simulation time 1398209482 ps
CPU time 10.46 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:50:22 PM PST 24
Peak memory 218176 kb
Host smart-67faca57-1d14-462a-b4d6-42def59f74b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768323678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2768323678
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.846658090
Short name T60
Test name
Test status
Simulation time 6478594497 ps
CPU time 228.48 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:52:07 PM PST 24
Peak memory 251292 kb
Host smart-dac0118d-20f2-4126-bb18-aed1f4aa01a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846658090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.846658090
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1091049957
Short name T10
Test name
Test status
Simulation time 1014226314 ps
CPU time 8.6 seconds
Started Jan 17 12:48:08 PM PST 24
Finished Jan 17 12:48:18 PM PST 24
Peak memory 218040 kb
Host smart-17b02f35-6811-4471-9ee8-9505ed5b9f1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091049957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
091049957
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1056413215
Short name T103
Test name
Test status
Simulation time 73701112 ps
CPU time 1.34 seconds
Started Jan 17 12:53:50 PM PST 24
Finished Jan 17 12:53:54 PM PST 24
Peak memory 209424 kb
Host smart-ec727c9c-db31-47ed-8dd6-401dca6c721b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056413215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1056413215
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.620874289
Short name T70
Test name
Test status
Simulation time 4970624647 ps
CPU time 174.14 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:51:12 PM PST 24
Peak memory 251168 kb
Host smart-7974628b-d284-4393-ac2b-902efc845f80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620874289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.620874289
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3658153102
Short name T102
Test name
Test status
Simulation time 98330903 ps
CPU time 1.02 seconds
Started Jan 17 12:54:03 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 211080 kb
Host smart-949bc0e7-e093-4669-b02f-49cba412edea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658153102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3658153102
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2492243596
Short name T36
Test name
Test status
Simulation time 281004895 ps
CPU time 7.5 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:18 PM PST 24
Peak memory 218180 kb
Host smart-64dc668b-5846-4234-8962-885a11461754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492243596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2492243596
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1163267044
Short name T104
Test name
Test status
Simulation time 111802741 ps
CPU time 3.94 seconds
Started Jan 17 12:54:47 PM PST 24
Finished Jan 17 12:54:57 PM PST 24
Peak memory 217720 kb
Host smart-815a7f04-36b7-46d8-a9f2-dfbd43830ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163267044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1163267044
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3977190901
Short name T39
Test name
Test status
Simulation time 38157561 ps
CPU time 0.88 seconds
Started Jan 17 12:47:50 PM PST 24
Finished Jan 17 12:47:54 PM PST 24
Peak memory 208352 kb
Host smart-a7113040-e81c-49e9-96b9-eecc22394649
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977190901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3977190901
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.221214451
Short name T31
Test name
Test status
Simulation time 452913802 ps
CPU time 27.11 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:38 PM PST 24
Peak memory 251244 kb
Host smart-cb3638c1-7841-43e6-a5b1-58dbf7ed0fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221214451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.221214451
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2450098644
Short name T105
Test name
Test status
Simulation time 118865634 ps
CPU time 24.51 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:27 PM PST 24
Peak memory 281876 kb
Host smart-0788a994-0345-428e-85f3-0aeb0fb14164
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450098644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2450098644
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.892555563
Short name T56
Test name
Test status
Simulation time 4127520463 ps
CPU time 171.05 seconds
Started Jan 17 12:49:21 PM PST 24
Finished Jan 17 12:52:14 PM PST 24
Peak memory 272320 kb
Host smart-22473080-12c3-4b73-9afd-063a3971a343
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892555563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.892555563
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2426763471
Short name T126
Test name
Test status
Simulation time 47847930 ps
CPU time 2.71 seconds
Started Jan 17 12:54:22 PM PST 24
Finished Jan 17 12:54:26 PM PST 24
Peak memory 217768 kb
Host smart-46822bff-cec7-4a62-a633-a8f61f6a8ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426763471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2426763471
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3662623864
Short name T370
Test name
Test status
Simulation time 1807876828 ps
CPU time 10.56 seconds
Started Jan 17 12:49:45 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 218188 kb
Host smart-41836556-f791-40d6-aaf9-4f5d3797b6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662623864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3662623864
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.4262509283
Short name T108
Test name
Test status
Simulation time 21448184 ps
CPU time 0.95 seconds
Started Jan 17 12:48:34 PM PST 24
Finished Jan 17 12:48:36 PM PST 24
Peak memory 208564 kb
Host smart-43b593bc-a8c5-45dc-b9ba-f3265f1cb8dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262509283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.4262509283
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3992895875
Short name T111
Test name
Test status
Simulation time 181055449 ps
CPU time 3.89 seconds
Started Jan 17 12:54:59 PM PST 24
Finished Jan 17 12:55:04 PM PST 24
Peak memory 217788 kb
Host smart-82bc79e6-d6f7-4003-a9a1-b5a9bd34a0a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992895875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3992895875
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.628992631
Short name T6
Test name
Test status
Simulation time 1304627358 ps
CPU time 2.98 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:14 PM PST 24
Peak memory 209644 kb
Host smart-ef1ca659-16ae-442d-9334-c63093fe3c52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628992631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_ac
cess.628992631
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.902579528
Short name T53
Test name
Test status
Simulation time 18419312 ps
CPU time 0.98 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:50:24 PM PST 24
Peak memory 212768 kb
Host smart-d3240d80-8c5e-43ab-b502-5931f2406655
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902579528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.902579528
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2528277084
Short name T159
Test name
Test status
Simulation time 77211712 ps
CPU time 1.38 seconds
Started Jan 17 12:54:26 PM PST 24
Finished Jan 17 12:54:29 PM PST 24
Peak memory 211188 kb
Host smart-e3f5507a-2edc-4954-a2e5-edfb4bbc0f5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528277084 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2528277084
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3480477113
Short name T3
Test name
Test status
Simulation time 203912416 ps
CPU time 20.99 seconds
Started Jan 17 01:10:07 PM PST 24
Finished Jan 17 01:10:29 PM PST 24
Peak memory 251104 kb
Host smart-3ab21518-b5bb-4262-b43f-cffb81786705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480477113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3480477113
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1838136798
Short name T165
Test name
Test status
Simulation time 23210256 ps
CPU time 1.07 seconds
Started Jan 17 12:53:56 PM PST 24
Finished Jan 17 12:53:58 PM PST 24
Peak memory 209892 kb
Host smart-077c44f9-3009-4c8c-91be-533852a269f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838136798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1838136798
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2653453608
Short name T137
Test name
Test status
Simulation time 80650228 ps
CPU time 2.8 seconds
Started Jan 17 12:54:35 PM PST 24
Finished Jan 17 12:54:38 PM PST 24
Peak memory 221704 kb
Host smart-e830decb-efab-4d39-bcb0-ad3339d32f09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653453608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2653453608
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4171306172
Short name T460
Test name
Test status
Simulation time 408936019 ps
CPU time 14 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:48:07 PM PST 24
Peak memory 218192 kb
Host smart-8b449369-718e-41eb-8375-6bd2ecda3f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171306172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4171306172
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.39483567
Short name T375
Test name
Test status
Simulation time 18739224 ps
CPU time 0.82 seconds
Started Jan 17 12:47:54 PM PST 24
Finished Jan 17 12:47:56 PM PST 24
Peak memory 208376 kb
Host smart-36ea134e-c912-4335-b655-1376f2ac5da0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_volatile_unlock_smoke.39483567
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3430073242
Short name T128
Test name
Test status
Simulation time 176135893 ps
CPU time 1.71 seconds
Started Jan 17 12:53:58 PM PST 24
Finished Jan 17 12:54:00 PM PST 24
Peak memory 221472 kb
Host smart-5246ac67-12ad-4e00-abb9-f18c079799d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430073242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3430073242
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.947371821
Short name T18
Test name
Test status
Simulation time 1244171756 ps
CPU time 22.88 seconds
Started Jan 17 12:48:25 PM PST 24
Finished Jan 17 12:48:49 PM PST 24
Peak memory 218124 kb
Host smart-f633d0a9-d157-493f-bc91-c0954b2c3199
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947371821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.947371821
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2093560888
Short name T448
Test name
Test status
Simulation time 37789092 ps
CPU time 2.71 seconds
Started Jan 17 12:48:17 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 214256 kb
Host smart-d1fcf7b2-cb2e-4c88-a75c-af2b7fe0f3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093560888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2093560888
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.330279443
Short name T141
Test name
Test status
Simulation time 280970988 ps
CPU time 5.73 seconds
Started Jan 17 12:54:16 PM PST 24
Finished Jan 17 12:54:27 PM PST 24
Peak memory 218224 kb
Host smart-cef5b256-f84e-49ad-97f4-27430ab1241b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330279443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.330279443
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1507407915
Short name T176
Test name
Test status
Simulation time 83082286 ps
CPU time 0.78 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:47:53 PM PST 24
Peak memory 208044 kb
Host smart-d38f0253-2a75-4ba7-b455-0360660710fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507407915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1507407915
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1539438701
Short name T322
Test name
Test status
Simulation time 1632155385 ps
CPU time 9.81 seconds
Started Jan 17 12:48:34 PM PST 24
Finished Jan 17 12:48:45 PM PST 24
Peak memory 218116 kb
Host smart-923742c2-58fd-4320-8b3f-49137ede70cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539438701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1539438701
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1663151537
Short name T178
Test name
Test status
Simulation time 14326285 ps
CPU time 0.84 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:47:53 PM PST 24
Peak memory 208164 kb
Host smart-2aed038c-e86e-4e7a-9fcc-8ff6f13774a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663151537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1663151537
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.50583163
Short name T123
Test name
Test status
Simulation time 74418992 ps
CPU time 1.8 seconds
Started Jan 17 12:54:00 PM PST 24
Finished Jan 17 12:54:03 PM PST 24
Peak memory 219052 kb
Host smart-831925ad-8807-4927-ac2c-0d6054bfd4aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505831
63 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.50583163
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.753055453
Short name T140
Test name
Test status
Simulation time 208502489 ps
CPU time 4.1 seconds
Started Jan 17 12:54:18 PM PST 24
Finished Jan 17 12:54:25 PM PST 24
Peak memory 217712 kb
Host smart-9f1811b6-86ca-421b-aa72-fc2324aab4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753055453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.753055453
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2520281304
Short name T130
Test name
Test status
Simulation time 91015397 ps
CPU time 1.92 seconds
Started Jan 17 12:54:42 PM PST 24
Finished Jan 17 12:54:46 PM PST 24
Peak memory 221644 kb
Host smart-73474991-7ff0-4e87-a30a-0f0a9d01db7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520281304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2520281304
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4059640994
Short name T132
Test name
Test status
Simulation time 276018543 ps
CPU time 3.42 seconds
Started Jan 17 12:55:02 PM PST 24
Finished Jan 17 12:55:06 PM PST 24
Peak memory 217416 kb
Host smart-db7b00bc-0d86-4d61-9750-ef27f01aa1d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059640994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.4059640994
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2194914480
Short name T63
Test name
Test status
Simulation time 1320022440 ps
CPU time 12.86 seconds
Started Jan 17 12:49:59 PM PST 24
Finished Jan 17 12:50:15 PM PST 24
Peak memory 218148 kb
Host smart-0fb47802-98b5-4eb7-95cc-f495942afade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194914480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2194914480
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.952090177
Short name T120
Test name
Test status
Simulation time 23759657419 ps
CPU time 211.66 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:52:42 PM PST 24
Peak memory 267740 kb
Host smart-1eb018d3-8871-4cb4-946e-ca0c90044965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=952090177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.952090177
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2545359114
Short name T168
Test name
Test status
Simulation time 132257453 ps
CPU time 1.25 seconds
Started Jan 17 12:53:59 PM PST 24
Finished Jan 17 12:54:01 PM PST 24
Peak memory 209540 kb
Host smart-d4caf032-6b34-4846-b2a3-956c56dfd9ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545359114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2545359114
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1899321480
Short name T237
Test name
Test status
Simulation time 257453155 ps
CPU time 1.95 seconds
Started Jan 17 12:53:59 PM PST 24
Finished Jan 17 12:54:02 PM PST 24
Peak memory 208392 kb
Host smart-d2aee92a-54f1-4166-894f-c169a66416fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899321480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1899321480
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.509073343
Short name T191
Test name
Test status
Simulation time 27270860 ps
CPU time 0.89 seconds
Started Jan 17 12:53:49 PM PST 24
Finished Jan 17 12:53:52 PM PST 24
Peak memory 209804 kb
Host smart-846c99ab-fa03-4b42-9c21-4b7b425b98f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509073343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.509073343
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3352029169
Short name T273
Test name
Test status
Simulation time 74422614 ps
CPU time 1.1 seconds
Started Jan 17 12:53:59 PM PST 24
Finished Jan 17 12:54:01 PM PST 24
Peak memory 218476 kb
Host smart-b58b6239-686a-4b59-9cbe-d3fda6a2276a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352029169 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3352029169
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.235675275
Short name T298
Test name
Test status
Simulation time 31629673 ps
CPU time 1.07 seconds
Started Jan 17 12:53:52 PM PST 24
Finished Jan 17 12:53:54 PM PST 24
Peak memory 209476 kb
Host smart-2676fdc9-becc-4fb7-b35a-c3245f140423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235675275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.235675275
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.738220074
Short name T205
Test name
Test status
Simulation time 43963401 ps
CPU time 1.13 seconds
Started Jan 17 12:53:52 PM PST 24
Finished Jan 17 12:53:54 PM PST 24
Peak memory 207904 kb
Host smart-83a2bfbb-aef3-4db4-848d-5eff38a9cda4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738220074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.738220074
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1140838827
Short name T201
Test name
Test status
Simulation time 796939872 ps
CPU time 5.46 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:53:58 PM PST 24
Peak memory 209492 kb
Host smart-27d00f80-068d-4638-8abc-fa402632ecc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140838827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1140838827
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3858482995
Short name T148
Test name
Test status
Simulation time 1071530918 ps
CPU time 24.57 seconds
Started Jan 17 12:53:52 PM PST 24
Finished Jan 17 12:54:18 PM PST 24
Peak memory 209464 kb
Host smart-d66dbe3a-71f5-4ec6-a971-6e51b81726fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858482995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3858482995
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3898814313
Short name T236
Test name
Test status
Simulation time 53341904 ps
CPU time 1.95 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:53:55 PM PST 24
Peak memory 210812 kb
Host smart-b33b87d6-ec32-4665-94ed-b77cb82735ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898814313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3898814313
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2291158520
Short name T220
Test name
Test status
Simulation time 149565520 ps
CPU time 2.03 seconds
Started Jan 17 12:53:49 PM PST 24
Finished Jan 17 12:53:53 PM PST 24
Peak memory 218396 kb
Host smart-baf3abf3-9bd2-40e0-b0e3-ef5be89952cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229115
8520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2291158520
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1378732520
Short name T258
Test name
Test status
Simulation time 100813631 ps
CPU time 1.05 seconds
Started Jan 17 12:53:50 PM PST 24
Finished Jan 17 12:53:53 PM PST 24
Peak memory 209548 kb
Host smart-b816de72-85c8-4017-883c-3abefc25be22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378732520 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1378732520
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3132190747
Short name T190
Test name
Test status
Simulation time 87124508 ps
CPU time 1.53 seconds
Started Jan 17 12:53:53 PM PST 24
Finished Jan 17 12:53:56 PM PST 24
Peak memory 211616 kb
Host smart-ddb1b0ef-c19f-4147-935b-e5ac08a637f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132190747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3132190747
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3251344806
Short name T249
Test name
Test status
Simulation time 388397193 ps
CPU time 2.6 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:53:55 PM PST 24
Peak memory 217696 kb
Host smart-826dacd5-1e2f-48bf-ab0c-c12cdbebad31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251344806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3251344806
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3693149130
Short name T110
Test name
Test status
Simulation time 65057310 ps
CPU time 2.69 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:53:55 PM PST 24
Peak memory 218072 kb
Host smart-4978efb3-5d31-4607-b17e-f2c918c9e9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693149130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3693149130
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.821814925
Short name T170
Test name
Test status
Simulation time 69827797 ps
CPU time 1.29 seconds
Started Jan 17 12:54:01 PM PST 24
Finished Jan 17 12:54:03 PM PST 24
Peak memory 209712 kb
Host smart-58aff6d3-8a09-41da-8e54-274bcb11fdb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821814925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.821814925
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2673725703
Short name T283
Test name
Test status
Simulation time 613674005 ps
CPU time 2.09 seconds
Started Jan 17 12:53:59 PM PST 24
Finished Jan 17 12:54:02 PM PST 24
Peak memory 209532 kb
Host smart-57876c82-8e54-4fe5-9839-bb5ef94195eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673725703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2673725703
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1456941603
Short name T109
Test name
Test status
Simulation time 25081102 ps
CPU time 0.99 seconds
Started Jan 17 12:54:01 PM PST 24
Finished Jan 17 12:54:03 PM PST 24
Peak memory 210252 kb
Host smart-3c89a835-4e86-4b37-a82b-fe4ac5b91108
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456941603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1456941603
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.32017068
Short name T287
Test name
Test status
Simulation time 251418440 ps
CPU time 1.07 seconds
Started Jan 17 12:54:00 PM PST 24
Finished Jan 17 12:54:02 PM PST 24
Peak memory 219164 kb
Host smart-47f8e9d7-bf94-49c6-8de3-8047c2c9b5cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32017068 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.32017068
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1503874539
Short name T167
Test name
Test status
Simulation time 45167493 ps
CPU time 0.92 seconds
Started Jan 17 12:54:01 PM PST 24
Finished Jan 17 12:54:03 PM PST 24
Peak memory 209540 kb
Host smart-c29ce8d4-772f-469b-8323-93221d87011b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503874539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1503874539
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.987016316
Short name T207
Test name
Test status
Simulation time 164935981 ps
CPU time 1.2 seconds
Started Jan 17 12:53:57 PM PST 24
Finished Jan 17 12:54:00 PM PST 24
Peak memory 207856 kb
Host smart-ca9dc4b9-45f9-4e14-9a0d-e37aaef83319
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987016316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.987016316
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2384428869
Short name T259
Test name
Test status
Simulation time 362987403 ps
CPU time 4.64 seconds
Started Jan 17 12:53:58 PM PST 24
Finished Jan 17 12:54:04 PM PST 24
Peak memory 209452 kb
Host smart-56014220-956b-4682-9d57-c17a4c86d471
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384428869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2384428869
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.766411323
Short name T122
Test name
Test status
Simulation time 3340595739 ps
CPU time 21.43 seconds
Started Jan 17 12:54:04 PM PST 24
Finished Jan 17 12:54:27 PM PST 24
Peak memory 209500 kb
Host smart-a375010e-10bb-41ce-8edc-17a2744676c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766411323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.766411323
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3646969724
Short name T241
Test name
Test status
Simulation time 291587177 ps
CPU time 1.75 seconds
Started Jan 17 12:54:00 PM PST 24
Finished Jan 17 12:54:03 PM PST 24
Peak memory 210756 kb
Host smart-633a487f-527e-482f-a6e2-55f7f860747e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646969724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3646969724
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2647971637
Short name T96
Test name
Test status
Simulation time 66985525 ps
CPU time 1.81 seconds
Started Jan 17 12:53:59 PM PST 24
Finished Jan 17 12:54:02 PM PST 24
Peak memory 209540 kb
Host smart-5766a378-e263-4f9e-8b68-365af734c471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264797
1637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2647971637
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2934362492
Short name T210
Test name
Test status
Simulation time 218730718 ps
CPU time 1.13 seconds
Started Jan 17 12:54:04 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 208240 kb
Host smart-f0fc99ab-f928-4570-87cd-42b86a63a627
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934362492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2934362492
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3122354046
Short name T195
Test name
Test status
Simulation time 33787817 ps
CPU time 1.12 seconds
Started Jan 17 12:53:58 PM PST 24
Finished Jan 17 12:54:00 PM PST 24
Peak memory 209684 kb
Host smart-30e8419f-c0a6-4698-94ab-7ef84d9aa48d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122354046 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3122354046
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1124748023
Short name T299
Test name
Test status
Simulation time 297067332 ps
CPU time 1.1 seconds
Started Jan 17 12:54:04 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 209440 kb
Host smart-97a09e7e-b990-4393-b162-41344b7f6609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124748023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1124748023
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.187333311
Short name T243
Test name
Test status
Simulation time 96120020 ps
CPU time 2.72 seconds
Started Jan 17 12:53:58 PM PST 24
Finished Jan 17 12:54:02 PM PST 24
Peak memory 217624 kb
Host smart-8eac7a4a-ffaa-4866-b91f-2a7639a64e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187333311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.187333311
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3521340161
Short name T235
Test name
Test status
Simulation time 20747559 ps
CPU time 1.31 seconds
Started Jan 17 12:54:44 PM PST 24
Finished Jan 17 12:54:46 PM PST 24
Peak memory 222796 kb
Host smart-ed811959-63ab-4df5-8def-e08fbcb0cc97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521340161 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3521340161
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1464634966
Short name T173
Test name
Test status
Simulation time 36353615 ps
CPU time 0.89 seconds
Started Jan 17 12:54:36 PM PST 24
Finished Jan 17 12:54:38 PM PST 24
Peak memory 209324 kb
Host smart-42083c60-575c-49a6-8e87-f3b0e6195d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464634966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1464634966
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2802420423
Short name T239
Test name
Test status
Simulation time 31863606 ps
CPU time 1.14 seconds
Started Jan 17 12:54:40 PM PST 24
Finished Jan 17 12:54:44 PM PST 24
Peak memory 209508 kb
Host smart-4e4c3ea3-e074-4d4d-a55e-47b35ce972d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802420423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2802420423
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2847268727
Short name T192
Test name
Test status
Simulation time 287857397 ps
CPU time 3.13 seconds
Started Jan 17 12:54:43 PM PST 24
Finished Jan 17 12:54:47 PM PST 24
Peak memory 217604 kb
Host smart-e212297e-6f0c-4e41-8668-0974a9534a96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847268727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2847268727
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4184602571
Short name T193
Test name
Test status
Simulation time 186007368 ps
CPU time 1.32 seconds
Started Jan 17 12:54:45 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 219244 kb
Host smart-4e966beb-95ec-412d-81ea-ac8f80cca8a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184602571 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4184602571
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1965058279
Short name T97
Test name
Test status
Simulation time 59889885 ps
CPU time 1.09 seconds
Started Jan 17 12:54:41 PM PST 24
Finished Jan 17 12:54:44 PM PST 24
Peak memory 208904 kb
Host smart-f7b0a60a-c965-4566-b35f-3f3128f10a09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965058279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1965058279
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.34195682
Short name T234
Test name
Test status
Simulation time 47109812 ps
CPU time 1.09 seconds
Started Jan 17 12:54:51 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 209584 kb
Host smart-5b7d20f8-f1dc-4f38-93cd-b2cc3961a30b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34195682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
same_csr_outstanding.34195682
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4186733569
Short name T196
Test name
Test status
Simulation time 178709100 ps
CPU time 3.41 seconds
Started Jan 17 12:54:42 PM PST 24
Finished Jan 17 12:54:48 PM PST 24
Peak memory 217680 kb
Host smart-9403cdae-37d2-4fc0-b9a4-ca31c41103bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186733569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4186733569
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3453196024
Short name T194
Test name
Test status
Simulation time 312357782 ps
CPU time 2.08 seconds
Started Jan 17 12:54:42 PM PST 24
Finished Jan 17 12:54:46 PM PST 24
Peak memory 217740 kb
Host smart-aaac38cb-3832-4b27-b2f9-b61e60efbe3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453196024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3453196024
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2594713967
Short name T274
Test name
Test status
Simulation time 13772628 ps
CPU time 1.07 seconds
Started Jan 17 12:54:47 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 209596 kb
Host smart-652f22c1-938f-4f35-b756-6e309371076e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594713967 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2594713967
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2701347908
Short name T278
Test name
Test status
Simulation time 26920077 ps
CPU time 0.86 seconds
Started Jan 17 12:54:42 PM PST 24
Finished Jan 17 12:54:45 PM PST 24
Peak memory 208936 kb
Host smart-e6975739-e4ac-46d9-8d29-2e2e3a4a4f2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701347908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2701347908
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.981597168
Short name T98
Test name
Test status
Simulation time 16337719 ps
CPU time 1 seconds
Started Jan 17 12:54:44 PM PST 24
Finished Jan 17 12:54:46 PM PST 24
Peak memory 209512 kb
Host smart-3bff8b35-edbe-4d82-a8e4-3e964c44aaba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981597168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.981597168
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2067107827
Short name T215
Test name
Test status
Simulation time 85710249 ps
CPU time 3.79 seconds
Started Jan 17 12:54:45 PM PST 24
Finished Jan 17 12:54:56 PM PST 24
Peak memory 217716 kb
Host smart-32042e53-feda-4035-aa01-7ae0383c1ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067107827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2067107827
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.781283785
Short name T143
Test name
Test status
Simulation time 88849691 ps
CPU time 1.72 seconds
Started Jan 17 12:54:45 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 221400 kb
Host smart-ad634ba8-2d37-4d84-83b2-0f581823b76a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781283785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.781283785
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2505129278
Short name T240
Test name
Test status
Simulation time 86093536 ps
CPU time 1.19 seconds
Started Jan 17 12:54:47 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 218412 kb
Host smart-94723ea0-7c56-4f9e-ba6d-b6217f0b696b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505129278 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2505129278
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1233419891
Short name T199
Test name
Test status
Simulation time 77879012 ps
CPU time 0.82 seconds
Started Jan 17 12:54:41 PM PST 24
Finished Jan 17 12:54:44 PM PST 24
Peak memory 208660 kb
Host smart-35acf75f-7ad4-4619-92dd-411b8a61b350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233419891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1233419891
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1727525972
Short name T294
Test name
Test status
Simulation time 36279540 ps
CPU time 1.8 seconds
Started Jan 17 12:54:44 PM PST 24
Finished Jan 17 12:54:47 PM PST 24
Peak memory 211352 kb
Host smart-0e4893e8-61e1-4408-9148-87d9dfcddb5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727525972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1727525972
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.994996348
Short name T268
Test name
Test status
Simulation time 107206429 ps
CPU time 1.78 seconds
Started Jan 17 12:54:49 PM PST 24
Finished Jan 17 12:54:55 PM PST 24
Peak memory 218860 kb
Host smart-fc428db4-043f-434e-aec8-1c123aa03a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994996348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.994996348
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1138960137
Short name T297
Test name
Test status
Simulation time 54118093 ps
CPU time 1.9 seconds
Started Jan 17 12:55:05 PM PST 24
Finished Jan 17 12:55:08 PM PST 24
Peak memory 219612 kb
Host smart-1342204f-0eec-4596-9c00-b0a1ba8bea36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138960137 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1138960137
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1604889085
Short name T295
Test name
Test status
Simulation time 12593830 ps
CPU time 0.87 seconds
Started Jan 17 12:54:48 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 208892 kb
Host smart-704ebc9b-a4b4-4a63-bf49-94dd4ea990ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604889085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1604889085
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.474113282
Short name T248
Test name
Test status
Simulation time 84630109 ps
CPU time 1.01 seconds
Started Jan 17 12:54:56 PM PST 24
Finished Jan 17 12:54:58 PM PST 24
Peak memory 208468 kb
Host smart-cd0192b8-bc1e-4da0-8c38-94211702031e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474113282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.474113282
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3829899498
Short name T291
Test name
Test status
Simulation time 78354793 ps
CPU time 3.03 seconds
Started Jan 17 12:54:45 PM PST 24
Finished Jan 17 12:54:55 PM PST 24
Peak memory 218092 kb
Host smart-3f27ab26-af42-462a-bc44-d51837a483a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829899498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3829899498
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.672459992
Short name T133
Test name
Test status
Simulation time 118828871 ps
CPU time 2.67 seconds
Started Jan 17 12:54:48 PM PST 24
Finished Jan 17 12:54:56 PM PST 24
Peak memory 217752 kb
Host smart-18242783-d920-491c-9173-210079306f40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672459992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.672459992
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2995492022
Short name T153
Test name
Test status
Simulation time 53940991 ps
CPU time 1.25 seconds
Started Jan 17 12:54:49 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 218768 kb
Host smart-74ee78cb-8c99-4e4a-8e1d-0d573ee52c8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995492022 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2995492022
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3762926151
Short name T101
Test name
Test status
Simulation time 14408145 ps
CPU time 0.9 seconds
Started Jan 17 12:54:56 PM PST 24
Finished Jan 17 12:54:58 PM PST 24
Peak memory 209456 kb
Host smart-f8f13dbb-799f-46dc-914f-8a56f311572c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762926151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3762926151
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3605198851
Short name T265
Test name
Test status
Simulation time 93757995 ps
CPU time 1.36 seconds
Started Jan 17 12:54:51 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 209516 kb
Host smart-e82e47ba-8b9e-4844-8f7a-e7a088ce8fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605198851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3605198851
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2904117142
Short name T134
Test name
Test status
Simulation time 148417310 ps
CPU time 4 seconds
Started Jan 17 12:55:02 PM PST 24
Finished Jan 17 12:55:06 PM PST 24
Peak memory 217332 kb
Host smart-ced1de23-9b1a-4759-ae45-507fde2e0e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904117142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2904117142
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2718821562
Short name T139
Test name
Test status
Simulation time 151856961 ps
CPU time 3.2 seconds
Started Jan 17 12:55:04 PM PST 24
Finished Jan 17 12:55:08 PM PST 24
Peak memory 222040 kb
Host smart-f2093e0e-8881-4595-a128-7c65363c2156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718821562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2718821562
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2636425664
Short name T218
Test name
Test status
Simulation time 28106074 ps
CPU time 1.76 seconds
Started Jan 17 12:54:48 PM PST 24
Finished Jan 17 12:54:55 PM PST 24
Peak memory 223216 kb
Host smart-c4eaabeb-64b3-4f74-9635-ca950110109b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636425664 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2636425664
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.239928409
Short name T217
Test name
Test status
Simulation time 41180516 ps
CPU time 0.91 seconds
Started Jan 17 12:54:55 PM PST 24
Finished Jan 17 12:54:56 PM PST 24
Peak memory 208956 kb
Host smart-58e73162-53fe-4a33-b078-1c4e5f1a5edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239928409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.239928409
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2593324991
Short name T260
Test name
Test status
Simulation time 205115949 ps
CPU time 1.11 seconds
Started Jan 17 12:54:54 PM PST 24
Finished Jan 17 12:54:56 PM PST 24
Peak memory 209516 kb
Host smart-4b471825-2901-4d67-a388-62078bb573ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593324991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2593324991
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2223369444
Short name T244
Test name
Test status
Simulation time 55295296 ps
CPU time 2.23 seconds
Started Jan 17 12:54:55 PM PST 24
Finished Jan 17 12:54:58 PM PST 24
Peak memory 217604 kb
Host smart-d6e58da3-1005-499a-935d-27dcae553953
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223369444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2223369444
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3421736570
Short name T282
Test name
Test status
Simulation time 43126477 ps
CPU time 1.3 seconds
Started Jan 17 12:54:55 PM PST 24
Finished Jan 17 12:54:56 PM PST 24
Peak memory 218832 kb
Host smart-daa9a369-6784-42d4-b09c-e40bdd110946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421736570 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3421736570
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1857404491
Short name T157
Test name
Test status
Simulation time 16986512 ps
CPU time 1.16 seconds
Started Jan 17 12:55:01 PM PST 24
Finished Jan 17 12:55:03 PM PST 24
Peak memory 209536 kb
Host smart-8ffde90f-3a9b-4988-bc72-e813731f8b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857404491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1857404491
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2723692793
Short name T163
Test name
Test status
Simulation time 37247095 ps
CPU time 1.44 seconds
Started Jan 17 12:54:49 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 211364 kb
Host smart-90a7a236-0494-45bc-8bdc-0ba4cf1cc0a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723692793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2723692793
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3645629985
Short name T206
Test name
Test status
Simulation time 256972400 ps
CPU time 3.4 seconds
Started Jan 17 12:54:58 PM PST 24
Finished Jan 17 12:55:02 PM PST 24
Peak memory 218480 kb
Host smart-f5297424-c2b7-42bf-844c-c065e39f8fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645629985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3645629985
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.406626657
Short name T280
Test name
Test status
Simulation time 55815321 ps
CPU time 1.02 seconds
Started Jan 17 12:54:52 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 217780 kb
Host smart-f8ff82ce-e3a6-4e50-9e3e-b2a95d2c2868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406626657 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.406626657
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2390934704
Short name T155
Test name
Test status
Simulation time 13478369 ps
CPU time 0.85 seconds
Started Jan 17 12:54:58 PM PST 24
Finished Jan 17 12:54:59 PM PST 24
Peak memory 208600 kb
Host smart-006524dd-2d1b-44a9-bdc9-88e3afe85dbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390934704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2390934704
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3902032908
Short name T99
Test name
Test status
Simulation time 186756820 ps
CPU time 1.04 seconds
Started Jan 17 12:54:54 PM PST 24
Finished Jan 17 12:54:56 PM PST 24
Peak memory 209564 kb
Host smart-75485755-e18f-48b0-b3d1-7b01c8ccb4dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902032908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3902032908
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1458394803
Short name T204
Test name
Test status
Simulation time 128658870 ps
CPU time 3.26 seconds
Started Jan 17 12:54:57 PM PST 24
Finished Jan 17 12:55:01 PM PST 24
Peak memory 217852 kb
Host smart-850e351e-58f4-4dc3-8138-f302c132476e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458394803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1458394803
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1072882191
Short name T142
Test name
Test status
Simulation time 295378162 ps
CPU time 2.76 seconds
Started Jan 17 12:54:48 PM PST 24
Finished Jan 17 12:54:56 PM PST 24
Peak memory 221864 kb
Host smart-60c92fa6-ce73-4192-9933-1d158709255a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072882191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1072882191
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2741592058
Short name T285
Test name
Test status
Simulation time 25591336 ps
CPU time 1.06 seconds
Started Jan 17 12:54:55 PM PST 24
Finished Jan 17 12:54:57 PM PST 24
Peak memory 217912 kb
Host smart-827528b0-9f1b-457a-8a3a-c947760b1c14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741592058 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2741592058
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4291287930
Short name T232
Test name
Test status
Simulation time 39103115 ps
CPU time 0.83 seconds
Started Jan 17 12:54:58 PM PST 24
Finished Jan 17 12:54:59 PM PST 24
Peak memory 209324 kb
Host smart-662f0307-31bd-4af0-86d4-4894468ab14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291287930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.4291287930
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1281275744
Short name T288
Test name
Test status
Simulation time 107492639 ps
CPU time 1.44 seconds
Started Jan 17 12:54:56 PM PST 24
Finished Jan 17 12:54:58 PM PST 24
Peak memory 209528 kb
Host smart-3cdd347f-b71f-4452-a8ae-165eb190953c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281275744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1281275744
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2925481432
Short name T226
Test name
Test status
Simulation time 59211140 ps
CPU time 1.99 seconds
Started Jan 17 12:54:59 PM PST 24
Finished Jan 17 12:55:02 PM PST 24
Peak memory 217816 kb
Host smart-ca00a939-b246-4e15-8f26-b6c8f2f5e23a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925481432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2925481432
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3365918367
Short name T136
Test name
Test status
Simulation time 390664980 ps
CPU time 2.94 seconds
Started Jan 17 12:55:01 PM PST 24
Finished Jan 17 12:55:05 PM PST 24
Peak memory 221828 kb
Host smart-14c9eddb-370c-400c-999c-bb74efddf836
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365918367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3365918367
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2705526238
Short name T154
Test name
Test status
Simulation time 83847039 ps
CPU time 1.06 seconds
Started Jan 17 12:54:04 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 209476 kb
Host smart-d5095b1a-5d18-4fda-ac99-70e581bfbc57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705526238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2705526238
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.186619214
Short name T158
Test name
Test status
Simulation time 188489861 ps
CPU time 2.04 seconds
Started Jan 17 12:54:02 PM PST 24
Finished Jan 17 12:54:05 PM PST 24
Peak memory 209320 kb
Host smart-f965fa20-bf9a-48ee-b0e5-6c228453a7b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186619214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.186619214
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1042156542
Short name T262
Test name
Test status
Simulation time 12896825 ps
CPU time 1.13 seconds
Started Jan 17 12:54:03 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 209536 kb
Host smart-f4bd20df-058b-4ba7-9d7b-0cde62c36ab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042156542 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1042156542
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2259207688
Short name T169
Test name
Test status
Simulation time 17024527 ps
CPU time 1.12 seconds
Started Jan 17 12:54:02 PM PST 24
Finished Jan 17 12:54:04 PM PST 24
Peak memory 209220 kb
Host smart-31e535c2-79af-4cf7-b58b-f503cdf14030
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259207688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2259207688
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1446502107
Short name T246
Test name
Test status
Simulation time 57422875 ps
CPU time 1.85 seconds
Started Jan 17 12:53:58 PM PST 24
Finished Jan 17 12:54:01 PM PST 24
Peak memory 209348 kb
Host smart-8fde4978-f9dc-475c-bd7a-a48540f3f0a6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446502107 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1446502107
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1414064595
Short name T219
Test name
Test status
Simulation time 573803335 ps
CPU time 11.48 seconds
Started Jan 17 12:54:00 PM PST 24
Finished Jan 17 12:54:13 PM PST 24
Peak memory 209424 kb
Host smart-7c14c0f4-aa62-4e58-8569-4bd94a5f316a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414064595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1414064595
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2385507551
Short name T225
Test name
Test status
Simulation time 26732604103 ps
CPU time 41.51 seconds
Started Jan 17 12:54:00 PM PST 24
Finished Jan 17 12:54:43 PM PST 24
Peak memory 209264 kb
Host smart-585c5294-8f38-4c85-ae10-c7e35597a51a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385507551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2385507551
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3212522287
Short name T254
Test name
Test status
Simulation time 119948237 ps
CPU time 1.38 seconds
Started Jan 17 12:54:00 PM PST 24
Finished Jan 17 12:54:02 PM PST 24
Peak memory 210684 kb
Host smart-51cc8c45-c80d-41a6-9fa4-7f40e5143dc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212522287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3212522287
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4024987838
Short name T281
Test name
Test status
Simulation time 526505283 ps
CPU time 1.75 seconds
Started Jan 17 12:53:59 PM PST 24
Finished Jan 17 12:54:01 PM PST 24
Peak memory 209412 kb
Host smart-95bc4898-8554-4436-83f7-dcb461eab89d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024987838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.4024987838
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2174055075
Short name T113
Test name
Test status
Simulation time 94330110 ps
CPU time 1.68 seconds
Started Jan 17 12:53:54 PM PST 24
Finished Jan 17 12:53:57 PM PST 24
Peak memory 211308 kb
Host smart-3e290662-ff10-4af6-9e4b-d522a3e8f1e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174055075 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2174055075
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2437133045
Short name T198
Test name
Test status
Simulation time 124689475 ps
CPU time 1.11 seconds
Started Jan 17 12:54:02 PM PST 24
Finished Jan 17 12:54:04 PM PST 24
Peak memory 209596 kb
Host smart-1cad1b45-6504-47d8-8a92-543fd7dfc207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437133045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2437133045
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.395910626
Short name T124
Test name
Test status
Simulation time 148379747 ps
CPU time 1.25 seconds
Started Jan 17 12:54:04 PM PST 24
Finished Jan 17 12:54:07 PM PST 24
Peak memory 217680 kb
Host smart-c3423d0c-c9d4-4dfa-8ca2-b55b7ec4f2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395910626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.395910626
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.597370744
Short name T144
Test name
Test status
Simulation time 441117562 ps
CPU time 3.82 seconds
Started Jan 17 12:54:00 PM PST 24
Finished Jan 17 12:54:05 PM PST 24
Peak memory 217664 kb
Host smart-08246c34-0e24-4485-a77b-bb96233e5e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597370744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.597370744
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.100673121
Short name T256
Test name
Test status
Simulation time 33657138 ps
CPU time 1.22 seconds
Started Jan 17 12:54:11 PM PST 24
Finished Jan 17 12:54:14 PM PST 24
Peak memory 209568 kb
Host smart-affbc7e4-27d2-468d-a6bb-53e0399b22d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100673121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.100673121
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4210909468
Short name T293
Test name
Test status
Simulation time 102387135 ps
CPU time 1.4 seconds
Started Jan 17 12:54:04 PM PST 24
Finished Jan 17 12:54:07 PM PST 24
Peak memory 209500 kb
Host smart-3258425d-7ce1-4710-8c9a-75b3994a5b42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210909468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.4210909468
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3857092036
Short name T203
Test name
Test status
Simulation time 17542448 ps
CPU time 1 seconds
Started Jan 17 12:54:03 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 210428 kb
Host smart-8e212361-fd26-4fa5-9a95-b099bdf7acac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857092036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3857092036
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3444121608
Short name T208
Test name
Test status
Simulation time 26886710 ps
CPU time 1.16 seconds
Started Jan 17 12:54:02 PM PST 24
Finished Jan 17 12:54:04 PM PST 24
Peak memory 217736 kb
Host smart-c19767e2-1451-44a2-ae79-71a91848e7b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444121608 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3444121608
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2478088913
Short name T160
Test name
Test status
Simulation time 12021716 ps
CPU time 0.85 seconds
Started Jan 17 12:54:02 PM PST 24
Finished Jan 17 12:54:03 PM PST 24
Peak memory 209368 kb
Host smart-76df4377-8cda-4692-852b-65ef9b915348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478088913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2478088913
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1867029223
Short name T230
Test name
Test status
Simulation time 56957127 ps
CPU time 1.01 seconds
Started Jan 17 12:54:09 PM PST 24
Finished Jan 17 12:54:11 PM PST 24
Peak memory 207724 kb
Host smart-ba3d4e7f-7265-4840-b17b-ee6441ab5f4c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867029223 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1867029223
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.361616205
Short name T266
Test name
Test status
Simulation time 221372146 ps
CPU time 5.03 seconds
Started Jan 17 12:54:13 PM PST 24
Finished Jan 17 12:54:18 PM PST 24
Peak memory 208456 kb
Host smart-945edb2f-6dd3-4611-858a-6d57eab8fe6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361616205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.361616205
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.379943851
Short name T275
Test name
Test status
Simulation time 4623221094 ps
CPU time 9.04 seconds
Started Jan 17 12:54:09 PM PST 24
Finished Jan 17 12:54:19 PM PST 24
Peak memory 209464 kb
Host smart-25b1daaa-212f-4a2f-9b26-4d82cd494649
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379943851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.379943851
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1347405363
Short name T276
Test name
Test status
Simulation time 104331950 ps
CPU time 1.28 seconds
Started Jan 17 12:54:02 PM PST 24
Finished Jan 17 12:54:04 PM PST 24
Peak memory 210288 kb
Host smart-41dc7f55-70fe-476b-b49e-c7880bdcd652
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347405363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1347405363
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.736890649
Short name T261
Test name
Test status
Simulation time 69869566 ps
CPU time 1.51 seconds
Started Jan 17 12:54:12 PM PST 24
Finished Jan 17 12:54:15 PM PST 24
Peak memory 209544 kb
Host smart-d09efbf4-7e75-456b-ac38-0499ad971aab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736890
649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.736890649
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3163283103
Short name T152
Test name
Test status
Simulation time 62672691 ps
CPU time 2.22 seconds
Started Jan 17 12:54:00 PM PST 24
Finished Jan 17 12:54:03 PM PST 24
Peak memory 209408 kb
Host smart-debf63c1-8a77-46dd-9847-bed7f7df3a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163283103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3163283103
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2741111912
Short name T221
Test name
Test status
Simulation time 95163105 ps
CPU time 1.41 seconds
Started Jan 17 12:54:06 PM PST 24
Finished Jan 17 12:54:08 PM PST 24
Peak memory 209552 kb
Host smart-00efa942-8975-44e2-92fc-a5f93e325f99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741111912 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2741111912
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1744968639
Short name T211
Test name
Test status
Simulation time 15263918 ps
CPU time 1.15 seconds
Started Jan 17 12:54:02 PM PST 24
Finished Jan 17 12:54:04 PM PST 24
Peak memory 209588 kb
Host smart-93675f16-b81a-4bee-8da8-e51044a08318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744968639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1744968639
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1654035820
Short name T253
Test name
Test status
Simulation time 140530970 ps
CPU time 2.06 seconds
Started Jan 17 12:54:02 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 217668 kb
Host smart-f8ee804c-0041-4961-8874-7c512c486f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654035820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1654035820
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.222568140
Short name T138
Test name
Test status
Simulation time 67421619 ps
CPU time 1.98 seconds
Started Jan 17 12:54:05 PM PST 24
Finished Jan 17 12:54:08 PM PST 24
Peak memory 221184 kb
Host smart-97b75578-231e-4c08-84aa-d26100b8bdd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222568140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.222568140
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3244234921
Short name T277
Test name
Test status
Simulation time 24982038 ps
CPU time 1.07 seconds
Started Jan 17 12:54:12 PM PST 24
Finished Jan 17 12:54:14 PM PST 24
Peak memory 209576 kb
Host smart-1ec7c854-890a-4647-829c-aee4efc9052f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244234921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3244234921
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2144604284
Short name T200
Test name
Test status
Simulation time 143105380 ps
CPU time 1.23 seconds
Started Jan 17 12:54:16 PM PST 24
Finished Jan 17 12:54:22 PM PST 24
Peak memory 209564 kb
Host smart-6f02e265-f111-4bfd-8baf-410b80c6c537
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144604284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2144604284
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.356605003
Short name T114
Test name
Test status
Simulation time 106931559 ps
CPU time 1.65 seconds
Started Jan 17 12:54:18 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 217876 kb
Host smart-d01b7478-9c42-451a-a447-96230137af05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356605003 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.356605003
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3507816550
Short name T172
Test name
Test status
Simulation time 42282323 ps
CPU time 0.91 seconds
Started Jan 17 12:54:19 PM PST 24
Finished Jan 17 12:54:22 PM PST 24
Peak memory 209076 kb
Host smart-827315bd-4576-4a3b-b42b-c36987756c60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507816550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3507816550
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3974066343
Short name T145
Test name
Test status
Simulation time 37998063 ps
CPU time 1.1 seconds
Started Jan 17 12:54:08 PM PST 24
Finished Jan 17 12:54:11 PM PST 24
Peak memory 207732 kb
Host smart-7e786b93-6be2-4746-aaa7-1e2ff2530190
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974066343 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3974066343
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.34401752
Short name T271
Test name
Test status
Simulation time 1418681814 ps
CPU time 3.66 seconds
Started Jan 17 12:54:01 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 208456 kb
Host smart-342aa26a-f1be-46b7-aadd-8d08b1835e52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34401752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.lc_ctrl_jtag_csr_aliasing.34401752
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2811184640
Short name T187
Test name
Test status
Simulation time 545412046 ps
CPU time 12.6 seconds
Started Jan 17 12:54:04 PM PST 24
Finished Jan 17 12:54:18 PM PST 24
Peak memory 208456 kb
Host smart-58db8e27-93b1-4d61-8c1e-be65c377abde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811184640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2811184640
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.49520486
Short name T223
Test name
Test status
Simulation time 69063402 ps
CPU time 1.3 seconds
Started Jan 17 12:54:11 PM PST 24
Finished Jan 17 12:54:14 PM PST 24
Peak memory 210560 kb
Host smart-5112bc5f-7e0a-4191-b4dd-3c8c5a7779e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49520486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.49520486
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3612025965
Short name T112
Test name
Test status
Simulation time 35476294 ps
CPU time 1.32 seconds
Started Jan 17 12:54:01 PM PST 24
Finished Jan 17 12:54:03 PM PST 24
Peak memory 219092 kb
Host smart-c2705b22-4bb4-4b25-9f9e-95051a895c3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361202
5965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3612025965
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2909692926
Short name T189
Test name
Test status
Simulation time 786329967 ps
CPU time 1.36 seconds
Started Jan 17 12:54:06 PM PST 24
Finished Jan 17 12:54:08 PM PST 24
Peak memory 209476 kb
Host smart-980208eb-eca6-4b58-a46e-dbba94fc0788
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909692926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2909692926
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2228442941
Short name T162
Test name
Test status
Simulation time 94726239 ps
CPU time 1.19 seconds
Started Jan 17 12:54:12 PM PST 24
Finished Jan 17 12:54:14 PM PST 24
Peak memory 211368 kb
Host smart-ebec80b1-9c7a-40ad-a375-76c7456768db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228442941 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2228442941
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.231318462
Short name T164
Test name
Test status
Simulation time 21340440 ps
CPU time 1.25 seconds
Started Jan 17 12:54:11 PM PST 24
Finished Jan 17 12:54:14 PM PST 24
Peak memory 209540 kb
Host smart-56db15d2-35c8-4395-a0aa-61d7f821c51c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231318462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.231318462
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2253878124
Short name T209
Test name
Test status
Simulation time 91282354 ps
CPU time 2.91 seconds
Started Jan 17 12:54:12 PM PST 24
Finished Jan 17 12:54:16 PM PST 24
Peak memory 218688 kb
Host smart-ea78ea36-2afd-4890-a44b-db8a8744cf71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253878124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2253878124
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1209974990
Short name T135
Test name
Test status
Simulation time 311300593 ps
CPU time 2.62 seconds
Started Jan 17 12:54:11 PM PST 24
Finished Jan 17 12:54:15 PM PST 24
Peak memory 221636 kb
Host smart-acf4ca65-9deb-4224-9610-ba1a110a798e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209974990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1209974990
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2672887958
Short name T292
Test name
Test status
Simulation time 70277971 ps
CPU time 1.24 seconds
Started Jan 17 12:54:14 PM PST 24
Finished Jan 17 12:54:22 PM PST 24
Peak memory 217796 kb
Host smart-bdb86fe0-3c70-482a-a2f6-fe4ff2e89e47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672887958 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2672887958
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.64927998
Short name T272
Test name
Test status
Simulation time 30683726 ps
CPU time 0.89 seconds
Started Jan 17 12:54:14 PM PST 24
Finished Jan 17 12:54:22 PM PST 24
Peak memory 209536 kb
Host smart-2fd88acb-7329-4c70-903a-346341a01707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64927998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.64927998
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2739567017
Short name T228
Test name
Test status
Simulation time 129536539 ps
CPU time 1.41 seconds
Started Jan 17 12:54:13 PM PST 24
Finished Jan 17 12:54:15 PM PST 24
Peak memory 207884 kb
Host smart-0c997efd-d4cd-493e-8b2d-628108c09a1d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739567017 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2739567017
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2488072820
Short name T188
Test name
Test status
Simulation time 856285862 ps
CPU time 5.31 seconds
Started Jan 17 12:54:12 PM PST 24
Finished Jan 17 12:54:18 PM PST 24
Peak memory 209460 kb
Host smart-1e09c226-7556-4043-9583-d54bc5a44f06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488072820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2488072820
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3961754469
Short name T242
Test name
Test status
Simulation time 412770957 ps
CPU time 4.68 seconds
Started Jan 17 12:54:11 PM PST 24
Finished Jan 17 12:54:17 PM PST 24
Peak memory 207924 kb
Host smart-5a0f83e3-8a58-43f0-b197-034e25653adc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961754469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3961754469
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2388831304
Short name T247
Test name
Test status
Simulation time 369600204 ps
CPU time 1.67 seconds
Started Jan 17 12:54:12 PM PST 24
Finished Jan 17 12:54:15 PM PST 24
Peak memory 210872 kb
Host smart-ff5d1001-071f-4c0c-a27d-1f792fb6cadd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388831304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2388831304
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4130841352
Short name T257
Test name
Test status
Simulation time 100543171 ps
CPU time 2.14 seconds
Started Jan 17 12:54:25 PM PST 24
Finished Jan 17 12:54:28 PM PST 24
Peak memory 218428 kb
Host smart-ad12c649-1bba-4dea-b552-2739418bf0be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413084
1352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4130841352
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1513660176
Short name T146
Test name
Test status
Simulation time 54246698 ps
CPU time 1.97 seconds
Started Jan 17 12:54:19 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 208536 kb
Host smart-648b8518-a1d8-4cbe-803a-d265d9189287
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513660176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1513660176
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3557164459
Short name T127
Test name
Test status
Simulation time 15194712 ps
CPU time 1.21 seconds
Started Jan 17 12:54:10 PM PST 24
Finished Jan 17 12:54:14 PM PST 24
Peak memory 209560 kb
Host smart-772cb447-bf11-44a1-9238-10b6b78f410c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557164459 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3557164459
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.788032343
Short name T156
Test name
Test status
Simulation time 331818628 ps
CPU time 1.11 seconds
Started Jan 17 12:54:13 PM PST 24
Finished Jan 17 12:54:22 PM PST 24
Peak memory 209564 kb
Host smart-cedd2526-f989-424a-b483-eb5ecfafb6c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788032343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.788032343
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3995276036
Short name T131
Test name
Test status
Simulation time 80547584 ps
CPU time 1.69 seconds
Started Jan 17 12:54:16 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 217744 kb
Host smart-8dac88ae-fc88-43ea-90a2-3fc4e6d7522b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995276036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3995276036
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3183629189
Short name T279
Test name
Test status
Simulation time 457510913 ps
CPU time 2.81 seconds
Started Jan 17 12:54:17 PM PST 24
Finished Jan 17 12:54:24 PM PST 24
Peak memory 221584 kb
Host smart-e710d5d6-7deb-4058-ae35-6f6719aa745e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183629189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3183629189
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.235527851
Short name T296
Test name
Test status
Simulation time 173211203 ps
CPU time 1.66 seconds
Started Jan 17 12:54:29 PM PST 24
Finished Jan 17 12:54:32 PM PST 24
Peak memory 219448 kb
Host smart-f61923f8-d290-4e6c-8597-61b4dcb12b92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235527851 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.235527851
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4266921446
Short name T171
Test name
Test status
Simulation time 19855031 ps
CPU time 1.15 seconds
Started Jan 17 12:54:18 PM PST 24
Finished Jan 17 12:54:22 PM PST 24
Peak memory 209468 kb
Host smart-fb123f28-c3a6-43dc-977d-0b43eac46bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266921446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4266921446
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.317085948
Short name T100
Test name
Test status
Simulation time 367489822 ps
CPU time 1.72 seconds
Started Jan 17 12:54:19 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 209376 kb
Host smart-59b8f66b-0813-4ee4-96c2-9150af422d83
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317085948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.317085948
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3420175281
Short name T229
Test name
Test status
Simulation time 1330079883 ps
CPU time 3.86 seconds
Started Jan 17 12:54:10 PM PST 24
Finished Jan 17 12:54:16 PM PST 24
Peak memory 209468 kb
Host smart-07d8b3dd-0c67-49b5-8393-516328a77fce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420175281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3420175281
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1418852779
Short name T231
Test name
Test status
Simulation time 1026207908 ps
CPU time 5.89 seconds
Started Jan 17 12:54:16 PM PST 24
Finished Jan 17 12:54:27 PM PST 24
Peak memory 209472 kb
Host smart-3d38c889-f9c9-4fa2-a2bf-07813513c59f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418852779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1418852779
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.562511739
Short name T227
Test name
Test status
Simulation time 89401271 ps
CPU time 1.73 seconds
Started Jan 17 12:54:13 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 210720 kb
Host smart-d1ca27a7-a7bc-45bc-a824-810e83fd65c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562511739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.562511739
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1531881466
Short name T286
Test name
Test status
Simulation time 60490317 ps
CPU time 1.48 seconds
Started Jan 17 12:54:18 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 218880 kb
Host smart-78bc32b5-184f-4b93-a80f-d8c03d4f5181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153188
1466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1531881466
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.642323477
Short name T984
Test name
Test status
Simulation time 38906113 ps
CPU time 1.09 seconds
Started Jan 17 12:54:11 PM PST 24
Finished Jan 17 12:54:14 PM PST 24
Peak memory 209300 kb
Host smart-731efbac-e565-4a75-86e9-3310b2f3f864
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642323477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.642323477
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.503132907
Short name T250
Test name
Test status
Simulation time 41193544 ps
CPU time 1.47 seconds
Started Jan 17 12:54:18 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 211472 kb
Host smart-406444ef-b3e0-4311-88c2-6c3154ffdbe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503132907 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.503132907
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.397190829
Short name T267
Test name
Test status
Simulation time 18105854 ps
CPU time 1.41 seconds
Started Jan 17 12:54:17 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 209548 kb
Host smart-b2b7a575-b3ca-4afe-a4e8-42d393f273ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397190829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.397190829
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2836809507
Short name T290
Test name
Test status
Simulation time 73847699 ps
CPU time 2.02 seconds
Started Jan 17 12:54:17 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 217668 kb
Host smart-95bd3707-68da-4da1-b0a2-615728ced20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836809507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2836809507
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1356591897
Short name T269
Test name
Test status
Simulation time 50520680 ps
CPU time 1.03 seconds
Started Jan 17 12:54:27 PM PST 24
Finished Jan 17 12:54:29 PM PST 24
Peak memory 218888 kb
Host smart-4bafca83-a9cb-4e40-994d-5ab4d74f632e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356591897 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1356591897
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2618723445
Short name T166
Test name
Test status
Simulation time 18732272 ps
CPU time 0.84 seconds
Started Jan 17 12:54:17 PM PST 24
Finished Jan 17 12:54:22 PM PST 24
Peak memory 209360 kb
Host smart-e95e6f21-88cc-4f62-bc46-34daf18c363c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618723445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2618723445
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1778867045
Short name T252
Test name
Test status
Simulation time 138753055 ps
CPU time 1.15 seconds
Started Jan 17 12:54:17 PM PST 24
Finished Jan 17 12:54:22 PM PST 24
Peak memory 207820 kb
Host smart-17a650da-0158-4fce-8a6f-89b73fe1c9f1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778867045 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1778867045
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1368993658
Short name T270
Test name
Test status
Simulation time 395964843 ps
CPU time 7.27 seconds
Started Jan 17 12:54:19 PM PST 24
Finished Jan 17 12:54:29 PM PST 24
Peak memory 208384 kb
Host smart-365c39fe-c042-4014-bf38-2ca0310eed83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368993658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1368993658
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1329840935
Short name T213
Test name
Test status
Simulation time 2686592198 ps
CPU time 58.57 seconds
Started Jan 17 12:54:29 PM PST 24
Finished Jan 17 12:55:29 PM PST 24
Peak memory 209488 kb
Host smart-a2de43ba-62e2-4974-8c0e-5c3e6f791ecc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329840935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1329840935
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1549896824
Short name T197
Test name
Test status
Simulation time 2258781347 ps
CPU time 3.67 seconds
Started Jan 17 12:54:19 PM PST 24
Finished Jan 17 12:54:25 PM PST 24
Peak memory 211000 kb
Host smart-07757f33-e710-4b90-8cd1-ad22100de608
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549896824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1549896824
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2561952138
Short name T125
Test name
Test status
Simulation time 324813872 ps
CPU time 3.25 seconds
Started Jan 17 12:54:19 PM PST 24
Finished Jan 17 12:54:25 PM PST 24
Peak memory 219104 kb
Host smart-0427e4b0-93bb-4187-b3be-7582e00ea261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256195
2138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2561952138
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3514036283
Short name T245
Test name
Test status
Simulation time 326409380 ps
CPU time 2.61 seconds
Started Jan 17 12:54:20 PM PST 24
Finished Jan 17 12:54:24 PM PST 24
Peak memory 209640 kb
Host smart-8a697ea2-04fa-49fe-97a6-75191560062b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514036283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3514036283
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1579550656
Short name T224
Test name
Test status
Simulation time 59124094 ps
CPU time 1.46 seconds
Started Jan 17 12:54:18 PM PST 24
Finished Jan 17 12:54:23 PM PST 24
Peak memory 209524 kb
Host smart-7672e178-d267-47a9-abe4-5c453179e7ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579550656 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1579550656
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2820073330
Short name T255
Test name
Test status
Simulation time 19562046 ps
CPU time 1.41 seconds
Started Jan 17 12:54:26 PM PST 24
Finished Jan 17 12:54:29 PM PST 24
Peak memory 209448 kb
Host smart-5cc6005f-30e7-4ec2-9dd2-fab2719427e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820073330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2820073330
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3629452808
Short name T289
Test name
Test status
Simulation time 111442006 ps
CPU time 1.74 seconds
Started Jan 17 12:54:43 PM PST 24
Finished Jan 17 12:54:46 PM PST 24
Peak memory 219416 kb
Host smart-948c93a3-baec-4d67-aedd-62360ca8326d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629452808 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3629452808
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3017445116
Short name T238
Test name
Test status
Simulation time 52602172 ps
CPU time 0.99 seconds
Started Jan 17 12:54:26 PM PST 24
Finished Jan 17 12:54:28 PM PST 24
Peak memory 209584 kb
Host smart-75866036-25af-44ff-839c-7f23311991e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017445116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3017445116
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1421409852
Short name T147
Test name
Test status
Simulation time 240402606 ps
CPU time 1.22 seconds
Started Jan 17 12:54:26 PM PST 24
Finished Jan 17 12:54:28 PM PST 24
Peak memory 209296 kb
Host smart-d05b5dfd-abbf-4655-848c-cde0579917b5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421409852 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1421409852
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3852615040
Short name T202
Test name
Test status
Simulation time 3439050897 ps
CPU time 7.75 seconds
Started Jan 17 12:54:28 PM PST 24
Finished Jan 17 12:54:37 PM PST 24
Peak memory 209600 kb
Host smart-2a1d475c-c700-4379-a92a-c5f725977c54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852615040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3852615040
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2828855419
Short name T150
Test name
Test status
Simulation time 1566986072 ps
CPU time 18.3 seconds
Started Jan 17 12:54:28 PM PST 24
Finished Jan 17 12:54:48 PM PST 24
Peak memory 209480 kb
Host smart-9e80e49f-291b-4620-83c7-c52cdd4ef905
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828855419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2828855419
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4120735067
Short name T214
Test name
Test status
Simulation time 306329924 ps
CPU time 1.61 seconds
Started Jan 17 12:54:36 PM PST 24
Finished Jan 17 12:54:39 PM PST 24
Peak memory 210896 kb
Host smart-dbc6e64c-148d-4eb1-97c5-ecb55a2fbf27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120735067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4120735067
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1960475334
Short name T264
Test name
Test status
Simulation time 146300939 ps
CPU time 2.47 seconds
Started Jan 17 12:54:26 PM PST 24
Finished Jan 17 12:54:29 PM PST 24
Peak memory 222928 kb
Host smart-585103aa-daa3-43d7-ac66-89a13f8bce3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196047
5334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1960475334
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2331111713
Short name T222
Test name
Test status
Simulation time 96482142 ps
CPU time 1.55 seconds
Started Jan 17 12:54:28 PM PST 24
Finished Jan 17 12:54:31 PM PST 24
Peak memory 209420 kb
Host smart-61ddf775-e19b-46b7-ba82-fac081fc5e8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331111713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2331111713
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1540798685
Short name T161
Test name
Test status
Simulation time 29420474 ps
CPU time 1.14 seconds
Started Jan 17 12:54:25 PM PST 24
Finished Jan 17 12:54:27 PM PST 24
Peak memory 209512 kb
Host smart-ee6914e8-d1ca-4bd9-9a33-e685bd41eb7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540798685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1540798685
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4277434971
Short name T129
Test name
Test status
Simulation time 70693203 ps
CPU time 2.34 seconds
Started Jan 17 12:54:31 PM PST 24
Finished Jan 17 12:54:35 PM PST 24
Peak memory 217604 kb
Host smart-5073892c-7b1b-4594-900e-b65a507d065e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277434971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.4277434971
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.82941948
Short name T251
Test name
Test status
Simulation time 53452265 ps
CPU time 1.32 seconds
Started Jan 17 12:54:44 PM PST 24
Finished Jan 17 12:54:46 PM PST 24
Peak memory 219296 kb
Host smart-0a2200f8-4ca0-4f2d-91f7-093cd1abfafe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82941948 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.82941948
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2425954930
Short name T174
Test name
Test status
Simulation time 33373044 ps
CPU time 0.94 seconds
Started Jan 17 12:54:36 PM PST 24
Finished Jan 17 12:54:37 PM PST 24
Peak memory 209492 kb
Host smart-2d222f7d-ed92-4e6e-a0f8-501ee1ad52f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425954930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2425954930
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3335349013
Short name T186
Test name
Test status
Simulation time 138027569 ps
CPU time 1.19 seconds
Started Jan 17 12:54:38 PM PST 24
Finished Jan 17 12:54:42 PM PST 24
Peak memory 209436 kb
Host smart-859eca73-60db-4dec-a723-1dd88d9b8972
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335349013 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3335349013
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1159840284
Short name T149
Test name
Test status
Simulation time 840012490 ps
CPU time 5.51 seconds
Started Jan 17 12:54:44 PM PST 24
Finished Jan 17 12:54:50 PM PST 24
Peak memory 209452 kb
Host smart-ae32b4df-b318-4399-a8f2-68f1ac79f339
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159840284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1159840284
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.706575174
Short name T233
Test name
Test status
Simulation time 2540649152 ps
CPU time 21.29 seconds
Started Jan 17 12:54:35 PM PST 24
Finished Jan 17 12:54:57 PM PST 24
Peak memory 208268 kb
Host smart-60082f43-2c53-4ee2-9de0-3954f373099d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706575174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.706575174
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1906311497
Short name T151
Test name
Test status
Simulation time 288931960 ps
CPU time 1.72 seconds
Started Jan 17 12:54:45 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 210596 kb
Host smart-648ea65c-1687-4861-b3cf-956aa9492ec9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906311497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1906311497
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3872710186
Short name T263
Test name
Test status
Simulation time 61120723 ps
CPU time 1.45 seconds
Started Jan 17 12:54:38 PM PST 24
Finished Jan 17 12:54:41 PM PST 24
Peak memory 209468 kb
Host smart-a12de396-cf7e-4f40-b7cc-b672d4ebf915
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872710186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3872710186
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3586688555
Short name T212
Test name
Test status
Simulation time 130242419 ps
CPU time 1.36 seconds
Started Jan 17 12:54:44 PM PST 24
Finished Jan 17 12:54:46 PM PST 24
Peak memory 211380 kb
Host smart-0c87b1ef-b183-40ae-87a3-80838db76348
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586688555 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3586688555
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1169780232
Short name T216
Test name
Test status
Simulation time 22395451 ps
CPU time 1.2 seconds
Started Jan 17 12:54:45 PM PST 24
Finished Jan 17 12:54:54 PM PST 24
Peak memory 209576 kb
Host smart-5462c1f7-dd1c-4fbe-81da-15e47da23d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169780232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1169780232
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2155474557
Short name T284
Test name
Test status
Simulation time 107366905 ps
CPU time 2.82 seconds
Started Jan 17 12:54:42 PM PST 24
Finished Jan 17 12:54:47 PM PST 24
Peak memory 217792 kb
Host smart-bfe115c4-8a42-4ea3-a467-b997811e434a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155474557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2155474557
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.278399720
Short name T444
Test name
Test status
Simulation time 81293076 ps
CPU time 1.12 seconds
Started Jan 17 12:47:57 PM PST 24
Finished Jan 17 12:47:59 PM PST 24
Peak memory 208428 kb
Host smart-b1ed8dcc-c153-4532-bc58-041288a98327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278399720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.278399720
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3484229017
Short name T864
Test name
Test status
Simulation time 24571075 ps
CPU time 0.77 seconds
Started Jan 17 12:47:44 PM PST 24
Finished Jan 17 12:47:50 PM PST 24
Peak memory 209344 kb
Host smart-a6a040f7-e0cc-4c20-ac51-9d4442690422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484229017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3484229017
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.577767311
Short name T507
Test name
Test status
Simulation time 1643132004 ps
CPU time 14.51 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:48:07 PM PST 24
Peak memory 218172 kb
Host smart-e93f3443-e959-4bf1-b4bd-f6ecddb41c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577767311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.577767311
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2855888826
Short name T487
Test name
Test status
Simulation time 483026016 ps
CPU time 2.55 seconds
Started Jan 17 12:47:52 PM PST 24
Finished Jan 17 12:47:57 PM PST 24
Peak memory 209628 kb
Host smart-401baf73-3165-4a25-b6d2-771e6c98c9a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855888826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.2855888826
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3698641794
Short name T657
Test name
Test status
Simulation time 11748509690 ps
CPU time 76.83 seconds
Started Jan 17 12:47:55 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 218732 kb
Host smart-8a7d2c67-2694-411e-ae49-f9d82c93a65e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698641794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3698641794
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2110254631
Short name T563
Test name
Test status
Simulation time 235019443 ps
CPU time 1.81 seconds
Started Jan 17 12:47:47 PM PST 24
Finished Jan 17 12:47:51 PM PST 24
Peak memory 209736 kb
Host smart-99807d09-55a1-4574-bf38-2d5224deb2de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110254631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.2110254631
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1912450406
Short name T851
Test name
Test status
Simulation time 94031131 ps
CPU time 2.67 seconds
Started Jan 17 12:47:54 PM PST 24
Finished Jan 17 12:47:58 PM PST 24
Peak memory 218140 kb
Host smart-c91b0a2b-3060-4190-bb29-8b14996a32a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912450406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1912450406
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2715012383
Short name T476
Test name
Test status
Simulation time 975941768 ps
CPU time 14.77 seconds
Started Jan 17 12:47:51 PM PST 24
Finished Jan 17 12:48:09 PM PST 24
Peak memory 213404 kb
Host smart-abe5d871-8ad8-4b2c-bfd9-428983a35c1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715012383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2715012383
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3227526026
Short name T744
Test name
Test status
Simulation time 969621665 ps
CPU time 4.44 seconds
Started Jan 17 12:47:44 PM PST 24
Finished Jan 17 12:47:53 PM PST 24
Peak memory 213084 kb
Host smart-4c27f285-0078-49b5-96c8-68cc78838d78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227526026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3227526026
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1095021408
Short name T484
Test name
Test status
Simulation time 1485004410 ps
CPU time 48.58 seconds
Started Jan 17 12:47:47 PM PST 24
Finished Jan 17 12:48:38 PM PST 24
Peak memory 251020 kb
Host smart-ad5ae054-decd-4cf4-999b-ff4bfd973079
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095021408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1095021408
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3126778851
Short name T17
Test name
Test status
Simulation time 521061967 ps
CPU time 17.53 seconds
Started Jan 17 12:47:58 PM PST 24
Finished Jan 17 12:48:17 PM PST 24
Peak memory 250852 kb
Host smart-f20b5ede-0fb2-426e-9c8b-72df9612930d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126778851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3126778851
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.639951021
Short name T429
Test name
Test status
Simulation time 44971316 ps
CPU time 2.45 seconds
Started Jan 17 12:47:42 PM PST 24
Finished Jan 17 12:47:51 PM PST 24
Peak memory 218184 kb
Host smart-73273e38-8272-4222-80a6-d060a7bde05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639951021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.639951021
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1269395307
Short name T360
Test name
Test status
Simulation time 531418909 ps
CPU time 6.29 seconds
Started Jan 17 12:47:41 PM PST 24
Finished Jan 17 12:47:55 PM PST 24
Peak memory 214164 kb
Host smart-d08400c2-256b-4a3f-97bf-02e1c8dee8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269395307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1269395307
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3659725704
Short name T106
Test name
Test status
Simulation time 409972797 ps
CPU time 41.24 seconds
Started Jan 17 12:47:56 PM PST 24
Finished Jan 17 12:48:38 PM PST 24
Peak memory 267100 kb
Host smart-a95bfc97-f9b2-4900-a8b9-8831042c87bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659725704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3659725704
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2127949460
Short name T770
Test name
Test status
Simulation time 350989152 ps
CPU time 12.67 seconds
Started Jan 17 12:47:58 PM PST 24
Finished Jan 17 12:48:12 PM PST 24
Peak memory 218492 kb
Host smart-6a25233a-9f68-49fb-b454-fa0ddfe2a781
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127949460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2127949460
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1770409401
Short name T630
Test name
Test status
Simulation time 565263961 ps
CPU time 11.11 seconds
Started Jan 17 12:47:58 PM PST 24
Finished Jan 17 12:48:10 PM PST 24
Peak memory 218116 kb
Host smart-89a82d83-8cb6-4336-b7d3-966da347c2b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770409401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1770409401
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3257089697
Short name T30
Test name
Test status
Simulation time 214127856 ps
CPU time 5.36 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:07 PM PST 24
Peak memory 218208 kb
Host smart-03e1f31f-73a1-4917-81d7-34c644fefc0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257089697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
257089697
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.266152817
Short name T404
Test name
Test status
Simulation time 486281666 ps
CPU time 15.76 seconds
Started Jan 17 12:47:45 PM PST 24
Finished Jan 17 12:48:05 PM PST 24
Peak memory 218176 kb
Host smart-5dd8e547-0ab2-4651-9f38-c7aca323c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266152817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.266152817
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.471597656
Short name T796
Test name
Test status
Simulation time 57591688 ps
CPU time 2.1 seconds
Started Jan 17 12:47:41 PM PST 24
Finished Jan 17 12:47:51 PM PST 24
Peak memory 213672 kb
Host smart-0c7aa737-4409-4b48-a5ec-944d7575a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471597656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.471597656
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3279497191
Short name T594
Test name
Test status
Simulation time 315131740 ps
CPU time 23.1 seconds
Started Jan 17 12:47:38 PM PST 24
Finished Jan 17 12:48:10 PM PST 24
Peak memory 251084 kb
Host smart-7fbc5713-bead-4f01-a993-a53372754247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279497191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3279497191
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3709094643
Short name T778
Test name
Test status
Simulation time 365888300 ps
CPU time 6.43 seconds
Started Jan 17 12:47:41 PM PST 24
Finished Jan 17 12:47:55 PM PST 24
Peak memory 246664 kb
Host smart-e513e4c8-d2a6-4624-bb5b-3bfa8bc760bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709094643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3709094643
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1243397147
Short name T347
Test name
Test status
Simulation time 22003046748 ps
CPU time 91.46 seconds
Started Jan 17 12:47:47 PM PST 24
Finished Jan 17 12:49:21 PM PST 24
Peak memory 283904 kb
Host smart-d51de6e1-7a2f-4862-b5c3-03a25d6735e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243397147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1243397147
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.752516261
Short name T760
Test name
Test status
Simulation time 40330537 ps
CPU time 0.79 seconds
Started Jan 17 12:47:42 PM PST 24
Finished Jan 17 12:47:50 PM PST 24
Peak memory 208464 kb
Host smart-e398963d-7c62-40ba-b66b-f62e6beabcd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752516261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.752516261
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1706825032
Short name T982
Test name
Test status
Simulation time 16079497 ps
CPU time 1 seconds
Started Jan 17 12:47:54 PM PST 24
Finished Jan 17 12:47:56 PM PST 24
Peak memory 209856 kb
Host smart-1de7c964-1bde-42e2-ae67-5152358df9eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706825032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1706825032
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.4174297104
Short name T869
Test name
Test status
Simulation time 6998193678 ps
CPU time 6.5 seconds
Started Jan 17 12:47:44 PM PST 24
Finished Jan 17 12:47:55 PM PST 24
Peak memory 209488 kb
Host smart-be6a44c4-5db8-4b99-8198-fb82efe179d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174297104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.4174297104
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2715646534
Short name T474
Test name
Test status
Simulation time 2001983625 ps
CPU time 31.65 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:48:24 PM PST 24
Peak memory 218128 kb
Host smart-38aaf67c-205a-4281-ae49-d7877b00c2cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715646534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2715646534
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2351770632
Short name T427
Test name
Test status
Simulation time 3315188864 ps
CPU time 28.61 seconds
Started Jan 17 12:47:53 PM PST 24
Finished Jan 17 12:48:24 PM PST 24
Peak memory 217976 kb
Host smart-77a3a220-47bb-48b9-8725-21db256fe4af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351770632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.2351770632
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1765249640
Short name T582
Test name
Test status
Simulation time 1436729132 ps
CPU time 11.29 seconds
Started Jan 17 12:47:52 PM PST 24
Finished Jan 17 12:48:06 PM PST 24
Peak memory 218108 kb
Host smart-bd2675b1-8b62-4b76-b10c-7ca3005f4990
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765249640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1765249640
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2368740055
Short name T526
Test name
Test status
Simulation time 2366676843 ps
CPU time 34 seconds
Started Jan 17 12:47:49 PM PST 24
Finished Jan 17 12:48:27 PM PST 24
Peak memory 213336 kb
Host smart-ed72be9f-57c1-4cc4-8c75-0be8d4b00661
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368740055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2368740055
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3406270167
Short name T351
Test name
Test status
Simulation time 74007896 ps
CPU time 1.6 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:47:54 PM PST 24
Peak memory 212404 kb
Host smart-d557086c-81d3-431c-92bb-8cfdcbb91e52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406270167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3406270167
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1568753212
Short name T452
Test name
Test status
Simulation time 2147734065 ps
CPU time 32.91 seconds
Started Jan 17 12:47:46 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 251160 kb
Host smart-e15a2f31-f30d-41df-87bc-a8ba4a8d2aa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568753212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1568753212
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1559365880
Short name T827
Test name
Test status
Simulation time 2066674652 ps
CPU time 21.17 seconds
Started Jan 17 12:47:54 PM PST 24
Finished Jan 17 12:48:17 PM PST 24
Peak memory 251076 kb
Host smart-e94bfbb2-b57a-4939-96da-fe1c7bc71f05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559365880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1559365880
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1864214984
Short name T810
Test name
Test status
Simulation time 21103342 ps
CPU time 1.64 seconds
Started Jan 17 12:47:52 PM PST 24
Finished Jan 17 12:47:56 PM PST 24
Peak memory 218176 kb
Host smart-7ba9ade9-d69c-482d-a5df-65dea1287edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864214984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1864214984
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.573311458
Short name T824
Test name
Test status
Simulation time 248148522 ps
CPU time 16.49 seconds
Started Jan 17 12:47:52 PM PST 24
Finished Jan 17 12:48:11 PM PST 24
Peak memory 214180 kb
Host smart-f37a32bd-5799-428a-b65d-429f050c0a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573311458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.573311458
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.892189866
Short name T14
Test name
Test status
Simulation time 1329868797 ps
CPU time 35.5 seconds
Started Jan 17 12:47:57 PM PST 24
Finished Jan 17 12:48:33 PM PST 24
Peak memory 284444 kb
Host smart-5fcd3b0d-abef-40cd-961a-6e8aac64fed1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892189866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.892189866
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4125162271
Short name T559
Test name
Test status
Simulation time 335708950 ps
CPU time 15.45 seconds
Started Jan 17 12:47:46 PM PST 24
Finished Jan 17 12:48:04 PM PST 24
Peak memory 219168 kb
Host smart-1663d299-16c5-4640-bcb2-a32c6bf5ee38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125162271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4125162271
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3844335073
Short name T626
Test name
Test status
Simulation time 1677556924 ps
CPU time 12.04 seconds
Started Jan 17 12:47:44 PM PST 24
Finished Jan 17 12:48:01 PM PST 24
Peak memory 218116 kb
Host smart-8251ae21-c179-4af6-a4e5-fbf34e005d3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844335073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3844335073
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2125515460
Short name T608
Test name
Test status
Simulation time 557068918 ps
CPU time 12.46 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:14 PM PST 24
Peak memory 218064 kb
Host smart-2cd08ef0-a3df-46a9-b6e7-d4eda2121656
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125515460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
125515460
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4037601196
Short name T674
Test name
Test status
Simulation time 244187205 ps
CPU time 10.61 seconds
Started Jan 17 12:47:40 PM PST 24
Finished Jan 17 12:47:59 PM PST 24
Peak memory 218168 kb
Host smart-fb7be40d-70dd-405a-8bad-d0163f46c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037601196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4037601196
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2484428868
Short name T900
Test name
Test status
Simulation time 170075217 ps
CPU time 2.52 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:03 PM PST 24
Peak memory 213712 kb
Host smart-44b111fa-b178-42b9-84e4-5cda0bc09a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484428868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2484428868
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.4013758322
Short name T926
Test name
Test status
Simulation time 541153337 ps
CPU time 21.88 seconds
Started Jan 17 12:47:53 PM PST 24
Finished Jan 17 12:48:17 PM PST 24
Peak memory 251092 kb
Host smart-b6df9f45-3cb3-4370-b1ea-c0250d432674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013758322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.4013758322
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.814472760
Short name T536
Test name
Test status
Simulation time 139451155 ps
CPU time 7.19 seconds
Started Jan 17 12:47:42 PM PST 24
Finished Jan 17 12:47:56 PM PST 24
Peak memory 246212 kb
Host smart-406fd685-17e4-4359-a10d-fff241e732e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814472760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.814472760
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4038527943
Short name T66
Test name
Test status
Simulation time 6422935723 ps
CPU time 163.32 seconds
Started Jan 17 12:47:47 PM PST 24
Finished Jan 17 12:50:33 PM PST 24
Peak memory 251248 kb
Host smart-3156fe94-327b-4070-b064-a0476ab904ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038527943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4038527943
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3572141039
Short name T946
Test name
Test status
Simulation time 21831151 ps
CPU time 1.05 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 209656 kb
Host smart-e286ad40-0171-4fa8-b69b-9dbf00080557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572141039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3572141039
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2459588752
Short name T710
Test name
Test status
Simulation time 830496967 ps
CPU time 10.95 seconds
Started Jan 17 12:48:18 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 218252 kb
Host smart-58754843-b6dd-4fda-96d1-77c794fe6bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459588752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2459588752
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3505057992
Short name T954
Test name
Test status
Simulation time 748321755 ps
CPU time 5.44 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:26 PM PST 24
Peak memory 209912 kb
Host smart-0c50ee0b-91aa-4f5b-9394-cd0e6e374027
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505057992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.3505057992
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2497011748
Short name T434
Test name
Test status
Simulation time 1311863875 ps
CPU time 28 seconds
Started Jan 17 12:48:17 PM PST 24
Finished Jan 17 12:48:48 PM PST 24
Peak memory 218096 kb
Host smart-915154a1-a71d-465b-87ce-807c64530c7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497011748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2497011748
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1140046251
Short name T867
Test name
Test status
Simulation time 371720465 ps
CPU time 11.6 seconds
Started Jan 17 12:48:17 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 218124 kb
Host smart-593b58b8-6ba7-45d8-9a9a-72e0af80a907
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140046251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1140046251
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3751253322
Short name T88
Test name
Test status
Simulation time 989792646 ps
CPU time 3.94 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 213176 kb
Host smart-bf1f5dd6-7344-4c23-a383-ca1a7de8e2df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751253322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3751253322
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.4264977393
Short name T19
Test name
Test status
Simulation time 2259705476 ps
CPU time 62.36 seconds
Started Jan 17 12:48:43 PM PST 24
Finished Jan 17 12:49:49 PM PST 24
Peak memory 283788 kb
Host smart-378a7540-37e9-422f-8984-2c97094a5fd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264977393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.4264977393
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.109762159
Short name T607
Test name
Test status
Simulation time 749387566 ps
CPU time 18.15 seconds
Started Jan 17 12:48:22 PM PST 24
Finished Jan 17 12:48:41 PM PST 24
Peak memory 251092 kb
Host smart-cba615ec-bb7c-4411-b9f3-c35a32b81819
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109762159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.109762159
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2447618774
Short name T394
Test name
Test status
Simulation time 25251034 ps
CPU time 2.05 seconds
Started Jan 17 12:48:35 PM PST 24
Finished Jan 17 12:48:38 PM PST 24
Peak memory 218120 kb
Host smart-5fb0935f-fbcf-4f4e-840a-2e5d8828ecdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447618774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2447618774
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1726784422
Short name T915
Test name
Test status
Simulation time 276320132 ps
CPU time 9.71 seconds
Started Jan 17 12:48:15 PM PST 24
Finished Jan 17 12:48:29 PM PST 24
Peak memory 218348 kb
Host smart-3716a93d-8792-451d-914f-c58a47c5bb6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726784422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1726784422
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.122969678
Short name T706
Test name
Test status
Simulation time 4551631821 ps
CPU time 12.49 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:33 PM PST 24
Peak memory 218148 kb
Host smart-5490a390-4a8f-4479-adc3-26996747a922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122969678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.122969678
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1667851007
Short name T416
Test name
Test status
Simulation time 2527524125 ps
CPU time 10.79 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:48:32 PM PST 24
Peak memory 218456 kb
Host smart-8ef19fe6-2142-4328-a082-1bb2c40644a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667851007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1667851007
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.976324494
Short name T368
Test name
Test status
Simulation time 930767730 ps
CPU time 21.19 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 251112 kb
Host smart-c5c07ed2-352a-463c-a346-4f138508c033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976324494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.976324494
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3770731483
Short name T718
Test name
Test status
Simulation time 285560029 ps
CPU time 6.93 seconds
Started Jan 17 12:48:15 PM PST 24
Finished Jan 17 12:48:26 PM PST 24
Peak memory 245312 kb
Host smart-2b0cf28f-3313-45fd-a409-f555df75e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770731483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3770731483
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3406795747
Short name T579
Test name
Test status
Simulation time 39748748 ps
CPU time 0.87 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 208104 kb
Host smart-d60e0da7-0855-4edc-8e13-f0d62d5a5ca3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406795747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3406795747
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3147300600
Short name T459
Test name
Test status
Simulation time 24482472 ps
CPU time 1.27 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:48:23 PM PST 24
Peak memory 209668 kb
Host smart-1e4d04be-a662-466b-b641-8ff3a2816a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147300600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3147300600
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.251203591
Short name T541
Test name
Test status
Simulation time 233783790 ps
CPU time 7.65 seconds
Started Jan 17 12:48:23 PM PST 24
Finished Jan 17 12:48:32 PM PST 24
Peak memory 218116 kb
Host smart-c91b3433-9225-4402-ad27-032dd6457bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251203591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.251203591
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3092767473
Short name T540
Test name
Test status
Simulation time 1156963178 ps
CPU time 25.62 seconds
Started Jan 17 12:48:17 PM PST 24
Finished Jan 17 12:48:45 PM PST 24
Peak memory 209608 kb
Host smart-37a9aecb-e701-478c-82c6-10c398ff290d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092767473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.3092767473
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3596628756
Short name T522
Test name
Test status
Simulation time 6453246171 ps
CPU time 29.83 seconds
Started Jan 17 12:48:18 PM PST 24
Finished Jan 17 12:48:50 PM PST 24
Peak memory 218456 kb
Host smart-e26f8475-1321-4b59-aa5d-80a4c2654e56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596628756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3596628756
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1595544234
Short name T670
Test name
Test status
Simulation time 96855506 ps
CPU time 2.62 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:20 PM PST 24
Peak memory 218088 kb
Host smart-4e55544f-6e04-4562-b70d-ea695a7f4690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595544234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1595544234
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.39343833
Short name T529
Test name
Test status
Simulation time 65425297 ps
CPU time 2.51 seconds
Started Jan 17 12:48:26 PM PST 24
Finished Jan 17 12:48:29 PM PST 24
Peak memory 212684 kb
Host smart-52920414-feac-4d3f-86af-0e11d1b1111c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39343833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.39343833
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1164847764
Short name T369
Test name
Test status
Simulation time 930542851 ps
CPU time 30.08 seconds
Started Jan 17 12:48:25 PM PST 24
Finished Jan 17 12:48:56 PM PST 24
Peak memory 250916 kb
Host smart-263c9508-6cc3-421d-954a-fbe3cecfed86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164847764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1164847764
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1350939080
Short name T398
Test name
Test status
Simulation time 1962123528 ps
CPU time 19.13 seconds
Started Jan 17 12:48:18 PM PST 24
Finished Jan 17 12:48:39 PM PST 24
Peak memory 250596 kb
Host smart-34d7e7b5-2ed9-46f6-9845-0cfde11b0411
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350939080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1350939080
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.4004071565
Short name T504
Test name
Test status
Simulation time 209353990 ps
CPU time 1.77 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 218156 kb
Host smart-a7615527-34d7-4fe4-a2da-eaaa121bcba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004071565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.4004071565
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.731708515
Short name T409
Test name
Test status
Simulation time 265139232 ps
CPU time 11.16 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:29 PM PST 24
Peak memory 219196 kb
Host smart-c10542d9-8a9f-4f09-9234-613bd4070785
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731708515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.731708515
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2698998334
Short name T893
Test name
Test status
Simulation time 288398215 ps
CPU time 9.44 seconds
Started Jan 17 12:48:18 PM PST 24
Finished Jan 17 12:48:29 PM PST 24
Peak memory 218076 kb
Host smart-ad5b0283-5bd8-4764-8ffd-a4ef9344c976
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698998334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2698998334
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1530710218
Short name T791
Test name
Test status
Simulation time 698832820 ps
CPU time 13.1 seconds
Started Jan 17 12:48:17 PM PST 24
Finished Jan 17 12:48:33 PM PST 24
Peak memory 218064 kb
Host smart-7b658f1d-3989-42ba-af81-9b6f39eaf545
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530710218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1530710218
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1390879563
Short name T458
Test name
Test status
Simulation time 258943419 ps
CPU time 9.65 seconds
Started Jan 17 12:48:23 PM PST 24
Finished Jan 17 12:48:34 PM PST 24
Peak memory 218120 kb
Host smart-5b8edcfd-1f9a-4da5-b5ec-82f7c45b3bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390879563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1390879563
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2014342224
Short name T912
Test name
Test status
Simulation time 86470295 ps
CPU time 2.51 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:48:48 PM PST 24
Peak memory 214068 kb
Host smart-6aa38637-bde9-428b-bc00-c84f2a08fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014342224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2014342224
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3102047359
Short name T786
Test name
Test status
Simulation time 256185635 ps
CPU time 32.42 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:48:54 PM PST 24
Peak memory 251088 kb
Host smart-341790c8-976c-4513-b8bb-024b0663f464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102047359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3102047359
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1928144492
Short name T552
Test name
Test status
Simulation time 364779922 ps
CPU time 7.7 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:26 PM PST 24
Peak memory 245908 kb
Host smart-7d6b7e3d-976f-4240-a074-89fe7af9619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928144492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1928144492
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1434012876
Short name T600
Test name
Test status
Simulation time 25531606978 ps
CPU time 190.85 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:51:22 PM PST 24
Peak memory 283460 kb
Host smart-82a79e8e-0e31-49bc-9d3c-c556d7cbe9b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434012876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1434012876
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3123119613
Short name T767
Test name
Test status
Simulation time 21647398 ps
CPU time 0.74 seconds
Started Jan 17 12:48:24 PM PST 24
Finished Jan 17 12:48:25 PM PST 24
Peak memory 207812 kb
Host smart-dc39bc12-634f-4c3a-a0ad-b26dc409ab5c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123119613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3123119613
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1912985461
Short name T553
Test name
Test status
Simulation time 799354228 ps
CPU time 9.13 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 218160 kb
Host smart-7bc00e28-e4de-445d-940e-1472b4856658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912985461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1912985461
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.59917469
Short name T442
Test name
Test status
Simulation time 149104515 ps
CPU time 1.12 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 12:52:15 PM PST 24
Peak memory 209768 kb
Host smart-aa61e3ea-b7a5-4d13-b3ef-e7414be2772d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59917469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_acc
ess.59917469
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1306850429
Short name T704
Test name
Test status
Simulation time 6145780340 ps
CPU time 40.73 seconds
Started Jan 17 12:48:23 PM PST 24
Finished Jan 17 12:49:05 PM PST 24
Peak memory 218324 kb
Host smart-7ae02013-5dcb-4beb-b501-49bbe4bc8e1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306850429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1306850429
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3924014113
Short name T500
Test name
Test status
Simulation time 164014420 ps
CPU time 4.07 seconds
Started Jan 17 12:48:32 PM PST 24
Finished Jan 17 12:48:37 PM PST 24
Peak memory 218108 kb
Host smart-bfdc4e69-a776-401e-b36f-6d4183b65bf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924014113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3924014113
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1876708236
Short name T742
Test name
Test status
Simulation time 174888403 ps
CPU time 3.64 seconds
Started Jan 17 12:48:33 PM PST 24
Finished Jan 17 12:48:38 PM PST 24
Peak memory 213120 kb
Host smart-206747c1-5557-482a-9d62-02e81473510e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876708236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1876708236
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.420254474
Short name T665
Test name
Test status
Simulation time 1609397918 ps
CPU time 42.63 seconds
Started Jan 17 12:48:33 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 267452 kb
Host smart-1287136d-fd71-433c-b95c-197ed1001937
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420254474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.420254474
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2354300259
Short name T853
Test name
Test status
Simulation time 293378396 ps
CPU time 12.55 seconds
Started Jan 17 12:48:29 PM PST 24
Finished Jan 17 12:48:43 PM PST 24
Peak memory 251052 kb
Host smart-e76c7980-cc37-401f-a725-c3cc8d1ed6aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354300259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2354300259
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.649417938
Short name T414
Test name
Test status
Simulation time 41107928 ps
CPU time 2.47 seconds
Started Jan 17 12:48:22 PM PST 24
Finished Jan 17 12:48:25 PM PST 24
Peak memory 218196 kb
Host smart-96e36f18-b31c-472d-aebf-326862a28d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649417938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.649417938
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.4244180398
Short name T933
Test name
Test status
Simulation time 384475937 ps
CPU time 14.89 seconds
Started Jan 17 12:48:35 PM PST 24
Finished Jan 17 12:48:51 PM PST 24
Peak memory 218808 kb
Host smart-1bac6cdf-5953-462d-86f3-012fb8751673
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244180398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.4244180398
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2660550504
Short name T966
Test name
Test status
Simulation time 788013500 ps
CPU time 9.59 seconds
Started Jan 17 12:48:20 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 218136 kb
Host smart-a9063fb2-6542-476d-849a-69068faba688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660550504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2660550504
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3555258924
Short name T518
Test name
Test status
Simulation time 333498937 ps
CPU time 8.03 seconds
Started Jan 17 12:48:27 PM PST 24
Finished Jan 17 12:48:36 PM PST 24
Peak memory 218120 kb
Host smart-8e6e5537-bba9-40f8-8bc6-b3b5d62b3241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555258924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3555258924
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.137757239
Short name T511
Test name
Test status
Simulation time 842748434 ps
CPU time 15.11 seconds
Started Jan 17 12:48:20 PM PST 24
Finished Jan 17 12:48:36 PM PST 24
Peak memory 218140 kb
Host smart-33ad9dd9-b735-4ca0-846a-564467ecc35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137757239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.137757239
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.533924268
Short name T386
Test name
Test status
Simulation time 136913080 ps
CPU time 9.48 seconds
Started Jan 17 12:48:25 PM PST 24
Finished Jan 17 12:48:35 PM PST 24
Peak memory 213792 kb
Host smart-155a8a5c-ef1f-446d-9233-abb38ee59d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533924268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.533924268
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1073176973
Short name T482
Test name
Test status
Simulation time 386559161 ps
CPU time 37.87 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:58 PM PST 24
Peak memory 251104 kb
Host smart-da14ef79-a557-40b9-b622-d6c57d67dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073176973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1073176973
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2758638401
Short name T380
Test name
Test status
Simulation time 101059410 ps
CPU time 7.94 seconds
Started Jan 17 12:48:26 PM PST 24
Finished Jan 17 12:48:35 PM PST 24
Peak memory 251128 kb
Host smart-dcc91a1e-0e63-4400-95bb-23b5dc68c3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758638401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2758638401
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2486096337
Short name T603
Test name
Test status
Simulation time 8756531883 ps
CPU time 111.26 seconds
Started Jan 17 12:48:29 PM PST 24
Finished Jan 17 12:50:22 PM PST 24
Peak memory 276300 kb
Host smart-28e99645-544b-4118-8ccb-acc99bcf7032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486096337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2486096337
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4294455517
Short name T566
Test name
Test status
Simulation time 13488980 ps
CPU time 0.79 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:21 PM PST 24
Peak memory 208332 kb
Host smart-603ce882-ead6-47bc-8462-341a10592834
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294455517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4294455517
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3174605075
Short name T107
Test name
Test status
Simulation time 19158999 ps
CPU time 1.26 seconds
Started Jan 17 12:48:23 PM PST 24
Finished Jan 17 12:48:25 PM PST 24
Peak memory 209640 kb
Host smart-43ad80bb-ea6c-4432-b6d6-28d1806aff06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174605075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3174605075
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.577977696
Short name T348
Test name
Test status
Simulation time 1789917157 ps
CPU time 12.57 seconds
Started Jan 17 12:48:28 PM PST 24
Finished Jan 17 12:48:41 PM PST 24
Peak memory 218220 kb
Host smart-f057fc88-bafe-40ac-b712-9d4b9c6b3e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577977696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.577977696
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3345707622
Short name T965
Test name
Test status
Simulation time 2100820184 ps
CPU time 7.67 seconds
Started Jan 17 12:48:35 PM PST 24
Finished Jan 17 12:48:43 PM PST 24
Peak memory 209588 kb
Host smart-b40e2085-b6cd-4b72-bdb9-ac22d1c417c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345707622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_a
ccess.3345707622
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1560797129
Short name T405
Test name
Test status
Simulation time 470928078 ps
CPU time 4.37 seconds
Started Jan 17 12:48:24 PM PST 24
Finished Jan 17 12:48:29 PM PST 24
Peak memory 218136 kb
Host smart-bc9e8c06-16bb-4898-bb77-bcee6876b5d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560797129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1560797129
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2653877438
Short name T705
Test name
Test status
Simulation time 500539122 ps
CPU time 5.71 seconds
Started Jan 17 12:48:30 PM PST 24
Finished Jan 17 12:48:37 PM PST 24
Peak memory 213120 kb
Host smart-9f1e2f53-f86d-4452-9088-6ab8413bc3ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653877438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2653877438
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1456706628
Short name T748
Test name
Test status
Simulation time 1083120900 ps
CPU time 29.45 seconds
Started Jan 17 12:48:22 PM PST 24
Finished Jan 17 12:48:53 PM PST 24
Peak memory 251076 kb
Host smart-95977f31-9432-4ab4-ac20-357964572da1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456706628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1456706628
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1843499849
Short name T754
Test name
Test status
Simulation time 486067382 ps
CPU time 20.82 seconds
Started Jan 17 12:48:31 PM PST 24
Finished Jan 17 12:48:53 PM PST 24
Peak memory 251032 kb
Host smart-6f11309f-842c-460c-86da-54c9f11ce048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843499849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1843499849
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1667023884
Short name T771
Test name
Test status
Simulation time 14262143 ps
CPU time 1.58 seconds
Started Jan 17 12:48:28 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 218176 kb
Host smart-1b15483b-8638-438d-84ae-94e348f4748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667023884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1667023884
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1298070723
Short name T883
Test name
Test status
Simulation time 696008242 ps
CPU time 12.19 seconds
Started Jan 17 12:48:28 PM PST 24
Finished Jan 17 12:48:41 PM PST 24
Peak memory 218180 kb
Host smart-7ea0f9d6-436b-4122-b81e-494d16a8f8f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298070723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1298070723
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3914058858
Short name T838
Test name
Test status
Simulation time 1414207188 ps
CPU time 9.15 seconds
Started Jan 17 12:48:28 PM PST 24
Finished Jan 17 12:48:38 PM PST 24
Peak memory 218108 kb
Host smart-6223be3a-d05e-4872-8fdc-5b4aba2058dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914058858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3914058858
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2609757046
Short name T306
Test name
Test status
Simulation time 1823630320 ps
CPU time 8.01 seconds
Started Jan 17 12:48:42 PM PST 24
Finished Jan 17 12:48:54 PM PST 24
Peak memory 218048 kb
Host smart-74e5b515-bfc9-4fc5-83de-1c481ea20873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609757046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2609757046
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2346362609
Short name T910
Test name
Test status
Simulation time 409619743 ps
CPU time 9.58 seconds
Started Jan 17 12:48:22 PM PST 24
Finished Jan 17 12:48:32 PM PST 24
Peak memory 218200 kb
Host smart-869b129d-38e8-4db3-ad91-2c955bd695ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346362609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2346362609
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2015636841
Short name T81
Test name
Test status
Simulation time 132782247 ps
CPU time 2.8 seconds
Started Jan 17 12:48:20 PM PST 24
Finished Jan 17 12:48:24 PM PST 24
Peak memory 214184 kb
Host smart-df109846-a663-4e7b-b3bf-3d1631d318b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015636841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2015636841
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2736829509
Short name T461
Test name
Test status
Simulation time 1103639894 ps
CPU time 31.14 seconds
Started Jan 17 12:48:23 PM PST 24
Finished Jan 17 12:48:55 PM PST 24
Peak memory 251152 kb
Host smart-870c00c9-c5b1-432b-8b33-c26281beef84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736829509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2736829509
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2088484375
Short name T960
Test name
Test status
Simulation time 63154580 ps
CPU time 3.93 seconds
Started Jan 17 12:48:29 PM PST 24
Finished Jan 17 12:48:34 PM PST 24
Peak memory 222324 kb
Host smart-c159041b-bb71-4d25-b1c8-66305dec5c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088484375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2088484375
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2722484298
Short name T921
Test name
Test status
Simulation time 8595857769 ps
CPU time 27.79 seconds
Started Jan 17 12:48:29 PM PST 24
Finished Jan 17 12:48:58 PM PST 24
Peak memory 216272 kb
Host smart-5297c0b0-90bb-44e9-90e7-98dc1d1522fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722484298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2722484298
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.472461385
Short name T463
Test name
Test status
Simulation time 12898137 ps
CPU time 1.01 seconds
Started Jan 17 12:48:28 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 208364 kb
Host smart-c4c30c52-ddb8-46fd-8ef4-bf01398a5329
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472461385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.472461385
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3112400098
Short name T613
Test name
Test status
Simulation time 39697197 ps
CPU time 1.04 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:48:45 PM PST 24
Peak memory 209068 kb
Host smart-fcfafc47-f194-4956-b0b0-e78cad6d1772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112400098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3112400098
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2877914969
Short name T330
Test name
Test status
Simulation time 442345346 ps
CPU time 14.2 seconds
Started Jan 17 12:48:33 PM PST 24
Finished Jan 17 12:48:48 PM PST 24
Peak memory 218448 kb
Host smart-a866ff3c-2421-4483-aee3-f3810da61fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877914969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2877914969
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.996515838
Short name T530
Test name
Test status
Simulation time 267124404 ps
CPU time 3.88 seconds
Started Jan 17 12:48:27 PM PST 24
Finished Jan 17 12:48:32 PM PST 24
Peak memory 208528 kb
Host smart-0fa38ff0-6b75-49d0-bbd0-2acf53297595
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996515838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_ac
cess.996515838
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1385030456
Short name T792
Test name
Test status
Simulation time 1039252854 ps
CPU time 22.05 seconds
Started Jan 17 12:48:23 PM PST 24
Finished Jan 17 12:48:46 PM PST 24
Peak memory 218136 kb
Host smart-072200d1-3074-4efc-b488-ea549eae69b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385030456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1385030456
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2463086381
Short name T682
Test name
Test status
Simulation time 771336912 ps
CPU time 7.89 seconds
Started Jan 17 12:48:23 PM PST 24
Finished Jan 17 12:48:32 PM PST 24
Peak memory 218120 kb
Host smart-660044ee-7cfd-4f91-bfd4-198eba049df9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463086381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2463086381
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2235723755
Short name T539
Test name
Test status
Simulation time 1754937719 ps
CPU time 5.58 seconds
Started Jan 17 12:48:35 PM PST 24
Finished Jan 17 12:48:42 PM PST 24
Peak memory 213172 kb
Host smart-32dd54e2-3d0a-4e88-821c-0ecf650d681b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235723755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2235723755
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2522736989
Short name T494
Test name
Test status
Simulation time 5920787548 ps
CPU time 49.46 seconds
Started Jan 17 12:48:44 PM PST 24
Finished Jan 17 12:49:37 PM PST 24
Peak memory 267568 kb
Host smart-707a8098-1f12-4e1b-831d-17322780a6bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522736989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2522736989
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.634634967
Short name T947
Test name
Test status
Simulation time 1199519422 ps
CPU time 17.51 seconds
Started Jan 17 12:48:27 PM PST 24
Finished Jan 17 12:48:46 PM PST 24
Peak memory 249928 kb
Host smart-6c2f9c38-e08f-41c7-aaa2-07be68c8863e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634634967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.634634967
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.562968493
Short name T806
Test name
Test status
Simulation time 80773615 ps
CPU time 3.07 seconds
Started Jan 17 12:48:22 PM PST 24
Finished Jan 17 12:48:26 PM PST 24
Peak memory 218168 kb
Host smart-e77f1f73-8ab1-48da-8685-eda39d3297cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562968493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.562968493
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1125740735
Short name T49
Test name
Test status
Simulation time 3886632643 ps
CPU time 14.46 seconds
Started Jan 17 12:48:32 PM PST 24
Finished Jan 17 12:48:47 PM PST 24
Peak memory 219320 kb
Host smart-fc2f72b6-281c-49ea-b22d-cd87cd1cfd70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125740735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1125740735
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2785371205
Short name T605
Test name
Test status
Simulation time 9083569388 ps
CPU time 21.51 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:49:07 PM PST 24
Peak memory 218044 kb
Host smart-cc4fc169-7e35-4b6f-a283-76439e0e7812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785371205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2785371205
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.869569988
Short name T365
Test name
Test status
Simulation time 202988987 ps
CPU time 6.18 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:48:51 PM PST 24
Peak memory 218108 kb
Host smart-367ef8f4-4c66-45f4-a8b9-e6a21f7c6e8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869569988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.869569988
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.44531016
Short name T357
Test name
Test status
Simulation time 197054582 ps
CPU time 6.54 seconds
Started Jan 17 12:48:23 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 218180 kb
Host smart-971f8518-b815-4320-8498-215887bd73a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44531016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.44531016
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1478186269
Short name T419
Test name
Test status
Simulation time 20662298 ps
CPU time 1.83 seconds
Started Jan 17 12:48:26 PM PST 24
Finished Jan 17 12:48:29 PM PST 24
Peak memory 213672 kb
Host smart-768231e5-bcbd-4f40-ac58-5eae27e0e00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478186269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1478186269
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3502966777
Short name T450
Test name
Test status
Simulation time 744292762 ps
CPU time 17.2 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:48:39 PM PST 24
Peak memory 251120 kb
Host smart-ef383d3d-57b0-4d4d-b7ec-e79d2fdfc5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502966777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3502966777
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1940867899
Short name T815
Test name
Test status
Simulation time 252912102 ps
CPU time 7.92 seconds
Started Jan 17 12:48:28 PM PST 24
Finished Jan 17 12:48:37 PM PST 24
Peak memory 251180 kb
Host smart-35d425c3-e559-4014-ad89-51ab76ed4441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940867899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1940867899
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2302211356
Short name T73
Test name
Test status
Simulation time 21326641262 ps
CPU time 90.31 seconds
Started Jan 17 12:48:42 PM PST 24
Finished Jan 17 12:50:16 PM PST 24
Peak memory 288164 kb
Host smart-8e168b69-81cb-494d-a637-95b0b101b5aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302211356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2302211356
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3234224867
Short name T785
Test name
Test status
Simulation time 34802721 ps
CPU time 0.75 seconds
Started Jan 17 12:48:27 PM PST 24
Finished Jan 17 12:48:28 PM PST 24
Peak memory 207924 kb
Host smart-a5babd5e-00d4-4f82-8cf0-01d51fe6fed2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234224867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3234224867
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2185081937
Short name T325
Test name
Test status
Simulation time 43923018 ps
CPU time 0.79 seconds
Started Jan 17 12:48:36 PM PST 24
Finished Jan 17 12:48:38 PM PST 24
Peak memory 209536 kb
Host smart-aeee4e7b-0835-477c-91a8-261864857d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185081937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2185081937
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1129255258
Short name T309
Test name
Test status
Simulation time 9044751280 ps
CPU time 20.62 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:49:05 PM PST 24
Peak memory 218488 kb
Host smart-6dc94f42-6750-4309-9808-03513326a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129255258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1129255258
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2378040479
Short name T496
Test name
Test status
Simulation time 408184108 ps
CPU time 9.24 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:48:54 PM PST 24
Peak memory 209660 kb
Host smart-b3279b07-f7b6-4492-9c43-5a20b0deb765
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378040479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.2378040479
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1431003093
Short name T615
Test name
Test status
Simulation time 1299538284 ps
CPU time 26.34 seconds
Started Jan 17 12:48:34 PM PST 24
Finished Jan 17 12:49:02 PM PST 24
Peak memory 218144 kb
Host smart-7092f06d-694e-4d6f-8db1-c9b194d1ed4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431003093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1431003093
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1482333652
Short name T700
Test name
Test status
Simulation time 702337005 ps
CPU time 18.38 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:49:03 PM PST 24
Peak memory 217504 kb
Host smart-d47dd49a-7271-4f08-aa82-94a2d42dd291
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482333652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1482333652
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2686352428
Short name T752
Test name
Test status
Simulation time 1795923529 ps
CPU time 7.34 seconds
Started Jan 17 12:48:32 PM PST 24
Finished Jan 17 12:48:40 PM PST 24
Peak memory 213644 kb
Host smart-60aeca38-9170-4e4d-abc6-7a433a0c6883
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686352428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2686352428
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3907602014
Short name T761
Test name
Test status
Simulation time 3496367829 ps
CPU time 81.13 seconds
Started Jan 17 12:48:42 PM PST 24
Finished Jan 17 12:50:07 PM PST 24
Peak memory 283800 kb
Host smart-fed63656-fd9e-4814-a9fb-7e04128da374
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907602014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3907602014
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1612190052
Short name T4
Test name
Test status
Simulation time 15614681723 ps
CPU time 18.29 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:49:03 PM PST 24
Peak memory 226560 kb
Host smart-3f496f9d-8e63-4d02-8239-90c8d72ff86b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612190052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1612190052
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1580129949
Short name T308
Test name
Test status
Simulation time 180905858 ps
CPU time 2.94 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:48:51 PM PST 24
Peak memory 218208 kb
Host smart-e32dfed2-6331-42fd-8fdc-e1a5f4da2c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580129949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1580129949
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.461777260
Short name T378
Test name
Test status
Simulation time 478820437 ps
CPU time 14.06 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:48:59 PM PST 24
Peak memory 219176 kb
Host smart-882c9f18-68a6-4931-bac6-75200a64c542
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461777260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.461777260
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2321384763
Short name T655
Test name
Test status
Simulation time 971314329 ps
CPU time 11.07 seconds
Started Jan 17 12:48:38 PM PST 24
Finished Jan 17 12:48:50 PM PST 24
Peak memory 218100 kb
Host smart-4c24bb55-f0bb-485c-9d01-0493f2bd9a1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321384763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2321384763
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1610778740
Short name T349
Test name
Test status
Simulation time 1071111100 ps
CPU time 7.19 seconds
Started Jan 17 12:48:38 PM PST 24
Finished Jan 17 12:48:46 PM PST 24
Peak memory 218132 kb
Host smart-ef931376-17f0-4959-8a68-d0dcfba06b75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610778740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1610778740
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2211749005
Short name T181
Test name
Test status
Simulation time 872109777 ps
CPU time 11.66 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:48:57 PM PST 24
Peak memory 218136 kb
Host smart-b2658053-933a-4003-8999-e4fed8dffe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211749005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2211749005
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2631498785
Short name T932
Test name
Test status
Simulation time 376088153 ps
CPU time 5.62 seconds
Started Jan 17 12:48:42 PM PST 24
Finished Jan 17 12:48:52 PM PST 24
Peak memory 214336 kb
Host smart-0f90ddf0-7cc7-445e-874a-0ffc5e51ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631498785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2631498785
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.626145375
Short name T353
Test name
Test status
Simulation time 513909142 ps
CPU time 28.92 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:49:14 PM PST 24
Peak memory 251068 kb
Host smart-a82a91bd-143d-4d27-bfbb-1e2a01eef56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626145375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.626145375
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.42860213
Short name T680
Test name
Test status
Simulation time 100837567 ps
CPU time 8.07 seconds
Started Jan 17 12:48:35 PM PST 24
Finished Jan 17 12:48:44 PM PST 24
Peak memory 245980 kb
Host smart-c4db2219-d3a5-4d61-b2f1-79d0b15a327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42860213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.42860213
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.517561107
Short name T346
Test name
Test status
Simulation time 7946826839 ps
CPU time 60.11 seconds
Started Jan 17 12:48:39 PM PST 24
Finished Jan 17 12:49:39 PM PST 24
Peak memory 267628 kb
Host smart-afa09eb6-50b0-4078-a921-f60920e9417c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517561107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.517561107
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3954835481
Short name T40
Test name
Test status
Simulation time 136670486 ps
CPU time 0.78 seconds
Started Jan 17 12:48:34 PM PST 24
Finished Jan 17 12:48:36 PM PST 24
Peak memory 208164 kb
Host smart-fafac72f-1c29-4f08-9ed4-c6eb75b3cb54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954835481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3954835481
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3143111492
Short name T774
Test name
Test status
Simulation time 118925076 ps
CPU time 1.15 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:48:46 PM PST 24
Peak memory 209716 kb
Host smart-79673ea6-cabe-4d55-a052-2689fef78a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143111492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3143111492
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1424619062
Short name T676
Test name
Test status
Simulation time 332132068 ps
CPU time 17.06 seconds
Started Jan 17 12:48:38 PM PST 24
Finished Jan 17 12:48:56 PM PST 24
Peak memory 218104 kb
Host smart-90285fb3-a245-42be-8210-ab0ac43098ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424619062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1424619062
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1035684222
Short name T493
Test name
Test status
Simulation time 192341974 ps
CPU time 1.35 seconds
Started Jan 17 12:48:44 PM PST 24
Finished Jan 17 12:48:49 PM PST 24
Peak memory 209700 kb
Host smart-45a0e3fb-3662-4b38-8077-54a29a2434a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035684222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.1035684222
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3920844853
Short name T561
Test name
Test status
Simulation time 5066765133 ps
CPU time 57.68 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:49:43 PM PST 24
Peak memory 219204 kb
Host smart-8b3aefe9-e962-4fdc-9ed5-9b5f952b9d02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920844853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3920844853
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.550531026
Short name T521
Test name
Test status
Simulation time 64394852 ps
CPU time 2.04 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:48:47 PM PST 24
Peak memory 218124 kb
Host smart-276820e3-440a-4537-b12e-87b21bae05ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550531026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.550531026
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.394851951
Short name T852
Test name
Test status
Simulation time 286755955 ps
CPU time 5.19 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:48:50 PM PST 24
Peak memory 213488 kb
Host smart-47631fc9-0dd0-4f1a-ac6a-5097dc1d4d99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394851951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
394851951
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3169850507
Short name T677
Test name
Test status
Simulation time 1940212798 ps
CPU time 72.9 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:49:58 PM PST 24
Peak memory 283816 kb
Host smart-b8c6bfa8-5215-4ccb-9c41-a0293e9237c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169850507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3169850507
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3930848554
Short name T338
Test name
Test status
Simulation time 3508497552 ps
CPU time 16.4 seconds
Started Jan 17 12:48:37 PM PST 24
Finished Jan 17 12:48:55 PM PST 24
Peak memory 251276 kb
Host smart-8aa4b975-781a-40e1-8549-1258b557b4e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930848554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3930848554
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1588191231
Short name T502
Test name
Test status
Simulation time 256938437 ps
CPU time 2.29 seconds
Started Jan 17 12:48:37 PM PST 24
Finished Jan 17 12:48:40 PM PST 24
Peak memory 218176 kb
Host smart-681ef89e-6e75-4c43-a38f-0b32d29fe547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588191231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1588191231
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1455879046
Short name T802
Test name
Test status
Simulation time 3498899903 ps
CPU time 18.1 seconds
Started Jan 17 12:48:39 PM PST 24
Finished Jan 17 12:48:59 PM PST 24
Peak memory 219296 kb
Host smart-75c58252-c5b6-4287-9b87-944431b8afc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455879046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1455879046
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3647959917
Short name T722
Test name
Test status
Simulation time 743530530 ps
CPU time 13.51 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:49:01 PM PST 24
Peak memory 218100 kb
Host smart-0e8bc625-e06d-417b-9d11-01926440febf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647959917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3647959917
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.729231106
Short name T884
Test name
Test status
Simulation time 1948594946 ps
CPU time 12.36 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:48:57 PM PST 24
Peak memory 218140 kb
Host smart-d71860c7-7b49-486c-8ba2-d296eb231207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729231106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.729231106
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3284101389
Short name T858
Test name
Test status
Simulation time 607066347 ps
CPU time 10.12 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:48:55 PM PST 24
Peak memory 218160 kb
Host smart-5a833a49-3595-42b2-97e7-f8ffcc42bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284101389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3284101389
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2804219387
Short name T89
Test name
Test status
Simulation time 218532642 ps
CPU time 6.43 seconds
Started Jan 17 12:48:39 PM PST 24
Finished Jan 17 12:48:48 PM PST 24
Peak memory 214572 kb
Host smart-44091398-8188-4d05-b74a-64221b31725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804219387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2804219387
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3787909802
Short name T546
Test name
Test status
Simulation time 537875960 ps
CPU time 29.51 seconds
Started Jan 17 12:48:36 PM PST 24
Finished Jan 17 12:49:06 PM PST 24
Peak memory 251184 kb
Host smart-f8fe65bc-6222-4ea9-a9c7-22caa7e45aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787909802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3787909802
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.252058139
Short name T570
Test name
Test status
Simulation time 332076427 ps
CPU time 6.72 seconds
Started Jan 17 12:48:36 PM PST 24
Finished Jan 17 12:48:44 PM PST 24
Peak memory 244100 kb
Host smart-baca8d1b-c074-4e0a-a271-d49344d296db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252058139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.252058139
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1556111115
Short name T715
Test name
Test status
Simulation time 2398794563 ps
CPU time 70.95 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:49:59 PM PST 24
Peak memory 226400 kb
Host smart-65186744-18e8-491a-a89f-a0723d6583a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556111115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1556111115
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.486515659
Short name T970
Test name
Test status
Simulation time 11024619 ps
CPU time 0.76 seconds
Started Jan 17 12:48:35 PM PST 24
Finished Jan 17 12:48:37 PM PST 24
Peak memory 208328 kb
Host smart-9aa672f6-d965-4e4d-bd11-05de9698ad00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486515659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.486515659
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1890566520
Short name T462
Test name
Test status
Simulation time 46832707 ps
CPU time 0.84 seconds
Started Jan 17 12:48:48 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 208212 kb
Host smart-032419e6-8614-4414-be39-5782320e3356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890566520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1890566520
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3879586352
Short name T669
Test name
Test status
Simulation time 1267815484 ps
CPU time 14.93 seconds
Started Jan 17 12:48:39 PM PST 24
Finished Jan 17 12:48:56 PM PST 24
Peak memory 218188 kb
Host smart-b50edac2-3829-413e-a0b2-212d257c6939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879586352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3879586352
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3402917503
Short name T654
Test name
Test status
Simulation time 991225396 ps
CPU time 5.27 seconds
Started Jan 17 12:48:46 PM PST 24
Finished Jan 17 12:48:53 PM PST 24
Peak memory 209620 kb
Host smart-dc9ce01b-d414-442c-9071-d17a4fe340d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402917503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.3402917503
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1368564489
Short name T593
Test name
Test status
Simulation time 6017237227 ps
CPU time 5.81 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:17 PM PST 24
Peak memory 218064 kb
Host smart-40917e55-894c-4896-9c44-cda087ce490e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368564489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1368564489
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3996286235
Short name T686
Test name
Test status
Simulation time 245129564 ps
CPU time 6.7 seconds
Started Jan 17 12:48:42 PM PST 24
Finished Jan 17 12:48:53 PM PST 24
Peak memory 213012 kb
Host smart-d4df4d99-b3f5-4587-8708-84d90d73cca9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996286235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3996286235
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1586501029
Short name T803
Test name
Test status
Simulation time 2894395943 ps
CPU time 57.81 seconds
Started Jan 17 12:48:46 PM PST 24
Finished Jan 17 12:49:46 PM PST 24
Peak memory 280760 kb
Host smart-dbbfc866-bed2-4e39-b1b7-098aefefe7a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586501029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1586501029
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2145690434
Short name T906
Test name
Test status
Simulation time 2231047504 ps
CPU time 12.29 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:49:00 PM PST 24
Peak memory 251156 kb
Host smart-3743bf0d-d308-4749-86e0-40e2bc28d944
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145690434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2145690434
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1946565138
Short name T679
Test name
Test status
Simulation time 130065887 ps
CPU time 1.99 seconds
Started Jan 17 12:48:37 PM PST 24
Finished Jan 17 12:48:40 PM PST 24
Peak memory 218096 kb
Host smart-583bb043-e320-424f-97fd-a2860a476d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946565138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1946565138
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1220259914
Short name T57
Test name
Test status
Simulation time 1055266530 ps
CPU time 13.29 seconds
Started Jan 17 12:48:43 PM PST 24
Finished Jan 17 12:49:00 PM PST 24
Peak memory 218208 kb
Host smart-bc9767ed-9984-437f-a8d8-38c32ab3b78f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220259914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1220259914
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2165157046
Short name T702
Test name
Test status
Simulation time 2320333562 ps
CPU time 12.01 seconds
Started Jan 17 12:48:47 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 218068 kb
Host smart-d7130bb4-1fad-4b6a-a316-3ae6c3405c9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165157046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2165157046
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.645257092
Short name T46
Test name
Test status
Simulation time 1139527953 ps
CPU time 9.96 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:48:55 PM PST 24
Peak memory 218064 kb
Host smart-a972ccbb-7acf-4b54-bd73-5dff33509151
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645257092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.645257092
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3376696515
Short name T878
Test name
Test status
Simulation time 894943122 ps
CPU time 8.54 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:48:53 PM PST 24
Peak memory 218208 kb
Host smart-3acce649-6acc-46bd-ae63-1bf90837b610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376696515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3376696515
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.620160606
Short name T576
Test name
Test status
Simulation time 166311300 ps
CPU time 1.99 seconds
Started Jan 17 12:48:47 PM PST 24
Finished Jan 17 12:49:10 PM PST 24
Peak memory 213824 kb
Host smart-25ff02ac-35c4-4807-b8d4-9a0fadc8c992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620160606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.620160606
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3379968099
Short name T456
Test name
Test status
Simulation time 513039110 ps
CPU time 26.83 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:49:15 PM PST 24
Peak memory 251232 kb
Host smart-907c6d0f-93ee-4146-bd74-9fe8c2f90a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379968099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3379968099
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.775000452
Short name T604
Test name
Test status
Simulation time 248301681 ps
CPU time 6.42 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:48:54 PM PST 24
Peak memory 250736 kb
Host smart-b0a83484-6f63-4ca5-bd2f-2148eed7d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775000452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.775000452
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3376353075
Short name T383
Test name
Test status
Simulation time 20398171367 ps
CPU time 703.68 seconds
Started Jan 17 12:48:43 PM PST 24
Finished Jan 17 01:00:31 PM PST 24
Peak memory 272884 kb
Host smart-c2686a9a-6ef3-4f52-9a5c-6b161123d070
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376353075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3376353075
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3963373586
Short name T64
Test name
Test status
Simulation time 32098255 ps
CPU time 0.89 seconds
Started Jan 17 12:48:42 PM PST 24
Finished Jan 17 12:48:47 PM PST 24
Peak memory 208080 kb
Host smart-15b275d6-f52c-47f3-b23d-acfd5a2e27cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963373586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3963373586
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.4237282283
Short name T758
Test name
Test status
Simulation time 20782469 ps
CPU time 1.18 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:48:49 PM PST 24
Peak memory 209644 kb
Host smart-988f54a3-b689-4c68-b5ac-98dab3004cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237282283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4237282283
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3040276757
Short name T945
Test name
Test status
Simulation time 344811221 ps
CPU time 11.09 seconds
Started Jan 17 12:48:48 PM PST 24
Finished Jan 17 12:49:21 PM PST 24
Peak memory 218212 kb
Host smart-9ae47c0c-e683-4fa7-819c-87eaa86ff8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040276757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3040276757
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1501364189
Short name T836
Test name
Test status
Simulation time 1052765570 ps
CPU time 6.78 seconds
Started Jan 17 12:48:50 PM PST 24
Finished Jan 17 12:49:17 PM PST 24
Peak memory 209656 kb
Host smart-a51841fe-d4d7-47fe-9a2f-1d6e66fb7dc0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501364189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.1501364189
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1762057
Short name T981
Test name
Test status
Simulation time 7133659127 ps
CPU time 26.31 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 218156 kb
Host smart-5bc9b56f-f20b-4fac-9fb6-6f11749a6f82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_erro
rs.1762057
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.628814685
Short name T15
Test name
Test status
Simulation time 407559678 ps
CPU time 6.36 seconds
Started Jan 17 12:48:43 PM PST 24
Finished Jan 17 12:48:53 PM PST 24
Peak memory 218120 kb
Host smart-26cecb0c-6cbe-4c46-a52f-e5b911dd79c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628814685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.628814685
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.287729234
Short name T724
Test name
Test status
Simulation time 250249668 ps
CPU time 3.21 seconds
Started Jan 17 12:48:41 PM PST 24
Finished Jan 17 12:48:48 PM PST 24
Peak memory 212968 kb
Host smart-b884f1dc-3a8b-43e0-85c8-ba67e42db321
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287729234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
287729234
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.737115824
Short name T765
Test name
Test status
Simulation time 23371897460 ps
CPU time 75.84 seconds
Started Jan 17 12:48:48 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 268152 kb
Host smart-cd650543-0dec-4acc-adec-0aee619fd2eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737115824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.737115824
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2597457813
Short name T685
Test name
Test status
Simulation time 544691005 ps
CPU time 9.31 seconds
Started Jan 17 12:48:50 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 222544 kb
Host smart-2ebcc07f-01b4-46a4-a97c-013914a07749
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597457813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2597457813
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1948752034
Short name T508
Test name
Test status
Simulation time 133872221 ps
CPU time 2.04 seconds
Started Jan 17 12:48:48 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 218176 kb
Host smart-8c0547b0-9ca1-4029-a506-5a6dca603bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948752034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1948752034
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3439250175
Short name T927
Test name
Test status
Simulation time 588234259 ps
CPU time 11.89 seconds
Started Jan 17 12:48:50 PM PST 24
Finished Jan 17 12:49:22 PM PST 24
Peak memory 218028 kb
Host smart-eeccf0e3-c9a5-40ee-b5c1-4ee3ba9a488f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439250175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3439250175
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1289780814
Short name T489
Test name
Test status
Simulation time 943006290 ps
CPU time 13.76 seconds
Started Jan 17 12:48:50 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 217884 kb
Host smart-94eb4d44-11a3-4c9d-995a-8e7b1522d9d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289780814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1289780814
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2977775027
Short name T668
Test name
Test status
Simulation time 2331806428 ps
CPU time 12.85 seconds
Started Jan 17 12:48:47 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 218184 kb
Host smart-ff38f01e-cac3-49e3-a308-c1d861ea3c59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977775027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2977775027
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1160958867
Short name T956
Test name
Test status
Simulation time 1668590172 ps
CPU time 8.86 seconds
Started Jan 17 12:48:43 PM PST 24
Finished Jan 17 12:48:55 PM PST 24
Peak memory 218232 kb
Host smart-3a2b3de2-5731-4134-93a8-a0ba8e37d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160958867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1160958867
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2651725565
Short name T713
Test name
Test status
Simulation time 68649226 ps
CPU time 2.83 seconds
Started Jan 17 12:48:43 PM PST 24
Finished Jan 17 12:48:49 PM PST 24
Peak memory 213844 kb
Host smart-753bf3f2-b183-48f8-a04e-fe93e2d6c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651725565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2651725565
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2448213186
Short name T312
Test name
Test status
Simulation time 826633855 ps
CPU time 25.18 seconds
Started Jan 17 12:48:46 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 246268 kb
Host smart-657580b8-a91d-4597-9724-37dab6e0c456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448213186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2448213186
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2792773904
Short name T973
Test name
Test status
Simulation time 190898021 ps
CPU time 9.12 seconds
Started Jan 17 12:48:48 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 251176 kb
Host smart-3ea2f25c-34ea-4813-9475-780d2d674b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792773904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2792773904
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1322408374
Short name T121
Test name
Test status
Simulation time 4193011778 ps
CPU time 151.43 seconds
Started Jan 17 12:48:37 PM PST 24
Finished Jan 17 12:51:09 PM PST 24
Peak memory 270756 kb
Host smart-57a40cb6-ccfc-4f5b-83a8-053fa72bb0fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322408374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1322408374
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2817091247
Short name T737
Test name
Test status
Simulation time 155725910079 ps
CPU time 904.43 seconds
Started Jan 17 12:48:48 PM PST 24
Finished Jan 17 01:04:12 PM PST 24
Peak memory 283900 kb
Host smart-81ebc8d8-d3f5-40a6-bcee-0810d2c63f07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2817091247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2817091247
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1741604752
Short name T952
Test name
Test status
Simulation time 51124700 ps
CPU time 0.8 seconds
Started Jan 17 12:48:39 PM PST 24
Finished Jan 17 12:48:42 PM PST 24
Peak memory 208416 kb
Host smart-a96a2208-b5dc-48e2-85e1-b471509b5851
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741604752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1741604752
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2067574914
Short name T528
Test name
Test status
Simulation time 61068026 ps
CPU time 1.32 seconds
Started Jan 17 12:48:46 PM PST 24
Finished Jan 17 12:48:49 PM PST 24
Peak memory 208480 kb
Host smart-7fbe3d01-9231-468f-b260-e7de59c8102e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067574914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2067574914
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2630200161
Short name T751
Test name
Test status
Simulation time 810730618 ps
CPU time 17.42 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:28 PM PST 24
Peak memory 218172 kb
Host smart-14974007-eda5-48ed-af36-fa1a10b0355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630200161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2630200161
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2341853625
Short name T28
Test name
Test status
Simulation time 246510310 ps
CPU time 2.27 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 209440 kb
Host smart-0240181b-292f-4c9d-8f40-9339a7d1c7d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341853625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.2341853625
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1392109741
Short name T585
Test name
Test status
Simulation time 5359103234 ps
CPU time 34.07 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:44 PM PST 24
Peak memory 218516 kb
Host smart-af1cc52a-81aa-4c06-8855-9f3062291ee6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392109741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1392109741
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.895735166
Short name T328
Test name
Test status
Simulation time 258225531 ps
CPU time 4.15 seconds
Started Jan 17 12:48:44 PM PST 24
Finished Jan 17 12:48:51 PM PST 24
Peak memory 218104 kb
Host smart-33212b15-7a5c-40bb-839a-00b0a4b5406d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895735166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.895735166
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.788286280
Short name T656
Test name
Test status
Simulation time 644137890 ps
CPU time 3.63 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:14 PM PST 24
Peak memory 212772 kb
Host smart-77186122-e4bb-4b5c-bcbb-b2563ba00c27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788286280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
788286280
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.639863652
Short name T363
Test name
Test status
Simulation time 1044966125 ps
CPU time 49.63 seconds
Started Jan 17 12:48:43 PM PST 24
Finished Jan 17 12:49:37 PM PST 24
Peak memory 267408 kb
Host smart-ec9604b0-be53-47e5-978d-0e0c0ed28c8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639863652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.639863652
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3963378308
Short name T818
Test name
Test status
Simulation time 2422060693 ps
CPU time 20.04 seconds
Started Jan 17 12:48:44 PM PST 24
Finished Jan 17 12:49:07 PM PST 24
Peak memory 251132 kb
Host smart-56e5b45e-36fe-43b3-8d46-317fe6293855
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963378308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3963378308
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4058606506
Short name T319
Test name
Test status
Simulation time 18662872 ps
CPU time 1.45 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:48:49 PM PST 24
Peak memory 218236 kb
Host smart-03221a08-08dd-45d7-aab8-3b45794b3d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058606506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4058606506
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1052402380
Short name T420
Test name
Test status
Simulation time 501892352 ps
CPU time 9.44 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 219188 kb
Host smart-c13b98db-3d6b-4dc6-b7e0-8e850fb9bad7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052402380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1052402380
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1253531255
Short name T473
Test name
Test status
Simulation time 523021571 ps
CPU time 18.57 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:49:07 PM PST 24
Peak memory 217052 kb
Host smart-6430f3ac-e486-4098-86b8-bdb29b8a5267
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253531255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1253531255
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.175918543
Short name T510
Test name
Test status
Simulation time 276016148 ps
CPU time 9.95 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:21 PM PST 24
Peak memory 217980 kb
Host smart-aaf8bde2-79ed-4019-ad46-5b743425642e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175918543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.175918543
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3870530215
Short name T34
Test name
Test status
Simulation time 3197752055 ps
CPU time 13.24 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 218228 kb
Host smart-74d20a48-2ce1-4260-9784-dc8e2bb7dc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870530215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3870530215
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2550876332
Short name T712
Test name
Test status
Simulation time 95797942 ps
CPU time 1.89 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 213420 kb
Host smart-0e954288-8abf-4dcf-a088-43b7ce10e14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550876332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2550876332
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3217337636
Short name T924
Test name
Test status
Simulation time 4259011622 ps
CPU time 29.91 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 250988 kb
Host smart-0fe21400-8b88-4300-98d9-8f393b144f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217337636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3217337636
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3952386110
Short name T812
Test name
Test status
Simulation time 311095945 ps
CPU time 6.92 seconds
Started Jan 17 12:48:50 PM PST 24
Finished Jan 17 12:49:17 PM PST 24
Peak memory 250180 kb
Host smart-7d93f211-cf85-4181-8e79-72d5fe1da6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952386110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3952386110
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2148898277
Short name T433
Test name
Test status
Simulation time 4235903972 ps
CPU time 95.19 seconds
Started Jan 17 12:48:54 PM PST 24
Finished Jan 17 12:50:46 PM PST 24
Peak memory 268436 kb
Host smart-7ab7f93c-c8b3-4997-9595-e4312d86f80e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148898277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2148898277
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3979475036
Short name T863
Test name
Test status
Simulation time 27531174 ps
CPU time 0.74 seconds
Started Jan 17 12:48:38 PM PST 24
Finished Jan 17 12:48:40 PM PST 24
Peak memory 208184 kb
Host smart-1e5697d5-b720-4b76-b264-65a73c846630
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979475036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3979475036
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.997547578
Short name T408
Test name
Test status
Simulation time 22868026 ps
CPU time 1.04 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:02 PM PST 24
Peak memory 209660 kb
Host smart-fa16ecef-99cd-4d12-b406-f71da4b15547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997547578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.997547578
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.4176843503
Short name T373
Test name
Test status
Simulation time 16258410 ps
CPU time 0.81 seconds
Started Jan 17 12:47:56 PM PST 24
Finished Jan 17 12:47:58 PM PST 24
Peak memory 209352 kb
Host smart-28be7d46-f074-47af-a222-f804a5060107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176843503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4176843503
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1073198719
Short name T48
Test name
Test status
Simulation time 2035546022 ps
CPU time 15.61 seconds
Started Jan 17 12:47:52 PM PST 24
Finished Jan 17 12:48:10 PM PST 24
Peak memory 218152 kb
Host smart-9c85c3d4-ce0e-4dd2-80b6-d4213ca5dde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073198719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1073198719
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2402746968
Short name T814
Test name
Test status
Simulation time 531448129 ps
CPU time 13.68 seconds
Started Jan 17 12:47:57 PM PST 24
Finished Jan 17 12:48:11 PM PST 24
Peak memory 209624 kb
Host smart-b08d6509-ff74-43e7-8401-bf24894d8309
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402746968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ac
cess.2402746968
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.4146629534
Short name T940
Test name
Test status
Simulation time 1583623733 ps
CPU time 40.3 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:52 PM PST 24
Peak memory 218092 kb
Host smart-086426ab-5431-4fe5-ac01-1e174358e92b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146629534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.4146629534
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3454285992
Short name T727
Test name
Test status
Simulation time 394751888 ps
CPU time 5.73 seconds
Started Jan 17 12:47:46 PM PST 24
Finished Jan 17 12:47:55 PM PST 24
Peak memory 217904 kb
Host smart-53cdf60f-7a67-46f2-beee-9f07228ef494
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454285992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.3454285992
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.927659145
Short name T844
Test name
Test status
Simulation time 464144671 ps
CPU time 13.46 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:15 PM PST 24
Peak memory 218068 kb
Host smart-e881cc61-72d3-42f3-8369-01fde6f37182
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927659145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.927659145
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2118221886
Short name T78
Test name
Test status
Simulation time 1147828773 ps
CPU time 16.69 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:48:09 PM PST 24
Peak memory 213116 kb
Host smart-aee645a8-f6d7-41a8-9fb3-b8559558e7d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118221886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2118221886
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1549952992
Short name T591
Test name
Test status
Simulation time 1635692965 ps
CPU time 5.99 seconds
Started Jan 17 12:47:57 PM PST 24
Finished Jan 17 12:48:04 PM PST 24
Peak memory 213448 kb
Host smart-474887b3-6a36-430f-ad6a-64f66325056e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549952992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1549952992
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3451090117
Short name T388
Test name
Test status
Simulation time 1120467843 ps
CPU time 54.56 seconds
Started Jan 17 12:47:51 PM PST 24
Finished Jan 17 12:48:48 PM PST 24
Peak memory 267440 kb
Host smart-80b896e9-be8f-42e8-9df9-16525c6d0d3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451090117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3451090117
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3807999385
Short name T772
Test name
Test status
Simulation time 1819086059 ps
CPU time 17.23 seconds
Started Jan 17 12:47:54 PM PST 24
Finished Jan 17 12:48:13 PM PST 24
Peak memory 247336 kb
Host smart-4c6e1046-b08b-4bad-bbc6-95d497552c17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807999385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3807999385
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3766321576
Short name T387
Test name
Test status
Simulation time 70205567 ps
CPU time 1.41 seconds
Started Jan 17 12:47:47 PM PST 24
Finished Jan 17 12:47:51 PM PST 24
Peak memory 218160 kb
Host smart-8e649b1e-157c-47a7-bd2b-44b2e6a44fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766321576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3766321576
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1840144126
Short name T384
Test name
Test status
Simulation time 1041086705 ps
CPU time 18.96 seconds
Started Jan 17 12:47:44 PM PST 24
Finished Jan 17 12:48:08 PM PST 24
Peak memory 213972 kb
Host smart-f24ebd2d-0f3f-4990-9106-1f40ff466a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840144126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1840144126
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1019705188
Short name T117
Test name
Test status
Simulation time 2122737416 ps
CPU time 36.01 seconds
Started Jan 17 12:47:59 PM PST 24
Finished Jan 17 12:48:36 PM PST 24
Peak memory 269248 kb
Host smart-5df504fa-6dae-477b-a170-634618c58f20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019705188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1019705188
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.4110993905
Short name T491
Test name
Test status
Simulation time 755666114 ps
CPU time 14.94 seconds
Started Jan 17 12:47:51 PM PST 24
Finished Jan 17 12:48:09 PM PST 24
Peak memory 219228 kb
Host smart-383531c1-0e3b-4aa9-aa32-7482685dd15e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110993905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.4110993905
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.986679335
Short name T719
Test name
Test status
Simulation time 514917601 ps
CPU time 8.36 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 218040 kb
Host smart-93585cd3-30dd-4bc8-b373-eb596e01d877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986679335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.986679335
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2360664412
Short name T847
Test name
Test status
Simulation time 357152434 ps
CPU time 8.55 seconds
Started Jan 17 12:47:47 PM PST 24
Finished Jan 17 12:47:58 PM PST 24
Peak memory 218088 kb
Host smart-b060d84f-6fc0-42da-807b-01ef40e851d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360664412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
360664412
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2425444347
Short name T859
Test name
Test status
Simulation time 331197021 ps
CPU time 10.98 seconds
Started Jan 17 12:47:40 PM PST 24
Finished Jan 17 12:48:00 PM PST 24
Peak memory 218056 kb
Host smart-18ea554c-265f-4731-9e0c-4498410874c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425444347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2425444347
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1767179855
Short name T331
Test name
Test status
Simulation time 279545514 ps
CPU time 2.21 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:04 PM PST 24
Peak memory 213964 kb
Host smart-174f2665-c212-449e-97a6-1d5be1856aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767179855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1767179855
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1522696973
Short name T694
Test name
Test status
Simulation time 982049365 ps
CPU time 30.84 seconds
Started Jan 17 12:47:56 PM PST 24
Finished Jan 17 12:48:27 PM PST 24
Peak memory 251056 kb
Host smart-e065ea5b-c8fa-457a-af75-0aba85ef3fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522696973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1522696973
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.4124491054
Short name T523
Test name
Test status
Simulation time 148680814 ps
CPU time 6.35 seconds
Started Jan 17 12:47:49 PM PST 24
Finished Jan 17 12:47:59 PM PST 24
Peak memory 246316 kb
Host smart-b96b38b6-db84-48ca-ab35-58e3fb3d4815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124491054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.4124491054
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.750927729
Short name T731
Test name
Test status
Simulation time 29336857849 ps
CPU time 264.33 seconds
Started Jan 17 12:47:58 PM PST 24
Finished Jan 17 12:52:23 PM PST 24
Peak memory 248248 kb
Host smart-802bec23-68ec-4c51-8d2d-1346cdd2ad7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750927729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.750927729
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.298007514
Short name T648
Test name
Test status
Simulation time 44243002 ps
CPU time 0.91 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:47:53 PM PST 24
Peak memory 208160 kb
Host smart-bf7dc6e5-854b-42cd-9fbf-e733dd7d6fdd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298007514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.298007514
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.4001426770
Short name T741
Test name
Test status
Simulation time 76921797 ps
CPU time 1.21 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 208672 kb
Host smart-5917c5d1-6aa1-45e6-989d-c4ad42919ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001426770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4001426770
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3533047132
Short name T830
Test name
Test status
Simulation time 382508120 ps
CPU time 11.62 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:22 PM PST 24
Peak memory 218164 kb
Host smart-f7daf1f8-3744-4042-9a94-d58adef86f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533047132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3533047132
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2868575914
Short name T532
Test name
Test status
Simulation time 524320954 ps
CPU time 3.99 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:14 PM PST 24
Peak memory 218184 kb
Host smart-9e03167b-3924-491a-bbb0-d9688615fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868575914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2868575914
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.238349486
Short name T614
Test name
Test status
Simulation time 469303447 ps
CPU time 10.41 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:21 PM PST 24
Peak memory 217964 kb
Host smart-2bb45db0-b4d2-4ca2-9ee1-0511eadd7063
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238349486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.238349486
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.240648825
Short name T50
Test name
Test status
Simulation time 1138677314 ps
CPU time 11.19 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:22 PM PST 24
Peak memory 218188 kb
Host smart-f2082f01-e7e2-4da7-a542-330a94189693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240648825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.240648825
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3413740787
Short name T610
Test name
Test status
Simulation time 176003474 ps
CPU time 7.41 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 218076 kb
Host smart-b93c419b-dd88-4255-b043-402397f7a71a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413740787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3413740787
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.920836633
Short name T93
Test name
Test status
Simulation time 386292579 ps
CPU time 9.11 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 218168 kb
Host smart-47ef297b-c282-497b-9bd2-ff14152cd17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920836633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.920836633
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3759501211
Short name T628
Test name
Test status
Simulation time 44414870 ps
CPU time 1.76 seconds
Started Jan 17 12:48:40 PM PST 24
Finished Jan 17 12:48:46 PM PST 24
Peak memory 213368 kb
Host smart-512cd3f7-b1e3-42dc-95f3-70ef616422b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759501211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3759501211
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3385017158
Short name T747
Test name
Test status
Simulation time 698137207 ps
CPU time 28.55 seconds
Started Jan 17 12:48:44 PM PST 24
Finished Jan 17 12:49:16 PM PST 24
Peak memory 250980 kb
Host smart-629eb02a-1083-4a75-a8e6-d47abbb056e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385017158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3385017158
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.604780323
Short name T597
Test name
Test status
Simulation time 198802802 ps
CPU time 2.81 seconds
Started Jan 17 12:48:43 PM PST 24
Finished Jan 17 12:48:49 PM PST 24
Peak memory 222176 kb
Host smart-88923f40-f60a-43fa-ae73-aec7f5e8fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604780323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.604780323
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2301678481
Short name T931
Test name
Test status
Simulation time 932354667 ps
CPU time 24.35 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:35 PM PST 24
Peak memory 218316 kb
Host smart-20a33d1b-6b39-45db-8402-3e6268f1b3b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301678481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2301678481
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1225571296
Short name T637
Test name
Test status
Simulation time 10864585 ps
CPU time 0.88 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 208008 kb
Host smart-f996e83c-e05a-4df7-a10f-ee14efe9195d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225571296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1225571296
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1535071392
Short name T538
Test name
Test status
Simulation time 62770886 ps
CPU time 0.99 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 209616 kb
Host smart-64d33b7c-a2bf-41f6-be42-a526e88cdd34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535071392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1535071392
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4126170030
Short name T377
Test name
Test status
Simulation time 423217855 ps
CPU time 13.08 seconds
Started Jan 17 12:48:46 PM PST 24
Finished Jan 17 12:49:01 PM PST 24
Peak memory 218168 kb
Host smart-1878e33b-ef75-4a2e-9a93-e8e4d1fd15e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126170030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4126170030
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3527808649
Short name T27
Test name
Test status
Simulation time 558484188 ps
CPU time 5.84 seconds
Started Jan 17 12:48:45 PM PST 24
Finished Jan 17 12:48:53 PM PST 24
Peak memory 209624 kb
Host smart-b0913f0e-0f3c-431b-86da-94aa077494eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527808649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.3527808649
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.95148871
Short name T395
Test name
Test status
Simulation time 91655874 ps
CPU time 3.96 seconds
Started Jan 17 12:50:34 PM PST 24
Finished Jan 17 12:50:39 PM PST 24
Peak memory 218036 kb
Host smart-b9c80a4b-b5c9-42d1-972f-758c2ccdd4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95148871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.95148871
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3932444748
Short name T684
Test name
Test status
Simulation time 392955876 ps
CPU time 17.47 seconds
Started Jan 17 12:48:42 PM PST 24
Finished Jan 17 12:49:04 PM PST 24
Peak memory 218228 kb
Host smart-14f6ff50-b725-4f04-9902-6fe88b4dc92a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932444748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3932444748
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3345636973
Short name T621
Test name
Test status
Simulation time 1265977077 ps
CPU time 12.11 seconds
Started Jan 17 12:48:54 PM PST 24
Finished Jan 17 12:49:23 PM PST 24
Peak memory 218112 kb
Host smart-682a38d0-e86c-4d25-a691-815e26e8aa68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345636973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3345636973
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4176984159
Short name T581
Test name
Test status
Simulation time 1957731660 ps
CPU time 12.52 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:23 PM PST 24
Peak memory 218092 kb
Host smart-82621845-7965-4180-809a-4a22b4da3d12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176984159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4176984159
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2638192149
Short name T918
Test name
Test status
Simulation time 1092770506 ps
CPU time 9.37 seconds
Started Jan 17 12:48:47 PM PST 24
Finished Jan 17 12:49:15 PM PST 24
Peak memory 218156 kb
Host smart-9868007a-8964-40b3-a034-a215b5ecd810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638192149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2638192149
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1528067665
Short name T451
Test name
Test status
Simulation time 101972115 ps
CPU time 2.85 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 214200 kb
Host smart-f2ccaf73-976c-4bbf-bbaf-10ea46ba9676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528067665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1528067665
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2732925263
Short name T51
Test name
Test status
Simulation time 70487997 ps
CPU time 3.39 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:14 PM PST 24
Peak memory 218216 kb
Host smart-08c606ea-afda-49aa-a39b-e7e750274712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732925263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2732925263
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4167803800
Short name T693
Test name
Test status
Simulation time 2082214600 ps
CPU time 67.64 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:50:18 PM PST 24
Peak memory 269788 kb
Host smart-b7843c6f-8beb-422f-b898-a6d4befd3ddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167803800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4167803800
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.726257374
Short name T314
Test name
Test status
Simulation time 43860893 ps
CPU time 0.73 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 207140 kb
Host smart-17766862-961b-4cc1-995f-493944ea87c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726257374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.726257374
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2908959961
Short name T499
Test name
Test status
Simulation time 15290061 ps
CPU time 0.95 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 209588 kb
Host smart-a114065c-2d03-4da4-bc77-31f6b8ee0b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908959961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2908959961
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1137867638
Short name T659
Test name
Test status
Simulation time 368458171 ps
CPU time 17.17 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:28 PM PST 24
Peak memory 218104 kb
Host smart-49804419-3767-4b4d-8ad6-2dc58e3ec60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137867638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1137867638
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.975153744
Short name T8
Test name
Test status
Simulation time 1173348147 ps
CPU time 7.56 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 209648 kb
Host smart-47f78acd-42a5-4707-88d2-4301ec6c88eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975153744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_ac
cess.975153744
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1285180579
Short name T587
Test name
Test status
Simulation time 105065499 ps
CPU time 2.17 seconds
Started Jan 17 12:48:48 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 218188 kb
Host smart-737c73e5-d3e6-4a6b-86e5-51970d061981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285180579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1285180579
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2332395565
Short name T569
Test name
Test status
Simulation time 1450474310 ps
CPU time 14.61 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:25 PM PST 24
Peak memory 218492 kb
Host smart-5effbf9c-2945-4af6-b28c-a2a94bc2f14d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332395565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2332395565
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2842710426
Short name T944
Test name
Test status
Simulation time 895963415 ps
CPU time 13.33 seconds
Started Jan 17 12:48:52 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 218120 kb
Host smart-6c267fbc-3241-449f-9db7-f59c6a566207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842710426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2842710426
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4168601068
Short name T371
Test name
Test status
Simulation time 243772227 ps
CPU time 7.15 seconds
Started Jan 17 12:48:52 PM PST 24
Finished Jan 17 12:49:17 PM PST 24
Peak memory 218108 kb
Host smart-fe7ceb07-04dc-4f99-be06-c2a64be61b21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168601068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4168601068
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.582388077
Short name T829
Test name
Test status
Simulation time 790855144 ps
CPU time 14.47 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:25 PM PST 24
Peak memory 218120 kb
Host smart-84c243f6-3313-4925-9890-d4207e5823ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582388077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.582388077
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4131709238
Short name T374
Test name
Test status
Simulation time 23217320 ps
CPU time 1.54 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 213544 kb
Host smart-6acba1e9-27c9-46ab-8774-5860421d1337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131709238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4131709238
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2096217748
Short name T647
Test name
Test status
Simulation time 262882400 ps
CPU time 24.12 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 251120 kb
Host smart-17a6e2ec-786e-4d2a-b8bd-ea39aaeee41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096217748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2096217748
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2305345267
Short name T631
Test name
Test status
Simulation time 438082367 ps
CPU time 3.62 seconds
Started Jan 17 12:48:49 PM PST 24
Finished Jan 17 12:49:14 PM PST 24
Peak memory 218188 kb
Host smart-a1c70573-3f1e-4f8d-ba11-e884b90cd43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305345267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2305345267
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1177603970
Short name T366
Test name
Test status
Simulation time 9125631485 ps
CPU time 283.86 seconds
Started Jan 17 12:48:53 PM PST 24
Finished Jan 17 12:53:54 PM PST 24
Peak memory 220816 kb
Host smart-0a75b7bf-d2a9-4390-be2b-d17078e3c64b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177603970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1177603970
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.534040966
Short name T454
Test name
Test status
Simulation time 37020648 ps
CPU time 1.23 seconds
Started Jan 17 12:48:46 PM PST 24
Finished Jan 17 12:49:07 PM PST 24
Peak memory 211428 kb
Host smart-c9a095e9-0647-4407-81d4-40d4465fc9f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534040966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.534040966
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.4278832256
Short name T828
Test name
Test status
Simulation time 15365880 ps
CPU time 1.05 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 208428 kb
Host smart-60bb53eb-f7b4-4382-93b6-d9c34eb801a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278832256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4278832256
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2086781585
Short name T874
Test name
Test status
Simulation time 348546829 ps
CPU time 16.36 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:27 PM PST 24
Peak memory 218108 kb
Host smart-8627efce-be93-4827-9679-7904c8dbebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086781585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2086781585
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.995031199
Short name T488
Test name
Test status
Simulation time 603608319 ps
CPU time 2.21 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 209568 kb
Host smart-fc1c1088-3cff-4514-8581-9298bc9c4a16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995031199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_ac
cess.995031199
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2713375226
Short name T465
Test name
Test status
Simulation time 139433431 ps
CPU time 2.31 seconds
Started Jan 17 12:48:44 PM PST 24
Finished Jan 17 12:48:50 PM PST 24
Peak memory 218204 kb
Host smart-a39dc95b-44f5-46cc-93e3-5d3fb38a1433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713375226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2713375226
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2806648640
Short name T816
Test name
Test status
Simulation time 1246069461 ps
CPU time 13.07 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 219120 kb
Host smart-68dd97a5-e028-49e3-8f2e-9af6512ff302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806648640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2806648640
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1585582891
Short name T12
Test name
Test status
Simulation time 2152106277 ps
CPU time 12.9 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:23 PM PST 24
Peak memory 218076 kb
Host smart-aab4edb1-4b96-470b-9693-dfeb0c03b49d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585582891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1585582891
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3411394509
Short name T735
Test name
Test status
Simulation time 651539621 ps
CPU time 15.55 seconds
Started Jan 17 12:48:51 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 218076 kb
Host smart-0dae7c2c-3394-451b-9783-63a68edf4d22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411394509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3411394509
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.715279619
Short name T640
Test name
Test status
Simulation time 240649467 ps
CPU time 9.38 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 218096 kb
Host smart-9a7993b3-87b4-4d74-b374-ff612b45c4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715279619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.715279619
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.4201733136
Short name T52
Test name
Test status
Simulation time 44941651 ps
CPU time 2.41 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 214128 kb
Host smart-6cca5e9e-40ce-4a4e-bcb5-fbe3b1409051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201733136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.4201733136
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4159107885
Short name T964
Test name
Test status
Simulation time 287855407 ps
CPU time 25.13 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:35 PM PST 24
Peak memory 251068 kb
Host smart-f7c9e706-4fa5-49bf-83b7-a63ded6fe859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159107885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4159107885
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2501343792
Short name T399
Test name
Test status
Simulation time 103867355 ps
CPU time 7.02 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:17 PM PST 24
Peak memory 246936 kb
Host smart-5024fb49-d4d3-429f-83b3-9a69622b8eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501343792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2501343792
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3678754867
Short name T967
Test name
Test status
Simulation time 37963047384 ps
CPU time 200.08 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:52:31 PM PST 24
Peak memory 284000 kb
Host smart-59bf38d5-4c91-42cb-b0ed-a53f747f3a8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678754867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3678754867
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3509096545
Short name T38
Test name
Test status
Simulation time 13705534 ps
CPU time 0.89 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 208256 kb
Host smart-1424a230-4e00-4883-94f5-d93ceec62c7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509096545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3509096545
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.237416360
Short name T519
Test name
Test status
Simulation time 115208044 ps
CPU time 1.12 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 207916 kb
Host smart-9109c01e-e4a0-4830-a825-83676f400592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237416360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.237416360
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2533203730
Short name T403
Test name
Test status
Simulation time 630440752 ps
CPU time 11.4 seconds
Started Jan 17 12:48:59 PM PST 24
Finished Jan 17 12:49:22 PM PST 24
Peak memory 217916 kb
Host smart-3e8f964e-8692-45c2-8740-f3f3f5f741fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533203730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2533203730
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1107751515
Short name T560
Test name
Test status
Simulation time 121801060 ps
CPU time 3.47 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:14 PM PST 24
Peak memory 209692 kb
Host smart-d27d9dd4-ee41-434d-aa8d-f33de8f95681
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107751515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_a
ccess.1107751515
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.436742881
Short name T919
Test name
Test status
Simulation time 104290367 ps
CPU time 2.49 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 218184 kb
Host smart-d5de4b5d-6d7a-4123-8f2e-2659de0f51a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436742881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.436742881
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1337040814
Short name T925
Test name
Test status
Simulation time 363944473 ps
CPU time 13.29 seconds
Started Jan 17 12:50:34 PM PST 24
Finished Jan 17 12:50:48 PM PST 24
Peak memory 218040 kb
Host smart-fa7cd48f-0dd5-46e3-866c-75da318bdc67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337040814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1337040814
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2111016256
Short name T625
Test name
Test status
Simulation time 1078907824 ps
CPU time 8.1 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:50:34 PM PST 24
Peak memory 217208 kb
Host smart-0395885a-b7ad-40bc-82f3-5338538fec6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111016256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2111016256
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2221373568
Short name T311
Test name
Test status
Simulation time 659827344 ps
CPU time 7.14 seconds
Started Jan 17 12:50:34 PM PST 24
Finished Jan 17 12:50:42 PM PST 24
Peak memory 217956 kb
Host smart-bfc990ca-cc92-43ff-90e4-371a3a4b3602
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221373568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2221373568
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3365899824
Short name T180
Test name
Test status
Simulation time 276346094 ps
CPU time 7.96 seconds
Started Jan 17 12:50:34 PM PST 24
Finished Jan 17 12:50:43 PM PST 24
Peak memory 218036 kb
Host smart-472e5b21-88bc-4ae9-89d5-4f73720d2f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365899824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3365899824
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3051598717
Short name T527
Test name
Test status
Simulation time 33336301 ps
CPU time 1.91 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 213696 kb
Host smart-4989c70d-dae9-4ee0-95c5-540c45a30258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051598717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3051598717
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3541378994
Short name T653
Test name
Test status
Simulation time 241173710 ps
CPU time 30.39 seconds
Started Jan 17 12:48:59 PM PST 24
Finished Jan 17 12:49:41 PM PST 24
Peak memory 250808 kb
Host smart-0c3a7f28-058a-4442-b579-4b002546079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541378994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3541378994
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.877621899
Short name T877
Test name
Test status
Simulation time 136146584 ps
CPU time 8.1 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 250988 kb
Host smart-99e5a622-7b89-4818-9946-aab6383e2be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877621899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.877621899
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1441024458
Short name T840
Test name
Test status
Simulation time 5911204689 ps
CPU time 81.34 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:50:32 PM PST 24
Peak memory 250780 kb
Host smart-ace5b19d-838f-4e57-b1b1-a0070a049ee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441024458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1441024458
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3999231904
Short name T757
Test name
Test status
Simulation time 13856611 ps
CPU time 0.77 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 208508 kb
Host smart-dc14136e-cc23-4570-b73d-63629e51d207
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999231904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3999231904
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.862470793
Short name T324
Test name
Test status
Simulation time 13152884 ps
CPU time 1.04 seconds
Started Jan 17 12:49:00 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 209688 kb
Host smart-54117371-f877-4572-9ebe-1d6f8d3ef23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862470793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.862470793
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2865631592
Short name T535
Test name
Test status
Simulation time 546909475 ps
CPU time 9.11 seconds
Started Jan 17 12:49:00 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 218176 kb
Host smart-db65874c-27da-4eed-843d-ce5461868278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865631592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2865631592
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2956038615
Short name T658
Test name
Test status
Simulation time 2964712357 ps
CPU time 9.43 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 209724 kb
Host smart-24e0aaab-2f6f-44cd-acc7-52adb957a6be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956038615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_a
ccess.2956038615
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.237501523
Short name T776
Test name
Test status
Simulation time 440441293 ps
CPU time 2.36 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 218136 kb
Host smart-72d24f25-cad9-47c9-8fcd-cf7e52a47c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237501523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.237501523
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2690369424
Short name T780
Test name
Test status
Simulation time 1704849945 ps
CPU time 17.01 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:27 PM PST 24
Peak memory 218912 kb
Host smart-a88cce25-d296-435c-a678-8bf62726927f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690369424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2690369424
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2861190479
Short name T649
Test name
Test status
Simulation time 1379199050 ps
CPU time 20.25 seconds
Started Jan 17 12:48:59 PM PST 24
Finished Jan 17 12:49:31 PM PST 24
Peak memory 218100 kb
Host smart-3f31c7d7-83cc-4d4d-9395-390f13ff4fb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861190479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2861190479
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1182866644
Short name T439
Test name
Test status
Simulation time 1510091820 ps
CPU time 12.78 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:23 PM PST 24
Peak memory 218228 kb
Host smart-d553826a-3fc7-496b-8c0d-851d16297dd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182866644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1182866644
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1247472590
Short name T562
Test name
Test status
Simulation time 2462883025 ps
CPU time 13.14 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 218372 kb
Host smart-fca3e343-af1c-42a4-a3c6-34fc0b4942e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247472590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1247472590
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2284568564
Short name T775
Test name
Test status
Simulation time 28541248 ps
CPU time 2.08 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 213892 kb
Host smart-99ba99e7-12a0-4287-bb58-ef8c8ef6646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284568564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2284568564
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2175322157
Short name T11
Test name
Test status
Simulation time 328746145 ps
CPU time 27.23 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:37 PM PST 24
Peak memory 251156 kb
Host smart-c97a2399-4b8a-4624-b148-df54bfa8ecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175322157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2175322157
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3890676287
Short name T437
Test name
Test status
Simulation time 544729207 ps
CPU time 8.11 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 251148 kb
Host smart-523de01a-eae5-4184-9c96-3ed941ccf9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890676287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3890676287
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2863124957
Short name T577
Test name
Test status
Simulation time 19519435614 ps
CPU time 213.64 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:52:44 PM PST 24
Peak memory 278276 kb
Host smart-3ea59642-f0ef-4cb8-a6e9-d4e0834aa56a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863124957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2863124957
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2610476915
Short name T711
Test name
Test status
Simulation time 33799478 ps
CPU time 0.74 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 206952 kb
Host smart-db7bcec9-0603-4363-a0c4-9aa111195891
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610476915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2610476915
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1352585935
Short name T736
Test name
Test status
Simulation time 106405188 ps
CPU time 0.89 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 208440 kb
Host smart-fb81751b-a91a-48fd-bfa4-cc39b6f8b4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352585935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1352585935
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.362048465
Short name T620
Test name
Test status
Simulation time 2340689133 ps
CPU time 15.21 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 218192 kb
Host smart-e1fb224f-e56b-4143-bc2a-8d8bd0f067c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362048465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.362048465
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2295671502
Short name T7
Test name
Test status
Simulation time 82836383 ps
CPU time 1.61 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 209584 kb
Host smart-edcdc99e-7aad-45c8-bfba-f76515092686
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295671502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.2295671502
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3767459841
Short name T379
Test name
Test status
Simulation time 34613448 ps
CPU time 1.72 seconds
Started Jan 17 12:48:59 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 218176 kb
Host smart-17a01c74-cf61-47d9-a451-02c4ed685b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767459841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3767459841
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3167464262
Short name T402
Test name
Test status
Simulation time 2054101032 ps
CPU time 19.76 seconds
Started Jan 17 12:48:59 PM PST 24
Finished Jan 17 12:49:31 PM PST 24
Peak memory 218748 kb
Host smart-3e7a226b-c877-4dd0-bc3b-535804d39b04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167464262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3167464262
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.275176019
Short name T595
Test name
Test status
Simulation time 3361605812 ps
CPU time 7.75 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 218448 kb
Host smart-2f2ec2c5-cf40-4221-8cdd-f7a7c2f297b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275176019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.275176019
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2902041005
Short name T773
Test name
Test status
Simulation time 219289086 ps
CPU time 7.1 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 218120 kb
Host smart-1ac292da-b71f-490f-8b58-05f9cfcf5cc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902041005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2902041005
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1749814748
Short name T393
Test name
Test status
Simulation time 1410999014 ps
CPU time 8.3 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 218168 kb
Host smart-e9059754-f337-499c-bc38-412c36f42774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749814748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1749814748
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3435980482
Short name T90
Test name
Test status
Simulation time 47332790 ps
CPU time 2.95 seconds
Started Jan 17 12:48:54 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 213376 kb
Host smart-61df725d-22a8-4464-8f45-9478e85d2b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435980482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3435980482
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1141205007
Short name T817
Test name
Test status
Simulation time 1831042118 ps
CPU time 22 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 251076 kb
Host smart-6f63e693-fd46-4335-aa3d-bfe1ae242e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141205007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1141205007
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3447301580
Short name T468
Test name
Test status
Simulation time 262979742 ps
CPU time 6.69 seconds
Started Jan 17 12:49:00 PM PST 24
Finished Jan 17 12:49:17 PM PST 24
Peak memory 250556 kb
Host smart-e05a4d08-d328-45f2-8be0-096b278b760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447301580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3447301580
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4241346525
Short name T361
Test name
Test status
Simulation time 4916821696 ps
CPU time 47.9 seconds
Started Jan 17 12:48:59 PM PST 24
Finished Jan 17 12:49:59 PM PST 24
Peak memory 250728 kb
Host smart-e02ab823-df12-4bed-a2d8-1e67ad0c1db9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241346525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4241346525
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1534279585
Short name T355
Test name
Test status
Simulation time 33580713 ps
CPU time 0.87 seconds
Started Jan 17 12:48:54 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 208128 kb
Host smart-71bd5faf-0497-46dc-ae8f-2b9f0768243c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534279585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1534279585
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1571640804
Short name T766
Test name
Test status
Simulation time 83482623 ps
CPU time 0.92 seconds
Started Jan 17 12:49:02 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 209656 kb
Host smart-67101eba-62b4-4927-b5c7-88e8f0217ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571640804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1571640804
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2578944637
Short name T333
Test name
Test status
Simulation time 625162765 ps
CPU time 11.14 seconds
Started Jan 17 12:48:53 PM PST 24
Finished Jan 17 12:49:21 PM PST 24
Peak memory 218192 kb
Host smart-a4a1e491-77f8-47f8-9eb4-cbd71bc49dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578944637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2578944637
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1301259379
Short name T849
Test name
Test status
Simulation time 431635421 ps
CPU time 4.6 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:15 PM PST 24
Peak memory 209636 kb
Host smart-b591094e-4939-4055-a226-04ba36195e85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301259379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.1301259379
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4024075516
Short name T717
Test name
Test status
Simulation time 314144209 ps
CPU time 2.58 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 218136 kb
Host smart-9d688bb2-7f03-4006-8535-28da15653cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024075516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4024075516
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2510106222
Short name T811
Test name
Test status
Simulation time 828862392 ps
CPU time 9.41 seconds
Started Jan 17 12:48:57 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 218648 kb
Host smart-e7bc6785-228b-48f8-adff-46c73eabcea5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510106222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2510106222
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3666334315
Short name T497
Test name
Test status
Simulation time 1287944809 ps
CPU time 13.71 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 218116 kb
Host smart-7ab6ebf5-411d-49f9-87d0-4159bf0f13f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666334315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3666334315
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2728365966
Short name T424
Test name
Test status
Simulation time 425090949 ps
CPU time 6.34 seconds
Started Jan 17 12:48:55 PM PST 24
Finished Jan 17 12:49:17 PM PST 24
Peak memory 218120 kb
Host smart-6bb78283-b40d-44f6-811d-dbc05c824ff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728365966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2728365966
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1603020235
Short name T781
Test name
Test status
Simulation time 1939959948 ps
CPU time 8.95 seconds
Started Jan 17 12:48:56 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 218180 kb
Host smart-53c59017-03be-4cf3-8fbb-aee9a41a731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603020235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1603020235
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.15171999
Short name T568
Test name
Test status
Simulation time 351714875 ps
CPU time 1.55 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 213520 kb
Host smart-83f1583e-da68-43ba-90ed-b2cebee4c6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15171999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.15171999
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.685307067
Short name T301
Test name
Test status
Simulation time 245246137 ps
CPU time 29.52 seconds
Started Jan 17 12:48:53 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 251056 kb
Host smart-a407fe94-e2cb-45c0-875e-dfe9194cf692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685307067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.685307067
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1695626510
Short name T871
Test name
Test status
Simulation time 75571973 ps
CPU time 6.15 seconds
Started Jan 17 12:48:58 PM PST 24
Finished Jan 17 12:49:16 PM PST 24
Peak memory 246308 kb
Host smart-ba6f21bd-7506-452b-bcf1-27781c90c7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695626510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1695626510
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3295010586
Short name T68
Test name
Test status
Simulation time 36710844599 ps
CPU time 671.28 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 01:00:30 PM PST 24
Peak memory 268404 kb
Host smart-edde9cb5-5b64-46b3-9516-c59a7ce9b9a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295010586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3295010586
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2137644723
Short name T835
Test name
Test status
Simulation time 178955776794 ps
CPU time 717.36 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 01:01:19 PM PST 24
Peak memory 342464 kb
Host smart-3898c932-8723-4eec-9724-89809c786ea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2137644723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2137644723
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2439518883
Short name T888
Test name
Test status
Simulation time 11875013 ps
CPU time 0.92 seconds
Started Jan 17 12:48:53 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 208084 kb
Host smart-eba6dd96-2c50-407b-8f24-6bf154f17b6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439518883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2439518883
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2691851819
Short name T963
Test name
Test status
Simulation time 82512014 ps
CPU time 0.87 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 209564 kb
Host smart-cbd0fea5-3dc2-4935-995f-50f19dc1be58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691851819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2691851819
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.607786334
Short name T969
Test name
Test status
Simulation time 282030808 ps
CPU time 13.05 seconds
Started Jan 17 12:49:00 PM PST 24
Finished Jan 17 12:49:23 PM PST 24
Peak memory 218136 kb
Host smart-27d36635-831e-4128-bdc1-bdaf5f071b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607786334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.607786334
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3430185335
Short name T550
Test name
Test status
Simulation time 1320929036 ps
CPU time 8.77 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 209604 kb
Host smart-69f3b582-99d8-47de-b09e-87d9fb32662a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430185335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.3430185335
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2966306673
Short name T457
Test name
Test status
Simulation time 378827331 ps
CPU time 3.21 seconds
Started Jan 17 12:49:12 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 218292 kb
Host smart-23b9c90a-ff6f-416f-8d2b-8d0f5082c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966306673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2966306673
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3082773026
Short name T848
Test name
Test status
Simulation time 336732253 ps
CPU time 12.02 seconds
Started Jan 17 12:49:05 PM PST 24
Finished Jan 17 12:49:23 PM PST 24
Peak memory 218184 kb
Host smart-d5113d6e-5f88-40aa-b7a6-4bb16ee4cfd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082773026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3082773026
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.751239829
Short name T517
Test name
Test status
Simulation time 263059952 ps
CPU time 9.91 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 218068 kb
Host smart-a526c5ea-4907-408e-8954-2be737864a23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751239829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.751239829
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1674595518
Short name T609
Test name
Test status
Simulation time 485766451 ps
CPU time 8.11 seconds
Started Jan 17 12:49:08 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 218088 kb
Host smart-b6503599-9c56-4d32-894b-dc8116560630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674595518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1674595518
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2206454786
Short name T372
Test name
Test status
Simulation time 276323749 ps
CPU time 7.59 seconds
Started Jan 17 12:49:02 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 218132 kb
Host smart-151cb87c-811b-4e86-aa36-7c3f67d9f4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206454786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2206454786
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.797260742
Short name T624
Test name
Test status
Simulation time 71367078 ps
CPU time 2.21 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 213504 kb
Host smart-743f9e06-e97d-4e02-8225-a64df9795e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797260742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.797260742
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2656751038
Short name T307
Test name
Test status
Simulation time 210722860 ps
CPU time 24.16 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 251108 kb
Host smart-76bec0f5-c603-4daa-b5a2-d934d1d005ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656751038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2656751038
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2832193276
Short name T907
Test name
Test status
Simulation time 337316280 ps
CPU time 7.69 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:30 PM PST 24
Peak memory 251168 kb
Host smart-74341186-a9e6-4ba8-af35-ca58c19271f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832193276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2832193276
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.687041079
Short name T913
Test name
Test status
Simulation time 1515352158 ps
CPU time 19.85 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:30 PM PST 24
Peak memory 226340 kb
Host smart-c204176b-99dc-4c46-8fa8-f09fa7ab30d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687041079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.687041079
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.97968564
Short name T720
Test name
Test status
Simulation time 36888866 ps
CPU time 1.19 seconds
Started Jan 17 12:49:04 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 212552 kb
Host smart-c7a599d1-32fe-4368-8536-654975ae7da1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97968564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctr
l_volatile_unlock_smoke.97968564
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1995468733
Short name T745
Test name
Test status
Simulation time 41870856 ps
CPU time 0.92 seconds
Started Jan 17 12:49:05 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 209680 kb
Host smart-69f8f09c-4573-4f9e-b286-d415ddc108d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995468733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1995468733
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3101522076
Short name T318
Test name
Test status
Simulation time 4297976051 ps
CPU time 11.25 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:28 PM PST 24
Peak memory 218248 kb
Host smart-f7c20c99-3f28-42bf-be9c-740d3604de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101522076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3101522076
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2001853033
Short name T697
Test name
Test status
Simulation time 385381579 ps
CPU time 9.42 seconds
Started Jan 17 12:49:15 PM PST 24
Finished Jan 17 12:49:25 PM PST 24
Peak memory 209688 kb
Host smart-dcad35fd-cbb7-4340-bbf3-337e29b7ddc1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001853033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.2001853033
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3232298887
Short name T866
Test name
Test status
Simulation time 184648195 ps
CPU time 2.86 seconds
Started Jan 17 12:49:03 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 218344 kb
Host smart-ad31bdab-a8db-4397-bf92-1808f83eb7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232298887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3232298887
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2023394672
Short name T885
Test name
Test status
Simulation time 308693709 ps
CPU time 9.4 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 218120 kb
Host smart-57857bbf-42e4-4c8f-b4e8-63e4bf71df3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023394672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2023394672
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1816765048
Short name T808
Test name
Test status
Simulation time 625275683 ps
CPU time 21.56 seconds
Started Jan 17 12:49:02 PM PST 24
Finished Jan 17 12:49:32 PM PST 24
Peak memory 218124 kb
Host smart-c614e140-fe5d-4e5f-a68a-b4f113448f23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816765048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1816765048
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3908659207
Short name T558
Test name
Test status
Simulation time 1521518171 ps
CPU time 8.11 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:31 PM PST 24
Peak memory 218052 kb
Host smart-c5dfd269-25e7-44d8-a0f5-6fd600abbd69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908659207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3908659207
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.647673119
Short name T390
Test name
Test status
Simulation time 862069359 ps
CPU time 7.02 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 218228 kb
Host smart-1cce3ffc-97bb-42db-93d2-a888f0a04522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647673119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.647673119
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3579050259
Short name T798
Test name
Test status
Simulation time 43803966 ps
CPU time 1.67 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 213708 kb
Host smart-b387ef95-0850-4c3c-88ac-9f12cf15b597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579050259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3579050259
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.868416493
Short name T881
Test name
Test status
Simulation time 247866789 ps
CPU time 29.73 seconds
Started Jan 17 12:49:02 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 246284 kb
Host smart-a581f020-79cf-4d10-9774-629146fadef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868416493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.868416493
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2195086083
Short name T446
Test name
Test status
Simulation time 68549674 ps
CPU time 8.05 seconds
Started Jan 17 12:49:02 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 251168 kb
Host smart-69638c7c-d01c-4d70-b31b-968f8eb25f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195086083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2195086083
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3913789648
Short name T903
Test name
Test status
Simulation time 2991908673 ps
CPU time 39.59 seconds
Started Jan 17 12:49:05 PM PST 24
Finished Jan 17 12:49:50 PM PST 24
Peak memory 219180 kb
Host smart-cf247aca-f403-4d21-94e8-29e35fbacda6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913789648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3913789648
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2631094068
Short name T782
Test name
Test status
Simulation time 53365950 ps
CPU time 0.82 seconds
Started Jan 17 12:49:02 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 208540 kb
Host smart-fc132483-8c5b-4778-b0d7-8ae7ff0c23e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631094068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2631094068
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3355858611
Short name T84
Test name
Test status
Simulation time 103769080 ps
CPU time 0.88 seconds
Started Jan 17 12:47:56 PM PST 24
Finished Jan 17 12:47:57 PM PST 24
Peak memory 209660 kb
Host smart-efe10a7d-9af4-44db-8c14-a04e2e0d21c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355858611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3355858611
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1443821646
Short name T464
Test name
Test status
Simulation time 1051731286 ps
CPU time 14.36 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:48:06 PM PST 24
Peak memory 218196 kb
Host smart-ca36dc2c-9ffb-4451-a664-528d61bed0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443821646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1443821646
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.861515493
Short name T887
Test name
Test status
Simulation time 514965138 ps
CPU time 4.03 seconds
Started Jan 17 12:47:55 PM PST 24
Finished Jan 17 12:48:00 PM PST 24
Peak memory 209696 kb
Host smart-9c76198e-471f-4483-9757-ea030aca9b31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861515493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_acc
ess.861515493
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.901900661
Short name T543
Test name
Test status
Simulation time 2411725965 ps
CPU time 35.51 seconds
Started Jan 17 12:47:53 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 218172 kb
Host smart-68a4cda6-7cfa-4e6f-bd13-aab6d7428abb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901900661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.901900661
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3819413649
Short name T565
Test name
Test status
Simulation time 2471390367 ps
CPU time 9.81 seconds
Started Jan 17 12:47:59 PM PST 24
Finished Jan 17 12:48:10 PM PST 24
Peak memory 217972 kb
Host smart-45e63fec-5f68-4c7f-898f-2425bee0c401
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819413649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.3819413649
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.44731028
Short name T407
Test name
Test status
Simulation time 680390377 ps
CPU time 18.41 seconds
Started Jan 17 12:47:49 PM PST 24
Finished Jan 17 12:48:11 PM PST 24
Peak memory 218136 kb
Host smart-88328709-c67b-4671-9385-0a59157f30b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44731028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_p
rog_failure.44731028
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2060989159
Short name T428
Test name
Test status
Simulation time 3823468485 ps
CPU time 23.43 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:35 PM PST 24
Peak memory 213632 kb
Host smart-fdc41970-80cd-4879-9568-c180781a1e97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060989159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2060989159
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2297358925
Short name T588
Test name
Test status
Simulation time 884630775 ps
CPU time 5.37 seconds
Started Jan 17 12:47:59 PM PST 24
Finished Jan 17 12:48:05 PM PST 24
Peak memory 213248 kb
Host smart-9fef810e-ec8c-42d0-ab20-3dbecd175ba4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297358925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2297358925
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2700832340
Short name T337
Test name
Test status
Simulation time 1440907058 ps
CPU time 33.72 seconds
Started Jan 17 12:47:59 PM PST 24
Finished Jan 17 12:48:34 PM PST 24
Peak memory 251040 kb
Host smart-a40587a8-da2e-4909-b5e5-6893fbe05537
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700832340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2700832340
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.916147419
Short name T492
Test name
Test status
Simulation time 5055767867 ps
CPU time 11.18 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 251180 kb
Host smart-17890ec0-2f05-45d8-ba0e-24d230df43e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916147419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.916147419
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2133259776
Short name T856
Test name
Test status
Simulation time 82483430 ps
CPU time 3.22 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 218076 kb
Host smart-31a0e592-31c4-4d1e-8f52-3069ab623849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133259776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2133259776
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.992340147
Short name T892
Test name
Test status
Simulation time 641799436 ps
CPU time 13.27 seconds
Started Jan 17 12:47:53 PM PST 24
Finished Jan 17 12:48:08 PM PST 24
Peak memory 214112 kb
Host smart-80b9a2b5-75d7-4d91-ae73-c1f8cc41d575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992340147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.992340147
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2719817012
Short name T116
Test name
Test status
Simulation time 111913355 ps
CPU time 24.37 seconds
Started Jan 17 12:47:55 PM PST 24
Finished Jan 17 12:48:20 PM PST 24
Peak memory 267452 kb
Host smart-d3f47e0d-ba0b-4892-9459-74fb5206f7a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719817012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2719817012
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1320542960
Short name T443
Test name
Test status
Simulation time 801929279 ps
CPU time 12.12 seconds
Started Jan 17 12:47:49 PM PST 24
Finished Jan 17 12:48:05 PM PST 24
Peak memory 218176 kb
Host smart-b05951e7-4054-47cf-9dd9-d393549b14e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320542960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1320542960
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1207935104
Short name T575
Test name
Test status
Simulation time 442803559 ps
CPU time 12.73 seconds
Started Jan 17 12:47:59 PM PST 24
Finished Jan 17 12:48:13 PM PST 24
Peak memory 218100 kb
Host smart-0cc5a8a6-5d49-4b37-a63e-13b9e3d42949
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207935104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1207935104
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1923649656
Short name T596
Test name
Test status
Simulation time 313670005 ps
CPU time 7.98 seconds
Started Jan 17 12:47:59 PM PST 24
Finished Jan 17 12:48:08 PM PST 24
Peak memory 218172 kb
Host smart-422abd98-182d-41e5-b3e7-2b36f00ae079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923649656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1923649656
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4227987096
Short name T632
Test name
Test status
Simulation time 229187198 ps
CPU time 2.96 seconds
Started Jan 17 12:47:53 PM PST 24
Finished Jan 17 12:47:58 PM PST 24
Peak memory 213432 kb
Host smart-a912b5e4-02d0-4ab0-8892-2f33fcdc4ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227987096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4227987096
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.4107043589
Short name T425
Test name
Test status
Simulation time 336129001 ps
CPU time 31.89 seconds
Started Jan 17 12:47:55 PM PST 24
Finished Jan 17 12:48:28 PM PST 24
Peak memory 251172 kb
Host smart-46c85493-c5da-4764-aa28-a10335a15e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107043589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.4107043589
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3680378785
Short name T602
Test name
Test status
Simulation time 178688080 ps
CPU time 6.1 seconds
Started Jan 17 12:47:55 PM PST 24
Finished Jan 17 12:48:02 PM PST 24
Peak memory 249956 kb
Host smart-c63aa50c-4426-492e-b1f4-40dda66b6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680378785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3680378785
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3048570638
Short name T505
Test name
Test status
Simulation time 2312522422 ps
CPU time 78.28 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 248868 kb
Host smart-9bdf479c-1d26-425c-8cd8-0c66ce24676e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048570638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3048570638
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2599346471
Short name T733
Test name
Test status
Simulation time 13526991 ps
CPU time 0.94 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:12 PM PST 24
Peak memory 207692 kb
Host smart-f1b92938-aa35-4866-bea1-eca17d954ee5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599346471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2599346471
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3946195366
Short name T397
Test name
Test status
Simulation time 50753023 ps
CPU time 0.85 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 208336 kb
Host smart-91b4cf7c-b195-4cae-91f6-e8c1c5f7bac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946195366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3946195366
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1389110202
Short name T356
Test name
Test status
Simulation time 285260346 ps
CPU time 15.03 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 218136 kb
Host smart-cd3dd685-c457-4cd3-8df1-9158f4b666a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389110202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1389110202
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.229778899
Short name T651
Test name
Test status
Simulation time 66919708 ps
CPU time 1.19 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:17 PM PST 24
Peak memory 209640 kb
Host smart-f5763c7f-6ce6-4caf-a93b-be9014acefd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229778899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_ac
cess.229778899
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3486863012
Short name T362
Test name
Test status
Simulation time 69383272 ps
CPU time 3.11 seconds
Started Jan 17 12:49:15 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 218112 kb
Host smart-343bf3ff-facd-42b0-be1f-75660840e96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486863012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3486863012
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2086606086
Short name T622
Test name
Test status
Simulation time 320244657 ps
CPU time 10.4 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:27 PM PST 24
Peak memory 219152 kb
Host smart-a32093a6-dbc8-4edb-94e3-ae15534c13ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086606086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2086606086
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3093727007
Short name T901
Test name
Test status
Simulation time 934418109 ps
CPU time 9.17 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:28 PM PST 24
Peak memory 218068 kb
Host smart-3eb53df0-42ce-4845-9f6c-1a1e8f053235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093727007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3093727007
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3491481209
Short name T666
Test name
Test status
Simulation time 522822337 ps
CPU time 11.08 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:29 PM PST 24
Peak memory 218108 kb
Host smart-a0a812ad-7793-4625-99e0-2322d0acde37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491481209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3491481209
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2649861644
Short name T896
Test name
Test status
Simulation time 5011206634 ps
CPU time 11.87 seconds
Started Jan 17 12:49:23 PM PST 24
Finished Jan 17 12:49:36 PM PST 24
Peak memory 218252 kb
Host smart-3a57c6fd-53f0-42d5-ab72-255fd0b5af33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649861644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2649861644
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2181408478
Short name T809
Test name
Test status
Simulation time 241840529 ps
CPU time 2.73 seconds
Started Jan 17 12:49:08 PM PST 24
Finished Jan 17 12:49:14 PM PST 24
Peak memory 214248 kb
Host smart-ad7d5928-55ca-4c84-9e1e-d891912b2faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181408478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2181408478
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3010446626
Short name T339
Test name
Test status
Simulation time 1014829996 ps
CPU time 23.78 seconds
Started Jan 17 12:49:01 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 251072 kb
Host smart-9f31886f-7f4e-4a68-9976-08634a94525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010446626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3010446626
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2640011670
Short name T977
Test name
Test status
Simulation time 410344749 ps
CPU time 2.74 seconds
Started Jan 17 12:49:04 PM PST 24
Finished Jan 17 12:49:13 PM PST 24
Peak memory 226556 kb
Host smart-04d59458-e549-4ad6-8934-2ce419186875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640011670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2640011670
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2062140112
Short name T573
Test name
Test status
Simulation time 35487636800 ps
CPU time 100.62 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:51:04 PM PST 24
Peak memory 282380 kb
Host smart-2a4de744-67f0-4f27-8f39-fe7d1347285a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062140112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2062140112
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.903130979
Short name T978
Test name
Test status
Simulation time 36757894 ps
CPU time 0.76 seconds
Started Jan 17 12:49:05 PM PST 24
Finished Jan 17 12:49:11 PM PST 24
Peak memory 207924 kb
Host smart-b46a5b51-efb5-41e1-b640-1697c9ca57af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903130979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.903130979
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.341931119
Short name T714
Test name
Test status
Simulation time 37535199 ps
CPU time 0.93 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 209664 kb
Host smart-69dc128b-8f7a-4630-812a-5fbbace37b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341931119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.341931119
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1383725698
Short name T32
Test name
Test status
Simulation time 1571559577 ps
CPU time 13.37 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:32 PM PST 24
Peak memory 218156 kb
Host smart-6b55021a-7084-46df-89b5-ad5e7c7d89db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383725698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1383725698
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1551337428
Short name T823
Test name
Test status
Simulation time 3834724750 ps
CPU time 22.76 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:46 PM PST 24
Peak memory 209680 kb
Host smart-9f54a354-79ba-4f17-9555-8c8d6b3f38ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551337428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.1551337428
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2336397025
Short name T313
Test name
Test status
Simulation time 101815555 ps
CPU time 1.7 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 218176 kb
Host smart-b3c34d0c-a608-4d96-ae13-909e6388ae8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336397025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2336397025
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4279598024
Short name T794
Test name
Test status
Simulation time 804501860 ps
CPU time 15.09 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 219204 kb
Host smart-906a26a5-f42a-4d14-96ab-9ddf5cd41ea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279598024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4279598024
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.642743768
Short name T567
Test name
Test status
Simulation time 2783720861 ps
CPU time 10.36 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:30 PM PST 24
Peak memory 218180 kb
Host smart-02ae0ab8-be08-4736-877a-ac21b16aeff9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642743768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.642743768
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.16394864
Short name T663
Test name
Test status
Simulation time 491633951 ps
CPU time 10.72 seconds
Started Jan 17 12:49:15 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 218116 kb
Host smart-f8e5773b-85b0-4261-b112-192d16d39ef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16394864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.16394864
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.817902837
Short name T432
Test name
Test status
Simulation time 317499074 ps
CPU time 13.19 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:36 PM PST 24
Peak memory 218224 kb
Host smart-883c6b88-9fa8-47cb-825a-08b86d167cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817902837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.817902837
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2117082422
Short name T750
Test name
Test status
Simulation time 82306328 ps
CPU time 3.11 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:25 PM PST 24
Peak memory 214124 kb
Host smart-61d806e1-f13c-4975-88fe-7f24aa4ae08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117082422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2117082422
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3896439142
Short name T417
Test name
Test status
Simulation time 1593160377 ps
CPU time 27.81 seconds
Started Jan 17 12:49:13 PM PST 24
Finished Jan 17 12:49:43 PM PST 24
Peak memory 250912 kb
Host smart-5ecd5a3a-21db-415e-ba97-52718c0296fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896439142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3896439142
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.827262047
Short name T305
Test name
Test status
Simulation time 352054725 ps
CPU time 7.52 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:31 PM PST 24
Peak memory 249772 kb
Host smart-ecf3d36a-7397-4d85-845b-992698146555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827262047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.827262047
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1063002471
Short name T725
Test name
Test status
Simulation time 4492334586 ps
CPU time 53.94 seconds
Started Jan 17 12:49:14 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 251252 kb
Host smart-df720c35-9fe8-48c9-950d-7ed1002ff246
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063002471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1063002471
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1118180571
Short name T692
Test name
Test status
Simulation time 46273931 ps
CPU time 0.84 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 208060 kb
Host smart-fbf39c35-467d-45b9-97c6-97dcaf8334ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118180571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1118180571
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2669659331
Short name T340
Test name
Test status
Simulation time 36678359 ps
CPU time 1.09 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 209696 kb
Host smart-5d9cacec-2ae2-4a00-8d25-da65fee98da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669659331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2669659331
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2410517152
Short name T822
Test name
Test status
Simulation time 253130175 ps
CPU time 13.19 seconds
Started Jan 17 12:49:14 PM PST 24
Finished Jan 17 12:49:28 PM PST 24
Peak memory 218208 kb
Host smart-75a753ba-8de0-408e-87f1-dc3779947bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410517152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2410517152
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1395917554
Short name T695
Test name
Test status
Simulation time 5916006145 ps
CPU time 19.2 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:36 PM PST 24
Peak memory 209992 kb
Host smart-db0169dd-119b-4af1-8b1a-2a65017f061c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395917554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.1395917554
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2988007174
Short name T834
Test name
Test status
Simulation time 290741400 ps
CPU time 3.03 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 218172 kb
Host smart-6c00271f-1af9-4943-895a-4c738ac43972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988007174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2988007174
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.482619467
Short name T889
Test name
Test status
Simulation time 388482190 ps
CPU time 13.49 seconds
Started Jan 17 12:49:21 PM PST 24
Finished Jan 17 12:49:37 PM PST 24
Peak memory 218500 kb
Host smart-7925d368-a223-4a84-b71f-697576dc4583
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482619467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.482619467
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.53085582
Short name T611
Test name
Test status
Simulation time 516670741 ps
CPU time 12.6 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:31 PM PST 24
Peak memory 218116 kb
Host smart-a6cf7b21-cf96-412d-869e-27e260e4099f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53085582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_dig
est.53085582
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.880910364
Short name T951
Test name
Test status
Simulation time 791796801 ps
CPU time 15.11 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:38 PM PST 24
Peak memory 218064 kb
Host smart-1591327e-776d-4196-81d0-6cfcf50b3aaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880910364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.880910364
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1248273639
Short name T708
Test name
Test status
Simulation time 295957143 ps
CPU time 7.99 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:31 PM PST 24
Peak memory 218076 kb
Host smart-627a1247-9bc8-422a-bc25-288a8be26995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248273639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1248273639
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2236681274
Short name T876
Test name
Test status
Simulation time 84118134 ps
CPU time 1.37 seconds
Started Jan 17 12:49:14 PM PST 24
Finished Jan 17 12:49:16 PM PST 24
Peak memory 213208 kb
Host smart-86fbf049-863f-4796-bd8e-8acb03b3994a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236681274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2236681274
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.278829964
Short name T821
Test name
Test status
Simulation time 933250037 ps
CPU time 16.76 seconds
Started Jan 17 12:49:15 PM PST 24
Finished Jan 17 12:49:32 PM PST 24
Peak memory 245964 kb
Host smart-685fa4c3-f8ad-465b-98b3-b1f0877533cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278829964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.278829964
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3006402811
Short name T976
Test name
Test status
Simulation time 64022136 ps
CPU time 9.11 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:27 PM PST 24
Peak memory 251108 kb
Host smart-6e3396f4-0171-403f-807f-daefba1072fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006402811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3006402811
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3333603556
Short name T413
Test name
Test status
Simulation time 2100627304 ps
CPU time 106.96 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:51:04 PM PST 24
Peak memory 275760 kb
Host smart-74b5fdc0-3f19-431a-baa1-32ff640002a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333603556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3333603556
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4282933209
Short name T749
Test name
Test status
Simulation time 41561493 ps
CPU time 0.97 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 208660 kb
Host smart-f124693a-1d72-4eb5-8f89-180d55a1a352
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282933209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.4282933209
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3298976053
Short name T302
Test name
Test status
Simulation time 24116537 ps
CPU time 1 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 209676 kb
Host smart-ffc9149c-c825-4647-b66a-d3c5e57807c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298976053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3298976053
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3807133645
Short name T421
Test name
Test status
Simulation time 907376330 ps
CPU time 15.2 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 218228 kb
Host smart-cb206213-6611-408e-b067-80c179cd617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807133645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3807133645
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3482644573
Short name T813
Test name
Test status
Simulation time 561705757 ps
CPU time 1.75 seconds
Started Jan 17 12:49:15 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 209676 kb
Host smart-347a1d10-d2ee-4489-b275-dceae3eb9a31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482644573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.3482644573
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3764793874
Short name T69
Test name
Test status
Simulation time 56792781 ps
CPU time 2.94 seconds
Started Jan 17 12:49:14 PM PST 24
Finished Jan 17 12:49:18 PM PST 24
Peak memory 218172 kb
Host smart-96a07bb0-1d95-427b-9d4e-6c31b8d4321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764793874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3764793874
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3917318659
Short name T548
Test name
Test status
Simulation time 1325370010 ps
CPU time 16.25 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 219228 kb
Host smart-f38ac132-b810-43fe-b8e4-88402746a855
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917318659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3917318659
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4108909889
Short name T799
Test name
Test status
Simulation time 1508615744 ps
CPU time 14.75 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:38 PM PST 24
Peak memory 218088 kb
Host smart-94bfc276-9790-4caa-b217-75297fdeb7e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108909889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4108909889
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2703183015
Short name T542
Test name
Test status
Simulation time 419554567 ps
CPU time 11.24 seconds
Started Jan 17 12:49:15 PM PST 24
Finished Jan 17 12:49:27 PM PST 24
Peak memory 218116 kb
Host smart-c5c26878-a0ee-4e3d-ba44-3cd2a05edcfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703183015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2703183015
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1824479114
Short name T94
Test name
Test status
Simulation time 292540886 ps
CPU time 10.97 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:35 PM PST 24
Peak memory 218192 kb
Host smart-ba7849f8-68e1-4568-bb6f-da26f49adb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824479114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1824479114
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2978330301
Short name T334
Test name
Test status
Simulation time 19279955 ps
CPU time 1.45 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:21 PM PST 24
Peak memory 213240 kb
Host smart-6bd91882-cc99-4225-9f65-b4e7cdaef0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978330301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2978330301
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.4023240013
Short name T406
Test name
Test status
Simulation time 807806512 ps
CPU time 23.93 seconds
Started Jan 17 12:49:15 PM PST 24
Finished Jan 17 12:49:39 PM PST 24
Peak memory 251116 kb
Host smart-676ef2fa-9c03-456e-9c6b-67ce51e6f83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023240013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.4023240013
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.535163809
Short name T787
Test name
Test status
Simulation time 225460207 ps
CPU time 7.11 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:29 PM PST 24
Peak memory 250516 kb
Host smart-30837ac9-3574-4574-9efc-b90e27b778dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535163809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.535163809
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.980206493
Short name T61
Test name
Test status
Simulation time 17796799390 ps
CPU time 187.59 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:52:31 PM PST 24
Peak memory 251252 kb
Host smart-cb0aca2a-dbe0-4c5c-9c5f-f11342d452c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980206493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.980206493
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1324291402
Short name T41
Test name
Test status
Simulation time 15359883 ps
CPU time 1.26 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:20 PM PST 24
Peak memory 212696 kb
Host smart-a766164b-0346-4a63-b540-3e9eeeb9dfb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324291402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1324291402
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2051437188
Short name T783
Test name
Test status
Simulation time 39091153 ps
CPU time 1.17 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 209688 kb
Host smart-a703b53d-de30-478a-ac6c-39ec98685aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051437188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2051437188
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2308948936
Short name T304
Test name
Test status
Simulation time 378519466 ps
CPU time 13.03 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:37 PM PST 24
Peak memory 218156 kb
Host smart-3d6563a4-4d0c-46f0-ad20-902065cf0d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308948936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2308948936
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4051910661
Short name T936
Test name
Test status
Simulation time 2588200577 ps
CPU time 4.54 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:21 PM PST 24
Peak memory 209668 kb
Host smart-e02bacec-73a7-4074-a95e-f4610347c547
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051910661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.4051910661
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2227369428
Short name T410
Test name
Test status
Simulation time 228026018 ps
CPU time 2.74 seconds
Started Jan 17 12:49:15 PM PST 24
Finished Jan 17 12:49:19 PM PST 24
Peak memory 218144 kb
Host smart-f6f361d5-e412-47b3-8c58-d94e26a845e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227369428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2227369428
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3186299986
Short name T672
Test name
Test status
Simulation time 510029544 ps
CPU time 11.31 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 218164 kb
Host smart-2dfcf47c-1ffc-47ea-a1da-eb742b68ea0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186299986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3186299986
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2270777558
Short name T440
Test name
Test status
Simulation time 394239255 ps
CPU time 11.96 seconds
Started Jan 17 12:49:16 PM PST 24
Finished Jan 17 12:49:30 PM PST 24
Peak memory 218080 kb
Host smart-2b9efae9-d6a2-4f5e-aa3e-fcef3c5ab9aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270777558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2270777558
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.794354004
Short name T411
Test name
Test status
Simulation time 208753473 ps
CPU time 6.28 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:29 PM PST 24
Peak memory 218092 kb
Host smart-0f3ef6b9-ff4b-4153-8986-f2e627900680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794354004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.794354004
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1546061584
Short name T554
Test name
Test status
Simulation time 317440955 ps
CPU time 11.09 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 218136 kb
Host smart-e9f1621d-eafd-47b5-84ac-f60f7f0e6a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546061584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1546061584
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3331438365
Short name T707
Test name
Test status
Simulation time 753425820 ps
CPU time 3.38 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 213984 kb
Host smart-769feee5-f2f3-4ccc-990d-4a5910d2d158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331438365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3331438365
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3273804608
Short name T850
Test name
Test status
Simulation time 1591828894 ps
CPU time 30.55 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:54 PM PST 24
Peak memory 250964 kb
Host smart-c3d9a59a-51a2-469e-8d47-f2ec86c3f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273804608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3273804608
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.747466448
Short name T671
Test name
Test status
Simulation time 59741978 ps
CPU time 6.26 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:29 PM PST 24
Peak memory 242752 kb
Host smart-0d3e82ff-ca7f-4d5b-986c-d03d163209d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747466448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.747466448
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4285832531
Short name T865
Test name
Test status
Simulation time 14218090 ps
CPU time 0.96 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 208156 kb
Host smart-a49f5876-7ae1-45d7-933a-b810e8629ce3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285832531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4285832531
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2246758727
Short name T389
Test name
Test status
Simulation time 13250380 ps
CPU time 1.03 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 208392 kb
Host smart-95103e82-e5b9-4a94-8b82-4ffc6df4ab95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246758727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2246758727
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.376772335
Short name T447
Test name
Test status
Simulation time 2079401921 ps
CPU time 18.33 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:43 PM PST 24
Peak memory 218184 kb
Host smart-fe78740d-148b-4303-9991-70f90adf0127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376772335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.376772335
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4128387528
Short name T534
Test name
Test status
Simulation time 764722368 ps
CPU time 8.42 seconds
Started Jan 17 12:49:23 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 209596 kb
Host smart-a4563423-4298-46af-93fb-d5637958ee8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128387528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.4128387528
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.842099224
Short name T882
Test name
Test status
Simulation time 99615077 ps
CPU time 3.09 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:22 PM PST 24
Peak memory 218180 kb
Host smart-dc68ed86-e71b-4a30-bdbc-29979dd1e6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842099224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.842099224
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1526661808
Short name T953
Test name
Test status
Simulation time 740551153 ps
CPU time 9.73 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 218068 kb
Host smart-f2a6db29-67e5-442c-b7d4-f5ed7af12c04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526661808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1526661808
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2253288845
Short name T641
Test name
Test status
Simulation time 3044094689 ps
CPU time 8.11 seconds
Started Jan 17 12:49:23 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 218160 kb
Host smart-3750dc45-52e1-4c40-aa80-bdef3c640d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253288845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2253288845
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.414299175
Short name T481
Test name
Test status
Simulation time 1165280018 ps
CPU time 11.19 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 218096 kb
Host smart-ecf8c4fe-8f5e-4340-989c-7ed75c6458d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414299175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.414299175
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2091158550
Short name T183
Test name
Test status
Simulation time 317052549 ps
CPU time 8.93 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:28 PM PST 24
Peak memory 218448 kb
Host smart-c6259d2a-897f-4fa9-a980-7caac228c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091158550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2091158550
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.529246705
Short name T503
Test name
Test status
Simulation time 176291954 ps
CPU time 3.1 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:29 PM PST 24
Peak memory 214536 kb
Host smart-a6cd2441-0af3-4293-bfe7-04b04fdf61ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529246705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.529246705
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.390415982
Short name T839
Test name
Test status
Simulation time 1859518625 ps
CPU time 26.19 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:48 PM PST 24
Peak memory 251000 kb
Host smart-b868ce69-b77d-4e0b-a4ed-c3e8c62a0c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390415982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.390415982
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.800633352
Short name T606
Test name
Test status
Simulation time 562949159 ps
CPU time 7.11 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:30 PM PST 24
Peak memory 250612 kb
Host smart-79bd6ee7-c673-49ff-a85a-15a3f765841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800633352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.800633352
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2296417658
Short name T344
Test name
Test status
Simulation time 15783188818 ps
CPU time 94.75 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 282748 kb
Host smart-64850f1f-92d4-4499-a7bc-e8796fe8e04b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296417658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2296417658
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1831919738
Short name T833
Test name
Test status
Simulation time 13948145 ps
CPU time 0.77 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 208060 kb
Host smart-0208f360-ea9a-4e21-8545-816b2e47d503
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831919738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1831919738
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3483043884
Short name T310
Test name
Test status
Simulation time 18287167 ps
CPU time 1.11 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:24 PM PST 24
Peak memory 208500 kb
Host smart-aa11f3ce-74d8-4d83-b889-9714f6304053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483043884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3483043884
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.958288196
Short name T45
Test name
Test status
Simulation time 591014345 ps
CPU time 12.43 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:38 PM PST 24
Peak memory 218092 kb
Host smart-751d7137-d67d-4317-b33f-cf28372b27e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958288196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.958288196
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.439104954
Short name T586
Test name
Test status
Simulation time 970089805 ps
CPU time 10.49 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 209592 kb
Host smart-f1406523-e888-49aa-ad8f-4d2e0326b4c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439104954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_ac
cess.439104954
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1242796995
Short name T469
Test name
Test status
Simulation time 143634421 ps
CPU time 2.31 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 218180 kb
Host smart-254e8154-c81c-498f-8acd-304c5ec0148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242796995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1242796995
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1523988468
Short name T564
Test name
Test status
Simulation time 1081386896 ps
CPU time 12.53 seconds
Started Jan 17 12:49:17 PM PST 24
Finished Jan 17 12:49:32 PM PST 24
Peak memory 218140 kb
Host smart-19cff0b9-ef19-4ed4-88ec-120cd7f73bf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523988468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1523988468
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1523744291
Short name T315
Test name
Test status
Simulation time 2209525971 ps
CPU time 13.85 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:37 PM PST 24
Peak memory 218160 kb
Host smart-96b28d1b-324a-404f-b2ed-5c6a3a9771a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523744291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1523744291
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2015087920
Short name T343
Test name
Test status
Simulation time 3581057495 ps
CPU time 10.62 seconds
Started Jan 17 12:49:21 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 218156 kb
Host smart-8ba2ef16-8a17-48cb-93f2-308ac8347710
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015087920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2015087920
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1796547905
Short name T495
Test name
Test status
Simulation time 906325058 ps
CPU time 8.73 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 218168 kb
Host smart-7c978a26-6ea2-47ab-9c86-df800a371364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796547905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1796547905
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.468868123
Short name T87
Test name
Test status
Simulation time 96195147 ps
CPU time 2.78 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:29 PM PST 24
Peak memory 213852 kb
Host smart-fd720738-992a-453d-afdb-fd6eac743e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468868123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.468868123
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3584633110
Short name T376
Test name
Test status
Simulation time 1779828550 ps
CPU time 35.32 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:58 PM PST 24
Peak memory 251052 kb
Host smart-6141649b-6c35-4e36-8306-1e2e5eb571eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584633110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3584633110
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2913748872
Short name T485
Test name
Test status
Simulation time 598152508 ps
CPU time 7.37 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:31 PM PST 24
Peak memory 246836 kb
Host smart-4aa53205-605d-44a1-bf8c-ffb59995cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913748872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2913748872
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2981550045
Short name T533
Test name
Test status
Simulation time 1579342918 ps
CPU time 63.08 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 245420 kb
Host smart-4dfe3f66-1627-4fcc-8377-ae83ce695231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981550045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2981550045
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3831964057
Short name T592
Test name
Test status
Simulation time 47941822 ps
CPU time 0.88 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 211388 kb
Host smart-f975622a-6c9e-4e3a-997b-3363309848fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831964057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3831964057
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.4006482333
Short name T555
Test name
Test status
Simulation time 36500470 ps
CPU time 0.96 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:27 PM PST 24
Peak memory 209584 kb
Host smart-4d5afaa7-8d52-4cb5-a753-a639c18a2a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006482333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4006482333
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3831980554
Short name T520
Test name
Test status
Simulation time 414995661 ps
CPU time 16.51 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:43 PM PST 24
Peak memory 218112 kb
Host smart-c2ccd733-2724-442a-95be-0da8a19935d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831980554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3831980554
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.4165065594
Short name T635
Test name
Test status
Simulation time 1908951708 ps
CPU time 5.51 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:31 PM PST 24
Peak memory 209660 kb
Host smart-fad26ec9-95dc-4606-9d08-4a3a565e2d0b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165065594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.4165065594
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2466171910
Short name T323
Test name
Test status
Simulation time 71321689 ps
CPU time 2.18 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 218160 kb
Host smart-f92be857-6f83-4cbe-9012-bd9cf7ffdd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466171910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2466171910
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2642310584
Short name T642
Test name
Test status
Simulation time 2930602009 ps
CPU time 14.87 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:41 PM PST 24
Peak memory 219260 kb
Host smart-f9ed016a-ae0c-484b-83f2-26c01f893b93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642310584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2642310584
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3529457995
Short name T501
Test name
Test status
Simulation time 1414813542 ps
CPU time 9.48 seconds
Started Jan 17 12:49:26 PM PST 24
Finished Jan 17 12:49:36 PM PST 24
Peak memory 218064 kb
Host smart-2b44b939-b284-4f78-af7a-b5a4a97d5384
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529457995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3529457995
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2717728898
Short name T664
Test name
Test status
Simulation time 334930623 ps
CPU time 11.86 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:35 PM PST 24
Peak memory 218096 kb
Host smart-a8d0d766-d30c-4b63-b0cf-c7a0550f1d99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717728898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2717728898
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3892103037
Short name T486
Test name
Test status
Simulation time 277792626 ps
CPU time 7.79 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:33 PM PST 24
Peak memory 218168 kb
Host smart-373f999a-2ccd-4c83-ad46-da6f8863a744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892103037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3892103037
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.4010441469
Short name T930
Test name
Test status
Simulation time 147178463 ps
CPU time 8.41 seconds
Started Jan 17 12:49:21 PM PST 24
Finished Jan 17 12:49:32 PM PST 24
Peak memory 214232 kb
Host smart-1e7de151-360a-4be0-8c12-8c42d2a9335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010441469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.4010441469
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2849215095
Short name T435
Test name
Test status
Simulation time 254666472 ps
CPU time 25.46 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:51 PM PST 24
Peak memory 251076 kb
Host smart-5d358d0e-d9ac-4754-8c17-8f2533237f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849215095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2849215095
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1991993215
Short name T739
Test name
Test status
Simulation time 153386369 ps
CPU time 9.01 seconds
Started Jan 17 12:49:26 PM PST 24
Finished Jan 17 12:49:36 PM PST 24
Peak memory 251128 kb
Host smart-4860d0da-55a8-4e8c-88ed-b5da123627ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991993215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1991993215
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.791617533
Short name T911
Test name
Test status
Simulation time 764475716 ps
CPU time 29.97 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:56 PM PST 24
Peak memory 251128 kb
Host smart-1d40d3c0-e8ad-46d4-bb30-ba480145b3a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791617533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.791617533
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.257825777
Short name T326
Test name
Test status
Simulation time 15503721 ps
CPU time 0.89 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 208112 kb
Host smart-7f33820d-119a-4aed-b1dc-47707c6c9cf0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257825777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.257825777
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2071274295
Short name T506
Test name
Test status
Simulation time 26364795 ps
CPU time 0.82 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 209688 kb
Host smart-e1bb421c-4eb6-454f-b6fe-3f151d904b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071274295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2071274295
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2362674024
Short name T412
Test name
Test status
Simulation time 351876077 ps
CPU time 16.43 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:49:55 PM PST 24
Peak memory 217716 kb
Host smart-e2b56bb2-b9e6-4337-a289-610cf030abde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362674024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2362674024
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1245335061
Short name T512
Test name
Test status
Simulation time 668029636 ps
CPU time 5.12 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:49:44 PM PST 24
Peak memory 208840 kb
Host smart-bb1737fb-d239-4e9e-bce0-3dea0c7d87f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245335061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.1245335061
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2002223541
Short name T922
Test name
Test status
Simulation time 53405579 ps
CPU time 2.75 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:25 PM PST 24
Peak memory 218132 kb
Host smart-3d525abc-ea17-4173-896c-496e7a0b977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002223541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2002223541
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2579503105
Short name T578
Test name
Test status
Simulation time 1676348128 ps
CPU time 13.48 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 219192 kb
Host smart-48eec620-bf01-46a1-bf31-8164520f93a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579503105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2579503105
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2473802074
Short name T797
Test name
Test status
Simulation time 556115783 ps
CPU time 12.53 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:37 PM PST 24
Peak memory 218112 kb
Host smart-39c29758-0011-4d9a-821c-81d8f7130cc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473802074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2473802074
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1422901410
Short name T703
Test name
Test status
Simulation time 851967950 ps
CPU time 9.44 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:49:36 PM PST 24
Peak memory 218096 kb
Host smart-8b69e294-08e8-4320-9ea0-e8e5cdb329fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422901410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1422901410
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2100816308
Short name T545
Test name
Test status
Simulation time 206009632 ps
CPU time 8.36 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:49:47 PM PST 24
Peak memory 218168 kb
Host smart-450763e6-5e27-4361-bfe8-86d629ac1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100816308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2100816308
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.609382109
Short name T13
Test name
Test status
Simulation time 74721195 ps
CPU time 1.24 seconds
Started Jan 17 12:49:18 PM PST 24
Finished Jan 17 12:49:23 PM PST 24
Peak memory 213056 kb
Host smart-7faf84f7-b44f-49c1-be55-cbc353a716db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609382109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.609382109
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3907766134
Short name T661
Test name
Test status
Simulation time 467386893 ps
CPU time 24.77 seconds
Started Jan 17 12:49:23 PM PST 24
Finished Jan 17 12:49:49 PM PST 24
Peak memory 251092 kb
Host smart-1ec2932f-cb15-40e9-9940-737c88fb50a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907766134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3907766134
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2440983548
Short name T789
Test name
Test status
Simulation time 931777650 ps
CPU time 7.8 seconds
Started Jan 17 12:49:29 PM PST 24
Finished Jan 17 12:49:46 PM PST 24
Peak memory 250724 kb
Host smart-4993112e-3da7-400a-a834-a106a095e3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440983548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2440983548
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3321519267
Short name T516
Test name
Test status
Simulation time 4302091605 ps
CPU time 42.65 seconds
Started Jan 17 12:49:25 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 226404 kb
Host smart-75dd5eaf-fadf-44f3-8ff0-7d1a39373dc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321519267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3321519267
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1547034015
Short name T768
Test name
Test status
Simulation time 34979820 ps
CPU time 1.15 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 212108 kb
Host smart-b5d00f78-df14-4222-9cf6-1f5abf2f2364
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547034015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1547034015
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2665447279
Short name T471
Test name
Test status
Simulation time 22847832 ps
CPU time 0.92 seconds
Started Jan 17 12:49:40 PM PST 24
Finished Jan 17 12:49:59 PM PST 24
Peak memory 209688 kb
Host smart-893c329d-1727-4c89-b1a9-5aba20f8f28e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665447279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2665447279
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2390634819
Short name T44
Test name
Test status
Simulation time 1689046386 ps
CPU time 16.64 seconds
Started Jan 17 12:49:30 PM PST 24
Finished Jan 17 12:49:55 PM PST 24
Peak memory 218164 kb
Host smart-fad88776-4121-4c75-be52-1fd181d4fbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390634819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2390634819
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2989243384
Short name T646
Test name
Test status
Simulation time 6466672353 ps
CPU time 6.89 seconds
Started Jan 17 12:49:21 PM PST 24
Finished Jan 17 12:49:30 PM PST 24
Peak memory 209632 kb
Host smart-00ebdf63-ac5b-4512-95ba-2a25b739d7c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989243384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.2989243384
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2507832667
Short name T336
Test name
Test status
Simulation time 196573172 ps
CPU time 2.58 seconds
Started Jan 17 12:49:21 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 218176 kb
Host smart-1d808d31-f358-4268-bf3e-dd27f90c55bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507832667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2507832667
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3916860793
Short name T690
Test name
Test status
Simulation time 838028199 ps
CPU time 12.54 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:36 PM PST 24
Peak memory 218464 kb
Host smart-a81c0328-f116-42d2-b37a-9154d1637702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916860793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3916860793
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1690578630
Short name T709
Test name
Test status
Simulation time 646711878 ps
CPU time 8.97 seconds
Started Jan 17 12:49:20 PM PST 24
Finished Jan 17 12:49:32 PM PST 24
Peak memory 217992 kb
Host smart-d272cbf7-172e-4201-aeb3-50eda072c50a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690578630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1690578630
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3494608973
Short name T788
Test name
Test status
Simulation time 368339139 ps
CPU time 12.24 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:49:51 PM PST 24
Peak memory 217260 kb
Host smart-16d64ba9-50ae-437c-b4c1-3e357c254f60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494608973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3494608973
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1856158046
Short name T762
Test name
Test status
Simulation time 1043156660 ps
CPU time 8.49 seconds
Started Jan 17 12:49:22 PM PST 24
Finished Jan 17 12:49:32 PM PST 24
Peak memory 218180 kb
Host smart-53ab0893-3e4a-456b-9257-3cb128d87e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856158046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1856158046
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2765319454
Short name T71
Test name
Test status
Simulation time 248710127 ps
CPU time 2.51 seconds
Started Jan 17 12:49:26 PM PST 24
Finished Jan 17 12:49:29 PM PST 24
Peak memory 213772 kb
Host smart-42dca776-7d39-4d2f-aadd-5b849d9ed170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765319454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2765319454
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2994880869
Short name T475
Test name
Test status
Simulation time 492006131 ps
CPU time 24.36 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:47 PM PST 24
Peak memory 250992 kb
Host smart-a41fc589-37ec-456e-8be2-906d0da8406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994880869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2994880869
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3787102711
Short name T75
Test name
Test status
Simulation time 141062106 ps
CPU time 7.34 seconds
Started Jan 17 12:49:19 PM PST 24
Finished Jan 17 12:49:30 PM PST 24
Peak memory 251188 kb
Host smart-ee9f9adb-e7c7-4560-bdf8-5482b38b8c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787102711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3787102711
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3812323419
Short name T934
Test name
Test status
Simulation time 2457027040 ps
CPU time 39.78 seconds
Started Jan 17 12:49:21 PM PST 24
Finished Jan 17 12:50:03 PM PST 24
Peak memory 226408 kb
Host smart-e1c5f910-4b83-42bd-922e-07cdabcd54b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812323419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3812323419
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2115551982
Short name T449
Test name
Test status
Simulation time 44407807 ps
CPU time 0.85 seconds
Started Jan 17 12:49:24 PM PST 24
Finished Jan 17 12:49:26 PM PST 24
Peak memory 208136 kb
Host smart-f281c6e3-973f-4249-90e7-5f74d7a27690
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115551982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2115551982
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2672670366
Short name T466
Test name
Test status
Simulation time 58197860 ps
CPU time 0.93 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:20 PM PST 24
Peak memory 209176 kb
Host smart-9dad75f4-ecdd-43df-a67e-97ea4291a79f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672670366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2672670366
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1096593705
Short name T623
Test name
Test status
Simulation time 102748299 ps
CPU time 0.82 seconds
Started Jan 17 12:47:50 PM PST 24
Finished Jan 17 12:47:54 PM PST 24
Peak memory 209456 kb
Host smart-10b814e5-8c34-4ba9-853c-2e17f6a5f1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096593705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1096593705
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2621064927
Short name T470
Test name
Test status
Simulation time 284549611 ps
CPU time 9.61 seconds
Started Jan 17 12:47:55 PM PST 24
Finished Jan 17 12:48:06 PM PST 24
Peak memory 218160 kb
Host smart-3b0aa063-c7af-4f34-ac7d-665a30b8482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621064927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2621064927
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3252213631
Short name T22
Test name
Test status
Simulation time 458391583 ps
CPU time 5.88 seconds
Started Jan 17 12:47:59 PM PST 24
Finished Jan 17 12:48:06 PM PST 24
Peak memory 209636 kb
Host smart-ae6e5768-2918-410e-9554-01232cf17cdd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252213631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ac
cess.3252213631
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3162171626
Short name T696
Test name
Test status
Simulation time 3915531335 ps
CPU time 59.8 seconds
Started Jan 17 12:48:06 PM PST 24
Finished Jan 17 12:49:09 PM PST 24
Peak memory 219240 kb
Host smart-c39c772f-befd-48be-a85f-178a566e335e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162171626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3162171626
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3857922263
Short name T175
Test name
Test status
Simulation time 625756424 ps
CPU time 6.18 seconds
Started Jan 17 12:47:48 PM PST 24
Finished Jan 17 12:47:59 PM PST 24
Peak memory 209672 kb
Host smart-811ed85a-d1f7-4639-bf3a-58c53ddee53a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857922263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.3857922263
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.642413079
Short name T185
Test name
Test status
Simulation time 705741335 ps
CPU time 18.9 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:38 PM PST 24
Peak memory 218020 kb
Host smart-569bf58e-c576-4c23-bbde-7ff88384b793
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642413079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.642413079
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1955447852
Short name T917
Test name
Test status
Simulation time 2396111061 ps
CPU time 33.61 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:45 PM PST 24
Peak memory 213288 kb
Host smart-b132cb77-d083-4103-9f6a-34744b08c312
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955447852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1955447852
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1895360655
Short name T958
Test name
Test status
Simulation time 577409898 ps
CPU time 4.88 seconds
Started Jan 17 12:47:54 PM PST 24
Finished Jan 17 12:48:00 PM PST 24
Peak memory 213056 kb
Host smart-dc71535b-f3a2-4eb0-9be8-3a5abc82a7fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895360655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1895360655
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3567379119
Short name T633
Test name
Test status
Simulation time 1389952793 ps
CPU time 61.3 seconds
Started Jan 17 12:47:45 PM PST 24
Finished Jan 17 12:48:50 PM PST 24
Peak memory 250912 kb
Host smart-04d79e34-c9d8-4708-a13f-faa0ab25c8ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567379119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3567379119
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.374284654
Short name T972
Test name
Test status
Simulation time 1880926510 ps
CPU time 13.23 seconds
Started Jan 17 12:47:53 PM PST 24
Finished Jan 17 12:48:08 PM PST 24
Peak memory 251076 kb
Host smart-ae2c369a-3c24-4058-9f7a-3e554ea69f54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374284654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.374284654
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3121003596
Short name T854
Test name
Test status
Simulation time 35941293 ps
CPU time 2.43 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:05 PM PST 24
Peak memory 218220 kb
Host smart-87d0fcf8-bc66-4d60-8fd9-cc237f3ec18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121003596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3121003596
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2422159757
Short name T961
Test name
Test status
Simulation time 652379720 ps
CPU time 17.74 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 214192 kb
Host smart-0e78547b-c0af-4bd3-976e-fb116e328c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422159757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2422159757
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.755082264
Short name T729
Test name
Test status
Simulation time 405020558 ps
CPU time 19.2 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:21 PM PST 24
Peak memory 218260 kb
Host smart-3cd7dce2-d4c4-42dd-b053-bcc56b9788fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755082264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.755082264
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3559783783
Short name T544
Test name
Test status
Simulation time 2507400573 ps
CPU time 16.18 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:28 PM PST 24
Peak memory 218152 kb
Host smart-eb113601-43fc-4b78-b334-945f51ae1eac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559783783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3559783783
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1147610414
Short name T477
Test name
Test status
Simulation time 777499139 ps
CPU time 6.42 seconds
Started Jan 17 12:48:05 PM PST 24
Finished Jan 17 12:48:15 PM PST 24
Peak memory 218096 kb
Host smart-a339fa23-76fc-48da-b8cf-5b351410cb31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147610414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
147610414
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2038108644
Short name T92
Test name
Test status
Simulation time 803661237 ps
CPU time 14.28 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:16 PM PST 24
Peak memory 218132 kb
Host smart-001b6624-20ee-4a1b-9599-49648951326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038108644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2038108644
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3207859393
Short name T962
Test name
Test status
Simulation time 15869359 ps
CPU time 1.4 seconds
Started Jan 17 12:47:55 PM PST 24
Finished Jan 17 12:47:57 PM PST 24
Peak memory 213184 kb
Host smart-1f3228c5-3841-492f-8539-0646766e45c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207859393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3207859393
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2060757179
Short name T804
Test name
Test status
Simulation time 2075948213 ps
CPU time 28.61 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 251076 kb
Host smart-c8e7f92d-2c60-49db-9b85-8cc4764b8e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060757179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2060757179
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3407175490
Short name T303
Test name
Test status
Simulation time 549446563 ps
CPU time 3.83 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:05 PM PST 24
Peak memory 218188 kb
Host smart-56f4236c-f2a5-438b-af92-eeba08ba01f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407175490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3407175490
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.529634096
Short name T916
Test name
Test status
Simulation time 2271192831 ps
CPU time 58.82 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:49:00 PM PST 24
Peak memory 252672 kb
Host smart-3d26ef0a-8e10-4ae9-8898-766b895dae63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529634096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.529634096
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2698680016
Short name T895
Test name
Test status
Simulation time 38507406 ps
CPU time 0.99 seconds
Started Jan 17 12:49:28 PM PST 24
Finished Jan 17 12:49:30 PM PST 24
Peak memory 208364 kb
Host smart-93915610-763b-49a6-a8d5-ba24ed4c4648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698680016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2698680016
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3071578290
Short name T728
Test name
Test status
Simulation time 415580493 ps
CPU time 8.85 seconds
Started Jan 17 12:49:35 PM PST 24
Finished Jan 17 12:49:48 PM PST 24
Peak memory 218132 kb
Host smart-f7d61f6c-f8e1-444d-b15e-b05311f3e332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071578290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3071578290
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1241666734
Short name T691
Test name
Test status
Simulation time 352871374 ps
CPU time 5.07 seconds
Started Jan 17 12:49:28 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 209528 kb
Host smart-80c07741-6a08-438c-a2eb-ed2998b4379c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241666734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.1241666734
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2950428743
Short name T795
Test name
Test status
Simulation time 114555062 ps
CPU time 2.66 seconds
Started Jan 17 12:49:42 PM PST 24
Finished Jan 17 12:50:01 PM PST 24
Peak memory 217984 kb
Host smart-58f5f6f7-0ab6-4f4e-b02e-acddc59cf4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950428743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2950428743
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2068809606
Short name T455
Test name
Test status
Simulation time 249175696 ps
CPU time 12.38 seconds
Started Jan 17 12:49:32 PM PST 24
Finished Jan 17 12:49:51 PM PST 24
Peak memory 219244 kb
Host smart-66a95fb4-ee70-4556-b09f-2e27ae314386
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068809606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2068809606
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2129651208
Short name T726
Test name
Test status
Simulation time 369667892 ps
CPU time 14.58 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:49:53 PM PST 24
Peak memory 218104 kb
Host smart-f3c5c6c6-6bef-4739-8d4d-67064bf907eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129651208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2129651208
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2034104482
Short name T908
Test name
Test status
Simulation time 703586462 ps
CPU time 13.22 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:49:52 PM PST 24
Peak memory 218120 kb
Host smart-956c777b-77ac-4ad2-8706-ba733f5176fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034104482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2034104482
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3551680252
Short name T683
Test name
Test status
Simulation time 2100289231 ps
CPU time 13.56 seconds
Started Jan 17 12:49:29 PM PST 24
Finished Jan 17 12:49:52 PM PST 24
Peak memory 218156 kb
Host smart-0b0341a5-d963-41bd-b7c9-577910cea25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551680252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3551680252
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4090084711
Short name T80
Test name
Test status
Simulation time 110536937 ps
CPU time 1.42 seconds
Started Jan 17 12:49:30 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 213480 kb
Host smart-9d534bbe-5d86-4ee6-bc5f-16bf3d1cad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090084711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4090084711
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3106701419
Short name T937
Test name
Test status
Simulation time 1166121329 ps
CPU time 23.55 seconds
Started Jan 17 12:49:28 PM PST 24
Finished Jan 17 12:49:53 PM PST 24
Peak memory 251020 kb
Host smart-8e038753-cc72-4a62-a84a-15c6fc3c7aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106701419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3106701419
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1711772273
Short name T1
Test name
Test status
Simulation time 106073657 ps
CPU time 10.07 seconds
Started Jan 17 12:49:30 PM PST 24
Finished Jan 17 12:49:49 PM PST 24
Peak memory 246448 kb
Host smart-9d05da2a-3570-4216-a10b-cf48e705f9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711772273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1711772273
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.4147058345
Short name T763
Test name
Test status
Simulation time 13627811860 ps
CPU time 45.94 seconds
Started Jan 17 12:49:30 PM PST 24
Finished Jan 17 12:50:25 PM PST 24
Peak memory 251248 kb
Host smart-8f5ce4d2-b9f4-4fad-a276-bcfcf68c9de9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147058345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.4147058345
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.505434437
Short name T350
Test name
Test status
Simulation time 12476986 ps
CPU time 0.98 seconds
Started Jan 17 12:49:30 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 208124 kb
Host smart-3c892665-5ed6-43b8-8281-44f01cd26d30
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505434437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.505434437
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3183067678
Short name T891
Test name
Test status
Simulation time 73606139 ps
CPU time 1.17 seconds
Started Jan 17 12:49:29 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 208408 kb
Host smart-1a29da67-2523-4e59-b497-a748594c80a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183067678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3183067678
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.254020214
Short name T897
Test name
Test status
Simulation time 7674546607 ps
CPU time 11.72 seconds
Started Jan 17 12:49:41 PM PST 24
Finished Jan 17 12:50:10 PM PST 24
Peak memory 218184 kb
Host smart-17586214-faa9-4050-b2dd-7c188bacf925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254020214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.254020214
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3960053128
Short name T618
Test name
Test status
Simulation time 423206429 ps
CPU time 4.59 seconds
Started Jan 17 12:49:29 PM PST 24
Finished Jan 17 12:49:43 PM PST 24
Peak memory 209660 kb
Host smart-8404c99a-387d-40fc-9134-2770ec54c7c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960053128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.3960053128
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1724139199
Short name T342
Test name
Test status
Simulation time 94602706 ps
CPU time 2.01 seconds
Started Jan 17 12:49:33 PM PST 24
Finished Jan 17 12:49:41 PM PST 24
Peak memory 218132 kb
Host smart-d9977372-135f-4c06-952e-7d19b0ac6f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724139199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1724139199
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3326737233
Short name T58
Test name
Test status
Simulation time 962984832 ps
CPU time 9.28 seconds
Started Jan 17 12:49:40 PM PST 24
Finished Jan 17 12:50:08 PM PST 24
Peak memory 218172 kb
Host smart-35d2e10b-d616-4280-ad16-ac5085e00571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326737233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3326737233
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.207990722
Short name T841
Test name
Test status
Simulation time 327932749 ps
CPU time 10.98 seconds
Started Jan 17 12:49:29 PM PST 24
Finished Jan 17 12:49:49 PM PST 24
Peak memory 218288 kb
Host smart-41650583-c3af-48a6-a029-afab321a1cfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207990722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.207990722
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1952056179
Short name T650
Test name
Test status
Simulation time 282445553 ps
CPU time 10.9 seconds
Started Jan 17 12:49:29 PM PST 24
Finished Jan 17 12:49:45 PM PST 24
Peak memory 218116 kb
Host smart-031b8dd1-359a-4505-b78d-516432cebf5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952056179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1952056179
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3212136785
Short name T790
Test name
Test status
Simulation time 380460961 ps
CPU time 11.44 seconds
Started Jan 17 12:49:26 PM PST 24
Finished Jan 17 12:49:39 PM PST 24
Peak memory 218188 kb
Host smart-c93e47db-5f55-4631-aef2-b6b3190ebdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212136785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3212136785
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2064673325
Short name T85
Test name
Test status
Simulation time 517998693 ps
CPU time 2.26 seconds
Started Jan 17 12:49:41 PM PST 24
Finished Jan 17 12:50:01 PM PST 24
Peak memory 213992 kb
Host smart-185173b9-d57c-43f9-99ad-fa1cd5c80e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064673325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2064673325
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.4292149037
Short name T381
Test name
Test status
Simulation time 312121232 ps
CPU time 27.99 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:50:07 PM PST 24
Peak memory 251088 kb
Host smart-0065a7bb-11e8-4444-98ae-2a9faa1c6b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292149037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4292149037
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2785062041
Short name T472
Test name
Test status
Simulation time 66053875 ps
CPU time 8.61 seconds
Started Jan 17 12:49:30 PM PST 24
Finished Jan 17 12:49:47 PM PST 24
Peak memory 251184 kb
Host smart-6b615ed2-2f39-4d11-8db4-eab3f5f39c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785062041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2785062041
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3656084385
Short name T352
Test name
Test status
Simulation time 23537357298 ps
CPU time 217.62 seconds
Started Jan 17 12:49:29 PM PST 24
Finished Jan 17 12:53:16 PM PST 24
Peak memory 251196 kb
Host smart-6c5c9a8a-7258-4a67-886e-f6df3b2efdad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656084385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3656084385
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1853778725
Short name T905
Test name
Test status
Simulation time 85382236 ps
CPU time 0.98 seconds
Started Jan 17 12:49:29 PM PST 24
Finished Jan 17 12:49:39 PM PST 24
Peak memory 211520 kb
Host smart-8550320d-4bae-4f84-90e9-32ae8a141706
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853778725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1853778725
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.242266326
Short name T826
Test name
Test status
Simulation time 17470251 ps
CPU time 1.09 seconds
Started Jan 17 12:49:50 PM PST 24
Finished Jan 17 12:50:00 PM PST 24
Peak memory 209576 kb
Host smart-5ada5754-2a4e-4c4a-84c4-1165ca8f4bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242266326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.242266326
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1544990985
Short name T983
Test name
Test status
Simulation time 907828698 ps
CPU time 10.74 seconds
Started Jan 17 12:49:30 PM PST 24
Finished Jan 17 12:49:49 PM PST 24
Peak memory 218084 kb
Host smart-3ae3fb3d-bdb9-41e1-b6c8-7fbfccff8ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544990985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1544990985
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.201181089
Short name T490
Test name
Test status
Simulation time 1392521831 ps
CPU time 8.08 seconds
Started Jan 17 12:49:49 PM PST 24
Finished Jan 17 12:50:07 PM PST 24
Peak memory 209636 kb
Host smart-ff10ba21-a2c5-4261-ab24-12d11d5d757f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201181089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_ac
cess.201181089
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1190778739
Short name T589
Test name
Test status
Simulation time 209747109 ps
CPU time 2.11 seconds
Started Jan 17 12:49:33 PM PST 24
Finished Jan 17 12:49:41 PM PST 24
Peak memory 218144 kb
Host smart-06ccb849-b0eb-44a7-b486-eb1501b6e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190778739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1190778739
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3775036939
Short name T547
Test name
Test status
Simulation time 1562325298 ps
CPU time 18.33 seconds
Started Jan 17 12:49:47 PM PST 24
Finished Jan 17 12:50:17 PM PST 24
Peak memory 218656 kb
Host smart-cbcf7e23-3742-42cd-9ea1-6aa82cb9f760
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775036939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3775036939
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1533171764
Short name T879
Test name
Test status
Simulation time 1652032417 ps
CPU time 7.97 seconds
Started Jan 17 12:49:42 PM PST 24
Finished Jan 17 12:50:07 PM PST 24
Peak memory 218076 kb
Host smart-f6aa48f9-8f3e-47b1-9bb0-f4602fc54741
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533171764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1533171764
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.539382893
Short name T845
Test name
Test status
Simulation time 577771011 ps
CPU time 9.41 seconds
Started Jan 17 12:49:43 PM PST 24
Finished Jan 17 12:50:08 PM PST 24
Peak memory 218132 kb
Host smart-fd3d5792-0732-4c6e-a7df-4703f9b7629a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539382893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.539382893
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.30903735
Short name T74
Test name
Test status
Simulation time 78522511 ps
CPU time 2.6 seconds
Started Jan 17 12:49:40 PM PST 24
Finished Jan 17 12:50:01 PM PST 24
Peak memory 213848 kb
Host smart-c1902094-93e8-41a0-b574-09c8a4b3a6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30903735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.30903735
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.651629204
Short name T467
Test name
Test status
Simulation time 279739095 ps
CPU time 26.12 seconds
Started Jan 17 12:49:40 PM PST 24
Finished Jan 17 12:50:25 PM PST 24
Peak memory 251112 kb
Host smart-31b27cae-e91e-414e-b13d-2877c9caf9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651629204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.651629204
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1495693509
Short name T862
Test name
Test status
Simulation time 78805489 ps
CPU time 7.01 seconds
Started Jan 17 12:49:40 PM PST 24
Finished Jan 17 12:50:06 PM PST 24
Peak memory 250676 kb
Host smart-2781eff1-7526-4409-b209-19822ac1b50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495693509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1495693509
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1248569717
Short name T980
Test name
Test status
Simulation time 739830524 ps
CPU time 15.56 seconds
Started Jan 17 12:49:40 PM PST 24
Finished Jan 17 12:50:14 PM PST 24
Peak memory 226308 kb
Host smart-c776f373-4a81-4722-bed6-b60f0e51d9ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248569717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1248569717
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3366026608
Short name T955
Test name
Test status
Simulation time 46672067 ps
CPU time 0.75 seconds
Started Jan 17 12:49:31 PM PST 24
Finished Jan 17 12:49:40 PM PST 24
Peak memory 207928 kb
Host smart-1ba3a7c4-0bcb-46e4-8ae2-f619cc8fe7a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366026608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3366026608
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1709107231
Short name T76
Test name
Test status
Simulation time 165724171 ps
CPU time 1.03 seconds
Started Jan 17 12:49:44 PM PST 24
Finished Jan 17 12:50:00 PM PST 24
Peak memory 209724 kb
Host smart-e7580575-dc4d-45e3-94b4-0423a9c9fb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709107231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1709107231
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.990124553
Short name T317
Test name
Test status
Simulation time 1391584393 ps
CPU time 10.81 seconds
Started Jan 17 12:49:43 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 218152 kb
Host smart-f8ebc323-5aef-4a73-aea5-f71c8771becb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990124553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.990124553
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.473943707
Short name T805
Test name
Test status
Simulation time 804439441 ps
CPU time 2.88 seconds
Started Jan 17 12:49:51 PM PST 24
Finished Jan 17 12:50:02 PM PST 24
Peak memory 209380 kb
Host smart-e470d504-9615-41fe-91bb-6a233b2ed838
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473943707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_ac
cess.473943707
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.59854816
Short name T777
Test name
Test status
Simulation time 807664313 ps
CPU time 2.95 seconds
Started Jan 17 12:49:45 PM PST 24
Finished Jan 17 12:50:01 PM PST 24
Peak memory 218164 kb
Host smart-2d4cd593-ddf7-40e5-8c78-2a85d0ad8391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59854816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.59854816
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3836292658
Short name T756
Test name
Test status
Simulation time 1777350663 ps
CPU time 17.16 seconds
Started Jan 17 12:49:38 PM PST 24
Finished Jan 17 12:49:56 PM PST 24
Peak memory 219164 kb
Host smart-57fb4b90-5c88-4fdd-bc5f-a1c995ee597e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836292658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3836292658
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1775411352
Short name T902
Test name
Test status
Simulation time 182802905 ps
CPU time 8.45 seconds
Started Jan 17 12:49:40 PM PST 24
Finished Jan 17 12:50:07 PM PST 24
Peak memory 218080 kb
Host smart-a69e21f8-eb65-4c8a-80fe-31f4874eb440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775411352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1775411352
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2361424989
Short name T939
Test name
Test status
Simulation time 1232008168 ps
CPU time 13.87 seconds
Started Jan 17 12:49:51 PM PST 24
Finished Jan 17 12:50:13 PM PST 24
Peak memory 217820 kb
Host smart-a2fb3c95-5164-4d5a-a052-61978490e29a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361424989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2361424989
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3969981278
Short name T415
Test name
Test status
Simulation time 257967497 ps
CPU time 10.91 seconds
Started Jan 17 12:49:50 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 218080 kb
Host smart-ea6d5923-83d8-455a-9609-ed396adec99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969981278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3969981278
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3757804685
Short name T599
Test name
Test status
Simulation time 301662370 ps
CPU time 9 seconds
Started Jan 17 12:49:44 PM PST 24
Finished Jan 17 12:50:07 PM PST 24
Peak memory 214552 kb
Host smart-2f9c7fcc-f6ca-43e1-8e49-a37ea3ec8aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757804685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3757804685
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1526650667
Short name T509
Test name
Test status
Simulation time 289447827 ps
CPU time 33.81 seconds
Started Jan 17 12:49:37 PM PST 24
Finished Jan 17 12:50:13 PM PST 24
Peak memory 251424 kb
Host smart-8f4f3007-f893-4ba5-b686-39e493f84ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526650667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1526650667
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1609697462
Short name T759
Test name
Test status
Simulation time 115293746 ps
CPU time 10.69 seconds
Started Jan 17 12:49:47 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 251176 kb
Host smart-e311692c-9933-4fe8-bcf3-742839deefcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609697462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1609697462
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.679409490
Short name T636
Test name
Test status
Simulation time 9032487363 ps
CPU time 141.41 seconds
Started Jan 17 12:49:46 PM PST 24
Finished Jan 17 12:52:20 PM PST 24
Peak memory 272760 kb
Host smart-d0ec0551-640b-4004-bac3-feab4d6b75d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679409490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.679409490
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1845792559
Short name T769
Test name
Test status
Simulation time 11992598 ps
CPU time 0.96 seconds
Started Jan 17 12:49:50 PM PST 24
Finished Jan 17 12:49:59 PM PST 24
Peak memory 208556 kb
Host smart-a1e17fa1-14a8-4f3b-8496-0b0e15344789
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845792559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1845792559
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.129491434
Short name T341
Test name
Test status
Simulation time 19183541 ps
CPU time 0.92 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:12 PM PST 24
Peak memory 209692 kb
Host smart-bdf0bdde-bbcc-4272-a58a-cbc45195434a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129491434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.129491434
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1141846606
Short name T551
Test name
Test status
Simulation time 7691494334 ps
CPU time 12.82 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:50:23 PM PST 24
Peak memory 209712 kb
Host smart-08dae4ae-85e0-42d4-8d18-9c5b43e37eb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141846606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.1141846606
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.932288662
Short name T975
Test name
Test status
Simulation time 77773174 ps
CPU time 2.43 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:13 PM PST 24
Peak memory 218136 kb
Host smart-4c99957f-0dc5-46de-9b49-87f5bb558305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932288662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.932288662
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3213526529
Short name T391
Test name
Test status
Simulation time 582494638 ps
CPU time 14.3 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:50:24 PM PST 24
Peak memory 218488 kb
Host smart-f4fd8deb-24cc-4f03-bb59-84973c742627
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213526529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3213526529
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2305666548
Short name T957
Test name
Test status
Simulation time 1437973080 ps
CPU time 8.6 seconds
Started Jan 17 12:49:58 PM PST 24
Finished Jan 17 12:50:10 PM PST 24
Peak memory 218168 kb
Host smart-d1ab308f-f57c-4c76-a74c-0b63f12fa1d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305666548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2305666548
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4147366857
Short name T574
Test name
Test status
Simulation time 557644698 ps
CPU time 13.41 seconds
Started Jan 17 12:49:58 PM PST 24
Finished Jan 17 12:50:14 PM PST 24
Peak memory 218060 kb
Host smart-1198cead-3a21-467d-94a1-5be4a31c3849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147366857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4147366857
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3760417624
Short name T873
Test name
Test status
Simulation time 753707654 ps
CPU time 10.85 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:19 PM PST 24
Peak memory 218172 kb
Host smart-3590d79f-6737-442e-adda-e8b89fbe8dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760417624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3760417624
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.546520164
Short name T909
Test name
Test status
Simulation time 90728533 ps
CPU time 3.2 seconds
Started Jan 17 12:49:51 PM PST 24
Finished Jan 17 12:50:02 PM PST 24
Peak memory 214524 kb
Host smart-d992b706-851c-472f-a6f7-f213413751a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546520164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.546520164
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3377192266
Short name T860
Test name
Test status
Simulation time 224506800 ps
CPU time 31.02 seconds
Started Jan 17 12:49:40 PM PST 24
Finished Jan 17 12:50:30 PM PST 24
Peak memory 251168 kb
Host smart-59e1c553-75eb-46eb-8f5f-04d4d813c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377192266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3377192266
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.4008981581
Short name T21
Test name
Test status
Simulation time 191199533 ps
CPU time 2.93 seconds
Started Jan 17 12:49:58 PM PST 24
Finished Jan 17 12:50:04 PM PST 24
Peak memory 218192 kb
Host smart-bde49115-09bb-4e6d-8ee1-08113fac3cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008981581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4008981581
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3844907463
Short name T72
Test name
Test status
Simulation time 3263931041 ps
CPU time 80.37 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 276608 kb
Host smart-3aeada78-82a9-4870-8c15-9c47551dfad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844907463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3844907463
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2302443462
Short name T42
Test name
Test status
Simulation time 11121374 ps
CPU time 0.96 seconds
Started Jan 17 12:49:49 PM PST 24
Finished Jan 17 12:50:00 PM PST 24
Peak memory 208324 kb
Host smart-f2897453-c66b-4c15-abda-e746457d133a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302443462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2302443462
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.308367151
Short name T392
Test name
Test status
Simulation time 17779819 ps
CPU time 1.08 seconds
Started Jan 17 01:08:41 PM PST 24
Finished Jan 17 01:08:43 PM PST 24
Peak memory 209676 kb
Host smart-f5015186-dd3d-4c40-b744-5e677743398b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308367151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.308367151
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2429793542
Short name T55
Test name
Test status
Simulation time 272282575 ps
CPU time 9.84 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:18 PM PST 24
Peak memory 218220 kb
Host smart-6a884bb9-f3ab-4afa-8c5e-1389e8dc220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429793542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2429793542
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.916174519
Short name T26
Test name
Test status
Simulation time 720887848 ps
CPU time 3.55 seconds
Started Jan 17 01:29:47 PM PST 24
Finished Jan 17 01:29:56 PM PST 24
Peak memory 209652 kb
Host smart-bb2710eb-7198-4608-b6c2-8af9f47108d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916174519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_ac
cess.916174519
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2511268310
Short name T418
Test name
Test status
Simulation time 28374419 ps
CPU time 2.18 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:13 PM PST 24
Peak memory 218188 kb
Host smart-b14528de-4ddc-42e7-9bf3-c590b1ea7892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511268310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2511268310
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3901604836
Short name T320
Test name
Test status
Simulation time 588231680 ps
CPU time 13.02 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:50:23 PM PST 24
Peak memory 218188 kb
Host smart-26a956ff-744a-4592-818a-6348ed06365f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901604836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3901604836
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.948738807
Short name T968
Test name
Test status
Simulation time 2530081899 ps
CPU time 14.19 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:23 PM PST 24
Peak memory 218112 kb
Host smart-2f828135-38fc-4ac4-8ab3-20c0d433cb7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948738807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.948738807
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1445412300
Short name T571
Test name
Test status
Simulation time 266185677 ps
CPU time 8.98 seconds
Started Jan 17 01:02:00 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 218180 kb
Host smart-09bd3def-615a-4201-910d-73fdc374ab21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445412300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1445412300
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.311840973
Short name T590
Test name
Test status
Simulation time 56293907 ps
CPU time 2.82 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:15 PM PST 24
Peak memory 214388 kb
Host smart-48d708eb-7d29-4df0-a179-26806cbfdd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311840973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.311840973
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1665556257
Short name T721
Test name
Test status
Simulation time 1105066149 ps
CPU time 23.18 seconds
Started Jan 17 12:49:57 PM PST 24
Finished Jan 17 12:50:22 PM PST 24
Peak memory 251120 kb
Host smart-a1d14ab2-f93e-4b91-adf6-3137ff44e9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665556257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1665556257
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.934327888
Short name T436
Test name
Test status
Simulation time 560521513 ps
CPU time 8.08 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:19 PM PST 24
Peak memory 251148 kb
Host smart-c27c9148-148d-4bdb-9cd7-d9d791c64dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934327888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.934327888
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1879339458
Short name T95
Test name
Test status
Simulation time 6674462516 ps
CPU time 59.26 seconds
Started Jan 17 01:02:53 PM PST 24
Finished Jan 17 01:03:53 PM PST 24
Peak memory 277104 kb
Host smart-86dc2906-a023-4e3a-9847-0a454381e810
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879339458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1879339458
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2741147963
Short name T556
Test name
Test status
Simulation time 15245674 ps
CPU time 0.94 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:50:12 PM PST 24
Peak memory 208168 kb
Host smart-6bb4815d-4e59-409e-b6e7-695fbbd68545
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741147963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2741147963
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1594184686
Short name T619
Test name
Test status
Simulation time 22099063 ps
CPU time 1.2 seconds
Started Jan 17 01:08:42 PM PST 24
Finished Jan 17 01:08:44 PM PST 24
Peak memory 208424 kb
Host smart-9b846e5d-4608-4b51-a77d-fa051d5aee49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594184686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1594184686
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1848074340
Short name T54
Test name
Test status
Simulation time 1066039313 ps
CPU time 12.28 seconds
Started Jan 17 01:18:12 PM PST 24
Finished Jan 17 01:18:26 PM PST 24
Peak memory 218188 kb
Host smart-e5dc9a58-e34b-48dd-8153-5a5061d63116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848074340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1848074340
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2424054559
Short name T935
Test name
Test status
Simulation time 357431222 ps
CPU time 4.56 seconds
Started Jan 17 12:50:15 PM PST 24
Finished Jan 17 12:50:29 PM PST 24
Peak memory 209632 kb
Host smart-aa6ffd35-7e92-4755-bd4e-f566032c6f78
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424054559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_a
ccess.2424054559
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1531249998
Short name T843
Test name
Test status
Simulation time 98951758 ps
CPU time 3.06 seconds
Started Jan 17 12:59:13 PM PST 24
Finished Jan 17 12:59:19 PM PST 24
Peak memory 218148 kb
Host smart-3e14e90b-8e17-48be-9e43-4b0763165529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531249998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1531249998
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3792763734
Short name T753
Test name
Test status
Simulation time 607988159 ps
CPU time 16.48 seconds
Started Jan 17 01:27:03 PM PST 24
Finished Jan 17 01:27:22 PM PST 24
Peak memory 218156 kb
Host smart-0b146d51-063c-4aaa-a854-5d5b9dbcabe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792763734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3792763734
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2423669631
Short name T740
Test name
Test status
Simulation time 1658170390 ps
CPU time 7.26 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:06:28 PM PST 24
Peak memory 218140 kb
Host smart-2ee29c51-dee2-4771-937c-3abf62766a48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423669631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2423669631
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.229603880
Short name T681
Test name
Test status
Simulation time 792259315 ps
CPU time 8.59 seconds
Started Jan 17 01:08:45 PM PST 24
Finished Jan 17 01:08:54 PM PST 24
Peak memory 218248 kb
Host smart-23e9a4b6-b5fd-404c-b24a-509f1412c42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229603880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.229603880
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2934947708
Short name T832
Test name
Test status
Simulation time 58947600 ps
CPU time 3.04 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:50:25 PM PST 24
Peak memory 214176 kb
Host smart-073bd6ed-e3b6-43cf-9826-3b67869104c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934947708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2934947708
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1291871901
Short name T938
Test name
Test status
Simulation time 60259310 ps
CPU time 6.27 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:18 PM PST 24
Peak memory 246784 kb
Host smart-aa95d585-02ec-4f5c-983f-897ce6836f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291871901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1291871901
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3174186935
Short name T396
Test name
Test status
Simulation time 2549092721 ps
CPU time 57.03 seconds
Started Jan 17 02:00:11 PM PST 24
Finished Jan 17 02:01:09 PM PST 24
Peak memory 251204 kb
Host smart-ea8a2df4-ea32-41f1-bb60-739be0255b7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174186935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3174186935
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3273545540
Short name T118
Test name
Test status
Simulation time 77271557890 ps
CPU time 2474.97 seconds
Started Jan 17 12:52:20 PM PST 24
Finished Jan 17 01:33:43 PM PST 24
Peak memory 1537308 kb
Host smart-95e549a8-9423-4713-88db-b7ab937423b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3273545540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3273545540
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.4056037608
Short name T743
Test name
Test status
Simulation time 22454251 ps
CPU time 0.9 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 209684 kb
Host smart-a97b0c77-b8d0-432f-ae95-3b1eb7ea6417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056037608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.4056037608
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2231550239
Short name T667
Test name
Test status
Simulation time 1104504608 ps
CPU time 14.9 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 218248 kb
Host smart-fb07ecfd-b609-49e6-b3a6-d71edad107b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231550239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2231550239
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.4105425492
Short name T842
Test name
Test status
Simulation time 229948880 ps
CPU time 2.22 seconds
Started Jan 17 12:50:01 PM PST 24
Finished Jan 17 12:50:05 PM PST 24
Peak memory 209748 kb
Host smart-27510470-13f8-4df4-91ec-013bcd873d4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105425492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_a
ccess.4105425492
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.26076218
Short name T825
Test name
Test status
Simulation time 101865942 ps
CPU time 3.91 seconds
Started Jan 17 01:42:11 PM PST 24
Finished Jan 17 01:42:16 PM PST 24
Peak memory 218200 kb
Host smart-fe00c034-45ec-42b9-8715-392798ec3250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26076218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.26076218
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3418818962
Short name T948
Test name
Test status
Simulation time 1861532690 ps
CPU time 17.25 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:28 PM PST 24
Peak memory 219196 kb
Host smart-72efb94e-99dd-4d89-b972-dcfaa4bb2770
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418818962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3418818962
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3722588218
Short name T898
Test name
Test status
Simulation time 411815955 ps
CPU time 8.49 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:19 PM PST 24
Peak memory 217956 kb
Host smart-6b7f2e14-a221-43f3-8f29-3a197c8f6fd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722588218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3722588218
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.677679416
Short name T453
Test name
Test status
Simulation time 390942965 ps
CPU time 13.7 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:22 PM PST 24
Peak memory 218096 kb
Host smart-adfff099-2a94-415a-b66a-26e05e434158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677679416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.677679416
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2384936650
Short name T644
Test name
Test status
Simulation time 451615935 ps
CPU time 14.42 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:22 PM PST 24
Peak memory 218128 kb
Host smart-d7ace850-820a-4d72-a572-fcf6da4b7f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384936650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2384936650
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.302111320
Short name T880
Test name
Test status
Simulation time 65672762 ps
CPU time 4.91 seconds
Started Jan 17 12:57:11 PM PST 24
Finished Jan 17 12:57:18 PM PST 24
Peak memory 214228 kb
Host smart-6f530534-1db9-403b-b42f-10fb24df9fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302111320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.302111320
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3142831276
Short name T483
Test name
Test status
Simulation time 460966292 ps
CPU time 36.2 seconds
Started Jan 17 01:21:20 PM PST 24
Finished Jan 17 01:21:57 PM PST 24
Peak memory 251144 kb
Host smart-c01a88d9-e91b-4cbe-a89e-d66d78587bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142831276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3142831276
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2602407767
Short name T537
Test name
Test status
Simulation time 61598524 ps
CPU time 7.29 seconds
Started Jan 17 12:53:56 PM PST 24
Finished Jan 17 12:54:04 PM PST 24
Peak memory 251164 kb
Host smart-370ecea5-4df5-4a20-bfad-ed02df9e646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602407767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2602407767
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.4059310246
Short name T62
Test name
Test status
Simulation time 24056424759 ps
CPU time 760.66 seconds
Started Jan 17 12:50:01 PM PST 24
Finished Jan 17 01:02:43 PM PST 24
Peak memory 251252 kb
Host smart-f90f3990-7127-43ef-bc01-99bc60972610
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059310246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.4059310246
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.4063568306
Short name T119
Test name
Test status
Simulation time 16985153219 ps
CPU time 499.76 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:58:29 PM PST 24
Peak memory 267752 kb
Host smart-1ff6392f-0b7e-4fb4-9226-ccbf4580c70c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4063568306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.4063568306
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1416076890
Short name T894
Test name
Test status
Simulation time 13747872 ps
CPU time 0.98 seconds
Started Jan 17 01:22:35 PM PST 24
Finished Jan 17 01:22:38 PM PST 24
Peak memory 211456 kb
Host smart-5cca81fc-c7c4-46d9-adca-72a890599317
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416076890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1416076890
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3881896778
Short name T698
Test name
Test status
Simulation time 115858182 ps
CPU time 1.47 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 209652 kb
Host smart-97ecf826-7d13-4932-ab95-be36c23c6fb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881896778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3881896778
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1623343599
Short name T364
Test name
Test status
Simulation time 769439504 ps
CPU time 11.2 seconds
Started Jan 17 12:50:03 PM PST 24
Finished Jan 17 12:50:17 PM PST 24
Peak memory 218204 kb
Host smart-4c2431b5-cf31-4477-9d36-9897eaa1950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623343599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1623343599
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2562466809
Short name T9
Test name
Test status
Simulation time 266077500 ps
CPU time 4.16 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:15 PM PST 24
Peak memory 209648 kb
Host smart-a5c5249a-9443-4cc2-b38f-69955409d12a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562466809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.2562466809
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.80580304
Short name T886
Test name
Test status
Simulation time 369249816 ps
CPU time 3.73 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:12 PM PST 24
Peak memory 218180 kb
Host smart-6fc6a73e-5f80-4beb-86c1-c62f690f2a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80580304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.80580304
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.119211214
Short name T321
Test name
Test status
Simulation time 2731858404 ps
CPU time 16.4 seconds
Started Jan 17 12:58:21 PM PST 24
Finished Jan 17 12:58:38 PM PST 24
Peak memory 219332 kb
Host smart-f4897edb-57db-40b8-b42e-701e23e8b8aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119211214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.119211214
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.357561879
Short name T673
Test name
Test status
Simulation time 865349588 ps
CPU time 11.81 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:35 PM PST 24
Peak memory 218128 kb
Host smart-0458033f-ada7-4314-bf8c-230efe11462e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357561879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.357561879
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3169310439
Short name T47
Test name
Test status
Simulation time 429604939 ps
CPU time 7.77 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:50:19 PM PST 24
Peak memory 218188 kb
Host smart-7aceaad0-9dc5-4f9b-a167-5d3816ed1c4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169310439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3169310439
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1114333930
Short name T182
Test name
Test status
Simulation time 987635619 ps
CPU time 7.35 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:50:31 PM PST 24
Peak memory 218192 kb
Host smart-cdaaaea4-8b3b-427c-8c30-c69793eb3eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114333930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1114333930
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3798257065
Short name T531
Test name
Test status
Simulation time 48909095 ps
CPU time 1.7 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:12 PM PST 24
Peak memory 217852 kb
Host smart-ffa11afe-0642-46d6-897f-94546f65d45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798257065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3798257065
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.902869515
Short name T959
Test name
Test status
Simulation time 183221927 ps
CPU time 24.5 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:50:34 PM PST 24
Peak memory 251056 kb
Host smart-9394f5b4-e465-40e5-83c6-dc547f9329aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902869515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.902869515
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.691706168
Short name T701
Test name
Test status
Simulation time 71450259 ps
CPU time 7.18 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:50:32 PM PST 24
Peak memory 251176 kb
Host smart-553b4015-d7dd-4cb9-ac61-8a5c923ddde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691706168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.691706168
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2379400878
Short name T974
Test name
Test status
Simulation time 3790977334 ps
CPU time 79.53 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:51:43 PM PST 24
Peak memory 268076 kb
Host smart-805b566a-009b-4ac7-a216-177342537776
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379400878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2379400878
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.695554335
Short name T514
Test name
Test status
Simulation time 12271208 ps
CPU time 0.77 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:12 PM PST 24
Peak memory 208100 kb
Host smart-cc63bfa8-4733-4572-aa67-b676381111be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695554335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.695554335
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2547971985
Short name T738
Test name
Test status
Simulation time 35236312 ps
CPU time 1.06 seconds
Started Jan 17 12:50:03 PM PST 24
Finished Jan 17 12:50:06 PM PST 24
Peak memory 209592 kb
Host smart-b8574ae2-a6dd-4592-b58c-5073f46fa7ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547971985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2547971985
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.4147148463
Short name T634
Test name
Test status
Simulation time 4712106922 ps
CPU time 17.33 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:50:27 PM PST 24
Peak memory 217404 kb
Host smart-3aa439c0-f405-4622-a991-d0b50b9fe908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147148463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4147148463
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1153802972
Short name T23
Test name
Test status
Simulation time 875113968 ps
CPU time 2.39 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:50:13 PM PST 24
Peak memory 209764 kb
Host smart-efb8b6df-06ad-47cd-a0c4-b733c1ffb242
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153802972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_a
ccess.1153802972
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2824988262
Short name T730
Test name
Test status
Simulation time 41604422 ps
CPU time 1.88 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:13 PM PST 24
Peak memory 218088 kb
Host smart-1ca95159-fa92-4e87-a300-ac5cced403b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824988262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2824988262
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.121933723
Short name T784
Test name
Test status
Simulation time 906294275 ps
CPU time 11.82 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:22 PM PST 24
Peak memory 218184 kb
Host smart-3096065e-1d54-4ce4-9afc-d92a5ef5267a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121933723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.121933723
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1211165484
Short name T914
Test name
Test status
Simulation time 318486094 ps
CPU time 12.41 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:50:23 PM PST 24
Peak memory 216988 kb
Host smart-48e307ab-2e63-445d-9209-60c1c87328b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211165484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1211165484
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4097951200
Short name T904
Test name
Test status
Simulation time 736596811 ps
CPU time 11.29 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:22 PM PST 24
Peak memory 218108 kb
Host smart-4f8e094b-7b90-4287-90a8-9e4e09683f09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097951200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4097951200
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2692957317
Short name T584
Test name
Test status
Simulation time 949118422 ps
CPU time 7.4 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:50:19 PM PST 24
Peak memory 218180 kb
Host smart-8237c25a-9c5a-4db6-a9c9-a8884e1cbcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692957317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2692957317
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3593705421
Short name T949
Test name
Test status
Simulation time 1083465055 ps
CPU time 6.51 seconds
Started Jan 17 01:34:59 PM PST 24
Finished Jan 17 01:35:06 PM PST 24
Peak memory 214624 kb
Host smart-22518c7a-4771-4ef3-a528-d949ed9f3e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593705421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3593705421
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3103901208
Short name T300
Test name
Test status
Simulation time 1400969013 ps
CPU time 31.15 seconds
Started Jan 17 01:17:48 PM PST 24
Finished Jan 17 01:18:21 PM PST 24
Peak memory 251116 kb
Host smart-6744e889-0323-46ca-9a97-82c82066407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103901208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3103901208
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1358926752
Short name T557
Test name
Test status
Simulation time 294109147 ps
CPU time 7.09 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:50:17 PM PST 24
Peak memory 251052 kb
Host smart-107c3729-41f7-4cd7-9644-8342f720957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358926752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1358926752
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.46922021
Short name T732
Test name
Test status
Simulation time 7747752248 ps
CPU time 309.74 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:55:21 PM PST 24
Peak memory 284248 kb
Host smart-328b74f4-e287-4378-ac93-3d106c6158f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46922021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.lc_ctrl_stress_all.46922021
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2891777149
Short name T807
Test name
Test status
Simulation time 29297866 ps
CPU time 0.84 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:13 PM PST 24
Peak memory 208112 kb
Host smart-7fabb204-b926-42e2-a90b-f3620f98823f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891777149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2891777149
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1666252190
Short name T689
Test name
Test status
Simulation time 14838376 ps
CPU time 1.05 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 209700 kb
Host smart-f23ec6cd-0ab4-491d-9661-2790e8a2fc77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666252190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1666252190
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3204353716
Short name T857
Test name
Test status
Simulation time 14123656 ps
CPU time 1.01 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:48:23 PM PST 24
Peak memory 209612 kb
Host smart-b35f1be7-1359-46c6-9cfc-7c9a8f834f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204353716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3204353716
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2764303472
Short name T688
Test name
Test status
Simulation time 272285761 ps
CPU time 12.09 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 217540 kb
Host smart-efbbbb89-6e63-453d-8cd3-293a21114673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764303472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2764303472
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.985614909
Short name T25
Test name
Test status
Simulation time 515869015 ps
CPU time 13.19 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 209416 kb
Host smart-f62aed26-cb00-480d-be2b-d0231cea1adc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985614909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_acc
ess.985614909
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1184645732
Short name T831
Test name
Test status
Simulation time 1731296071 ps
CPU time 24.84 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:36 PM PST 24
Peak memory 218056 kb
Host smart-1077df10-d905-4c87-9a80-4a11847a1e8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184645732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1184645732
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1580088323
Short name T675
Test name
Test status
Simulation time 390316043 ps
CPU time 4.87 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:23 PM PST 24
Peak memory 209700 kb
Host smart-3b0761c5-ff10-4fd0-ac77-30fb300f4c3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580088323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.1580088323
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1574506303
Short name T716
Test name
Test status
Simulation time 1299207455 ps
CPU time 11.93 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:14 PM PST 24
Peak memory 218080 kb
Host smart-dae54da7-c1ad-4e0e-b5d1-3400ef143d89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574506303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1574506303
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.721951846
Short name T79
Test name
Test status
Simulation time 5547409968 ps
CPU time 20.1 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:38 PM PST 24
Peak memory 213912 kb
Host smart-c8317932-f3a1-4a1e-9e05-a86280085e04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721951846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.721951846
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3513139674
Short name T928
Test name
Test status
Simulation time 645017561 ps
CPU time 7.69 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:25 PM PST 24
Peak memory 213456 kb
Host smart-22d48b2e-c6ee-434f-bc1f-9d08debfb79c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513139674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3513139674
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.230478867
Short name T2
Test name
Test status
Simulation time 2989099103 ps
CPU time 60.68 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:49:09 PM PST 24
Peak memory 255004 kb
Host smart-407c4048-48fc-4d78-a29f-13b960b70ff2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230478867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.230478867
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4112193894
Short name T942
Test name
Test status
Simulation time 706495859 ps
CPU time 11.68 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 222608 kb
Host smart-f9c65d2c-e527-4bc9-99c2-a4bdad113ca6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112193894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.4112193894
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2817510134
Short name T800
Test name
Test status
Simulation time 412763778 ps
CPU time 2.81 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:14 PM PST 24
Peak memory 218120 kb
Host smart-d0fa58de-8f20-4e63-ae44-df4262f6004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817510134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2817510134
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1090042218
Short name T82
Test name
Test status
Simulation time 157755333 ps
CPU time 10.41 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:27 PM PST 24
Peak memory 214028 kb
Host smart-9946e5da-2772-4a9e-bc2a-d9ab6aa2cac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090042218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1090042218
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1934962678
Short name T868
Test name
Test status
Simulation time 318385761 ps
CPU time 11.39 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 218164 kb
Host smart-11e923f9-f375-4266-aeeb-5a59a8d763cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934962678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1934962678
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1801617858
Short name T899
Test name
Test status
Simulation time 1719505026 ps
CPU time 14.57 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:25 PM PST 24
Peak memory 218104 kb
Host smart-da95b54d-8ef0-4707-b56e-f0407ed04d83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801617858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1801617858
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.803121190
Short name T345
Test name
Test status
Simulation time 1577232864 ps
CPU time 10.5 seconds
Started Jan 17 12:47:56 PM PST 24
Finished Jan 17 12:48:07 PM PST 24
Peak memory 218092 kb
Host smart-7119223e-2e08-4bc5-8e0c-efba18c793b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803121190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.803121190
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3678959409
Short name T601
Test name
Test status
Simulation time 3024784953 ps
CPU time 7.58 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:26 PM PST 24
Peak memory 218056 kb
Host smart-8ab29c41-5cea-4e5c-bb65-cdd1ed290c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678959409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3678959409
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4170845893
Short name T979
Test name
Test status
Simulation time 103285240 ps
CPU time 1.7 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:12 PM PST 24
Peak memory 213816 kb
Host smart-2ac04f9b-cc1a-4178-951b-0d2a48b66505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170845893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4170845893
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2498441847
Short name T385
Test name
Test status
Simulation time 259995286 ps
CPU time 25.99 seconds
Started Jan 17 12:48:06 PM PST 24
Finished Jan 17 12:48:34 PM PST 24
Peak memory 251084 kb
Host smart-366ebe41-1cf3-4388-b351-9750e27d10a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498441847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2498441847
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3641803988
Short name T820
Test name
Test status
Simulation time 46192081 ps
CPU time 5.92 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:25 PM PST 24
Peak memory 245772 kb
Host smart-85a74c15-0cb9-4cb1-8e9c-29059592833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641803988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3641803988
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1164896756
Short name T329
Test name
Test status
Simulation time 1188830595 ps
CPU time 38.44 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:39 PM PST 24
Peak memory 247036 kb
Host smart-be048801-27cb-4d76-ac56-65a913d5b043
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164896756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1164896756
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2379450515
Short name T316
Test name
Test status
Simulation time 10501819 ps
CPU time 0.95 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:20 PM PST 24
Peak memory 207928 kb
Host smart-c4c29739-11a5-4902-a005-6e03aa9fb8d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379450515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2379450515
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.242607668
Short name T83
Test name
Test status
Simulation time 29222307 ps
CPU time 1.13 seconds
Started Jan 17 12:48:06 PM PST 24
Finished Jan 17 12:48:10 PM PST 24
Peak memory 209624 kb
Host smart-58ca7383-7939-4e5d-b4f1-f8128305521e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242607668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.242607668
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2337816758
Short name T525
Test name
Test status
Simulation time 29049371 ps
CPU time 0.9 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 208164 kb
Host smart-ca405111-a8ae-4864-80c6-1224be595981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337816758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2337816758
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3829328406
Short name T583
Test name
Test status
Simulation time 659065111 ps
CPU time 12.81 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:24 PM PST 24
Peak memory 218116 kb
Host smart-15dd29c3-9cca-4105-ad6f-0129996b9211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829328406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3829328406
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2749229429
Short name T24
Test name
Test status
Simulation time 410349364 ps
CPU time 3.37 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:14 PM PST 24
Peak memory 209640 kb
Host smart-1b757c74-1726-4f1f-873a-ed1f4022e527
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749229429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.2749229429
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2775894522
Short name T837
Test name
Test status
Simulation time 3152326006 ps
CPU time 45.65 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:49 PM PST 24
Peak memory 218176 kb
Host smart-69a70cda-955b-449f-a3fc-c949e92098b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775894522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2775894522
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2502859458
Short name T438
Test name
Test status
Simulation time 205951234 ps
CPU time 3.3 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:05 PM PST 24
Peak memory 209708 kb
Host smart-6d3737d1-d369-4736-88ee-1703ee816fff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502859458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.2502859458
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3411424466
Short name T734
Test name
Test status
Simulation time 101638720 ps
CPU time 2.74 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:03 PM PST 24
Peak memory 218268 kb
Host smart-ae4204d6-ec9f-4a45-8195-3b16cfd9d690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411424466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3411424466
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1758024977
Short name T793
Test name
Test status
Simulation time 1082960343 ps
CPU time 16.22 seconds
Started Jan 17 12:48:06 PM PST 24
Finished Jan 17 12:48:25 PM PST 24
Peak memory 212836 kb
Host smart-bba12966-74c1-4a10-9d21-c15d94cd2a26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758024977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1758024977
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.647910134
Short name T430
Test name
Test status
Simulation time 815382169 ps
CPU time 3.97 seconds
Started Jan 17 12:48:02 PM PST 24
Finished Jan 17 12:48:10 PM PST 24
Peak memory 213128 kb
Host smart-b2eaa91f-4546-43cb-bb8e-274d40ccc0b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647910134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.647910134
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3855348610
Short name T423
Test name
Test status
Simulation time 2585896259 ps
CPU time 49.35 seconds
Started Jan 17 12:47:59 PM PST 24
Finished Jan 17 12:48:50 PM PST 24
Peak memory 267892 kb
Host smart-4c07f398-dddc-41a2-830e-bcf39c80f7d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855348610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3855348610
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.976217638
Short name T870
Test name
Test status
Simulation time 3852532836 ps
CPU time 26.48 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:37 PM PST 24
Peak memory 251232 kb
Host smart-72a41cde-c12c-4443-a042-1f95ef4c3a12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976217638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.976217638
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2447373627
Short name T971
Test name
Test status
Simulation time 47404397 ps
CPU time 2.47 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:14 PM PST 24
Peak memory 218164 kb
Host smart-e33187cf-0dba-469d-8e24-cc09e5deeb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447373627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2447373627
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1823611263
Short name T86
Test name
Test status
Simulation time 378018965 ps
CPU time 22.73 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:34 PM PST 24
Peak memory 214340 kb
Host smart-01b02b55-2bd6-4105-8759-dd77c3292db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823611263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1823611263
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.992397799
Short name T332
Test name
Test status
Simulation time 923286432 ps
CPU time 9.75 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:12 PM PST 24
Peak memory 218184 kb
Host smart-d7cefe39-15d4-4dc2-a2c8-38bf11ddb752
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992397799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.992397799
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3890961522
Short name T382
Test name
Test status
Simulation time 579449121 ps
CPU time 11.16 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 218100 kb
Host smart-d15b6938-6fe2-45c1-bef0-9e6bde0874f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890961522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3890961522
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2244257926
Short name T426
Test name
Test status
Simulation time 1211172601 ps
CPU time 8.8 seconds
Started Jan 17 12:48:02 PM PST 24
Finished Jan 17 12:48:15 PM PST 24
Peak memory 218100 kb
Host smart-0ce57ef3-4563-4f35-b8da-ba39c1216613
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244257926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
244257926
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1142245510
Short name T941
Test name
Test status
Simulation time 697996922 ps
CPU time 13.92 seconds
Started Jan 17 12:47:51 PM PST 24
Finished Jan 17 12:48:08 PM PST 24
Peak memory 218172 kb
Host smart-039ce56a-72c1-4e16-a8d9-9be7684993c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142245510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1142245510
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3804694294
Short name T479
Test name
Test status
Simulation time 105440691 ps
CPU time 2.28 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:14 PM PST 24
Peak memory 214036 kb
Host smart-3b90edd6-ff12-4806-b7b8-5117a7160cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804694294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3804694294
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.132975700
Short name T616
Test name
Test status
Simulation time 1168572279 ps
CPU time 20.69 seconds
Started Jan 17 12:48:00 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 251080 kb
Host smart-de1c1441-cffe-415c-87a5-c66b4ffaf3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132975700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.132975700
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3486602709
Short name T358
Test name
Test status
Simulation time 209437772 ps
CPU time 3.58 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:14 PM PST 24
Peak memory 222060 kb
Host smart-649fd152-c20e-4457-8f54-0a0381b6cdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486602709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3486602709
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.700499956
Short name T572
Test name
Test status
Simulation time 15880051808 ps
CPU time 53.25 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:49:01 PM PST 24
Peak memory 251276 kb
Host smart-3e3a6579-2056-4531-89e2-24dbf0dda81c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700499956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.700499956
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.974914554
Short name T779
Test name
Test status
Simulation time 31412764 ps
CPU time 0.78 seconds
Started Jan 17 12:48:02 PM PST 24
Finished Jan 17 12:48:07 PM PST 24
Peak memory 208380 kb
Host smart-fac82e47-d16d-45ba-8483-01c10ac6028f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974914554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.974914554
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2860620631
Short name T335
Test name
Test status
Simulation time 43166079 ps
CPU time 0.93 seconds
Started Jan 17 12:48:18 PM PST 24
Finished Jan 17 12:48:21 PM PST 24
Peak memory 209584 kb
Host smart-66e53aa4-945e-4064-84bc-a9efdc303dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860620631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2860620631
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2969418250
Short name T179
Test name
Test status
Simulation time 45256932 ps
CPU time 0.78 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:18 PM PST 24
Peak memory 209396 kb
Host smart-13487961-7cc0-4dd7-8ef8-9cbe1fc90137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969418250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2969418250
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3284682959
Short name T923
Test name
Test status
Simulation time 505095868 ps
CPU time 11.33 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 218180 kb
Host smart-58e80b72-da10-40df-b712-099ebe899cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284682959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3284682959
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1350937808
Short name T612
Test name
Test status
Simulation time 266251700 ps
CPU time 7.3 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:48:15 PM PST 24
Peak memory 209704 kb
Host smart-e840f39f-8392-4b55-a28d-cff34a8f3c79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350937808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.1350937808
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1469864649
Short name T359
Test name
Test status
Simulation time 1860946008 ps
CPU time 28.45 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:47 PM PST 24
Peak memory 218100 kb
Host smart-43207138-3146-4d8c-87f0-f7d9655a8867
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469864649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1469864649
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3771838234
Short name T639
Test name
Test status
Simulation time 125656405 ps
CPU time 3.6 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 217904 kb
Host smart-3bafd75a-1544-4787-a90d-94db6f27f49e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771838234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.3771838234
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.163911874
Short name T687
Test name
Test status
Simulation time 456208108 ps
CPU time 13 seconds
Started Jan 17 12:48:11 PM PST 24
Finished Jan 17 12:48:27 PM PST 24
Peak memory 218132 kb
Host smart-6368d3ba-0f89-4a3b-b1c8-b95d3512fc14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163911874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.163911874
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3028171359
Short name T16
Test name
Test status
Simulation time 786950968 ps
CPU time 13.03 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:24 PM PST 24
Peak memory 213072 kb
Host smart-9e08f585-e63c-4049-8bad-25f4d1bae593
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028171359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3028171359
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2864380752
Short name T77
Test name
Test status
Simulation time 478479160 ps
CPU time 3.87 seconds
Started Jan 17 12:48:09 PM PST 24
Finished Jan 17 12:48:15 PM PST 24
Peak memory 213224 kb
Host smart-ef679c30-7921-4da3-95ac-d22d9f7c5515
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864380752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2864380752
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.4256011312
Short name T746
Test name
Test status
Simulation time 5579958802 ps
CPU time 38.29 seconds
Started Jan 17 12:48:11 PM PST 24
Finished Jan 17 12:48:51 PM PST 24
Peak memory 277432 kb
Host smart-fdab2acc-68ca-41a8-a14a-9f46fa51584f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256011312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.4256011312
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.526734708
Short name T872
Test name
Test status
Simulation time 563684437 ps
CPU time 13.03 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 251004 kb
Host smart-4ec0860d-e966-4afe-a259-261dda5cefb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526734708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.526734708
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.277614002
Short name T645
Test name
Test status
Simulation time 66228692 ps
CPU time 1.52 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:18 PM PST 24
Peak memory 218172 kb
Host smart-b0f2b9e1-1342-4fc3-aef4-99d53f2e590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277614002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.277614002
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3626884189
Short name T478
Test name
Test status
Simulation time 252459236 ps
CPU time 6.86 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:48:15 PM PST 24
Peak memory 213988 kb
Host smart-e022150b-3c7b-4700-a7a7-3b34d78a5495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626884189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3626884189
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2836444729
Short name T699
Test name
Test status
Simulation time 294274530 ps
CPU time 12.52 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:48:20 PM PST 24
Peak memory 218240 kb
Host smart-59a9672e-2166-4ad4-afe8-049f082276c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836444729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2836444729
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1583920513
Short name T515
Test name
Test status
Simulation time 3248280286 ps
CPU time 11.02 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 218160 kb
Host smart-1d6480f0-8104-4400-b164-7a6deadbeab3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583920513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1583920513
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1580386142
Short name T652
Test name
Test status
Simulation time 3700793569 ps
CPU time 11.7 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:29 PM PST 24
Peak memory 218160 kb
Host smart-3e49dea1-8c92-4f8b-9816-c7085d045f31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580386142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
580386142
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.41591936
Short name T660
Test name
Test status
Simulation time 330094818 ps
CPU time 11.8 seconds
Started Jan 17 12:48:03 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 218184 kb
Host smart-bb3f79ca-6110-4005-a07b-7891456cfb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41591936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.41591936
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.633108888
Short name T67
Test name
Test status
Simulation time 121978485 ps
CPU time 2.6 seconds
Started Jan 17 12:47:56 PM PST 24
Finished Jan 17 12:47:59 PM PST 24
Peak memory 214212 kb
Host smart-82c2daab-9d7c-428d-89a7-15c8f334d255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633108888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.633108888
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3125964704
Short name T327
Test name
Test status
Simulation time 250191985 ps
CPU time 23.36 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:35 PM PST 24
Peak memory 250944 kb
Host smart-bef3e967-9af1-4f74-bddb-45f88aa49d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125964704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3125964704
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1566049552
Short name T627
Test name
Test status
Simulation time 483210944 ps
CPU time 8.06 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:23 PM PST 24
Peak memory 251164 kb
Host smart-1b521717-cc9b-406b-930d-28c6abcbf30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566049552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1566049552
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3392006013
Short name T801
Test name
Test status
Simulation time 13825455630 ps
CPU time 252.91 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:52:31 PM PST 24
Peak memory 270928 kb
Host smart-20775684-2f81-4db9-bc9d-62466342d8b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392006013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3392006013
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.204394239
Short name T43
Test name
Test status
Simulation time 16568553 ps
CPU time 1 seconds
Started Jan 17 12:48:05 PM PST 24
Finished Jan 17 12:48:09 PM PST 24
Peak memory 208412 kb
Host smart-9b16367a-e731-4cde-9c67-9ff1e31102a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204394239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.204394239
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1650495831
Short name T943
Test name
Test status
Simulation time 21219083 ps
CPU time 1.18 seconds
Started Jan 17 12:48:01 PM PST 24
Finished Jan 17 12:48:05 PM PST 24
Peak memory 209664 kb
Host smart-ba7d1dc3-fa54-49cd-b722-9b5339924e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650495831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1650495831
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3163848375
Short name T580
Test name
Test status
Simulation time 21732651 ps
CPU time 0.82 seconds
Started Jan 17 12:48:08 PM PST 24
Finished Jan 17 12:48:10 PM PST 24
Peak memory 209392 kb
Host smart-27a40703-3217-4557-b04e-4f342b8ed947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163848375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3163848375
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1623660648
Short name T29
Test name
Test status
Simulation time 995121995 ps
CPU time 9.7 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:48:17 PM PST 24
Peak memory 217852 kb
Host smart-5d74752c-d588-4a6d-88e3-3c837808de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623660648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1623660648
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.756076318
Short name T846
Test name
Test status
Simulation time 645301808 ps
CPU time 2.24 seconds
Started Jan 17 12:48:16 PM PST 24
Finished Jan 17 12:48:22 PM PST 24
Peak memory 209536 kb
Host smart-9b1c87b7-b679-4503-8f6e-319fe0a92937
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756076318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_acc
ess.756076318
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1983323761
Short name T480
Test name
Test status
Simulation time 1302539938 ps
CPU time 22.7 seconds
Started Jan 17 12:48:04 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 217828 kb
Host smart-24a29d3a-e62a-4ec9-8a81-c0b96c80042d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983323761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1983323761
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1936193938
Short name T950
Test name
Test status
Simulation time 665254413 ps
CPU time 4.56 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:23 PM PST 24
Peak memory 217904 kb
Host smart-5285dbaa-a650-4bd1-8961-7a07cdb2f875
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936193938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.1936193938
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2598594624
Short name T920
Test name
Test status
Simulation time 2507899966 ps
CPU time 16.01 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:35 PM PST 24
Peak memory 218184 kb
Host smart-d3230923-0bf8-4c87-bca0-c90901c3916c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598594624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2598594624
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3858769764
Short name T422
Test name
Test status
Simulation time 813704039 ps
CPU time 12.89 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 212916 kb
Host smart-8c8ccc85-722d-4745-8e6f-67ba5fe77d4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858769764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3858769764
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3285318882
Short name T513
Test name
Test status
Simulation time 394026565 ps
CPU time 2.07 seconds
Started Jan 17 12:48:02 PM PST 24
Finished Jan 17 12:48:07 PM PST 24
Peak memory 212796 kb
Host smart-33250ce9-923d-4ef4-8c78-c4acb7d09f7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285318882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3285318882
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3598427218
Short name T367
Test name
Test status
Simulation time 1646603912 ps
CPU time 63.68 seconds
Started Jan 17 12:48:05 PM PST 24
Finished Jan 17 12:49:12 PM PST 24
Peak memory 268540 kb
Host smart-f7ec1a22-c006-4610-8a79-dfc4683872c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598427218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3598427218
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.565092201
Short name T929
Test name
Test status
Simulation time 3579958854 ps
CPU time 18.69 seconds
Started Jan 17 12:48:03 PM PST 24
Finished Jan 17 12:48:26 PM PST 24
Peak memory 250672 kb
Host smart-b5834637-467e-41b1-ac02-4c3fd604abaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565092201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.565092201
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3883644448
Short name T629
Test name
Test status
Simulation time 109588811 ps
CPU time 1.99 seconds
Started Jan 17 12:48:02 PM PST 24
Finished Jan 17 12:48:08 PM PST 24
Peak memory 218064 kb
Host smart-d3f66e4c-facf-4a3d-969b-458e3d58a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883644448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3883644448
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.592063618
Short name T498
Test name
Test status
Simulation time 493019080 ps
CPU time 21.12 seconds
Started Jan 17 12:48:03 PM PST 24
Finished Jan 17 12:48:27 PM PST 24
Peak memory 213672 kb
Host smart-d137db7a-0ac5-4fd7-a011-41dd3444c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592063618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.592063618
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2068389175
Short name T59
Test name
Test status
Simulation time 254442700 ps
CPU time 10.23 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:28 PM PST 24
Peak memory 217996 kb
Host smart-76cbb9b3-dc21-4a14-8d74-0d41accc7ec6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068389175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2068389175
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.956779488
Short name T643
Test name
Test status
Simulation time 761423833 ps
CPU time 9.97 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 218004 kb
Host smart-b0642427-73bc-4da0-acdb-85a973061108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956779488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.956779488
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3934896323
Short name T875
Test name
Test status
Simulation time 829055867 ps
CPU time 7.92 seconds
Started Jan 17 12:48:15 PM PST 24
Finished Jan 17 12:48:27 PM PST 24
Peak memory 218092 kb
Host smart-bf6a810c-44cd-43f1-a63b-e2e012ef6302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934896323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
934896323
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3542010301
Short name T441
Test name
Test status
Simulation time 2864319120 ps
CPU time 13.46 seconds
Started Jan 17 12:48:03 PM PST 24
Finished Jan 17 12:48:20 PM PST 24
Peak memory 218136 kb
Host smart-6cf9e4cf-b9d1-466f-a5a2-89b997edcdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542010301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3542010301
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1369556980
Short name T524
Test name
Test status
Simulation time 85237759 ps
CPU time 1.83 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:23 PM PST 24
Peak memory 213340 kb
Host smart-a4b92a84-bc18-4bc8-8af0-74df7b82dca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369556980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1369556980
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3452972811
Short name T617
Test name
Test status
Simulation time 1678664422 ps
CPU time 34.82 seconds
Started Jan 17 12:48:28 PM PST 24
Finished Jan 17 12:49:04 PM PST 24
Peak memory 250732 kb
Host smart-abe0879a-3924-4545-b43e-ecadee9e5768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452972811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3452972811
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2789236724
Short name T35
Test name
Test status
Simulation time 321904319 ps
CPU time 8.37 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:27 PM PST 24
Peak memory 251052 kb
Host smart-3c77efee-5403-4e61-b33a-ffb6f8c2f681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789236724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2789236724
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.939567424
Short name T91
Test name
Test status
Simulation time 39301657 ps
CPU time 0.89 seconds
Started Jan 17 12:48:13 PM PST 24
Finished Jan 17 12:48:19 PM PST 24
Peak memory 211312 kb
Host smart-9655516f-9b18-4e4e-8e36-331a10c0cb20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939567424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.939567424
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2590563191
Short name T638
Test name
Test status
Simulation time 59273880 ps
CPU time 1.09 seconds
Started Jan 17 12:48:28 PM PST 24
Finished Jan 17 12:48:30 PM PST 24
Peak memory 209688 kb
Host smart-d68f6627-c60a-4024-8816-da2a35f415d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590563191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2590563191
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3923579990
Short name T177
Test name
Test status
Simulation time 12899752 ps
CPU time 0.82 seconds
Started Jan 17 12:48:17 PM PST 24
Finished Jan 17 12:48:21 PM PST 24
Peak memory 209416 kb
Host smart-e2127f70-fc91-4b3e-9102-7e8518e2ac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923579990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3923579990
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1183963787
Short name T861
Test name
Test status
Simulation time 4406113176 ps
CPU time 15.23 seconds
Started Jan 17 12:48:15 PM PST 24
Finished Jan 17 12:48:34 PM PST 24
Peak memory 218256 kb
Host smart-19510e50-197e-4911-92bd-5c69c9b5ae96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183963787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1183963787
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.603168634
Short name T890
Test name
Test status
Simulation time 1874116848 ps
CPU time 4.8 seconds
Started Jan 17 12:48:16 PM PST 24
Finished Jan 17 12:48:24 PM PST 24
Peak memory 209560 kb
Host smart-35fb7d1c-acd6-4754-99db-fcb46dcf92af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603168634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_acc
ess.603168634
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4131282815
Short name T401
Test name
Test status
Simulation time 4477971687 ps
CPU time 63.06 seconds
Started Jan 17 12:48:15 PM PST 24
Finished Jan 17 12:49:22 PM PST 24
Peak memory 218504 kb
Host smart-38d72ab2-f2f1-489f-8ea4-7951b0243f67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131282815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4131282815
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.49661974
Short name T755
Test name
Test status
Simulation time 175524893 ps
CPU time 2.8 seconds
Started Jan 17 12:48:22 PM PST 24
Finished Jan 17 12:48:26 PM PST 24
Peak memory 209648 kb
Host smart-7f12efb4-75f1-4bbd-a5aa-2e0a9a92fd83
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49661974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_pr
iority.49661974
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.271460327
Short name T445
Test name
Test status
Simulation time 4080019855 ps
CPU time 7.56 seconds
Started Jan 17 12:48:37 PM PST 24
Finished Jan 17 12:48:45 PM PST 24
Peak memory 218124 kb
Host smart-8309141f-0b43-4cc9-a8f1-f3422bc765a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271460327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.271460327
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.204773695
Short name T354
Test name
Test status
Simulation time 2385912251 ps
CPU time 14.75 seconds
Started Jan 17 12:48:16 PM PST 24
Finished Jan 17 12:48:34 PM PST 24
Peak memory 213192 kb
Host smart-80d68a76-eaa1-4cf0-bd84-2210818b1fc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204773695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.204773695
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.419753745
Short name T20
Test name
Test status
Simulation time 96502661 ps
CPU time 1.7 seconds
Started Jan 17 12:48:24 PM PST 24
Finished Jan 17 12:48:26 PM PST 24
Peak memory 212412 kb
Host smart-bbc60263-63e1-43a9-b1d1-6fd56955a6cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419753745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.419753745
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2455369197
Short name T764
Test name
Test status
Simulation time 7541348698 ps
CPU time 40.02 seconds
Started Jan 17 12:48:10 PM PST 24
Finished Jan 17 12:48:51 PM PST 24
Peak memory 277196 kb
Host smart-9c311813-1bc9-40ae-af22-5a281e0898dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455369197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2455369197
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2219791437
Short name T723
Test name
Test status
Simulation time 329180683 ps
CPU time 11.35 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:32 PM PST 24
Peak memory 251096 kb
Host smart-69c60917-c76b-4d02-bc3b-6abf36f61b41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219791437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2219791437
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3424944341
Short name T184
Test name
Test status
Simulation time 620174660 ps
CPU time 2 seconds
Started Jan 17 12:48:11 PM PST 24
Finished Jan 17 12:48:13 PM PST 24
Peak memory 218180 kb
Host smart-34013b08-069c-40ad-a208-398f092d8588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424944341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3424944341
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3294802977
Short name T662
Test name
Test status
Simulation time 686652039 ps
CPU time 13.4 seconds
Started Jan 17 12:48:15 PM PST 24
Finished Jan 17 12:48:32 PM PST 24
Peak memory 213896 kb
Host smart-e4f91f59-45fb-4c03-a08f-7ed5ea5fbc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294802977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3294802977
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2289805582
Short name T598
Test name
Test status
Simulation time 198486387 ps
CPU time 9.37 seconds
Started Jan 17 12:48:16 PM PST 24
Finished Jan 17 12:48:29 PM PST 24
Peak memory 219184 kb
Host smart-0388a230-b2a7-4fb4-9ead-2b74a4d68107
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289805582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2289805582
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3300444834
Short name T549
Test name
Test status
Simulation time 4882924190 ps
CPU time 12.28 seconds
Started Jan 17 12:48:22 PM PST 24
Finished Jan 17 12:48:36 PM PST 24
Peak memory 218236 kb
Host smart-f97d8e97-f8a2-4441-ae06-7ae6d736958e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300444834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3300444834
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3018329265
Short name T678
Test name
Test status
Simulation time 781712792 ps
CPU time 9.49 seconds
Started Jan 17 12:48:21 PM PST 24
Finished Jan 17 12:48:31 PM PST 24
Peak memory 218112 kb
Host smart-cb6d0870-2164-4234-9cc0-bf2edcfbdc74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018329265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
018329265
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1324422330
Short name T819
Test name
Test status
Simulation time 235182682 ps
CPU time 13.41 seconds
Started Jan 17 12:48:18 PM PST 24
Finished Jan 17 12:48:34 PM PST 24
Peak memory 218184 kb
Host smart-591ec5de-0d82-4db5-8e85-52ac3553ac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324422330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1324422330
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3967243386
Short name T400
Test name
Test status
Simulation time 76956187 ps
CPU time 4.54 seconds
Started Jan 17 12:48:14 PM PST 24
Finished Jan 17 12:48:23 PM PST 24
Peak memory 213704 kb
Host smart-f1a1615d-b49d-4b14-86fb-f11c7c6bce9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967243386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3967243386
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1374389766
Short name T855
Test name
Test status
Simulation time 901624671 ps
CPU time 26.89 seconds
Started Jan 17 12:48:19 PM PST 24
Finished Jan 17 12:48:48 PM PST 24
Peak memory 245924 kb
Host smart-2bff5f77-6dea-4a1e-ba98-a9f22508104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374389766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1374389766
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.36614105
Short name T431
Test name
Test status
Simulation time 799287921 ps
CPU time 7.43 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:25 PM PST 24
Peak memory 251020 kb
Host smart-8c232b4c-b7f7-49eb-9fc5-23874533484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36614105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.36614105
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1882456439
Short name T37
Test name
Test status
Simulation time 110555314 ps
CPU time 0.84 seconds
Started Jan 17 12:48:12 PM PST 24
Finished Jan 17 12:48:18 PM PST 24
Peak memory 208352 kb
Host smart-c100784d-f2a3-4473-a4c0-6f90d47fae86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882456439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1882456439
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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