Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62390945

1

T61

7794

T93

1717

T94

1682

auto[1]

1142350

1

T1

297

T3

396

T11

792

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62387385

1

T61

7794

T93

1717

T94

1682

auto[1]

1145910

1

T1

99

T3

99

T11

693

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5157862	1			T61	1997		T93	101		T94	83
auto[IdleSt]	15432315	1			T61	5429		T93	1616		T94	1599
auto[ClkMuxSt]	29023	1			T1	68		T2	61		T3	8
auto[CntIncrSt]	28865	1			T1	68		T2	61		T3	8
auto[CntProgSt]	1428368	1			T1	124		T2	122		T3	350
auto[TransCheckSt]	22965	1			T1	60		T2	61		T3	8
auto[TokenHashSt]	20363039	1			T1	514		T2	2627		T3	606
auto[FlashRmaSt]	22541	1			T1	86		T2	61		T3	8
auto[TokenCheck0St]	10048	1			T1	21		T2	25		T3	8
auto[TokenCheck1St]	7146	1			T1	10		T2	11		T3	8
auto[TransProgSt]	318636	1			T1	20		T3	306		T11	418
auto[PostTransSt]	9045871	1			T1	9857		T2	9474		T3	2115
auto[ScrapSt]	162693	1			T61	368		T113	2476		T114	986
auto[EscalateSt]	4834727	1			T1	524		T3	1012		T11	1976
auto[InvalidSt]	6668036	1			T3	631		T13	1899		T16	8099

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1160	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6668036	1			T3	631		T13	1899		T16	8099
EscalateSt	4834727	1			T1	524		T3	1012		T11	1976
ScrapSt	162693	1			T61	368		T113	2476		T114	986
PostTransSt	9045871	1			T1	9857		T2	9474		T3	2115
TransProgSt	318636	1			T1	20		T3	306		T11	418
TokenCheck1St	7146	1			T1	10		T2	11		T3	8
TokenCheck0St	10048	1			T1	21		T2	25		T3	8
FlashRmaSt	22541	1			T1	86		T2	61		T3	8
TokenHashSt	20363039	1			T1	514		T2	2627		T3	606
TransCheckSt	22965	1			T1	60		T2	61		T3	8
CntProgSt	1428368	1			T1	124		T2	122		T3	350
CntIncrSt	28865	1			T1	68		T2	61		T3	8
ClkMuxSt	29023	1			T1	68		T2	61		T3	8
IdleSt	15432315	1			T61	5429		T93	1616		T94	1599
ResetSt	5157862	1			T61	1997		T93	101		T94	83
arcs[ResetSt=>IdleSt]	41449	1			T61	21		T93	2		T94	1
arcs[IdleSt=>ScrapSt]	222	1			T61	2		T113	1		T114	1
arcs[IdleSt=>ClkMuxSt]	28910	1			T1	68		T2	61		T3	8
arcs[ClkMuxSt=>CntIncrSt]	28865	1			T1	68		T2	61		T3	8
arcs[CntIncrSt=>PostTransSt]	1356	1			T1	4		T11	8		T18	5
arcs[CntIncrSt=>CntProgSt]	27443	1			T1	64		T2	61		T3	8
arcs[CntProgSt=>PostTransSt]	3431	1			T1	4		T11	15		T13	12
arcs[CntProgSt=>TransCheckSt]	22965	1			T1	60		T2	61		T3	8
arcs[TransCheckSt=>PostTransSt]	3389	1			T1	12		T2	30		T11	9
arcs[TransCheckSt=>TokenHashSt]	19433	1			T1	48		T2	31		T3	8
arcs[TokenHashSt=>PostTransSt]	8570	1			T1	27		T2	6		T11	29
arcs[TokenHashSt=>FlashRmaSt]	10175	1			T1	21		T2	25		T3	8
arcs[FlashRmaSt=>TokenCheck0St]	10048	1			T1	21		T2	25		T3	8
arcs[TokenCheck0St=>PostTransSt]	2876	1			T1	11		T2	14		T11	5
arcs[TokenCheck0St=>TokenCheck1St]	7146	1			T1	10		T2	11		T3	8
arcs[TokenCheck1St=>PostTransSt]	620	1			T2	11		T11	1		T13	1
arcs[TransProgSt=>PostTransSt]	5648	1			T1	10		T3	8		T11	11
arcs[IdleSt=>EscalateSt]	244	1			T12	6		T81	8		T68	5
arcs[ClkMuxSt=>EscalateSt]	45	1			T12	1		T49	1		T81	1
arcs[CntIncrSt=>EscalateSt]	66	1			T12	1		T49	1		T81	1
arcs[CntProgSt=>EscalateSt]	1047	1			T12	31		T49	25		T81	5
arcs[TransCheckSt=>EscalateSt]	143	1			T81	8		T68	6		T29	5
arcs[TokenHashSt=>EscalateSt]	682	1			T12	12		T4	1		T49	8
arcs[FlashRmaSt=>EscalateSt]	127	1			T12	3		T49	3		T81	1
arcs[TokenCheck0St=>EscalateSt]	26	1			T81	1		T68	2		T29	1
arcs[TokenCheck1St=>EscalateSt]	145	1			T12	3		T49	3		T81	3
arcs[TransProgSt=>EscalateSt]	733	1			T12	27		T49	21		T81	5
arcs[PostTransSt=>EscalateSt]	3664	1			T1	4		T11	15		T12	1
arcs[InvalidSt=>EscalateSt]	9931	1			T3	5		T13	14		T16	48

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5157701	1			T61	1997		T93	101		T94	83
auto[0]	auto[IdleSt]	15432154	1			T61	5429		T93	1616		T94	1599
auto[0]	auto[ClkMuxSt]	28997	1			T1	68		T2	61		T3	8
auto[0]	auto[CntIncrSt]	28823	1			T1	68		T2	61		T3	8
auto[0]	auto[CntProgSt]	1427662	1			T1	124		T2	122		T3	350
auto[0]	auto[TransCheckSt]	22872	1			T1	60		T2	61		T3	8
auto[0]	auto[TokenHashSt]	20362613	1			T1	514		T2	2627		T3	606
auto[0]	auto[FlashRmaSt]	22462	1			T1	86		T2	61		T3	8
auto[0]	auto[TokenCheck0St]	10031	1			T1	21		T2	25		T3	8
auto[0]	auto[TokenCheck1St]	7047	1			T1	10		T2	11		T3	8
auto[0]	auto[TransProgSt]	318135	1			T1	20		T3	306		T11	418
auto[0]	auto[PostTransSt]	9043960	1			T1	9854		T2	9474		T3	2115
auto[0]	auto[ScrapSt]	162652	1			T61	368		T113	2476		T114	986
auto[0]	auto[EscalateSt]	3701594	1			T1	230		T3	620		T11	1192
auto[0]	auto[InvalidSt]	6663082	1			T3	627		T13	1892		T16	8081
auto[1]	auto[ResetSt]	161	1			T12	1		T49	3		T81	5
auto[1]	auto[IdleSt]	161	1			T12	4		T81	5		T68	4
auto[1]	auto[ClkMuxSt]	26	1			T12	1		T29	1		T187	1
auto[1]	auto[CntIncrSt]	42	1			T12	1		T49	1		T81	1
auto[1]	auto[CntProgSt]	706	1			T12	24		T49	17		T81	5
auto[1]	auto[TransCheckSt]	93	1			T81	5		T68	3		T29	4
auto[1]	auto[TokenHashSt]	426	1			T12	6		T4	1		T49	6
auto[1]	auto[FlashRmaSt]	79	1			T12	2		T49	3		T68	1
auto[1]	auto[TokenCheck0St]	17	1			T81	1		T68	1		T29	1
auto[1]	auto[TokenCheck1St]	99	1			T12	3		T49	1		T81	3
auto[1]	auto[TransProgSt]	501	1			T12	19		T49	16		T81	3
auto[1]	auto[PostTransSt]	1911	1			T1	3		T11	8		T12	1
auto[1]	auto[ScrapSt]	41	1			T12	4		T81	2		T29	1
auto[1]	auto[EscalateSt]	1133133	1			T1	294		T3	392		T11	784
auto[1]	auto[InvalidSt]	4954	1			T3	4		T13	7		T16	18

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5157703	1			T61	1997		T93	101		T94	83
auto[0]	auto[IdleSt]	15432151	1			T61	5429		T93	1616		T94	1599
auto[0]	auto[ClkMuxSt]	28991	1			T1	68		T2	61		T3	8
auto[0]	auto[CntIncrSt]	28816	1			T1	68		T2	61		T3	8
auto[0]	auto[CntProgSt]	1427671	1			T1	124		T2	122		T3	350
auto[0]	auto[TransCheckSt]	22879	1			T1	60		T2	61		T3	8
auto[0]	auto[TokenHashSt]	20362557	1			T1	514		T2	2627		T3	606
auto[0]	auto[FlashRmaSt]	22454	1			T1	86		T2	61		T3	8
auto[0]	auto[TokenCheck0St]	10032	1			T1	21		T2	25		T3	8
auto[0]	auto[TokenCheck1St]	7042	1			T1	10		T2	11		T3	8
auto[0]	auto[TransProgSt]	318149	1			T1	20		T3	306		T11	418
auto[0]	auto[PostTransSt]	9044041	1			T1	9856		T2	9474		T3	2115
auto[0]	auto[ScrapSt]	162654	1			T61	368		T113	2476		T114	986
auto[0]	auto[EscalateSt]	3698026	1			T1	426		T3	914		T11	1290
auto[0]	auto[InvalidSt]	6663059	1			T3	630		T13	1892		T16	8069
auto[1]	auto[ResetSt]	159	1			T12	5		T49	4		T81	3
auto[1]	auto[IdleSt]	164	1			T12	4		T81	4		T68	2
auto[1]	auto[ClkMuxSt]	32	1			T49	1		T81	1		T29	2
auto[1]	auto[CntIncrSt]	49	1			T49	1		T68	2		T29	1
auto[1]	auto[CntProgSt]	697	1			T12	20		T49	21		T81	2
auto[1]	auto[TransCheckSt]	86	1			T81	7		T68	4		T29	1
auto[1]	auto[TokenHashSt]	482	1			T12	9		T49	6		T81	11
auto[1]	auto[FlashRmaSt]	87	1			T12	2		T49	2		T81	1
auto[1]	auto[TokenCheck0St]	16	1			T68	1		T29	1		T91	1
auto[1]	auto[TokenCheck1St]	104	1			T12	2		T49	3		T81	1
auto[1]	auto[TransProgSt]	487	1			T12	17		T49	16		T81	4
auto[1]	auto[PostTransSt]	1830	1			T1	1		T11	7		T12	1
auto[1]	auto[ScrapSt]	39	1			T12	2		T49	1		T29	1
auto[1]	auto[EscalateSt]	1136701	1			T1	98		T3	98		T11	686
auto[1]	auto[InvalidSt]	4977	1			T3	1		T13	7		T16	30