Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	824302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1011312

1

T61

616

T93

59

T94

168

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1548781	1			T61	90		T93	20		T94	21
values[0x0]	143013	1			T61	325		T93	29		T94	80
values[0x1]	143820	1			T61	336		T93	23		T94	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	652889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1182725

1

T61

659

T93

62

T94

168

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5289	1			T95	1		T97	1		T98	1
valid_sources[0x01]	5347	1			T61	2		T95	3		T97	4
valid_sources[0x02]	5283	1			T61	4		T95	2		T97	1
valid_sources[0x03]	5353	1			T93	1		T94	2		T95	1
valid_sources[0x04]	5264	1			T61	1		T95	1		T97	1
valid_sources[0x05]	6037	1			T61	13		T95	1		T98	1
valid_sources[0x06]	8420	1			T61	8		T94	1		T95	4
valid_sources[0x07]	7407	1			T61	1		T95	7		T97	4
valid_sources[0x08]	5327	1			T61	1		T95	2		T98	1
valid_sources[0x09]	5301	1			T94	1		T113	2		T114	3
valid_sources[0x0a]	5356	1			T61	12		T93	4		T98	2
valid_sources[0x0b]	5195	1			T94	2		T95	7		T97	1
valid_sources[0x0c]	5170	1			T93	1		T95	3		T97	1
valid_sources[0x0d]	8223	1			T61	13		T94	3		T95	5
valid_sources[0x0e]	7114	1			T95	2		T99	2		T101	7
valid_sources[0x0f]	6715	1			T61	1		T113	3		T114	2
valid_sources[0x10]	5328	1			T95	3		T99	2		T101	1
valid_sources[0x11]	5218	1			T94	1		T99	1		T113	1
valid_sources[0x12]	5517	1			T61	9		T93	1		T94	2
valid_sources[0x13]	7144	1			T95	2		T113	2		T114	2
valid_sources[0x14]	5351	1			T93	2		T95	1		T97	1
valid_sources[0x15]	5384	1			T93	1		T95	1		T101	4
valid_sources[0x16]	5292	1			T61	3		T93	1		T95	1
valid_sources[0x17]	10173	1			T94	3		T95	1		T97	2
valid_sources[0x18]	5187	1			T95	5		T113	2		T114	1
valid_sources[0x19]	7646	1			T61	14		T94	2		T95	1
valid_sources[0x1a]	5317	1			T61	3		T95	4		T97	1
valid_sources[0x1b]	5747	1			T61	19		T94	2		T95	1
valid_sources[0x1c]	5508	1			T95	1		T97	2		T98	2
valid_sources[0x1d]	5159	1			T61	3		T95	2		T99	1
valid_sources[0x1e]	5624	1			T95	2		T98	3		T113	1
valid_sources[0x1f]	5321	1			T93	1		T95	1		T98	2
valid_sources[0x20]	5436	1			T97	1		T99	3		T113	1
valid_sources[0x21]	5448	1			T95	4		T98	3		T99	2
valid_sources[0x22]	6996	1			T61	5		T95	2		T97	4
valid_sources[0x23]	6806	1			T61	8		T94	1		T95	1
valid_sources[0x24]	7182	1			T94	1		T95	3		T99	5
valid_sources[0x25]	5312	1			T61	9		T95	2		T98	1
valid_sources[0x26]	9721	1			T95	4		T113	2		T131	1
valid_sources[0x27]	5185	1			T93	1		T94	1		T95	1
valid_sources[0x28]	5362	1			T61	7		T95	1		T98	3
valid_sources[0x29]	5218	1			T61	11		T94	1		T98	1
valid_sources[0x2a]	7389	1			T95	1		T97	1		T113	2
valid_sources[0x2b]	7693	1			T94	2		T95	2		T97	2
valid_sources[0x2c]	5016	1			T61	3		T95	2		T99	1
valid_sources[0x2d]	5447	1			T61	4		T94	1		T95	2
valid_sources[0x2e]	5334	1			T61	4		T95	1		T98	1
valid_sources[0x2f]	5316	1			T61	2		T97	2		T98	3
valid_sources[0x30]	7209	1			T61	2		T94	1		T95	5
valid_sources[0x31]	6418	1			T61	4		T95	1		T98	1
valid_sources[0x32]	8061	1			T97	1		T100	12		T101	1
valid_sources[0x33]	6079	1			T94	2		T95	1		T97	1
valid_sources[0x34]	7058	1			T61	5		T94	2		T95	2
valid_sources[0x35]	6880	1			T93	1		T94	1		T95	4
valid_sources[0x36]	5838	1			T95	10		T98	5		T101	6
valid_sources[0x37]	6605	1			T95	1		T97	1		T98	1
valid_sources[0x38]	5080	1			T61	3		T95	3		T97	1
valid_sources[0x39]	5299	1			T93	2		T94	2		T95	1
valid_sources[0x3a]	5569	1			T94	2		T95	6		T100	9
valid_sources[0x3b]	20007	1			T61	7		T93	2		T97	3
valid_sources[0x3c]	5840	1			T61	12		T95	1		T97	2
valid_sources[0x3d]	5224	1			T61	3		T94	1		T98	2
valid_sources[0x3e]	5618	1			T94	1		T95	1		T97	1
valid_sources[0x3f]	6439	1			T93	1		T95	1		T113	2
valid_sources[0x40]	5395	1			T61	7		T95	1		T101	1
valid_sources[0x41]	5255	1			T95	4		T98	4		T100	4
valid_sources[0x42]	5514	1			T95	1		T97	3		T98	2
valid_sources[0x43]	5180	1			T95	1		T98	2		T101	2
valid_sources[0x44]	6818	1			T95	1		T97	5		T101	5
valid_sources[0x45]	5446	1			T94	4		T101	2		T131	2
valid_sources[0x46]	5527	1			T61	3		T94	1		T95	1
valid_sources[0x47]	5401	1			T61	9		T93	1		T95	1
valid_sources[0x48]	6930	1			T95	2		T97	3		T101	1
valid_sources[0x49]	5227	1			T94	2		T95	1		T98	1
valid_sources[0x4a]	8148	1			T95	3		T97	4		T98	1
valid_sources[0x4b]	5097	1			T98	4		T114	1		T169	2
valid_sources[0x4c]	5480	1			T61	3		T94	1		T97	3
valid_sources[0x4d]	5302	1			T95	7		T97	3		T98	2
valid_sources[0x4e]	5544	1			T61	3		T95	2		T98	2
valid_sources[0x4f]	5224	1			T61	2		T94	1		T98	1
valid_sources[0x50]	5259	1			T94	1		T95	2		T113	1
valid_sources[0x51]	9782	1			T93	1		T98	3		T99	1
valid_sources[0x52]	7374	1			T61	16		T95	3		T99	1
valid_sources[0x53]	5118	1			T94	3		T95	1		T97	2
valid_sources[0x54]	5438	1			T61	1		T95	3		T99	1
valid_sources[0x55]	5402	1			T61	3		T95	3		T97	3
valid_sources[0x56]	5448	1			T61	1		T95	4		T100	4
valid_sources[0x57]	5249	1			T61	2		T101	1		T114	1
valid_sources[0x58]	5626	1			T94	3		T95	10		T97	2
valid_sources[0x59]	5813	1			T61	2		T95	2		T97	3
valid_sources[0x5a]	4986	1			T94	2		T95	2		T97	1
valid_sources[0x5b]	5272	1			T61	4		T95	4		T98	1
valid_sources[0x5c]	5497	1			T61	4		T95	5		T99	1
valid_sources[0x5d]	110165	1			T95	2		T113	1		T114	4
valid_sources[0x5e]	5507	1			T61	1		T95	1		T97	3
valid_sources[0x5f]	5329	1			T94	1		T95	1		T98	4
valid_sources[0x60]	6867	1			T94	2		T99	1		T100	7
valid_sources[0x61]	5330	1			T61	9		T95	2		T97	1
valid_sources[0x62]	5239	1			T61	8		T95	1		T113	3
valid_sources[0x63]	5391	1			T95	1		T97	1		T99	1
valid_sources[0x64]	7286	1			T61	9		T94	2		T95	2
valid_sources[0x65]	5700	1			T94	1		T95	4		T98	2
valid_sources[0x66]	5237	1			T97	1		T101	1		T113	1
valid_sources[0x67]	5547	1			T94	2		T95	1		T101	3
valid_sources[0x68]	5447	1			T61	7		T93	1		T95	2
valid_sources[0x69]	5460	1			T94	2		T99	1		T101	1
valid_sources[0x6a]	6428	1			T95	2		T113	1		T114	1
valid_sources[0x6b]	7614	1			T95	2		T97	2		T101	1
valid_sources[0x6c]	7564	1			T95	1		T157	5		T161	1
valid_sources[0x6d]	5229	1			T61	18		T93	1		T95	2
valid_sources[0x6e]	6937	1			T61	2		T95	1		T101	1
valid_sources[0x6f]	5295	1			T61	2		T93	1		T95	3
valid_sources[0x70]	5281	1			T95	1		T97	2		T98	2
valid_sources[0x71]	5179	1			T93	1		T94	3		T97	1
valid_sources[0x72]	7019	1			T61	12		T94	5		T95	1
valid_sources[0x73]	8741	1			T95	5		T97	1		T101	7
valid_sources[0x74]	5318	1			T61	3		T94	1		T95	5
valid_sources[0x75]	6388	1			T61	4		T95	1		T97	3
valid_sources[0x76]	5563	1			T95	2		T101	5		T113	1
valid_sources[0x77]	5400	1			T61	3		T97	2		T98	5
valid_sources[0x78]	5248	1			T61	3		T94	1		T95	2
valid_sources[0x79]	14022	1			T94	1		T95	6		T99	1
valid_sources[0x7a]	10293	1			T61	1		T97	2		T98	3
valid_sources[0x7b]	5350	1			T93	1		T94	4		T95	2
valid_sources[0x7c]	12607	1			T94	1		T99	1		T101	3
valid_sources[0x7d]	5791	1			T61	21		T93	1		T94	2
valid_sources[0x7e]	5494	1			T94	1		T95	6		T100	3
valid_sources[0x7f]	4899	1			T95	2		T97	1		T98	1
valid_sources[0x80]	5540	1			T94	1		T95	4		T99	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

764546

1

T61

27

T93

12

T94

21

values[0x0]

all_enables

biggest_size

123952

1

T61

294

T93

25

T94

80

values[0x1]

all_enables

biggest_size

122814

1

T61

295

T93

22

T94

67