Group : dv_base_reg_pkg::mubi_cov#(4,32'sb00000000000000000000000000000101,32'sb00000000000000000000000000001010)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'sb00000000000000000000000000000101,32'sb00000000000000000000000000001010)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 90.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if 83.33 1 100 1 64 64
mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if 83.33 1 100 1 64 64
mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if 83.33 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 1 5 83.33 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 1 5 83.33 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 1 5 83.33 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 1 5 83.33


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
false 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 345 1 T13 4 T51 18 T54 12
others[1] 315 1 T13 2 T51 2 T54 8
others[2] 308 1 T13 4 T51 8 T54 8
others[3] 516 1 T13 10 T51 6 T54 16
true 42678 1 T61 21 T93 2 T94 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 1 5 83.33


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 334 1 T13 2 T51 2 T54 8
others[1] 311 1 T13 4 T51 8 T54 6
others[2] 365 1 T13 4 T51 8 T54 10
others[3] 487 1 T13 17 T51 3 T54 4
false 42688 1 T61 21 T93 2 T94 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 1 5 83.33


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
false 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 322 1 T13 2 T51 8 T54 2
others[1] 310 1 T13 7 T51 2 T54 5
others[2] 324 1 T13 4 T51 10 T54 2
others[3] 503 1 T13 4 T51 4 T54 5
true 42675 1 T61 21 T93 2 T94 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 162 1 T13 3 T51 4 T54 5
others[1] 146 1 T13 1 T51 3 T54 4
others[2] 154 1 T13 1 T51 3 T54 4
others[3] 262 1 T13 7 T51 2 T54 4
false 679010 1 T61 21 T93 2 T94 1
true 635484 1 T1 449 T11 2077 T18 1248


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 169 1 T13 1 T51 2 T54 5
others[1] 168 1 T13 3 T51 1 T54 6
others[2] 173 1 T13 5 T51 6 T54 3
others[3] 284 1 T13 8 T51 7 T54 7
false 1792065 1 T61 21 T93 2 T94 1
true 1748589 1 T1 1059 T2 3 T11 923

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