Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	63533013	14006	0	0
claim_transition_if_regwen_rd_A	63533013	1065	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63533013	14006	0	0
T61	7794	8	0	0
T93	1717	9	0	0
T94	1681	0	0	0
T95	9784	623	0	0
T96	5064	0	0	0
T97	2878	0	0	0
T98	2072	0	0	0
T99	2416	50	0	0
T100	1539	0	0	0
T101	3898	3	0	0
T108	0	43	0	0
T112	0	9	0	0
T113	0	375	0	0
T131	0	915	0	0
T134	0	227	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63533013	1065	0	0
T97	2878	17	0	0
T98	2072	0	0	0
T99	2416	20	0	0
T100	1539	0	0	0
T101	3898	0	0	0
T106	1819	0	0	0
T108	1816	0	0	0
T113	2583	0	0	0
T114	1069	0	0	0
T137	0	75	0	0
T146	0	11	0	0
T157	1437	1	0	0
T161	0	142	0	0
T162	0	6	0	0
T163	0	5	0	0
T164	0	3	0	0
T165	0	8	0	0