Unified Coverage Report :: Module :: lc_ctrl_fsm

Module : lc_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	97.73	85.87		75.51	96.00	93.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm	95.37	97.73	89.77		100.00	96.00	93.33

---

Module Instance : tb.dut.u_lc_ctrl_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.37	97.73	89.77		100.00	96.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.04	98.86	88.46		100.00	95.74	97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt_regs	100.00	100.00				100.00	100.00
u_fsm_state_regs	100.00	100.00				100.00	100.00
u_lc_ctrl_fsm_cov_if	96.97	100.00	90.91			100.00
u_lc_ctrl_signal_decode	98.86	99.21				97.37	100.00
u_lc_ctrl_state_decode	98.89	100.00	100.00			96.67
u_lc_ctrl_state_transition	89.21	96.92	79.17			91.53
u_prim_lc_sender_check_byp_en	100.00	100.00				100.00
u_prim_lc_sender_clk_byp_req	100.00	100.00				100.00
u_prim_lc_sender_flash_rma_req	100.00	100.00				100.00
u_prim_lc_sync_clk_byp_ack	100.00	100.00				100.00	100.00
u_prim_lc_sync_flash_rma_ack	100.00	100.00				100.00	100.00
u_prim_lc_sync_rma_token_valid	100.00	100.00					100.00
u_prim_lc_sync_test_token_valid	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		176	172	97.73
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	176	114	110	96.49
ALWAYS	556	3	3	100.00
ALWAYS	557	3	3	100.00
ALWAYS	558	3	3	100.00
ALWAYS	561	3	3	100.00
ALWAYS	580	5	5	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	649	15	15	100.00
ALWAYS	684	14	14	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
ALWAYS	852	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
125	1	1
143	1	1
150	1	1
151	1	1
176	1	1
177	1	1
178	1	1
181	1	1
182	1	1
185	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
195	1	1
196	1	1
203	1	1
204	1	1
210	1	1
211	1	1
212	1	1
214	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
			MISSING_ELSE
235	1	1
245	1	1
249	1	1
250	1	1
			MISSING_ELSE
256	1	1
257	1	1
265	1	1
267	1	1
271	1	1
273	1	1
277	1	1
281	1	1
284	1	1
286	1	1
288	0	1
289	0	1
293	1	1
298	1	1
299	1	1
			MISSING_ELSE
305	1	1
322	1	1
323	1	1
			MISSING_ELSE
			MISSING_ELSE
336	1	1
337	1	1
354	1	1
355	1	1
356	1	1
357	1	1
			MISSING_ELSE
360	1	1
363	1	1
370	1	1
371	1	1
373	1	1
379	1	1
383	1	1
384	1	1
385	1	1
			MISSING_ELSE
390	1	1
391	1	1
392	1	1
393	1	1
395	1	1
			MISSING_ELSE
403	1	1
404	1	1
406	1	1
417	1	1
418	1	1
424	1	1
427	1	1
429	1	1
430	1	1
			MISSING_ELSE
438	1	1
439	1	1
440	1	1
441	1	1
			MISSING_ELSE
444	1	1
454	1	1
455	1	1
459	1	1
465	1	1
468	1	1
471	1	1
473	1	1
476	0	1
477	0	1
481	1	1
482	1	1
492	1	1
496	1	1
497	1	1
498	1	1
501	1	1
505	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
			MISSING_ELSE
516	1	1
521	1	1
526	1	1
527	1	1
539	1	1
540	1	1
546	1	1
547	1	1
548	1	1
			MISSING_ELSE
556	3	3
557	3	3
558	3	3
561	1	1
562	1	1
564	1	1
580	1	1
581	1	1
582	1	1
584	1	1
587	1	1
591	1	1
638	1	1
639	1	1
640	1	1
649	1	1
651	1	1
653	1	1
656	1	1
657	1	1
			MISSING_ELSE
659	1	1
660	1	1
			MISSING_ELSE
663	1	1
664	1	1
			MISSING_ELSE
666	1	1
667	1	1
			MISSING_ELSE
670	1	1
671	1	1
			MISSING_ELSE
673	1	1
674	1	1
			MISSING_ELSE
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
690	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
697	1	1
698	1	1
704	1	1
708	1	1
712	1	1
714	1	1
721	1	1
852	3	3

---

Cond Coverage for Module : lc_ctrl_fsm

	Total	Covered	Percent
Conditions	92	79	85.87
Logical	92	79	85.87
Non-Logical	0	0
Event	0	0

 LINE       223
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T19,T5
1	1	Covered	T1,T2,T3

 LINE       256
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T49

 LINE       265
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i)
             -----------1----------    ----------2----------    -----3-----

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T14,T43,T44
-	1	1	Covered	T14,T43,T44

 LINE       267
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T14,T43,T45

 LINE       267
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Covered	T14,T45,T48
1	Covered	T14,T43,T44

 LINE       267
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T14,T44,T45
1	Covered	T14,T43,T45

 LINE       271
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T14,T43,T45

 LINE       277
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests
0	Covered	T14,T43,T45
1	Not Covered

 LINE       277
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Covered	T14,T43,T45
1	Not Covered

 LINE       383
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T13

 LINE       424
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Covered	T1,T11,T18
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       424
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T1,T2,T3

 LINE       438
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T12

 LINE       465
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       465
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       468
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T4,T5,T53

 LINE       501
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T54,T55,T56
1	0	Covered	T57,T58,T59

 LINE       501
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off)))
                 -----------------------------------1----------------------------------    ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T13
1	0	Covered	T1,T3,T11
1	1	Covered	T57,T58,T59

 LINE       501
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T3,T11

 LINE       501
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))
                 -------------1-------------    --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T57,T58,T59
1	0	Not Covered

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T12,T13

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_ack[1] != Off)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T12,T13

 LINE       501
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On)))
                 -----------------------------------1----------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T12,T13
1	1	Covered	T54,T55,T56

 LINE       501
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T12,T13

 LINE       501
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T13
0	1	Covered	T54,T55,T56
1	0	Not Covered

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T3,T11

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_ack[1] != On)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T3,T11

 LINE       539
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T3,T11

 LINE       546
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T19,T4
1	1	Covered	T3,T13,T16

 LINE       546
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T4
1	0	Covered	T3,T13,T16

 LINE       546
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       584
 SUB-EXPRESSION (set_strap_en_override || gen_strap_delay_regs.strap_en_override_q[0])
                 ----------1----------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T43,T45
1	0	Covered	T14,T43,T45

 LINE       704
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       704
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T7,T8,T10
1	1	Covered	T1,T2,T3

 LINE       708
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       708
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T7,T8,T10
1	1	Covered	T1,T2,T3

 LINE       721
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T60
1	0	Covered	T1,T11,T14

 LINE       721
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T60

---

FSM Coverage for Module : lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	47	35	74.47
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	299	Covered	T61
CntIncrSt	357	Covered	T61
CntProgSt	373	Covered	T61
EscalateSt	540	Covered	T61
FlashRmaSt	427	Covered	T61
IdleSt	224	Covered	T61
InvalidSt	547	Covered	T61
PostTransSt	289	Covered	T61
ResetSt	218	Covered	T61
ScrapSt	257	Covered	T61
TokenCheck0St	441	Covered	T61
TokenCheck1St	473	Covered	T61
TokenHashSt	406	Covered	T61
TransCheckSt	395	Covered	T61
TransProgSt	471	Covered	T61

transitions	Line No.	Covered	Tests
ClkMuxSt->CntIncrSt	357	Covered	T61
ClkMuxSt->EscalateSt	540	Covered	T61
ClkMuxSt->InvalidSt	547	Not Covered
CntIncrSt->CntProgSt	373	Covered	T61
CntIncrSt->EscalateSt	540	Covered	T61
CntIncrSt->InvalidSt	547	Not Covered
CntIncrSt->PostTransSt	371	Covered	T61
CntProgSt->EscalateSt	540	Covered	T61
CntProgSt->InvalidSt	547	Not Covered
CntProgSt->PostTransSt	384	Covered	T61
CntProgSt->TransCheckSt	395	Covered	T61
EscalateSt->InvalidSt	547	Not Covered
FlashRmaSt->EscalateSt	540	Covered	T61
FlashRmaSt->InvalidSt	547	Not Covered
FlashRmaSt->TokenCheck0St	441	Covered	T61
IdleSt->ClkMuxSt	299	Covered	T61
IdleSt->EscalateSt	540	Covered	T61
IdleSt->InvalidSt	547	Covered	T61
IdleSt->PostTransSt	289	Covered	T61
IdleSt->ScrapSt	257	Covered	T61
InvalidSt->EscalateSt	540	Covered	T61
PostTransSt->EscalateSt	540	Covered	T61
PostTransSt->InvalidSt	547	Not Covered
ResetSt->EscalateSt	540	Covered	T61
ResetSt->IdleSt	224	Covered	T61
ResetSt->InvalidSt	547	Not Covered
ScrapSt->EscalateSt	540	Covered	T61
ScrapSt->InvalidSt	547	Covered	T61
TokenCheck0St->EscalateSt	540	Covered	T61
TokenCheck0St->InvalidSt	547	Not Covered
TokenCheck0St->PostTransSt	455	Covered	T61
TokenCheck0St->TokenCheck1St	473	Covered	T61
TokenCheck1St->EscalateSt	540	Covered	T61
TokenCheck1St->InvalidSt	547	Not Covered
TokenCheck1St->PostTransSt	455	Covered	T61
TokenCheck1St->TransProgSt	471	Covered	T61
TokenHashSt->EscalateSt	540	Covered	T61
TokenHashSt->FlashRmaSt	427	Covered	T61
TokenHashSt->InvalidSt	547	Not Covered
TokenHashSt->PostTransSt	429	Covered	T61
TransCheckSt->EscalateSt	540	Covered	T61
TransCheckSt->InvalidSt	547	Not Covered
TransCheckSt->PostTransSt	404	Covered	T61
TransCheckSt->TokenHashSt	406	Covered	T61
TransProgSt->EscalateSt	540	Covered	T61
TransProgSt->InvalidSt	547	Not Covered
TransProgSt->PostTransSt	497	Covered	T61

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	12	57.14	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Not Covered
LcStProd	93	Not Covered
LcStProdEnd	94	Not Covered
LcStRaw	267	Covered	T61
LcStRma	305	Not Covered
LcStScrap	256	Not Covered
LcStTestLocked0	305	Covered	T61
LcStTestLocked1	305	Covered	T61
LcStTestLocked2	305	Covered	T61
LcStTestLocked3	305	Covered	T61
LcStTestLocked4	305	Covered	T61
LcStTestLocked5	305	Not Covered
LcStTestLocked6	305	Not Covered
LcStTestUnlocked0	273	Covered	T61
LcStTestUnlocked1	305	Covered	T61
LcStTestUnlocked2	305	Covered	T61
LcStTestUnlocked3	305	Covered	T61
LcStTestUnlocked4	305	Covered	T61
LcStTestUnlocked5	305	Covered	T61
LcStTestUnlocked6	305	Not Covered
LcStTestUnlocked7	305	Not Covered

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	273	Covered	T61

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	6	24.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	277	Covered	T61
LcCnt1	277	Covered	T61
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Covered	T61
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Covered	T61
LcCnt4	106	Covered	T61
LcCnt5	107	Covered	T61
LcCnt6	108	Not Covered
LcCnt7	109	Not Covered
LcCnt8	110	Not Covered
LcCnt9	111	Not Covered

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	277	Covered	T61

---

Branch Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		75	72	96.00
TERNARY	704	1	1	100.00
TERNARY	708	1	1	100.00
CASE	214	46	43	93.48
IF	539	3	3	100.00
IF	556	2	2	100.00
IF	557	2	2	100.00
IF	558	2	2	100.00
IF	561	2	2	100.00
IF	656	2	2	100.00
IF	659	2	2	100.00
IF	663	2	2	100.00
IF	666	2	2	100.00
IF	670	2	2	100.00
IF	673	2	2	100.00
IF	852	2	2	100.00
IF	580	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	704	(((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	708	(((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	214	case (fsm_state_q)
-2-:	223	if ((init_req_i && lc_state_valid_q))
-3-:	245	if (((!((SecVolatileRawUnlockEn && (lc_state_q == LcStTestUnlocked0)) && (lc_cnt_q != LcCnt0))) || prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)))
-4-:	256	if ((lc_state_q == LcStScrap))
-5-:	265	if (((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i))
-6-:	267	if ((((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})) && (!trans_invalid_error_o)))
-7-:	271	if ((unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed))
-8-:	277	((lc_cnt_q == LcCnt0)) ? 
-9-:	298	if (trans_cmd_i)
-10-:	305	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-11-:	322	if (use_ext_clock_i)
-12-:	337	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-13-:	354	if (use_ext_clock_i)
-14-:	356	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_ack[0]))
-15-:	370	if (trans_cnt_oflw_error_o)
-16-:	383	if ((lc_clk_byp_req_o != lc_clk_byp_ack[1]))
-17-:	390	if (otp_prog_ack_i)
-18-:	391	if (otp_prog_err_i)
-19-:	403	if (trans_invalid_error_o)
-20-:	418	if (token_hash_ack_i)
-21-:	424	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-22-:	438	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}))
-23-:	440	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack[0]))
-24-:	454	if (trans_invalid_error_o)
-25-:	459	if (((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_ack[1])) || (((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack[1]))))
-26-:	465	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-27-:	468	if ((fsm_state_q == TokenCheck1St))
-28-:	496	if ((lc_clk_byp_req_o != lc_clk_byp_ack[2]))
-29-:	501	if ((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))) || ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On)))))
-30-:	507	if (otp_prog_ack_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T43,T45
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T5,T49
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T43,T45
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T44,T45
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T50
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T50
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T62,T63,T64
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T18
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T13
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T4,T65
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T1,T2,T12
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Covered	T1,T2,T12
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T60,T66
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T1,T2,T3
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T1,T2,T3
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T11,T13
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T5,T53
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T54,T55,T56
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T1,T3,T11
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T1,T3,T11
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T19

	LineNo.	Expression
-1-:	539	if ((esc_scrap_state0_i || esc_scrap_state1_i))
-2-:	546	if ((((|state_invalid_error) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T11
0	1	Covered	T3,T13,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	656	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	659	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	663	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[2]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	666	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[3]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	670	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	673	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	852	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	580	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClkBypStaysOnOnceAsserted_A	61339496	3299480	0	80
EscStaysOnOnceAsserted_A	61339496	11516466	0	8
FlashRmaStaysOnOnceAsserted_A	61339496	424716	0	11
FsmStateKnown_A	61339496	58174010	0	0
LcCntKnown_A	61339496	58174010	0	0
LcStateKnown_A	61339496	58174010	0	0
NoClkBypInProdStates_A	61339496	7967182	0	0
SecCmCFILinear_A	61339496	0	0	1950
SecCmCFITerminal0_A	61339496	9023562	0	0
SecCmCFITerminal1_A	61339496	44053	0	0
SecCmCFITerminal2_A	61339496	4817564	0	0
SecCmCFITerminal3_A	61339496	6667679	0	0
u_cnt_regs_A	56665512	53767127	0	0
u_fsm_state_regs_A	59932703	56848208	0	0
u_state_regs_A	57719713	54807144	0	0

ClkBypStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	3299480	0	80
T4	441927	13472	0	0
T5	137387	1819	0	0
T6	92204	0	0	0
T7	0	58902	0	1
T8	0	0	0	1
T9	0	0	0	1
T20	0	32501	0	0
T21	0	36285	0	0
T22	0	42065	0	0
T24	0	36665	0	0
T25	0	3617	0	0
T26	1874	0	0	0
T27	26453	0	0	0
T30	0	0	0	1
T42	0	0	0	1
T50	5733	338	0	0
T52	86944	0	0	0
T62	0	1657	0	1
T65	7671	0	0	0
T67	1267	0	0	0
T68	24291	0	0	0
T69	0	0	0	1
T70	0	0	0	1
T71	0	0	0	1
T72	0	0	0	1

EscStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	11516466	0	8
T1	19896	516	0	0
T2	20231	0	0	0
T3	8520	1636	0	0
T11	31684	1946	0	0
T12	49297	20114	0	0
T13	27450	5370	0	0
T14	1447	0	0	0
T15	9316	2702	0	0
T16	23267	14853	0	0
T17	1436	0	0	0
T18	0	1433	0	0
T19	0	1426	0	0
T51	0	4827	0	0
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1
T77	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1

FlashRmaStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	424716	0	11
T1	19896	1103	0	0
T2	20231	529	0	0
T3	8520	0	0	0
T4	0	4990	0	0
T5	0	4667	0	0
T11	31684	0	0	0
T12	49297	369	0	0
T13	27450	488	0	0
T14	1447	0	0	0
T15	9316	0	0	0
T16	23267	0	0	0
T17	1436	0	0	0
T18	0	462	0	0
T25	0	0	0	1
T49	0	744	0	0
T51	0	236	0	0
T81	0	813	0	0
T82	0	0	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1
T88	0	0	0	1
T89	0	0	0	1
T90	0	0	0	1

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	58174010	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	8520	7468	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	23267	19087	0	0
T17	1436	1365	0	0

LcCntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	58174010	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	8520	7468	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	23267	19087	0	0
T17	1436	1365	0	0

LcStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	58174010	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	8520	7468	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	23267	19087	0	0
T17	1436	1365	0	0

NoClkBypInProdStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	7967182	0	0
T1	19896	1260	0	0
T2	20231	2504	0	0
T3	8520	1460	0	0
T11	31684	3320	0	0
T12	49297	6287	0	0
T13	27450	3495	0	0
T14	1447	0	0	0
T15	9316	1662	0	0
T16	23267	2271	0	0
T17	1436	0	0	0
T18	0	5522	0	0
T19	0	885	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	0	0	1950

SecCmCFITerminal0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	9023562	0	0
T1	19896	9793	0	0
T2	20231	9413	0	0
T3	8520	2107	0	0
T11	31684	12155	0	0
T12	49297	3	0	0
T13	27450	6911	0	0
T14	1447	1291	0	0
T15	9316	1616	0	0
T16	23267	0	0	0
T17	1436	0	0	0
T18	0	11485	0	0
T43	0	792	0	0

SecCmCFITerminal1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	44053	0	0
T5	0	1243	0	0
T12	49297	12	0	0
T13	27450	0	0	0
T14	1447	0	0	0
T15	9316	0	0	0
T16	23267	0	0	0
T17	1436	0	0	0
T18	51894	0	0	0
T19	5347	0	0	0
T22	0	1345	0	0
T29	0	6	0	0
T39	0	6	0	0
T40	0	1	0	0
T43	1237	0	0	0
T49	0	3	0	0
T50	0	31	0	0
T81	0	6	0	0
T91	0	3	0	0
T92	713	0	0	0

SecCmCFITerminal2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	4817564	0	0
T1	19896	520	0	0
T2	20231	0	0	0
T3	8520	1007	0	0
T11	31684	1961	0	0
T12	49297	20192	0	0
T13	27450	3497	0	0
T14	1447	0	0	0
T15	9316	2722	0	0
T16	23267	6784	0	0
T17	1436	0	0	0
T18	0	1444	0	0
T19	0	1021	0	0
T51	0	3154	0	0

SecCmCFITerminal3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	6667679	0	0
T3	8520	631	0	0
T4	0	5965	0	0
T5	0	20950	0	0
T11	31684	0	0	0
T12	49297	0	0	0
T13	27450	1899	0	0
T14	1447	0	0	0
T15	9316	0	0	0
T16	23267	8099	0	0
T17	1436	0	0	0
T18	51894	0	0	0
T19	0	408	0	0
T20	0	103431	0	0
T22	0	128962	0	0
T27	0	8396	0	0
T43	1237	0	0	0
T51	0	1696	0	0

u_cnt_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56665512	53767127	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	7451	6556	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	12802	10342	0	0
T17	1436	1365	0	0

u_fsm_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59932703	56848208	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	8027	7041	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	20973	17135	0	0
T17	1436	1365	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57719713	54807144	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	7669	6752	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	17978	14819	0	0
T17	1436	1365	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		176	172	97.73
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	176	114	110	96.49
ALWAYS	556	3	3	100.00
ALWAYS	557	3	3	100.00
ALWAYS	558	3	3	100.00
ALWAYS	561	3	3	100.00
ALWAYS	580	5	5	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	649	15	15	100.00
ALWAYS	684	14	14	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
ALWAYS	852	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
125	1	1
143	1	1
150	1	1
151	1	1
176	1	1
177	1	1
178	1	1
181	1	1
182	1	1
185	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
195	1	1
196	1	1
203	1	1
204	1	1
210	1	1
211	1	1
212	1	1
214	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
			MISSING_ELSE
235	1	1
245	1	1
249	1	1
250	1	1
			MISSING_ELSE
256	1	1
257	1	1
265	1	1
267	1	1
271	1	1
273	1	1
277	1	1
281	1	1
284	1	1
286	1	1
288	0	1
289	0	1
293	1	1
298	1	1
299	1	1
			MISSING_ELSE
305	1	1
322	1	1
323	1	1
			MISSING_ELSE
			MISSING_ELSE
336	1	1
337	1	1
354	1	1
355	1	1
356	1	1
357	1	1
			MISSING_ELSE
360	1	1
363	1	1
370	1	1
371	1	1
373	1	1
379	1	1
383	1	1
384	1	1
385	1	1
			MISSING_ELSE
390	1	1
391	1	1
392	1	1
393	1	1
395	1	1
			MISSING_ELSE
403	1	1
404	1	1
406	1	1
417	1	1
418	1	1
424	1	1
427	1	1
429	1	1
430	1	1
			MISSING_ELSE
438	1	1
439	1	1
440	1	1
441	1	1
			MISSING_ELSE
444	1	1
454	1	1
455	1	1
459	1	1
465	1	1
468	1	1
471	1	1
473	1	1
476	0	1
477	0	1
481	1	1
482	1	1
492	1	1
496	1	1
497	1	1
498	1	1
501	1	1
505	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
			MISSING_ELSE
516	1	1
521	1	1
526	1	1
527	1	1
539	1	1
540	1	1
546	1	1
547	1	1
548	1	1
			MISSING_ELSE
556	3	3
557	3	3
558	3	3
561	1	1
562	1	1
564	1	1
580	1	1
581	1	1
582	1	1
584	1	1
587	1	1
591	1	1
638	1	1
639	1	1
640	1	1
649	1	1
651	1	1
653	1	1
656	1	1
657	1	1
			MISSING_ELSE
659	1	1
660	1	1
			MISSING_ELSE
663	1	1
664	1	1
			MISSING_ELSE
666	1	1
667	1	1
			MISSING_ELSE
670	1	1
671	1	1
			MISSING_ELSE
673	1	1
674	1	1
			MISSING_ELSE
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
690	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
697	1	1
698	1	1
704	1	1
708	1	1
712	1	1
714	1	1
721	1	1
852	3	3

---

Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Covered	Percent
Conditions	88	79	89.77
Logical	88	79	89.77
Non-Logical	0	0
Event	0	0

 LINE       223
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T19,T5
1	1	Covered	T1,T2,T3

 LINE       256
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T49

 LINE       265
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i)
             -----------1----------    ----------2----------    -----3-----

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T14,T43,T44
-	1	1	Covered	T14,T43,T44

 LINE       267
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T14,T43,T45

 LINE       267
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Covered	T14,T45,T48
1	Covered	T14,T43,T44

 LINE       267
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T14,T44,T45
1	Covered	T14,T43,T45

 LINE       271
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T14,T43,T45

 LINE       277
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests
0	Covered	T14,T43,T45
1	Not Covered

 LINE       277
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Covered	T14,T43,T45
1	Not Covered

 LINE       383
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T13

 LINE       424
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Covered	T1,T11,T18
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       424
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T1,T2,T3

 LINE       438
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T12

 LINE       465
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       465
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       468
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T4,T5,T53

 LINE       501
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T54,T55,T56
1	0	Covered	T57,T58,T59

 LINE       501
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off)))
                 -----------------------------------1----------------------------------    ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T13
1	0	Covered	T1,T3,T11
1	1	Covered	T57,T58,T59

 LINE       501
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T3,T11

 LINE       501
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))
                 -------------1-------------    --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T57,T58,T59
1	0	Not Covered

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T12,T13

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_ack[1] != Off)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T12,T13

 LINE       501
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On)))
                 -----------------------------------1----------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T12,T13
1	1	Covered	T54,T55,T56

 LINE       501
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T12,T13

 LINE       501
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T13
0	1	Covered	T54,T55,T56
1	0	Not Covered

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T3,T11

 LINE       501
 SUB-EXPRESSION (lc_flash_rma_ack[1] != On)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T3,T11

 LINE       539
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T3,T11

 LINE       546
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T19,T4
1	1	Covered	T3,T13,T16

 LINE       546
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T4
1	0	Covered	T3,T13,T16

 LINE       546
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       584
 SUB-EXPRESSION (set_strap_en_override || gen_strap_delay_regs.strap_en_override_q[0])
                 ----------1----------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T43,T45
1	0	Covered	T14,T43,T45

 LINE       704
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       704
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T7,T8,T10
1	1	Covered	T1,T2,T3

 LINE       708
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       708
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T7,T8,T10
1	1	Covered	T1,T2,T3

 LINE       721
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T60
1	0	Covered	T1,T11,T14

 LINE       721
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T60

---

FSM Coverage for Instance : tb.dut.u_lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	35	35	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	299	Covered	T61
CntIncrSt	357	Covered	T61
CntProgSt	373	Covered	T61
EscalateSt	540	Covered	T61
FlashRmaSt	427	Covered	T61
IdleSt	224	Covered	T61
InvalidSt	547	Covered	T61
PostTransSt	289	Covered	T61
ResetSt	218	Covered	T61
ScrapSt	257	Covered	T61
TokenCheck0St	441	Covered	T61
TokenCheck1St	473	Covered	T61
TokenHashSt	406	Covered	T61
TransCheckSt	395	Covered	T61
TransProgSt	471	Covered	T61

transitions	Line No.	Covered	Tests	Exclude Annotation
ClkMuxSt->CntIncrSt	357	Covered	T61
ClkMuxSt->EscalateSt	540	Covered	T61
ClkMuxSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->CntProgSt	373	Covered	T61
CntIncrSt->EscalateSt	540	Covered	T61
CntIncrSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->PostTransSt	371	Covered	T61
CntProgSt->EscalateSt	540	Covered	T61
CntProgSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntProgSt->PostTransSt	384	Covered	T61
CntProgSt->TransCheckSt	395	Covered	T61
EscalateSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
FlashRmaSt->EscalateSt	540	Covered	T61
FlashRmaSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
FlashRmaSt->TokenCheck0St	441	Covered	T61
IdleSt->ClkMuxSt	299	Covered	T61
IdleSt->EscalateSt	540	Covered	T61
IdleSt->InvalidSt	547	Covered	T61
IdleSt->PostTransSt	289	Covered	T61
IdleSt->ScrapSt	257	Covered	T61
InvalidSt->EscalateSt	540	Covered	T61
PostTransSt->EscalateSt	540	Covered	T61
PostTransSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ResetSt->EscalateSt	540	Covered	T61
ResetSt->IdleSt	224	Covered	T61
ResetSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ScrapSt->EscalateSt	540	Covered	T61
ScrapSt->InvalidSt	547	Covered	T61
TokenCheck0St->EscalateSt	540	Covered	T61
TokenCheck0St->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck0St->PostTransSt	455	Covered	T61
TokenCheck0St->TokenCheck1St	473	Covered	T61
TokenCheck1St->EscalateSt	540	Covered	T61
TokenCheck1St->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck1St->PostTransSt	455	Covered	T61
TokenCheck1St->TransProgSt	471	Covered	T61
TokenHashSt->EscalateSt	540	Covered	T61
TokenHashSt->FlashRmaSt	427	Covered	T61
TokenHashSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenHashSt->PostTransSt	429	Covered	T61
TransCheckSt->EscalateSt	540	Covered	T61
TransCheckSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransCheckSt->PostTransSt	404	Covered	T61
TransCheckSt->TokenHashSt	406	Covered	T61
TransProgSt->EscalateSt	540	Covered	T61
TransProgSt->InvalidSt	547	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransProgSt->PostTransSt	497	Covered	T61

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	12	57.14	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Not Covered
LcStProd	93	Not Covered
LcStProdEnd	94	Not Covered
LcStRaw	267	Covered	T61
LcStRma	305	Not Covered
LcStScrap	256	Not Covered
LcStTestLocked0	305	Covered	T61
LcStTestLocked1	305	Covered	T61
LcStTestLocked2	305	Covered	T61
LcStTestLocked3	305	Covered	T61
LcStTestLocked4	305	Covered	T61
LcStTestLocked5	305	Not Covered
LcStTestLocked6	305	Not Covered
LcStTestUnlocked0	273	Covered	T61
LcStTestUnlocked1	305	Covered	T61
LcStTestUnlocked2	305	Covered	T61
LcStTestUnlocked3	305	Covered	T61
LcStTestUnlocked4	305	Covered	T61
LcStTestUnlocked5	305	Covered	T61
LcStTestUnlocked6	305	Not Covered
LcStTestUnlocked7	305	Not Covered

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	273	Covered	T61

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	6	24.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	277	Covered	T61
LcCnt1	277	Covered	T61
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Covered	T61
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Covered	T61
LcCnt4	106	Covered	T61
LcCnt5	107	Covered	T61
LcCnt6	108	Not Covered
LcCnt7	109	Not Covered
LcCnt8	110	Not Covered
LcCnt9	111	Not Covered

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	277	Covered	T61

---

Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		75	72	96.00
TERNARY	704	1	1	100.00
TERNARY	708	1	1	100.00
CASE	214	46	43	93.48
IF	539	3	3	100.00
IF	556	2	2	100.00
IF	557	2	2	100.00
IF	558	2	2	100.00
IF	561	2	2	100.00
IF	656	2	2	100.00
IF	659	2	2	100.00
IF	663	2	2	100.00
IF	666	2	2	100.00
IF	670	2	2	100.00
IF	673	2	2	100.00
IF	852	2	2	100.00
IF	580	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	704	(((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	708	(((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	214	case (fsm_state_q)
-2-:	223	if ((init_req_i && lc_state_valid_q))
-3-:	245	if (((!((SecVolatileRawUnlockEn && (lc_state_q == LcStTestUnlocked0)) && (lc_cnt_q != LcCnt0))) || prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)))
-4-:	256	if ((lc_state_q == LcStScrap))
-5-:	265	if (((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i))
-6-:	267	if ((((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})) && (!trans_invalid_error_o)))
-7-:	271	if ((unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed))
-8-:	277	((lc_cnt_q == LcCnt0)) ? 
-9-:	298	if (trans_cmd_i)
-10-:	305	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-11-:	322	if (use_ext_clock_i)
-12-:	337	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-13-:	354	if (use_ext_clock_i)
-14-:	356	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_ack[0]))
-15-:	370	if (trans_cnt_oflw_error_o)
-16-:	383	if ((lc_clk_byp_req_o != lc_clk_byp_ack[1]))
-17-:	390	if (otp_prog_ack_i)
-18-:	391	if (otp_prog_err_i)
-19-:	403	if (trans_invalid_error_o)
-20-:	418	if (token_hash_ack_i)
-21-:	424	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-22-:	438	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}))
-23-:	440	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack[0]))
-24-:	454	if (trans_invalid_error_o)
-25-:	459	if (((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_ack[1])) || (((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack[1]))))
-26-:	465	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-27-:	468	if ((fsm_state_q == TokenCheck1St))
-28-:	496	if ((lc_clk_byp_req_o != lc_clk_byp_ack[2]))
-29-:	501	if ((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack[1] != Off))) || ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack[1] != On)))))
-30-:	507	if (otp_prog_ack_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T43,T45
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T5,T49
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T43,T45
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T44,T45
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T50
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T50
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T62,T63,T64
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T18
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T13
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T4,T65
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T1,T2,T12
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Covered	T1,T2,T12
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T60,T66
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T1,T2,T3
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T1,T2,T3
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T11,T13
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T5,T53
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T54,T55,T56
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T1,T3,T11
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T1,T3,T11
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T19

	LineNo.	Expression
-1-:	539	if ((esc_scrap_state0_i || esc_scrap_state1_i))
-2-:	546	if ((((|state_invalid_error) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T11
0	1	Covered	T3,T13,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	656	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	659	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	663	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[2]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	666	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[3]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	670	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	673	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T51,T54

	LineNo.	Expression
-1-:	852	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	580	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClkBypStaysOnOnceAsserted_A	61339496	3299480	0	80
EscStaysOnOnceAsserted_A	61339496	11516466	0	8
FlashRmaStaysOnOnceAsserted_A	61339496	424716	0	11
FsmStateKnown_A	61339496	58174010	0	0
LcCntKnown_A	61339496	58174010	0	0
LcStateKnown_A	61339496	58174010	0	0
NoClkBypInProdStates_A	61339496	7967182	0	0
SecCmCFILinear_A	61339496	0	0	1950
SecCmCFITerminal0_A	61339496	9023562	0	0
SecCmCFITerminal1_A	61339496	44053	0	0
SecCmCFITerminal2_A	61339496	4817564	0	0
SecCmCFITerminal3_A	61339496	6667679	0	0
u_cnt_regs_A	56665512	53767127	0	0
u_fsm_state_regs_A	59932703	56848208	0	0
u_state_regs_A	57719713	54807144	0	0

ClkBypStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	3299480	0	80
T4	441927	13472	0	0
T5	137387	1819	0	0
T6	92204	0	0	0
T7	0	58902	0	1
T8	0	0	0	1
T9	0	0	0	1
T20	0	32501	0	0
T21	0	36285	0	0
T22	0	42065	0	0
T24	0	36665	0	0
T25	0	3617	0	0
T26	1874	0	0	0
T27	26453	0	0	0
T30	0	0	0	1
T42	0	0	0	1
T50	5733	338	0	0
T52	86944	0	0	0
T62	0	1657	0	1
T65	7671	0	0	0
T67	1267	0	0	0
T68	24291	0	0	0
T69	0	0	0	1
T70	0	0	0	1
T71	0	0	0	1
T72	0	0	0	1

EscStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	11516466	0	8
T1	19896	516	0	0
T2	20231	0	0	0
T3	8520	1636	0	0
T11	31684	1946	0	0
T12	49297	20114	0	0
T13	27450	5370	0	0
T14	1447	0	0	0
T15	9316	2702	0	0
T16	23267	14853	0	0
T17	1436	0	0	0
T18	0	1433	0	0
T19	0	1426	0	0
T51	0	4827	0	0
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1
T77	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1

FlashRmaStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	424716	0	11
T1	19896	1103	0	0
T2	20231	529	0	0
T3	8520	0	0	0
T4	0	4990	0	0
T5	0	4667	0	0
T11	31684	0	0	0
T12	49297	369	0	0
T13	27450	488	0	0
T14	1447	0	0	0
T15	9316	0	0	0
T16	23267	0	0	0
T17	1436	0	0	0
T18	0	462	0	0
T25	0	0	0	1
T49	0	744	0	0
T51	0	236	0	0
T81	0	813	0	0
T82	0	0	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1
T88	0	0	0	1
T89	0	0	0	1
T90	0	0	0	1

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	58174010	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	8520	7468	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	23267	19087	0	0
T17	1436	1365	0	0

LcCntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	58174010	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	8520	7468	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	23267	19087	0	0
T17	1436	1365	0	0

LcStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	58174010	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	8520	7468	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	23267	19087	0	0
T17	1436	1365	0	0

NoClkBypInProdStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	7967182	0	0
T1	19896	1260	0	0
T2	20231	2504	0	0
T3	8520	1460	0	0
T11	31684	3320	0	0
T12	49297	6287	0	0
T13	27450	3495	0	0
T14	1447	0	0	0
T15	9316	1662	0	0
T16	23267	2271	0	0
T17	1436	0	0	0
T18	0	5522	0	0
T19	0	885	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	0	0	1950

SecCmCFITerminal0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	9023562	0	0
T1	19896	9793	0	0
T2	20231	9413	0	0
T3	8520	2107	0	0
T11	31684	12155	0	0
T12	49297	3	0	0
T13	27450	6911	0	0
T14	1447	1291	0	0
T15	9316	1616	0	0
T16	23267	0	0	0
T17	1436	0	0	0
T18	0	11485	0	0
T43	0	792	0	0

SecCmCFITerminal1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	44053	0	0
T5	0	1243	0	0
T12	49297	12	0	0
T13	27450	0	0	0
T14	1447	0	0	0
T15	9316	0	0	0
T16	23267	0	0	0
T17	1436	0	0	0
T18	51894	0	0	0
T19	5347	0	0	0
T22	0	1345	0	0
T29	0	6	0	0
T39	0	6	0	0
T40	0	1	0	0
T43	1237	0	0	0
T49	0	3	0	0
T50	0	31	0	0
T81	0	6	0	0
T91	0	3	0	0
T92	713	0	0	0

SecCmCFITerminal2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	4817564	0	0
T1	19896	520	0	0
T2	20231	0	0	0
T3	8520	1007	0	0
T11	31684	1961	0	0
T12	49297	20192	0	0
T13	27450	3497	0	0
T14	1447	0	0	0
T15	9316	2722	0	0
T16	23267	6784	0	0
T17	1436	0	0	0
T18	0	1444	0	0
T19	0	1021	0	0
T51	0	3154	0	0

SecCmCFITerminal3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61339496	6667679	0	0
T3	8520	631	0	0
T4	0	5965	0	0
T5	0	20950	0	0
T11	31684	0	0	0
T12	49297	0	0	0
T13	27450	1899	0	0
T14	1447	0	0	0
T15	9316	0	0	0
T16	23267	8099	0	0
T17	1436	0	0	0
T18	51894	0	0	0
T19	0	408	0	0
T20	0	103431	0	0
T22	0	128962	0	0
T27	0	8396	0	0
T43	1237	0	0	0
T51	0	1696	0	0

u_cnt_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56665512	53767127	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	7451	6556	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	12802	10342	0	0
T17	1436	1365	0	0

u_fsm_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59932703	56848208	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	8027	7041	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	20973	17135	0	0
T17	1436	1365	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57719713	54807144	0	0
T1	19896	14899	0	0
T2	20231	15364	0	0
T3	7669	6752	0	0
T11	31684	25380	0	0
T12	49297	42100	0	0
T13	27450	22677	0	0
T14	1447	1357	0	0
T15	9316	7677	0	0
T16	17978	14819	0	0
T17	1436	1365	0	0