Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.97 97.29 95.61 91.98 97.67 95.93 98.48 94.82


Total test records in report: 984
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T758 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2233054075 Jan 21 10:29:10 PM PST 24 Jan 21 10:29:43 PM PST 24 576073899 ps
T759 /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.150609570 Jan 21 10:24:16 PM PST 24 Jan 21 10:24:30 PM PST 24 1137932658 ps
T760 /workspace/coverage/default/9.lc_ctrl_jtag_priority.290361998 Jan 21 10:23:28 PM PST 24 Jan 21 10:23:41 PM PST 24 1076647608 ps
T761 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.770849340 Jan 21 10:23:58 PM PST 24 Jan 21 10:24:14 PM PST 24 257851425 ps
T762 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.632432346 Jan 21 10:25:23 PM PST 24 Jan 21 10:25:43 PM PST 24 502733020 ps
T763 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1411975462 Jan 21 10:42:07 PM PST 24 Jan 21 10:42:22 PM PST 24 523538278 ps
T764 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1917254574 Jan 21 10:26:26 PM PST 24 Jan 21 10:26:59 PM PST 24 724902403 ps
T765 /workspace/coverage/default/46.lc_ctrl_jtag_access.224890510 Jan 21 10:29:43 PM PST 24 Jan 21 10:29:58 PM PST 24 1843096355 ps
T766 /workspace/coverage/default/33.lc_ctrl_errors.1127861782 Jan 21 10:27:40 PM PST 24 Jan 21 10:28:06 PM PST 24 3304305705 ps
T88 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2937741194 Jan 21 10:23:33 PM PST 24 Jan 21 10:23:42 PM PST 24 1494154801 ps
T767 /workspace/coverage/default/34.lc_ctrl_prog_failure.1368480524 Jan 21 10:27:49 PM PST 24 Jan 21 10:28:04 PM PST 24 207315307 ps
T768 /workspace/coverage/default/35.lc_ctrl_smoke.397728920 Jan 21 10:27:55 PM PST 24 Jan 21 10:28:07 PM PST 24 35044548 ps
T769 /workspace/coverage/default/28.lc_ctrl_alert_test.2449759005 Jan 21 10:26:57 PM PST 24 Jan 21 10:27:15 PM PST 24 61252957 ps
T770 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1848412015 Jan 21 11:44:32 PM PST 24 Jan 21 11:44:47 PM PST 24 2677142843 ps
T771 /workspace/coverage/default/27.lc_ctrl_jtag_access.2496316453 Jan 21 10:26:39 PM PST 24 Jan 21 10:27:07 PM PST 24 774459656 ps
T772 /workspace/coverage/default/46.lc_ctrl_stress_all.1693539640 Jan 21 10:57:21 PM PST 24 Jan 21 10:59:33 PM PST 24 63085286515 ps
T773 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.636125928 Jan 21 10:29:21 PM PST 24 Jan 21 10:29:44 PM PST 24 1971462135 ps
T774 /workspace/coverage/default/42.lc_ctrl_alert_test.1488607524 Jan 21 10:29:07 PM PST 24 Jan 21 10:29:20 PM PST 24 19187208 ps
T775 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2548790682 Jan 21 10:21:33 PM PST 24 Jan 21 10:21:46 PM PST 24 563698016 ps
T776 /workspace/coverage/default/15.lc_ctrl_state_failure.3965742985 Jan 21 10:24:28 PM PST 24 Jan 21 10:25:02 PM PST 24 576085902 ps
T777 /workspace/coverage/default/46.lc_ctrl_prog_failure.2370872194 Jan 21 10:29:40 PM PST 24 Jan 21 10:29:47 PM PST 24 398069715 ps
T778 /workspace/coverage/default/20.lc_ctrl_smoke.3157238014 Jan 21 10:25:24 PM PST 24 Jan 21 10:25:30 PM PST 24 36536713 ps
T779 /workspace/coverage/default/41.lc_ctrl_stress_all.1202776347 Jan 21 10:29:04 PM PST 24 Jan 21 10:37:28 PM PST 24 15013515014 ps
T780 /workspace/coverage/default/22.lc_ctrl_stress_all.1434482471 Jan 21 10:25:56 PM PST 24 Jan 21 10:27:18 PM PST 24 1676115420 ps
T781 /workspace/coverage/default/32.lc_ctrl_errors.1424855556 Jan 21 10:27:26 PM PST 24 Jan 21 10:28:00 PM PST 24 1195265559 ps
T782 /workspace/coverage/default/1.lc_ctrl_security_escalation.1778143579 Jan 21 10:21:28 PM PST 24 Jan 21 10:21:51 PM PST 24 346419658 ps
T89 /workspace/coverage/default/14.lc_ctrl_smoke.1586121803 Jan 21 10:24:07 PM PST 24 Jan 21 10:24:14 PM PST 24 71747263 ps
T783 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2217924588 Jan 21 10:23:26 PM PST 24 Jan 21 10:23:45 PM PST 24 1549532613 ps
T784 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2777177381 Jan 21 10:24:30 PM PST 24 Jan 21 10:24:38 PM PST 24 263997221 ps
T785 /workspace/coverage/default/12.lc_ctrl_state_post_trans.3921548543 Jan 21 10:51:31 PM PST 24 Jan 21 10:51:38 PM PST 24 53918835 ps
T786 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4210736857 Jan 21 10:25:52 PM PST 24 Jan 21 10:26:24 PM PST 24 1924243416 ps
T787 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2807395943 Jan 21 10:22:19 PM PST 24 Jan 21 10:22:30 PM PST 24 12142933 ps
T788 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1132993655 Jan 21 10:22:46 PM PST 24 Jan 21 10:23:02 PM PST 24 1259938617 ps
T789 /workspace/coverage/default/9.lc_ctrl_state_post_trans.1522607508 Jan 21 10:23:19 PM PST 24 Jan 21 10:23:33 PM PST 24 374645684 ps
T790 /workspace/coverage/default/32.lc_ctrl_jtag_access.4244386868 Jan 21 10:27:34 PM PST 24 Jan 21 10:28:06 PM PST 24 659503206 ps
T791 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2644017924 Jan 21 10:24:55 PM PST 24 Jan 21 10:25:23 PM PST 24 2439534363 ps
T792 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1853676860 Jan 21 10:22:27 PM PST 24 Jan 21 10:22:46 PM PST 24 272305865 ps
T793 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.4020232581 Jan 21 10:23:36 PM PST 24 Jan 21 10:23:51 PM PST 24 949479876 ps
T794 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2714073562 Jan 21 10:21:33 PM PST 24 Jan 21 10:22:01 PM PST 24 313025309 ps
T795 /workspace/coverage/default/4.lc_ctrl_errors.3149928697 Jan 21 10:22:22 PM PST 24 Jan 21 10:22:45 PM PST 24 296739673 ps
T184 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2662262848 Jan 21 10:22:21 PM PST 24 Jan 21 10:22:33 PM PST 24 19747021 ps
T796 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3133226905 Jan 21 10:29:37 PM PST 24 Jan 21 10:29:49 PM PST 24 265834523 ps
T797 /workspace/coverage/default/5.lc_ctrl_state_post_trans.2718278110 Jan 21 10:22:23 PM PST 24 Jan 21 10:22:36 PM PST 24 177561103 ps
T798 /workspace/coverage/default/40.lc_ctrl_stress_all.3313831597 Jan 21 10:28:53 PM PST 24 Jan 21 10:30:35 PM PST 24 2866502278 ps
T799 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4024274420 Jan 21 10:24:09 PM PST 24 Jan 21 10:24:25 PM PST 24 306366181 ps
T800 /workspace/coverage/default/10.lc_ctrl_prog_failure.2731308352 Jan 21 10:23:35 PM PST 24 Jan 21 10:23:42 PM PST 24 126948095 ps
T801 /workspace/coverage/default/48.lc_ctrl_state_failure.4088902668 Jan 21 10:30:05 PM PST 24 Jan 21 10:30:30 PM PST 24 504382548 ps
T802 /workspace/coverage/default/36.lc_ctrl_smoke.3394537120 Jan 21 10:28:01 PM PST 24 Jan 21 10:28:13 PM PST 24 602454906 ps
T803 /workspace/coverage/default/1.lc_ctrl_errors.1591413486 Jan 21 10:21:25 PM PST 24 Jan 21 10:21:47 PM PST 24 331193153 ps
T804 /workspace/coverage/default/23.lc_ctrl_state_post_trans.3837430213 Jan 21 10:25:58 PM PST 24 Jan 21 10:26:21 PM PST 24 949352722 ps
T805 /workspace/coverage/default/31.lc_ctrl_security_escalation.1978173861 Jan 21 10:27:20 PM PST 24 Jan 21 10:27:49 PM PST 24 886545474 ps
T806 /workspace/coverage/default/7.lc_ctrl_prog_failure.3556308830 Jan 21 10:54:59 PM PST 24 Jan 21 10:55:09 PM PST 24 88262120 ps
T807 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2751790949 Jan 21 10:26:54 PM PST 24 Jan 21 10:27:11 PM PST 24 102309163 ps
T808 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1792843797 Jan 21 10:21:28 PM PST 24 Jan 21 10:21:38 PM PST 24 14070395 ps
T809 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3970249475 Jan 21 10:21:30 PM PST 24 Jan 21 10:23:01 PM PST 24 1853679253 ps
T810 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2209971763 Jan 21 11:11:08 PM PST 24 Jan 21 11:11:19 PM PST 24 364398824 ps
T811 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4145936404 Jan 21 10:22:46 PM PST 24 Jan 21 10:23:04 PM PST 24 279853169 ps
T812 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1035461573 Jan 21 10:52:36 PM PST 24 Jan 21 10:52:52 PM PST 24 981654152 ps
T813 /workspace/coverage/default/29.lc_ctrl_smoke.2851459327 Jan 21 10:26:59 PM PST 24 Jan 21 10:27:18 PM PST 24 24778136 ps
T814 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1983826953 Jan 21 10:42:15 PM PST 24 Jan 21 10:42:19 PM PST 24 111473463 ps
T815 /workspace/coverage/default/32.lc_ctrl_stress_all.3896644507 Jan 21 10:27:28 PM PST 24 Jan 21 10:31:10 PM PST 24 20731613865 ps
T816 /workspace/coverage/default/3.lc_ctrl_claim_transition_if.154713779 Jan 21 10:21:57 PM PST 24 Jan 21 10:22:00 PM PST 24 25980681 ps
T817 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2939120141 Jan 21 10:24:32 PM PST 24 Jan 21 10:24:44 PM PST 24 385426949 ps
T818 /workspace/coverage/default/49.lc_ctrl_alert_test.1947494016 Jan 21 10:30:16 PM PST 24 Jan 21 10:30:28 PM PST 24 14582071 ps
T819 /workspace/coverage/default/28.lc_ctrl_state_post_trans.2282036834 Jan 21 10:26:52 PM PST 24 Jan 21 10:27:16 PM PST 24 69461336 ps
T820 /workspace/coverage/default/15.lc_ctrl_errors.1603698358 Jan 21 10:24:29 PM PST 24 Jan 21 10:24:44 PM PST 24 269649041 ps
T821 /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1336155818 Jan 21 10:27:37 PM PST 24 Jan 21 10:27:53 PM PST 24 39612987 ps
T822 /workspace/coverage/default/30.lc_ctrl_jtag_access.1613102650 Jan 21 10:27:12 PM PST 24 Jan 21 10:27:44 PM PST 24 638228686 ps
T823 /workspace/coverage/default/49.lc_ctrl_smoke.3329120542 Jan 21 10:30:11 PM PST 24 Jan 21 10:30:18 PM PST 24 131788219 ps
T824 /workspace/coverage/default/14.lc_ctrl_jtag_errors.1830871518 Jan 21 10:24:21 PM PST 24 Jan 21 10:24:51 PM PST 24 1550475531 ps
T825 /workspace/coverage/default/25.lc_ctrl_errors.2661664881 Jan 21 10:26:17 PM PST 24 Jan 21 10:26:44 PM PST 24 296352393 ps
T826 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.99966054 Jan 21 10:27:31 PM PST 24 Jan 21 10:27:57 PM PST 24 1423030754 ps
T827 /workspace/coverage/default/17.lc_ctrl_smoke.2276692342 Jan 21 11:21:16 PM PST 24 Jan 21 11:21:19 PM PST 24 37683755 ps
T828 /workspace/coverage/default/30.lc_ctrl_stress_all.1604341878 Jan 21 10:27:13 PM PST 24 Jan 21 10:28:05 PM PST 24 12846755965 ps
T829 /workspace/coverage/default/2.lc_ctrl_state_failure.3542276164 Jan 21 10:21:27 PM PST 24 Jan 21 10:22:10 PM PST 24 511312948 ps
T830 /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3846762023 Jan 21 10:26:14 PM PST 24 Jan 21 10:26:41 PM PST 24 786156299 ps
T831 /workspace/coverage/default/12.lc_ctrl_state_failure.3642474441 Jan 21 10:23:56 PM PST 24 Jan 21 10:24:21 PM PST 24 379354627 ps
T832 /workspace/coverage/default/43.lc_ctrl_security_escalation.1787774134 Jan 21 10:29:09 PM PST 24 Jan 21 10:29:31 PM PST 24 296880873 ps
T833 /workspace/coverage/default/41.lc_ctrl_sec_mubi.2648851748 Jan 21 10:28:58 PM PST 24 Jan 21 10:29:18 PM PST 24 2153746536 ps
T834 /workspace/coverage/default/25.lc_ctrl_state_failure.1279809254 Jan 21 10:26:13 PM PST 24 Jan 21 10:26:52 PM PST 24 350455251 ps
T835 /workspace/coverage/default/33.lc_ctrl_sec_mubi.4130698453 Jan 21 10:27:35 PM PST 24 Jan 21 10:28:03 PM PST 24 4595704467 ps
T836 /workspace/coverage/default/22.lc_ctrl_security_escalation.3366232731 Jan 21 10:25:51 PM PST 24 Jan 21 10:26:16 PM PST 24 1257647592 ps
T837 /workspace/coverage/default/35.lc_ctrl_sec_mubi.219752542 Jan 21 10:28:03 PM PST 24 Jan 21 10:28:23 PM PST 24 346927150 ps
T838 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3146868906 Jan 21 10:23:00 PM PST 24 Jan 21 10:23:22 PM PST 24 318271562 ps
T839 /workspace/coverage/default/44.lc_ctrl_prog_failure.2340943911 Jan 21 10:29:18 PM PST 24 Jan 21 10:29:32 PM PST 24 510566711 ps
T840 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.553850071 Jan 21 10:56:10 PM PST 24 Jan 21 10:56:14 PM PST 24 280596126 ps
T841 /workspace/coverage/default/34.lc_ctrl_sec_mubi.4154100142 Jan 21 10:27:51 PM PST 24 Jan 21 10:28:11 PM PST 24 695576238 ps
T842 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.197819853 Jan 21 10:26:41 PM PST 24 Jan 21 10:27:09 PM PST 24 941739612 ps
T843 /workspace/coverage/default/12.lc_ctrl_errors.1584473313 Jan 21 11:18:21 PM PST 24 Jan 21 11:18:33 PM PST 24 197957209 ps
T78 /workspace/coverage/default/0.lc_ctrl_smoke.1596497780 Jan 21 10:21:07 PM PST 24 Jan 21 10:21:19 PM PST 24 13512123 ps
T844 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3616118771 Jan 21 10:22:32 PM PST 24 Jan 21 10:22:46 PM PST 24 227730661 ps
T845 /workspace/coverage/default/34.lc_ctrl_errors.406560437 Jan 21 10:56:47 PM PST 24 Jan 21 10:56:58 PM PST 24 876419723 ps
T846 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.333106286 Jan 21 10:21:28 PM PST 24 Jan 21 10:21:42 PM PST 24 937832576 ps
T847 /workspace/coverage/default/15.lc_ctrl_prog_failure.999061351 Jan 21 10:24:23 PM PST 24 Jan 21 10:24:28 PM PST 24 42414580 ps
T848 /workspace/coverage/default/11.lc_ctrl_prog_failure.1565016239 Jan 21 10:54:59 PM PST 24 Jan 21 10:55:09 PM PST 24 307471929 ps
T849 /workspace/coverage/default/8.lc_ctrl_jtag_priority.374024167 Jan 21 10:23:07 PM PST 24 Jan 21 10:23:21 PM PST 24 488276431 ps
T850 /workspace/coverage/default/10.lc_ctrl_alert_test.3185881413 Jan 21 10:23:32 PM PST 24 Jan 21 10:23:38 PM PST 24 31915905 ps
T851 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.878169102 Jan 21 10:21:27 PM PST 24 Jan 21 10:21:45 PM PST 24 317468013 ps
T852 /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1469667698 Jan 21 10:22:13 PM PST 24 Jan 21 10:22:39 PM PST 24 4415926579 ps
T853 /workspace/coverage/default/28.lc_ctrl_state_failure.1596793160 Jan 21 10:26:52 PM PST 24 Jan 21 10:27:35 PM PST 24 198458690 ps
T79 /workspace/coverage/default/8.lc_ctrl_stress_all.2317575535 Jan 21 10:23:19 PM PST 24 Jan 21 10:24:09 PM PST 24 3282970328 ps
T854 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3116044024 Jan 21 10:25:17 PM PST 24 Jan 21 10:25:29 PM PST 24 328308203 ps
T855 /workspace/coverage/default/33.lc_ctrl_smoke.1881061762 Jan 21 10:27:42 PM PST 24 Jan 21 10:27:58 PM PST 24 84602448 ps
T856 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2122812912 Jan 21 10:24:51 PM PST 24 Jan 21 10:25:01 PM PST 24 332237268 ps
T857 /workspace/coverage/default/8.lc_ctrl_jtag_errors.1296303906 Jan 21 10:46:20 PM PST 24 Jan 21 10:46:58 PM PST 24 4930832018 ps
T858 /workspace/coverage/default/17.lc_ctrl_jtag_access.3257315102 Jan 21 10:25:00 PM PST 24 Jan 21 10:25:14 PM PST 24 2176876626 ps
T80 /workspace/coverage/default/28.lc_ctrl_smoke.3296113884 Jan 21 10:26:51 PM PST 24 Jan 21 10:27:09 PM PST 24 25211776 ps
T859 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2020846279 Jan 21 10:22:05 PM PST 24 Jan 21 10:22:23 PM PST 24 884643150 ps
T860 /workspace/coverage/default/38.lc_ctrl_errors.89834564 Jan 21 10:28:29 PM PST 24 Jan 21 10:28:51 PM PST 24 425644058 ps
T861 /workspace/coverage/default/16.lc_ctrl_alert_test.1376043693 Jan 21 10:24:42 PM PST 24 Jan 21 10:24:52 PM PST 24 37700260 ps
T862 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2874070328 Jan 21 10:21:24 PM PST 24 Jan 21 10:21:56 PM PST 24 874764475 ps
T863 /workspace/coverage/default/48.lc_ctrl_sec_mubi.2244594161 Jan 21 10:30:11 PM PST 24 Jan 21 10:30:30 PM PST 24 331694782 ps
T864 /workspace/coverage/default/42.lc_ctrl_sec_mubi.1693355255 Jan 21 10:29:16 PM PST 24 Jan 21 10:29:35 PM PST 24 1309766169 ps
T865 /workspace/coverage/default/26.lc_ctrl_jtag_access.4004535011 Jan 21 11:10:14 PM PST 24 Jan 21 11:10:19 PM PST 24 404398384 ps
T866 /workspace/coverage/default/23.lc_ctrl_sec_mubi.2159123243 Jan 21 10:26:01 PM PST 24 Jan 21 10:26:30 PM PST 24 10760133239 ps
T867 /workspace/coverage/default/13.lc_ctrl_state_failure.518221217 Jan 21 10:24:03 PM PST 24 Jan 21 10:24:29 PM PST 24 242464402 ps
T868 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2276215740 Jan 21 10:26:36 PM PST 24 Jan 21 10:26:55 PM PST 24 40836558 ps
T869 /workspace/coverage/default/17.lc_ctrl_state_failure.2550431553 Jan 21 10:24:42 PM PST 24 Jan 21 10:25:08 PM PST 24 727379824 ps
T870 /workspace/coverage/default/44.lc_ctrl_state_post_trans.3027350445 Jan 21 10:29:17 PM PST 24 Jan 21 10:29:31 PM PST 24 121065989 ps
T871 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2574235435 Jan 21 10:26:14 PM PST 24 Jan 21 10:26:41 PM PST 24 3771726174 ps
T872 /workspace/coverage/default/18.lc_ctrl_state_failure.1375322967 Jan 21 10:25:06 PM PST 24 Jan 21 10:25:28 PM PST 24 920050564 ps
T873 /workspace/coverage/default/27.lc_ctrl_state_failure.1566819148 Jan 21 10:26:33 PM PST 24 Jan 21 10:27:12 PM PST 24 170857950 ps
T874 /workspace/coverage/default/40.lc_ctrl_alert_test.1553818537 Jan 21 10:28:54 PM PST 24 Jan 21 10:29:00 PM PST 24 60296964 ps
T875 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2190933556 Jan 21 10:28:21 PM PST 24 Jan 21 10:28:31 PM PST 24 717452834 ps
T876 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.245926683 Jan 21 10:23:55 PM PST 24 Jan 21 10:24:01 PM PST 24 10868025 ps
T877 /workspace/coverage/default/27.lc_ctrl_state_post_trans.2641126391 Jan 21 10:26:33 PM PST 24 Jan 21 10:27:00 PM PST 24 93153756 ps
T878 /workspace/coverage/default/5.lc_ctrl_jtag_access.777690750 Jan 21 10:22:30 PM PST 24 Jan 21 10:22:47 PM PST 24 1454430954 ps
T879 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3992577683 Jan 21 10:24:41 PM PST 24 Jan 21 10:25:03 PM PST 24 390982416 ps
T880 /workspace/coverage/default/0.lc_ctrl_sec_mubi.3565175894 Jan 21 10:21:16 PM PST 24 Jan 21 10:21:42 PM PST 24 1195378357 ps
T881 /workspace/coverage/default/20.lc_ctrl_state_failure.2589093567 Jan 21 10:25:35 PM PST 24 Jan 21 10:26:17 PM PST 24 1094030553 ps
T882 /workspace/coverage/default/41.lc_ctrl_errors.3026345671 Jan 21 10:28:57 PM PST 24 Jan 21 10:29:18 PM PST 24 249517813 ps
T883 /workspace/coverage/default/14.lc_ctrl_state_failure.1607845347 Jan 21 10:50:00 PM PST 24 Jan 21 10:50:33 PM PST 24 256665180 ps
T884 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4060371751 Jan 21 10:29:11 PM PST 24 Jan 21 10:29:23 PM PST 24 112189566 ps
T885 /workspace/coverage/default/20.lc_ctrl_sec_mubi.140486130 Jan 21 10:25:40 PM PST 24 Jan 21 10:26:07 PM PST 24 176830621 ps
T886 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2241668464 Jan 21 10:21:12 PM PST 24 Jan 21 10:23:17 PM PST 24 4114280156 ps
T887 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1380169312 Jan 21 10:29:51 PM PST 24 Jan 21 10:30:17 PM PST 24 1051882231 ps
T888 /workspace/coverage/default/24.lc_ctrl_state_failure.4159919828 Jan 21 10:26:04 PM PST 24 Jan 21 10:26:33 PM PST 24 1270173631 ps
T889 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3711253916 Jan 21 10:28:42 PM PST 24 Jan 21 10:28:52 PM PST 24 20746272 ps
T890 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3673865149 Jan 21 10:27:16 PM PST 24 Jan 21 10:27:42 PM PST 24 273009308 ps
T891 /workspace/coverage/default/49.lc_ctrl_security_escalation.1949945079 Jan 21 10:30:09 PM PST 24 Jan 21 10:30:21 PM PST 24 2566984694 ps
T892 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1057199309 Jan 21 10:22:14 PM PST 24 Jan 21 10:22:27 PM PST 24 621350062 ps
T893 /workspace/coverage/default/45.lc_ctrl_errors.1276009462 Jan 21 10:29:26 PM PST 24 Jan 21 10:29:47 PM PST 24 1105669400 ps
T894 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2459810616 Jan 21 10:29:07 PM PST 24 Jan 21 10:29:20 PM PST 24 47422925 ps
T895 /workspace/coverage/default/40.lc_ctrl_sec_mubi.2263621887 Jan 21 10:28:51 PM PST 24 Jan 21 10:29:09 PM PST 24 4072994658 ps
T896 /workspace/coverage/default/11.lc_ctrl_sec_mubi.2537260030 Jan 21 10:23:40 PM PST 24 Jan 21 10:23:57 PM PST 24 249492715 ps
T90 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2275911948 Jan 21 10:21:52 PM PST 24 Jan 21 10:21:57 PM PST 24 469539478 ps
T897 /workspace/coverage/default/5.lc_ctrl_sec_mubi.545234817 Jan 21 10:52:41 PM PST 24 Jan 21 10:52:59 PM PST 24 1179430006 ps
T898 /workspace/coverage/default/32.lc_ctrl_prog_failure.2910463432 Jan 21 10:27:32 PM PST 24 Jan 21 10:27:53 PM PST 24 340216402 ps
T899 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.836614534 Jan 21 10:24:50 PM PST 24 Jan 21 10:25:18 PM PST 24 602284523 ps
T900 /workspace/coverage/default/2.lc_ctrl_prog_failure.891671679 Jan 21 10:21:34 PM PST 24 Jan 21 10:21:46 PM PST 24 111887426 ps
T901 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.885349880 Jan 21 10:22:28 PM PST 24 Jan 21 10:22:51 PM PST 24 1221052169 ps
T902 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2720718403 Jan 21 10:21:12 PM PST 24 Jan 21 10:21:34 PM PST 24 3793707506 ps
T903 /workspace/coverage/default/20.lc_ctrl_errors.227867031 Jan 21 10:25:35 PM PST 24 Jan 21 10:26:06 PM PST 24 467426776 ps
T904 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1937423843 Jan 21 10:25:35 PM PST 24 Jan 21 10:25:58 PM PST 24 288240044 ps
T905 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2680962820 Jan 21 11:40:54 PM PST 24 Jan 21 11:40:56 PM PST 24 31755911 ps
T906 /workspace/coverage/default/36.lc_ctrl_stress_all.414644090 Jan 21 10:28:18 PM PST 24 Jan 21 10:32:25 PM PST 24 9298383558 ps
T907 /workspace/coverage/default/0.lc_ctrl_errors.3613670140 Jan 21 10:21:06 PM PST 24 Jan 21 10:21:32 PM PST 24 500701291 ps
T908 /workspace/coverage/default/11.lc_ctrl_stress_all.4007202882 Jan 21 10:23:39 PM PST 24 Jan 21 10:26:03 PM PST 24 6477260872 ps
T909 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2201096884 Jan 21 10:27:09 PM PST 24 Jan 21 10:27:27 PM PST 24 35521311 ps
T910 /workspace/coverage/default/11.lc_ctrl_errors.139863071 Jan 21 10:49:34 PM PST 24 Jan 21 10:49:47 PM PST 24 390680268 ps
T911 /workspace/coverage/default/35.lc_ctrl_alert_test.1149070603 Jan 21 10:28:06 PM PST 24 Jan 21 10:28:11 PM PST 24 31168301 ps
T912 /workspace/coverage/default/48.lc_ctrl_errors.71532436 Jan 21 10:30:02 PM PST 24 Jan 21 10:30:16 PM PST 24 3140071809 ps
T913 /workspace/coverage/default/35.lc_ctrl_prog_failure.4143358320 Jan 21 10:27:56 PM PST 24 Jan 21 10:28:07 PM PST 24 51665769 ps
T914 /workspace/coverage/default/21.lc_ctrl_alert_test.1723314928 Jan 21 10:25:44 PM PST 24 Jan 21 10:25:59 PM PST 24 30708536 ps
T915 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1213908015 Jan 21 11:11:29 PM PST 24 Jan 21 11:11:36 PM PST 24 194073838 ps
T916 /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3690761515 Jan 21 10:29:48 PM PST 24 Jan 21 10:29:51 PM PST 24 18450900 ps
T917 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.590722398 Jan 21 10:22:13 PM PST 24 Jan 21 10:22:45 PM PST 24 908799378 ps
T918 /workspace/coverage/default/14.lc_ctrl_state_post_trans.4133338437 Jan 21 10:24:14 PM PST 24 Jan 21 10:24:25 PM PST 24 91303559 ps
T919 /workspace/coverage/default/14.lc_ctrl_security_escalation.3250644698 Jan 21 10:49:37 PM PST 24 Jan 21 10:49:50 PM PST 24 580750682 ps
T920 /workspace/coverage/default/29.lc_ctrl_state_failure.4266196925 Jan 21 10:26:54 PM PST 24 Jan 21 10:27:39 PM PST 24 326232780 ps
T921 /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4080015935 Jan 21 10:25:56 PM PST 24 Jan 21 10:26:21 PM PST 24 311365584 ps
T922 /workspace/coverage/default/40.lc_ctrl_errors.2906373242 Jan 21 10:28:51 PM PST 24 Jan 21 10:29:14 PM PST 24 1122264279 ps
T923 /workspace/coverage/default/24.lc_ctrl_sec_mubi.1982583654 Jan 21 10:26:02 PM PST 24 Jan 21 10:26:25 PM PST 24 599476872 ps
T924 /workspace/coverage/default/9.lc_ctrl_errors.2254000207 Jan 21 10:23:24 PM PST 24 Jan 21 10:23:47 PM PST 24 355797386 ps
T925 /workspace/coverage/default/48.lc_ctrl_smoke.1630613694 Jan 21 10:30:01 PM PST 24 Jan 21 10:30:06 PM PST 24 486980655 ps
T926 /workspace/coverage/default/49.lc_ctrl_stress_all.2716982440 Jan 21 10:55:30 PM PST 24 Jan 21 10:57:08 PM PST 24 14727401550 ps
T927 /workspace/coverage/default/6.lc_ctrl_sec_mubi.2058294399 Jan 21 10:22:42 PM PST 24 Jan 21 10:23:05 PM PST 24 2058677125 ps
T928 /workspace/coverage/default/19.lc_ctrl_smoke.3981519388 Jan 21 10:25:23 PM PST 24 Jan 21 10:25:32 PM PST 24 239540717 ps
T929 /workspace/coverage/default/7.lc_ctrl_sec_mubi.1270186878 Jan 21 11:23:40 PM PST 24 Jan 21 11:24:10 PM PST 24 1411418023 ps
T930 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.808859855 Jan 21 10:21:33 PM PST 24 Jan 21 10:21:53 PM PST 24 7220074439 ps
T931 /workspace/coverage/default/45.lc_ctrl_state_post_trans.530054989 Jan 21 10:29:29 PM PST 24 Jan 21 10:29:43 PM PST 24 178965560 ps
T932 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.653606348 Jan 21 10:22:19 PM PST 24 Jan 21 10:22:42 PM PST 24 286891384 ps
T933 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1614798424 Jan 21 10:22:46 PM PST 24 Jan 21 10:23:11 PM PST 24 1430698380 ps
T934 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2407149304 Jan 21 10:53:31 PM PST 24 Jan 21 10:53:39 PM PST 24 727668603 ps
T935 /workspace/coverage/default/26.lc_ctrl_alert_test.4235503749 Jan 21 10:26:35 PM PST 24 Jan 21 10:26:54 PM PST 24 61158921 ps
T936 /workspace/coverage/default/7.lc_ctrl_state_post_trans.1867727435 Jan 21 10:22:47 PM PST 24 Jan 21 10:23:00 PM PST 24 260410024 ps
T937 /workspace/coverage/default/33.lc_ctrl_prog_failure.3612817271 Jan 21 10:27:41 PM PST 24 Jan 21 10:27:58 PM PST 24 80298101 ps
T938 /workspace/coverage/default/2.lc_ctrl_jtag_access.867194754 Jan 21 10:21:31 PM PST 24 Jan 21 10:21:49 PM PST 24 593917681 ps
T939 /workspace/coverage/default/2.lc_ctrl_jtag_errors.4185104825 Jan 21 10:21:37 PM PST 24 Jan 21 10:22:41 PM PST 24 1872160788 ps
T940 /workspace/coverage/default/5.lc_ctrl_jtag_errors.1238161604 Jan 21 10:53:26 PM PST 24 Jan 21 10:54:53 PM PST 24 6889916919 ps
T941 /workspace/coverage/default/26.lc_ctrl_stress_all.538234275 Jan 21 10:26:28 PM PST 24 Jan 21 10:27:24 PM PST 24 4225239697 ps
T942 /workspace/coverage/default/22.lc_ctrl_smoke.2125155798 Jan 21 10:25:39 PM PST 24 Jan 21 10:26:00 PM PST 24 235504986 ps
T943 /workspace/coverage/default/19.lc_ctrl_prog_failure.2551739363 Jan 21 10:25:24 PM PST 24 Jan 21 10:25:31 PM PST 24 72543096 ps
T944 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3267982719 Jan 21 10:22:25 PM PST 24 Jan 21 10:23:40 PM PST 24 3202955287 ps
T945 /workspace/coverage/default/1.lc_ctrl_jtag_priority.3539104882 Jan 21 10:21:29 PM PST 24 Jan 21 10:21:41 PM PST 24 1565951799 ps
T946 /workspace/coverage/default/24.lc_ctrl_errors.2693666163 Jan 21 10:26:09 PM PST 24 Jan 21 10:26:46 PM PST 24 1261296509 ps
T947 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4198773151 Jan 21 10:23:36 PM PST 24 Jan 21 10:23:42 PM PST 24 332697702 ps
T948 /workspace/coverage/default/16.lc_ctrl_smoke.2610941189 Jan 21 10:24:32 PM PST 24 Jan 21 10:24:39 PM PST 24 65198933 ps
T949 /workspace/coverage/default/43.lc_ctrl_stress_all.2370568058 Jan 21 10:29:13 PM PST 24 Jan 21 10:31:43 PM PST 24 4198809208 ps
T950 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2418926806 Jan 21 10:27:37 PM PST 24 Jan 21 10:28:01 PM PST 24 1363826852 ps
T951 /workspace/coverage/default/8.lc_ctrl_smoke.2119712145 Jan 21 10:22:55 PM PST 24 Jan 21 10:22:59 PM PST 24 29543994 ps
T952 /workspace/coverage/default/12.lc_ctrl_stress_all.3550452970 Jan 21 10:23:52 PM PST 24 Jan 21 10:25:13 PM PST 24 68580839534 ps
T953 /workspace/coverage/default/4.lc_ctrl_jtag_errors.2129530272 Jan 21 10:22:19 PM PST 24 Jan 21 10:23:35 PM PST 24 9512573100 ps
T954 /workspace/coverage/default/11.lc_ctrl_jtag_access.1451913081 Jan 21 10:23:39 PM PST 24 Jan 21 10:23:55 PM PST 24 420590322 ps
T955 /workspace/coverage/default/29.lc_ctrl_stress_all.3813157815 Jan 21 10:27:12 PM PST 24 Jan 21 10:34:50 PM PST 24 13193199285 ps
T956 /workspace/coverage/default/23.lc_ctrl_state_failure.3112818430 Jan 21 10:26:04 PM PST 24 Jan 21 10:26:29 PM PST 24 677399696 ps
T957 /workspace/coverage/default/21.lc_ctrl_prog_failure.3050554493 Jan 21 10:25:37 PM PST 24 Jan 21 10:25:56 PM PST 24 372561388 ps
T958 /workspace/coverage/default/16.lc_ctrl_sec_mubi.306665898 Jan 21 10:24:44 PM PST 24 Jan 21 10:25:09 PM PST 24 1245694126 ps
T959 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2558249408 Jan 21 10:26:55 PM PST 24 Jan 21 10:27:19 PM PST 24 713665026 ps
T960 /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3778640311 Jan 21 10:25:32 PM PST 24 Jan 21 10:30:39 PM PST 24 13923128229 ps
T961 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.844064320 Jan 21 10:24:40 PM PST 24 Jan 21 10:24:54 PM PST 24 390425970 ps
T962 /workspace/coverage/default/43.lc_ctrl_sec_mubi.854109503 Jan 21 10:29:16 PM PST 24 Jan 21 10:29:45 PM PST 24 369319832 ps
T963 /workspace/coverage/default/21.lc_ctrl_smoke.1272089861 Jan 21 10:25:38 PM PST 24 Jan 21 10:25:58 PM PST 24 92011024 ps
T964 /workspace/coverage/default/32.lc_ctrl_security_escalation.3452043473 Jan 21 10:27:25 PM PST 24 Jan 21 10:27:55 PM PST 24 309721973 ps
T965 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2758603130 Jan 21 10:27:46 PM PST 24 Jan 21 10:27:59 PM PST 24 42232539 ps
T966 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4127316373 Jan 21 10:22:01 PM PST 24 Jan 21 10:22:21 PM PST 24 3047010150 ps
T967 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1013583215 Jan 21 10:21:20 PM PST 24 Jan 21 10:21:39 PM PST 24 1165252780 ps
T968 /workspace/coverage/default/20.lc_ctrl_jtag_access.4266150320 Jan 21 10:25:38 PM PST 24 Jan 21 10:25:56 PM PST 24 257936252 ps
T969 /workspace/coverage/default/44.lc_ctrl_stress_all.2311415807 Jan 21 10:29:18 PM PST 24 Jan 21 10:33:46 PM PST 24 7058548353 ps
T970 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3970916101 Jan 21 10:28:06 PM PST 24 Jan 21 10:28:18 PM PST 24 1835759886 ps
T971 /workspace/coverage/default/13.lc_ctrl_smoke.1280051296 Jan 21 10:23:57 PM PST 24 Jan 21 10:24:06 PM PST 24 60106005 ps
T972 /workspace/coverage/default/39.lc_ctrl_state_post_trans.964459135 Jan 21 10:28:34 PM PST 24 Jan 21 10:28:50 PM PST 24 696314842 ps
T973 /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3547741760 Jan 21 10:30:07 PM PST 24 Jan 21 10:30:18 PM PST 24 1139805969 ps
T974 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.500348954 Jan 21 10:27:15 PM PST 24 Jan 21 10:27:42 PM PST 24 277716434 ps
T975 /workspace/coverage/default/10.lc_ctrl_jtag_errors.2355478005 Jan 21 10:23:31 PM PST 24 Jan 21 10:24:30 PM PST 24 1826406233 ps
T976 /workspace/coverage/default/31.lc_ctrl_sec_mubi.4040582969 Jan 21 10:27:16 PM PST 24 Jan 21 10:27:51 PM PST 24 1221954536 ps
T977 /workspace/coverage/default/33.lc_ctrl_security_escalation.3416115518 Jan 21 10:27:42 PM PST 24 Jan 21 10:28:05 PM PST 24 297395594 ps
T978 /workspace/coverage/default/12.lc_ctrl_alert_test.745490985 Jan 21 10:23:54 PM PST 24 Jan 21 10:23:59 PM PST 24 66672058 ps
T979 /workspace/coverage/default/6.lc_ctrl_alert_test.757754719 Jan 21 10:22:44 PM PST 24 Jan 21 10:22:50 PM PST 24 16269237 ps
T980 /workspace/coverage/default/10.lc_ctrl_stress_all.4055230832 Jan 21 10:23:33 PM PST 24 Jan 21 10:32:48 PM PST 24 28556075768 ps
T981 /workspace/coverage/default/4.lc_ctrl_prog_failure.943442613 Jan 21 10:22:13 PM PST 24 Jan 21 10:22:21 PM PST 24 149395336 ps
T982 /workspace/coverage/default/15.lc_ctrl_jtag_errors.1347918139 Jan 21 10:24:30 PM PST 24 Jan 21 10:25:02 PM PST 24 7539353915 ps
T983 /workspace/coverage/default/27.lc_ctrl_smoke.2387669911 Jan 21 10:26:31 PM PST 24 Jan 21 10:26:58 PM PST 24 429047121 ps
T984 /workspace/coverage/default/31.lc_ctrl_alert_test.709353836 Jan 21 10:27:17 PM PST 24 Jan 21 10:27:37 PM PST 24 17969175 ps

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1120876774
Short name T61
Test name
Test status
Simulation time 324844851 ps
CPU time 3 seconds
Started Jan 21 03:05:35 PM PST 24
Finished Jan 21 03:05:40 PM PST 24
Peak memory 212836 kb
Host smart-a6793dbf-1f74-4e6d-9735-35a5c2655a34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120876774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1120876774
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3264846505
Short name T13
Test name
Test status
Simulation time 280123788 ps
CPU time 12.98 seconds
Started Jan 21 10:29:49 PM PST 24
Finished Jan 21 10:30:04 PM PST 24
Peak memory 217332 kb
Host smart-2c163f8f-4596-4ef7-89c1-cc2cacc6c641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264846505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3264846505
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3368896135
Short name T22
Test name
Test status
Simulation time 52911137597 ps
CPU time 451.62 seconds
Started Jan 21 10:29:52 PM PST 24
Finished Jan 21 10:37:25 PM PST 24
Peak memory 332684 kb
Host smart-61a65605-a8a5-4aff-8e84-7265d3c538d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3368896135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3368896135
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1308216901
Short name T129
Test name
Test status
Simulation time 109730540 ps
CPU time 3.1 seconds
Started Jan 21 03:05:08 PM PST 24
Finished Jan 21 03:05:13 PM PST 24
Peak memory 210360 kb
Host smart-be68614b-acf9-4f3c-8e75-824bc2f94724
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308216901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1308216901
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.805846697
Short name T131
Test name
Test status
Simulation time 144527262 ps
CPU time 3.21 seconds
Started Jan 21 03:05:41 PM PST 24
Finished Jan 21 03:05:45 PM PST 24
Peak memory 217728 kb
Host smart-8602fcda-52d7-4a60-92bb-f4bb7baf953b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805846697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.805846697
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3477497481
Short name T49
Test name
Test status
Simulation time 1504554530 ps
CPU time 11 seconds
Started Jan 21 10:26:16 PM PST 24
Finished Jan 21 10:26:45 PM PST 24
Peak memory 217160 kb
Host smart-db921871-0de7-4568-9cc3-7d228a0a84ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477497481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3477497481
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2918139224
Short name T161
Test name
Test status
Simulation time 37438974 ps
CPU time 1.42 seconds
Started Jan 21 03:04:25 PM PST 24
Finished Jan 21 03:04:27 PM PST 24
Peak memory 208512 kb
Host smart-a425665f-3775-425b-a7bb-fe34eb26b386
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918139224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2918139224
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3904705653
Short name T2
Test name
Test status
Simulation time 1556297423 ps
CPU time 6.72 seconds
Started Jan 21 10:29:03 PM PST 24
Finished Jan 21 10:29:23 PM PST 24
Peak memory 217312 kb
Host smart-09ebeb91-0232-43ae-ab89-7cf909ddbf11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904705653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3904705653
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.495797743
Short name T14
Test name
Test status
Simulation time 14501489 ps
CPU time 0.83 seconds
Started Jan 21 10:22:43 PM PST 24
Finished Jan 21 10:22:50 PM PST 24
Peak memory 207484 kb
Host smart-bd0b9585-13d4-43f4-8d4d-29feb6c50f05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495797743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.495797743
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3807122067
Short name T331
Test name
Test status
Simulation time 19357303533 ps
CPU time 169.36 seconds
Started Jan 21 10:30:12 PM PST 24
Finished Jan 21 10:33:10 PM PST 24
Peak memory 268392 kb
Host smart-3362c138-e8f0-434a-8383-e8aa6268c6c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807122067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3807122067
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1038444533
Short name T99
Test name
Test status
Simulation time 24418992 ps
CPU time 1.28 seconds
Started Jan 21 03:05:20 PM PST 24
Finished Jan 21 03:05:25 PM PST 24
Peak memory 217628 kb
Host smart-a320226b-8f52-4c60-ad1b-0ea98a94bd48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038444533 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1038444533
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.4137958029
Short name T40
Test name
Test status
Simulation time 1299085026 ps
CPU time 38.08 seconds
Started Jan 21 10:22:20 PM PST 24
Finished Jan 21 10:23:08 PM PST 24
Peak memory 268468 kb
Host smart-63a04dd5-a796-4210-8a1d-f345928da2e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137958029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.4137958029
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3512805203
Short name T334
Test name
Test status
Simulation time 1738027745 ps
CPU time 15.37 seconds
Started Jan 21 10:28:04 PM PST 24
Finished Jan 21 10:28:24 PM PST 24
Peak memory 217300 kb
Host smart-bfe4db6c-338c-4cc7-b738-6212065a4d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512805203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3512805203
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1247405701
Short name T101
Test name
Test status
Simulation time 155992900 ps
CPU time 2.27 seconds
Started Jan 21 03:05:16 PM PST 24
Finished Jan 21 03:05:20 PM PST 24
Peak memory 221364 kb
Host smart-f5570c57-178e-4980-b4c1-2c93e3f0dce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247405701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1247405701
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.898407518
Short name T42
Test name
Test status
Simulation time 9122360567 ps
CPU time 178.48 seconds
Started Jan 21 10:54:14 PM PST 24
Finished Jan 21 10:57:13 PM PST 24
Peak memory 267980 kb
Host smart-c6983e66-e239-4241-8226-519510872ad0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898407518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.898407518
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1410917784
Short name T321
Test name
Test status
Simulation time 16878998 ps
CPU time 0.92 seconds
Started Jan 21 10:21:25 PM PST 24
Finished Jan 21 10:21:34 PM PST 24
Peak memory 208860 kb
Host smart-9e69c1a1-a3ff-4cba-a960-c48a9e59c9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410917784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1410917784
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3851006926
Short name T112
Test name
Test status
Simulation time 202381412 ps
CPU time 3.34 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:23 PM PST 24
Peak memory 221268 kb
Host smart-7688c9e4-3b46-4497-8773-6e52e54db82e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851006926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3851006926
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.220151521
Short name T5
Test name
Test status
Simulation time 1401921678 ps
CPU time 51.13 seconds
Started Jan 21 10:21:34 PM PST 24
Finished Jan 21 10:22:35 PM PST 24
Peak memory 245780 kb
Host smart-9bacc8fc-65da-4a83-93e2-e8a3b6ee54db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220151521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.220151521
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3775729548
Short name T58
Test name
Test status
Simulation time 875359075 ps
CPU time 11.49 seconds
Started Jan 21 10:21:31 PM PST 24
Finished Jan 21 10:21:52 PM PST 24
Peak memory 217352 kb
Host smart-a21decb4-a0b8-4a30-a2b9-4b229064befd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775729548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3775729548
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4173630746
Short name T110
Test name
Test status
Simulation time 105723298 ps
CPU time 2.93 seconds
Started Jan 21 03:05:21 PM PST 24
Finished Jan 21 03:05:27 PM PST 24
Peak memory 221332 kb
Host smart-da975f5a-bde0-4771-813d-8ff86d456def
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173630746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.4173630746
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2439740401
Short name T7
Test name
Test status
Simulation time 1175728599 ps
CPU time 16.13 seconds
Started Jan 21 10:25:18 PM PST 24
Finished Jan 21 10:25:37 PM PST 24
Peak memory 208968 kb
Host smart-3056b609-9927-4cd8-9216-68922bc67465
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439740401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.2439740401
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2668079511
Short name T155
Test name
Test status
Simulation time 825232350 ps
CPU time 2.99 seconds
Started Jan 21 03:04:59 PM PST 24
Finished Jan 21 03:05:03 PM PST 24
Peak memory 210740 kb
Host smart-07def3ce-4235-4a38-aafd-bb8653b96a82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668079511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2668079511
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1900877891
Short name T63
Test name
Test status
Simulation time 67644813114 ps
CPU time 603.54 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:32:21 PM PST 24
Peak memory 282812 kb
Host smart-e5160a8e-3929-4cd8-a595-da228792904b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900877891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1900877891
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1239206688
Short name T100
Test name
Test status
Simulation time 29641022 ps
CPU time 1.01 seconds
Started Jan 21 03:05:08 PM PST 24
Finished Jan 21 03:05:11 PM PST 24
Peak memory 209532 kb
Host smart-7c09bad2-e1e4-4412-9c81-64efffaea111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239206688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1239206688
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2675925177
Short name T141
Test name
Test status
Simulation time 72038087 ps
CPU time 2.93 seconds
Started Jan 21 03:05:21 PM PST 24
Finished Jan 21 03:05:27 PM PST 24
Peak memory 221368 kb
Host smart-ed0ff5a9-877a-47eb-a83a-78ba330d4eec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675925177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2675925177
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3405309857
Short name T239
Test name
Test status
Simulation time 135887240 ps
CPU time 2.41 seconds
Started Jan 21 03:04:03 PM PST 24
Finished Jan 21 03:04:11 PM PST 24
Peak memory 217832 kb
Host smart-6cd97ebc-c462-4639-aeba-20e594017b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405309857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3405309857
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.694657249
Short name T490
Test name
Test status
Simulation time 1146016585 ps
CPU time 14.1 seconds
Started Jan 21 10:24:30 PM PST 24
Finished Jan 21 10:24:47 PM PST 24
Peak memory 218336 kb
Host smart-62111f3b-a600-48e5-af87-cb8252a55fe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694657249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.694657249
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2917183501
Short name T412
Test name
Test status
Simulation time 14502215 ps
CPU time 0.79 seconds
Started Jan 21 10:23:27 PM PST 24
Finished Jan 21 10:23:33 PM PST 24
Peak memory 207280 kb
Host smart-1895f599-35e8-49cb-a711-e44fb9da5a4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917183501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2917183501
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.659714220
Short name T12
Test name
Test status
Simulation time 912978202 ps
CPU time 11.9 seconds
Started Jan 21 10:21:08 PM PST 24
Finished Jan 21 10:21:31 PM PST 24
Peak memory 217312 kb
Host smart-a603c0e5-35e5-4a9d-b8a5-eac427f7de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659714220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.659714220
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2777404228
Short name T137
Test name
Test status
Simulation time 238485806 ps
CPU time 2.95 seconds
Started Jan 21 03:04:27 PM PST 24
Finished Jan 21 03:04:32 PM PST 24
Peak memory 221512 kb
Host smart-7dd377fb-84e9-4f8e-83b5-91e521fdf357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777404228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2777404228
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.223043651
Short name T138
Test name
Test status
Simulation time 239118698 ps
CPU time 2.55 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:22 PM PST 24
Peak memory 212200 kb
Host smart-4b40030e-1e0d-4956-8488-02a64a62954e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223043651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.223043651
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3402723327
Short name T148
Test name
Test status
Simulation time 57520567 ps
CPU time 1.82 seconds
Started Jan 21 03:04:18 PM PST 24
Finished Jan 21 03:04:21 PM PST 24
Peak memory 212124 kb
Host smart-dec36930-b20d-45c8-a621-4f89e849cdb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402723327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3402723327
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.4137403704
Short name T185
Test name
Test status
Simulation time 36333702 ps
CPU time 0.9 seconds
Started Jan 21 10:21:17 PM PST 24
Finished Jan 21 10:21:30 PM PST 24
Peak memory 207456 kb
Host smart-04cf83bb-7d0e-4771-97f7-a4822fa64256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137403704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4137403704
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2916326078
Short name T320
Test name
Test status
Simulation time 98786431 ps
CPU time 2.4 seconds
Started Jan 21 10:21:10 PM PST 24
Finished Jan 21 10:21:27 PM PST 24
Peak memory 217324 kb
Host smart-5ae91196-56c9-4447-b7ee-5453dd28f88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916326078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2916326078
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.522867463
Short name T183
Test name
Test status
Simulation time 34562093 ps
CPU time 0.8 seconds
Started Jan 21 10:21:27 PM PST 24
Finished Jan 21 10:21:36 PM PST 24
Peak memory 207296 kb
Host smart-01b22a88-500d-4ac1-aaa8-a386db4993e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522867463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.522867463
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.4022822191
Short name T186
Test name
Test status
Simulation time 12213291 ps
CPU time 0.99 seconds
Started Jan 21 10:22:35 PM PST 24
Finished Jan 21 10:22:45 PM PST 24
Peak memory 208880 kb
Host smart-18f62b5a-70d5-4b0c-b409-a1200d0706cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022822191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.4022822191
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.90485280
Short name T354
Test name
Test status
Simulation time 9610976787 ps
CPU time 84.72 seconds
Started Jan 21 10:56:10 PM PST 24
Finished Jan 21 10:57:35 PM PST 24
Peak memory 275132 kb
Host smart-cfefe669-1ce4-4985-ad27-147e9b4f88b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90485280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_state_failure.90485280
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4008389907
Short name T135
Test name
Test status
Simulation time 308725232 ps
CPU time 3.69 seconds
Started Jan 21 03:05:16 PM PST 24
Finished Jan 21 03:05:20 PM PST 24
Peak memory 217696 kb
Host smart-48942719-5101-4564-bb04-2335ff14eec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008389907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4008389907
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2137113080
Short name T115
Test name
Test status
Simulation time 98040315 ps
CPU time 2.77 seconds
Started Jan 21 03:11:42 PM PST 24
Finished Jan 21 03:11:45 PM PST 24
Peak memory 217708 kb
Host smart-0b3aa45a-4ca7-433b-bd79-56a71b798456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137113080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2137113080
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1356781126
Short name T144
Test name
Test status
Simulation time 421256125 ps
CPU time 2.86 seconds
Started Jan 21 03:05:30 PM PST 24
Finished Jan 21 03:05:35 PM PST 24
Peak memory 212548 kb
Host smart-bc95e78c-a47b-4a2b-81e4-509c6d76573e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356781126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1356781126
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2252100534
Short name T149
Test name
Test status
Simulation time 114844960 ps
CPU time 4.45 seconds
Started Jan 21 03:04:41 PM PST 24
Finished Jan 21 03:04:53 PM PST 24
Peak memory 217608 kb
Host smart-2c0837ef-fa3e-482a-b007-23446cf23e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252100534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2252100534
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1626840083
Short name T167
Test name
Test status
Simulation time 17493303 ps
CPU time 1 seconds
Started Jan 21 03:04:05 PM PST 24
Finished Jan 21 03:04:10 PM PST 24
Peak memory 209404 kb
Host smart-8c992eb9-f664-4097-8c6f-ffd609e6e340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626840083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1626840083
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3379917714
Short name T126
Test name
Test status
Simulation time 15812849660 ps
CPU time 286.37 seconds
Started Jan 21 10:21:35 PM PST 24
Finished Jan 21 10:26:31 PM PST 24
Peak memory 283280 kb
Host smart-41c06b0d-58d0-4de8-a5c5-99df097a825a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3379917714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3379917714
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.890612475
Short name T98
Test name
Test status
Simulation time 53141693 ps
CPU time 1.28 seconds
Started Jan 21 03:04:12 PM PST 24
Finished Jan 21 03:04:15 PM PST 24
Peak memory 209384 kb
Host smart-90961232-c49d-47bf-8547-8ef062ba71d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890612475 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.890612475
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.923294749
Short name T177
Test name
Test status
Simulation time 94711042 ps
CPU time 1.09 seconds
Started Jan 21 03:04:02 PM PST 24
Finished Jan 21 03:04:10 PM PST 24
Peak memory 209428 kb
Host smart-01ca72f7-e461-4f17-8077-8047a269d241
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923294749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.923294749
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3826216285
Short name T210
Test name
Test status
Simulation time 137930195 ps
CPU time 1.85 seconds
Started Jan 21 03:04:12 PM PST 24
Finished Jan 21 03:04:16 PM PST 24
Peak memory 209488 kb
Host smart-2d5fa52a-fdd1-4c81-b828-46ad377ed8ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826216285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3826216285
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.761566523
Short name T180
Test name
Test status
Simulation time 16662406 ps
CPU time 0.94 seconds
Started Jan 21 03:09:21 PM PST 24
Finished Jan 21 03:09:22 PM PST 24
Peak memory 209416 kb
Host smart-5a98587c-1af9-4d6d-b729-d7e0b7b42af5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761566523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.761566523
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3790960960
Short name T134
Test name
Test status
Simulation time 40193723 ps
CPU time 1.77 seconds
Started Jan 21 03:04:05 PM PST 24
Finished Jan 21 03:04:10 PM PST 24
Peak memory 225152 kb
Host smart-4acd9676-94be-4fe8-80b1-df22619e0012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790960960 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3790960960
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1182869379
Short name T284
Test name
Test status
Simulation time 105968189 ps
CPU time 0.85 seconds
Started Jan 21 03:04:03 PM PST 24
Finished Jan 21 03:04:09 PM PST 24
Peak memory 209448 kb
Host smart-fd982298-7c44-457b-9971-a293ef8edd0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182869379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1182869379
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.411927139
Short name T278
Test name
Test status
Simulation time 59249014 ps
CPU time 2.04 seconds
Started Jan 21 03:04:11 PM PST 24
Finished Jan 21 03:04:14 PM PST 24
Peak memory 209284 kb
Host smart-5ba2e367-0774-47b8-a32d-951ca5424b93
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411927139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.411927139
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2839607186
Short name T213
Test name
Test status
Simulation time 947577388 ps
CPU time 2.51 seconds
Started Jan 21 03:04:01 PM PST 24
Finished Jan 21 03:04:11 PM PST 24
Peak memory 209368 kb
Host smart-2e5258bc-9834-46f7-8f52-7df33608717e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839607186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2839607186
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3728926260
Short name T230
Test name
Test status
Simulation time 1612711294 ps
CPU time 8.63 seconds
Started Jan 21 03:04:11 PM PST 24
Finished Jan 21 03:04:21 PM PST 24
Peak memory 209320 kb
Host smart-659f182d-8efe-4894-9e39-4518d85a06b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728926260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3728926260
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3509777665
Short name T206
Test name
Test status
Simulation time 471770234 ps
CPU time 1.97 seconds
Started Jan 21 03:04:03 PM PST 24
Finished Jan 21 03:04:10 PM PST 24
Peak memory 210440 kb
Host smart-cd0668f8-0512-4680-a921-3bdba7365b37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509777665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3509777665
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3259443659
Short name T190
Test name
Test status
Simulation time 836950067 ps
CPU time 3.85 seconds
Started Jan 21 03:04:05 PM PST 24
Finished Jan 21 03:04:13 PM PST 24
Peak memory 218704 kb
Host smart-71ea651e-56b9-4df2-8364-c3621696468b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325944
3659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3259443659
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1175820693
Short name T156
Test name
Test status
Simulation time 291764102 ps
CPU time 1.34 seconds
Started Jan 21 03:04:11 PM PST 24
Finished Jan 21 03:04:13 PM PST 24
Peak memory 209400 kb
Host smart-6962f62b-844e-4050-a70e-7b9f0b5abf73
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175820693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1175820693
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.592027178
Short name T140
Test name
Test status
Simulation time 434092327 ps
CPU time 2.86 seconds
Started Jan 21 03:04:11 PM PST 24
Finished Jan 21 03:04:15 PM PST 24
Peak memory 212768 kb
Host smart-53380142-40de-47b5-97a8-c58be4b97fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592027178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.592027178
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1856037332
Short name T176
Test name
Test status
Simulation time 85633159 ps
CPU time 1.34 seconds
Started Jan 21 03:04:21 PM PST 24
Finished Jan 21 03:04:24 PM PST 24
Peak memory 209452 kb
Host smart-28b265d8-5456-4a87-9dbf-52926bbef646
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856037332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1856037332
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.405211414
Short name T195
Test name
Test status
Simulation time 130628598 ps
CPU time 2.05 seconds
Started Jan 21 03:04:29 PM PST 24
Finished Jan 21 03:04:32 PM PST 24
Peak memory 208292 kb
Host smart-deebe234-c079-473a-9689-55f9789b1c49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405211414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.405211414
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2986106776
Short name T178
Test name
Test status
Simulation time 42399322 ps
CPU time 1.11 seconds
Started Jan 21 03:04:19 PM PST 24
Finished Jan 21 03:04:21 PM PST 24
Peak memory 209508 kb
Host smart-6b44a4c1-977e-4fcd-a342-3f5b1defa604
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986106776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2986106776
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2901118140
Short name T288
Test name
Test status
Simulation time 147425619 ps
CPU time 1.51 seconds
Started Jan 21 03:04:18 PM PST 24
Finished Jan 21 03:04:20 PM PST 24
Peak memory 217684 kb
Host smart-ba0e23ef-1ddd-40f2-be72-fad3bda4cff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901118140 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2901118140
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2566089888
Short name T162
Test name
Test status
Simulation time 36922723 ps
CPU time 1.01 seconds
Started Jan 21 03:04:19 PM PST 24
Finished Jan 21 03:04:21 PM PST 24
Peak memory 208592 kb
Host smart-f1bfa193-1832-450a-aff3-39f525b13ac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566089888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2566089888
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3723940403
Short name T152
Test name
Test status
Simulation time 90564837 ps
CPU time 1.24 seconds
Started Jan 21 03:04:21 PM PST 24
Finished Jan 21 03:04:24 PM PST 24
Peak memory 209352 kb
Host smart-f977e93b-d35e-4d31-b566-010ed3c94fa6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723940403 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3723940403
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.514428708
Short name T201
Test name
Test status
Simulation time 2555717335 ps
CPU time 4.6 seconds
Started Jan 21 03:04:37 PM PST 24
Finished Jan 21 03:04:44 PM PST 24
Peak memory 209412 kb
Host smart-e6aed40c-9f78-4025-b1b6-d211ee0e3d6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514428708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.514428708
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3776442265
Short name T198
Test name
Test status
Simulation time 1742579191 ps
CPU time 8.56 seconds
Started Jan 21 03:04:18 PM PST 24
Finished Jan 21 03:04:27 PM PST 24
Peak memory 209380 kb
Host smart-d2f28a43-76a9-4363-bc4f-8e4425128396
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776442265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3776442265
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2260160444
Short name T269
Test name
Test status
Simulation time 275853106 ps
CPU time 1.47 seconds
Started Jan 21 03:04:12 PM PST 24
Finished Jan 21 03:04:15 PM PST 24
Peak memory 210416 kb
Host smart-97811889-eec0-4dad-96ea-a7a38b6e7054
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260160444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2260160444
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1450373676
Short name T143
Test name
Test status
Simulation time 116075610 ps
CPU time 1.48 seconds
Started Jan 21 03:04:29 PM PST 24
Finished Jan 21 03:04:33 PM PST 24
Peak memory 218992 kb
Host smart-e8761516-4e0e-4068-92d4-65619f2b9d7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145037
3676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1450373676
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.526449117
Short name T282
Test name
Test status
Simulation time 45550672 ps
CPU time 1.09 seconds
Started Jan 21 03:04:37 PM PST 24
Finished Jan 21 03:04:40 PM PST 24
Peak memory 207924 kb
Host smart-a90e61d4-d11f-4d00-826b-b10897d0c416
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526449117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.526449117
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.778868076
Short name T94
Test name
Test status
Simulation time 67335400 ps
CPU time 1.05 seconds
Started Jan 21 03:04:19 PM PST 24
Finished Jan 21 03:04:21 PM PST 24
Peak memory 209412 kb
Host smart-dca501a6-ccc1-464c-97d6-20dc0c035401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778868076 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.778868076
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.493621469
Short name T297
Test name
Test status
Simulation time 334285600 ps
CPU time 1.37 seconds
Started Jan 21 03:04:37 PM PST 24
Finished Jan 21 03:04:41 PM PST 24
Peak memory 210948 kb
Host smart-7b904f45-9c87-453c-8838-f33e82368715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493621469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.493621469
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1066359827
Short name T146
Test name
Test status
Simulation time 74720356 ps
CPU time 3.12 seconds
Started Jan 21 03:04:37 PM PST 24
Finished Jan 21 03:04:41 PM PST 24
Peak memory 217660 kb
Host smart-1928e4a3-5bf9-4d62-8317-03a80a730de8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066359827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1066359827
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2171420499
Short name T264
Test name
Test status
Simulation time 46302776 ps
CPU time 2.38 seconds
Started Jan 21 03:04:24 PM PST 24
Finished Jan 21 03:04:27 PM PST 24
Peak memory 221120 kb
Host smart-7fdb813f-92af-4812-9b4a-80aa023a1246
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171420499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2171420499
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1274905948
Short name T164
Test name
Test status
Simulation time 21895144 ps
CPU time 1.14 seconds
Started Jan 21 03:05:19 PM PST 24
Finished Jan 21 03:05:21 PM PST 24
Peak memory 218372 kb
Host smart-8b08baff-3e0b-4b7e-a47d-dd396abd2861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274905948 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1274905948
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2611607161
Short name T179
Test name
Test status
Simulation time 11968906 ps
CPU time 0.83 seconds
Started Jan 21 03:41:08 PM PST 24
Finished Jan 21 03:41:09 PM PST 24
Peak memory 209360 kb
Host smart-e554c86c-e065-4704-93fe-e3ebb5c91e02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611607161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2611607161
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2110250350
Short name T241
Test name
Test status
Simulation time 88303633 ps
CPU time 1.12 seconds
Started Jan 21 03:05:19 PM PST 24
Finished Jan 21 03:05:21 PM PST 24
Peak memory 209400 kb
Host smart-4ecc56e9-a16e-4f15-9e2e-1e55387775b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110250350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2110250350
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3888099092
Short name T242
Test name
Test status
Simulation time 498128595 ps
CPU time 5.07 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:24 PM PST 24
Peak memory 217756 kb
Host smart-64832807-48a7-480e-9020-6081913a85e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888099092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3888099092
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.996093596
Short name T238
Test name
Test status
Simulation time 20689122 ps
CPU time 1.49 seconds
Started Jan 21 03:05:20 PM PST 24
Finished Jan 21 03:05:22 PM PST 24
Peak memory 219420 kb
Host smart-7b9c5495-f919-441e-9d93-fea586695efa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996093596 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.996093596
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4095841099
Short name T174
Test name
Test status
Simulation time 96394856 ps
CPU time 0.86 seconds
Started Jan 21 03:05:35 PM PST 24
Finished Jan 21 03:05:38 PM PST 24
Peak memory 209304 kb
Host smart-f64478df-ada8-4d9b-aa09-1eef2c0f6fa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095841099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.4095841099
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3757860474
Short name T273
Test name
Test status
Simulation time 52621494 ps
CPU time 1.36 seconds
Started Jan 21 03:05:22 PM PST 24
Finished Jan 21 03:05:26 PM PST 24
Peak memory 209424 kb
Host smart-13845990-a515-4736-a94f-fb1b081a82d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757860474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3757860474
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2223702174
Short name T95
Test name
Test status
Simulation time 97868136 ps
CPU time 4.2 seconds
Started Jan 21 03:05:15 PM PST 24
Finished Jan 21 03:05:21 PM PST 24
Peak memory 217760 kb
Host smart-ebc50ab2-ccda-4605-abfc-92767b290285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223702174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2223702174
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1755014916
Short name T163
Test name
Test status
Simulation time 83519690 ps
CPU time 0.93 seconds
Started Jan 21 03:05:15 PM PST 24
Finished Jan 21 03:05:17 PM PST 24
Peak memory 209320 kb
Host smart-ab2bbce9-fd96-4c24-b369-508315947cca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755014916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1755014916
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4256498585
Short name T271
Test name
Test status
Simulation time 76624139 ps
CPU time 1.19 seconds
Started Jan 21 03:40:47 PM PST 24
Finished Jan 21 03:40:49 PM PST 24
Peak memory 209540 kb
Host smart-c66b6ff2-43ed-4228-9e2c-013b66f8704e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256498585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4256498585
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1902683004
Short name T113
Test name
Test status
Simulation time 26934640 ps
CPU time 2.03 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:22 PM PST 24
Peak memory 217776 kb
Host smart-eca25bc6-83f8-4512-9d3f-2ec49760a1c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902683004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1902683004
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3915292060
Short name T287
Test name
Test status
Simulation time 116751839 ps
CPU time 1.07 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:21 PM PST 24
Peak memory 209552 kb
Host smart-6d7b6225-a8e6-4eac-aad4-cccbfe7fba86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915292060 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3915292060
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2495278783
Short name T256
Test name
Test status
Simulation time 52016628 ps
CPU time 0.83 seconds
Started Jan 21 03:36:48 PM PST 24
Finished Jan 21 03:36:50 PM PST 24
Peak memory 209320 kb
Host smart-47552ef8-9930-4949-b31d-378490047b24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495278783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2495278783
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1962387000
Short name T171
Test name
Test status
Simulation time 71196947 ps
CPU time 1.17 seconds
Started Jan 21 03:05:13 PM PST 24
Finished Jan 21 03:05:15 PM PST 24
Peak memory 209404 kb
Host smart-c5be2c52-aac8-46dc-a933-56fc1a1dc773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962387000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1962387000
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1551871589
Short name T205
Test name
Test status
Simulation time 62453899 ps
CPU time 2.18 seconds
Started Jan 21 03:07:56 PM PST 24
Finished Jan 21 03:07:59 PM PST 24
Peak memory 217764 kb
Host smart-38c7391d-41f0-4c68-950e-5bf68e27aa86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551871589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1551871589
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1469891901
Short name T226
Test name
Test status
Simulation time 302762032 ps
CPU time 1.08 seconds
Started Jan 21 03:05:21 PM PST 24
Finished Jan 21 03:05:25 PM PST 24
Peak memory 218660 kb
Host smart-309c74da-029d-4fd9-a1e5-9798ff3baa3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469891901 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1469891901
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2887316825
Short name T175
Test name
Test status
Simulation time 38479354 ps
CPU time 0.86 seconds
Started Jan 21 03:09:22 PM PST 24
Finished Jan 21 03:09:24 PM PST 24
Peak memory 209332 kb
Host smart-8769b952-912c-4ab8-a8bf-d40bf3d33437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887316825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2887316825
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3601095502
Short name T233
Test name
Test status
Simulation time 166198339 ps
CPU time 1.92 seconds
Started Jan 21 03:05:16 PM PST 24
Finished Jan 21 03:05:19 PM PST 24
Peak memory 211280 kb
Host smart-7c3cca92-b43d-4c9a-9a99-dd4ef2a2d72b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601095502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3601095502
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3504182597
Short name T250
Test name
Test status
Simulation time 181347718 ps
CPU time 3.15 seconds
Started Jan 21 03:05:14 PM PST 24
Finished Jan 21 03:05:18 PM PST 24
Peak memory 217724 kb
Host smart-2c469a97-2204-4d17-84bc-dbb3062a24ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504182597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3504182597
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2464782318
Short name T222
Test name
Test status
Simulation time 107080046 ps
CPU time 1.1 seconds
Started Jan 21 03:05:22 PM PST 24
Finished Jan 21 03:05:27 PM PST 24
Peak memory 217724 kb
Host smart-5bb6c659-56c5-4ef9-8743-efd1fecefb57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464782318 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2464782318
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.262119415
Short name T191
Test name
Test status
Simulation time 12236599 ps
CPU time 1.02 seconds
Started Jan 21 03:05:26 PM PST 24
Finished Jan 21 03:05:28 PM PST 24
Peak memory 209500 kb
Host smart-c56400d6-ea77-453b-9f7a-893d9140cc64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262119415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.262119415
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1065793818
Short name T262
Test name
Test status
Simulation time 17766844 ps
CPU time 1.29 seconds
Started Jan 21 03:05:25 PM PST 24
Finished Jan 21 03:05:28 PM PST 24
Peak memory 209376 kb
Host smart-2c2f2934-12c7-43a3-bd62-c3e701d4f27f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065793818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1065793818
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1496519980
Short name T247
Test name
Test status
Simulation time 430830086 ps
CPU time 2.2 seconds
Started Jan 21 03:05:22 PM PST 24
Finished Jan 21 03:05:28 PM PST 24
Peak memory 217868 kb
Host smart-571fbee1-f464-4092-8cad-46359d7203f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496519980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1496519980
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3649725848
Short name T93
Test name
Test status
Simulation time 17539130 ps
CPU time 1.03 seconds
Started Jan 21 03:05:24 PM PST 24
Finished Jan 21 03:05:27 PM PST 24
Peak memory 217752 kb
Host smart-548d12fa-3e73-49f8-8f89-984217a6cf6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649725848 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3649725848
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3992767641
Short name T157
Test name
Test status
Simulation time 110548507 ps
CPU time 1.11 seconds
Started Jan 21 03:05:29 PM PST 24
Finished Jan 21 03:05:31 PM PST 24
Peak memory 208888 kb
Host smart-98442e7f-9187-4d18-a418-81bf37f29ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992767641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3992767641
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4185012682
Short name T212
Test name
Test status
Simulation time 55687768 ps
CPU time 1.01 seconds
Started Jan 21 03:05:24 PM PST 24
Finished Jan 21 03:05:27 PM PST 24
Peak memory 209536 kb
Host smart-35fbd912-4183-4144-88ed-25e5cb781bf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185012682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.4185012682
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1036105275
Short name T133
Test name
Test status
Simulation time 1807122401 ps
CPU time 3.38 seconds
Started Jan 21 03:05:29 PM PST 24
Finished Jan 21 03:05:34 PM PST 24
Peak memory 217688 kb
Host smart-2524afff-8ce1-478b-84aa-fb6af4b01aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036105275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1036105275
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3319228517
Short name T151
Test name
Test status
Simulation time 2284432732 ps
CPU time 3.52 seconds
Started Jan 21 03:05:26 PM PST 24
Finished Jan 21 03:05:31 PM PST 24
Peak memory 217788 kb
Host smart-2e172184-f9c6-4bfd-a56c-fcfbe70dbe25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319228517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3319228517
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.367042728
Short name T172
Test name
Test status
Simulation time 18605074 ps
CPU time 0.96 seconds
Started Jan 21 03:05:29 PM PST 24
Finished Jan 21 03:05:31 PM PST 24
Peak memory 209468 kb
Host smart-e36033db-8d41-4250-a812-120e12c34698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367042728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.367042728
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4092731904
Short name T277
Test name
Test status
Simulation time 55894877 ps
CPU time 1.22 seconds
Started Jan 21 03:05:20 PM PST 24
Finished Jan 21 03:05:24 PM PST 24
Peak memory 209456 kb
Host smart-96ea7a07-e975-4521-8f63-8af1c26c7d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092731904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.4092731904
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2417961512
Short name T283
Test name
Test status
Simulation time 34076741 ps
CPU time 2.16 seconds
Started Jan 21 03:05:27 PM PST 24
Finished Jan 21 03:05:30 PM PST 24
Peak memory 217784 kb
Host smart-d559e683-8ce9-40c2-b766-41304196e2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417961512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2417961512
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3806495170
Short name T165
Test name
Test status
Simulation time 29684332 ps
CPU time 1.32 seconds
Started Jan 21 03:05:39 PM PST 24
Finished Jan 21 03:05:41 PM PST 24
Peak memory 218604 kb
Host smart-02a7284a-8b43-4cfc-bd08-0b5abd58e4aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806495170 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3806495170
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.509160436
Short name T232
Test name
Test status
Simulation time 74430097 ps
CPU time 0.92 seconds
Started Jan 21 03:05:33 PM PST 24
Finished Jan 21 03:05:35 PM PST 24
Peak memory 209500 kb
Host smart-45f41318-a86e-4860-8433-f3688382ccc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509160436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.509160436
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1914902051
Short name T97
Test name
Test status
Simulation time 29385126 ps
CPU time 1.45 seconds
Started Jan 21 03:05:30 PM PST 24
Finished Jan 21 03:05:33 PM PST 24
Peak memory 209416 kb
Host smart-4a919ba5-cac0-450e-bc99-786cffdd9ace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914902051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1914902051
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3058958875
Short name T255
Test name
Test status
Simulation time 70673097 ps
CPU time 1.55 seconds
Started Jan 21 03:12:38 PM PST 24
Finished Jan 21 03:12:41 PM PST 24
Peak memory 218836 kb
Host smart-48848e02-95f4-43f4-883c-25458bbc4d8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058958875 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3058958875
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1903264982
Short name T111
Test name
Test status
Simulation time 17471860 ps
CPU time 0.88 seconds
Started Jan 21 03:13:55 PM PST 24
Finished Jan 21 03:13:56 PM PST 24
Peak memory 209436 kb
Host smart-f41fb489-17b2-41a2-8c5e-498a3348c111
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903264982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1903264982
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1477001696
Short name T275
Test name
Test status
Simulation time 26491689 ps
CPU time 1.28 seconds
Started Jan 21 03:49:11 PM PST 24
Finished Jan 21 03:49:15 PM PST 24
Peak memory 209492 kb
Host smart-14597cd8-12ed-48ae-8d5d-c2a9f7b6fd6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477001696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1477001696
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.597705371
Short name T294
Test name
Test status
Simulation time 465321789 ps
CPU time 3.38 seconds
Started Jan 21 03:05:41 PM PST 24
Finished Jan 21 03:05:45 PM PST 24
Peak memory 217756 kb
Host smart-1d80415e-acbd-4c2c-8928-56ae40dc68ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597705371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.597705371
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3626104985
Short name T150
Test name
Test status
Simulation time 157766972 ps
CPU time 2.31 seconds
Started Jan 21 03:13:56 PM PST 24
Finished Jan 21 03:13:59 PM PST 24
Peak memory 212516 kb
Host smart-4528e9af-fec3-4ac5-a781-f5b33532db68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626104985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3626104985
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1665387568
Short name T169
Test name
Test status
Simulation time 29433031 ps
CPU time 1.16 seconds
Started Jan 21 03:04:26 PM PST 24
Finished Jan 21 03:04:28 PM PST 24
Peak memory 209564 kb
Host smart-ebf077a0-6ee7-4f7a-a10f-3be0bd9ceaa8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665387568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1665387568
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2714359783
Short name T261
Test name
Test status
Simulation time 156152954 ps
CPU time 1.82 seconds
Started Jan 21 03:04:26 PM PST 24
Finished Jan 21 03:04:29 PM PST 24
Peak memory 209488 kb
Host smart-0e18e64c-38cc-4c33-8932-75f8705b8762
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714359783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2714359783
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2144970588
Short name T168
Test name
Test status
Simulation time 28979194 ps
CPU time 1.09 seconds
Started Jan 21 03:04:19 PM PST 24
Finished Jan 21 03:04:21 PM PST 24
Peak memory 209484 kb
Host smart-b276daf5-46ef-4dc5-a304-839fbeb26c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144970588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2144970588
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1238078786
Short name T296
Test name
Test status
Simulation time 72438785 ps
CPU time 1.17 seconds
Started Jan 21 03:04:28 PM PST 24
Finished Jan 21 03:04:31 PM PST 24
Peak memory 217724 kb
Host smart-9b99a288-1271-4d19-87d7-76622d2033aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238078786 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1238078786
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1785155126
Short name T251
Test name
Test status
Simulation time 46577721 ps
CPU time 1.03 seconds
Started Jan 21 03:04:24 PM PST 24
Finished Jan 21 03:04:25 PM PST 24
Peak memory 208756 kb
Host smart-138f68ff-4e82-4772-a78f-fee1923cf8f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785155126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1785155126
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1013270886
Short name T279
Test name
Test status
Simulation time 130556017 ps
CPU time 1.45 seconds
Started Jan 21 03:04:37 PM PST 24
Finished Jan 21 03:04:41 PM PST 24
Peak memory 209284 kb
Host smart-d4f80dac-d1a0-4aab-a134-18900446bc0d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013270886 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1013270886
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2864002692
Short name T267
Test name
Test status
Simulation time 605505999 ps
CPU time 13.68 seconds
Started Jan 21 03:04:18 PM PST 24
Finished Jan 21 03:04:32 PM PST 24
Peak memory 209324 kb
Host smart-d8d4d342-7c51-42c9-9480-a3b8f170b125
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864002692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2864002692
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2882985093
Short name T207
Test name
Test status
Simulation time 3040820538 ps
CPU time 15.43 seconds
Started Jan 21 03:04:16 PM PST 24
Finished Jan 21 03:04:32 PM PST 24
Peak memory 209484 kb
Host smart-e855acdd-c85c-462b-a5a9-241089e7abe6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882985093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2882985093
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1496313992
Short name T274
Test name
Test status
Simulation time 156074211 ps
CPU time 2.71 seconds
Started Jan 21 03:04:20 PM PST 24
Finished Jan 21 03:04:24 PM PST 24
Peak memory 210560 kb
Host smart-9d4dba33-c3d5-4450-af02-acc2ddc4636d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496313992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1496313992
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4230400153
Short name T204
Test name
Test status
Simulation time 297136162 ps
CPU time 2.41 seconds
Started Jan 21 03:04:18 PM PST 24
Finished Jan 21 03:04:21 PM PST 24
Peak memory 217988 kb
Host smart-a397e367-be55-498f-870f-bced6823d23b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423040
0153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4230400153
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4284382901
Short name T228
Test name
Test status
Simulation time 78155090 ps
CPU time 1.12 seconds
Started Jan 21 03:04:24 PM PST 24
Finished Jan 21 03:04:26 PM PST 24
Peak memory 209412 kb
Host smart-16ce7056-1131-4c76-9f0b-07d39950c77c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284382901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.4284382901
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3462802932
Short name T114
Test name
Test status
Simulation time 44642761 ps
CPU time 0.97 seconds
Started Jan 21 03:04:31 PM PST 24
Finished Jan 21 03:04:34 PM PST 24
Peak memory 208736 kb
Host smart-5f2b8c61-1b4d-44be-9a79-1d666ca10cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462802932 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3462802932
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3675051832
Short name T209
Test name
Test status
Simulation time 71585392 ps
CPU time 1.31 seconds
Started Jan 21 03:04:28 PM PST 24
Finished Jan 21 03:04:31 PM PST 24
Peak memory 209572 kb
Host smart-79cdf269-f018-40d3-86ad-3291f1a32fe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675051832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3675051832
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3325384383
Short name T266
Test name
Test status
Simulation time 256447810 ps
CPU time 2.95 seconds
Started Jan 21 03:04:19 PM PST 24
Finished Jan 21 03:04:23 PM PST 24
Peak memory 217716 kb
Host smart-2ad097da-a213-492c-92c6-9e6fecbd7512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325384383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3325384383
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1795996955
Short name T268
Test name
Test status
Simulation time 281361410 ps
CPU time 2.57 seconds
Started Jan 21 03:04:28 PM PST 24
Finished Jan 21 03:04:32 PM PST 24
Peak memory 209464 kb
Host smart-138559ba-3ad9-4851-81bc-3712ea4f431d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795996955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1795996955
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1142034659
Short name T260
Test name
Test status
Simulation time 50327815 ps
CPU time 1.02 seconds
Started Jan 21 03:04:28 PM PST 24
Finished Jan 21 03:04:31 PM PST 24
Peak memory 209460 kb
Host smart-e5d6b458-70d7-4f7e-b08f-6e3cf39b36d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142034659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1142034659
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.503593400
Short name T236
Test name
Test status
Simulation time 33701083 ps
CPU time 1.5 seconds
Started Jan 21 03:04:34 PM PST 24
Finished Jan 21 03:04:38 PM PST 24
Peak memory 217692 kb
Host smart-060208fe-72c4-47dc-9809-707a2e92e78b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503593400 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.503593400
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4227887455
Short name T225
Test name
Test status
Simulation time 42911161 ps
CPU time 0.95 seconds
Started Jan 21 03:04:27 PM PST 24
Finished Jan 21 03:04:30 PM PST 24
Peak memory 209464 kb
Host smart-81d146c6-b25a-4cf8-a1cf-20bf013eb63b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227887455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4227887455
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3069719610
Short name T235
Test name
Test status
Simulation time 28882312 ps
CPU time 1.33 seconds
Started Jan 21 03:04:29 PM PST 24
Finished Jan 21 03:04:33 PM PST 24
Peak memory 209364 kb
Host smart-ab18211d-0c6a-4a5f-8d34-b56e8dbe890f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069719610 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3069719610
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1274148054
Short name T192
Test name
Test status
Simulation time 796894654 ps
CPU time 5.56 seconds
Started Jan 21 03:37:02 PM PST 24
Finished Jan 21 03:37:18 PM PST 24
Peak memory 209356 kb
Host smart-535dcb66-3895-465d-9553-60dd6eab9de5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274148054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1274148054
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1041774371
Short name T276
Test name
Test status
Simulation time 5499123806 ps
CPU time 13.54 seconds
Started Jan 21 03:04:25 PM PST 24
Finished Jan 21 03:04:39 PM PST 24
Peak memory 209476 kb
Host smart-8528f28a-8feb-426f-a1e4-2f849aebe18c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041774371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1041774371
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2737476913
Short name T196
Test name
Test status
Simulation time 160589137 ps
CPU time 1.13 seconds
Started Jan 21 03:04:25 PM PST 24
Finished Jan 21 03:04:27 PM PST 24
Peak memory 210352 kb
Host smart-41890b64-6637-46cd-9f3d-0dde0893b6aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737476913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2737476913
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.198291362
Short name T215
Test name
Test status
Simulation time 34431190 ps
CPU time 1.59 seconds
Started Jan 21 03:39:50 PM PST 24
Finished Jan 21 03:39:54 PM PST 24
Peak memory 218408 kb
Host smart-ede7d0d5-093e-4aae-87b4-f5416622dc6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198291
362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.198291362
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2326601589
Short name T234
Test name
Test status
Simulation time 38172843 ps
CPU time 1.13 seconds
Started Jan 21 03:04:23 PM PST 24
Finished Jan 21 03:04:25 PM PST 24
Peak memory 209316 kb
Host smart-612d08c8-fc24-41b3-b011-72b11e95de1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326601589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2326601589
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1775355620
Short name T173
Test name
Test status
Simulation time 331549972 ps
CPU time 1.45 seconds
Started Jan 21 03:04:26 PM PST 24
Finished Jan 21 03:04:29 PM PST 24
Peak memory 211244 kb
Host smart-6ff26cc6-23c5-4446-b6af-1e81d21cf474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775355620 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1775355620
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3375200654
Short name T214
Test name
Test status
Simulation time 23031206 ps
CPU time 1.28 seconds
Started Jan 21 03:04:35 PM PST 24
Finished Jan 21 03:04:38 PM PST 24
Peak memory 211224 kb
Host smart-cb32e1eb-8802-455a-8ed6-529b319bf0c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375200654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3375200654
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3976723979
Short name T292
Test name
Test status
Simulation time 54257080 ps
CPU time 2.43 seconds
Started Jan 21 03:23:00 PM PST 24
Finished Jan 21 03:23:04 PM PST 24
Peak memory 217860 kb
Host smart-767e6488-63c5-4ec0-aec2-05a326739caf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976723979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3976723979
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2160130818
Short name T208
Test name
Test status
Simulation time 34504881 ps
CPU time 1.2 seconds
Started Jan 21 03:04:40 PM PST 24
Finished Jan 21 03:04:49 PM PST 24
Peak memory 208536 kb
Host smart-97b2ab7f-17dc-4ef6-8704-78f0ea797bbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160130818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2160130818
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3133667800
Short name T217
Test name
Test status
Simulation time 66061538 ps
CPU time 1.33 seconds
Started Jan 21 03:04:42 PM PST 24
Finished Jan 21 03:04:50 PM PST 24
Peak memory 209332 kb
Host smart-373144be-4280-48cd-9a35-54263c0f3e40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133667800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3133667800
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.913184555
Short name T286
Test name
Test status
Simulation time 24684104 ps
CPU time 1.04 seconds
Started Jan 21 03:04:42 PM PST 24
Finished Jan 21 03:04:50 PM PST 24
Peak memory 209412 kb
Host smart-b1cbdba5-65ef-4c6e-a62b-81b8180cb8bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913184555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.913184555
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4281186690
Short name T188
Test name
Test status
Simulation time 21239360 ps
CPU time 1.04 seconds
Started Jan 21 03:46:01 PM PST 24
Finished Jan 21 03:46:10 PM PST 24
Peak memory 218224 kb
Host smart-78bcf646-ee03-414a-9dd3-956e32107393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281186690 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.4281186690
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1226316669
Short name T170
Test name
Test status
Simulation time 16922361 ps
CPU time 0.91 seconds
Started Jan 21 03:04:45 PM PST 24
Finished Jan 21 03:04:50 PM PST 24
Peak memory 209396 kb
Host smart-f3b238d9-b044-4266-9751-59006cd18f01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226316669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1226316669
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4038749937
Short name T211
Test name
Test status
Simulation time 108589042 ps
CPU time 2.25 seconds
Started Jan 21 03:23:00 PM PST 24
Finished Jan 21 03:23:03 PM PST 24
Peak memory 207644 kb
Host smart-22c816e5-fa2d-4583-b2fe-0fefc01845a6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038749937 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.4038749937
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.924058446
Short name T295
Test name
Test status
Simulation time 357198257 ps
CPU time 4.47 seconds
Started Jan 21 03:17:23 PM PST 24
Finished Jan 21 03:17:29 PM PST 24
Peak memory 209432 kb
Host smart-334f9464-5407-4159-b457-a1882f7d2dfb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924058446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.924058446
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.102982614
Short name T219
Test name
Test status
Simulation time 1291758398 ps
CPU time 14.05 seconds
Started Jan 21 03:04:34 PM PST 24
Finished Jan 21 03:04:50 PM PST 24
Peak memory 206956 kb
Host smart-61ec6dfb-a890-4d5e-a3ca-718b4f53b20e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102982614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.102982614
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2011502756
Short name T194
Test name
Test status
Simulation time 47733388 ps
CPU time 1.47 seconds
Started Jan 21 03:04:32 PM PST 24
Finished Jan 21 03:04:35 PM PST 24
Peak memory 210176 kb
Host smart-0298dcf7-b986-490b-9a01-492749d5a8c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011502756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2011502756
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3100198223
Short name T142
Test name
Test status
Simulation time 382043628 ps
CPU time 2.37 seconds
Started Jan 21 03:04:46 PM PST 24
Finished Jan 21 03:04:52 PM PST 24
Peak memory 218892 kb
Host smart-6d077fb4-7724-4bd8-a867-8f97b1f878fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310019
8223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3100198223
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1095598433
Short name T229
Test name
Test status
Simulation time 91368764 ps
CPU time 2.79 seconds
Started Jan 21 03:04:33 PM PST 24
Finished Jan 21 03:04:37 PM PST 24
Peak memory 209172 kb
Host smart-b22524c4-cd48-4e85-845f-711a3a251ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095598433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1095598433
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3072844572
Short name T224
Test name
Test status
Simulation time 207835658 ps
CPU time 1.71 seconds
Started Jan 21 03:04:41 PM PST 24
Finished Jan 21 03:04:50 PM PST 24
Peak memory 209468 kb
Host smart-7f381f7c-6acf-4f29-ba77-4754911edb7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072844572 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3072844572
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.508053376
Short name T109
Test name
Test status
Simulation time 162863643 ps
CPU time 1.96 seconds
Started Jan 21 03:47:31 PM PST 24
Finished Jan 21 03:47:35 PM PST 24
Peak memory 209464 kb
Host smart-50d099b2-7118-4bcf-a177-78feee2633fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508053376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.508053376
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.885912422
Short name T202
Test name
Test status
Simulation time 69865452 ps
CPU time 2.02 seconds
Started Jan 21 03:18:48 PM PST 24
Finished Jan 21 03:18:52 PM PST 24
Peak memory 218920 kb
Host smart-5e1969d9-cdb9-455c-b1f1-6a995d8b45e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885912422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.885912422
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2586117521
Short name T108
Test name
Test status
Simulation time 75713956 ps
CPU time 1.45 seconds
Started Jan 21 03:04:52 PM PST 24
Finished Jan 21 03:04:55 PM PST 24
Peak memory 217628 kb
Host smart-7d551ce7-406a-443f-ae66-1b45f7c9e37c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586117521 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2586117521
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1394174863
Short name T280
Test name
Test status
Simulation time 58345144 ps
CPU time 0.9 seconds
Started Jan 21 03:04:47 PM PST 24
Finished Jan 21 03:04:51 PM PST 24
Peak memory 208544 kb
Host smart-8b72bcdf-0edd-464e-bc04-b518e285c2bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394174863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1394174863
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1887253766
Short name T220
Test name
Test status
Simulation time 57371075 ps
CPU time 1.07 seconds
Started Jan 21 03:13:15 PM PST 24
Finished Jan 21 03:13:18 PM PST 24
Peak memory 209416 kb
Host smart-ab69ad52-66ec-40e3-b46d-df78f35761d0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887253766 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1887253766
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1249040510
Short name T130
Test name
Test status
Simulation time 2203069248 ps
CPU time 6.07 seconds
Started Jan 21 03:04:42 PM PST 24
Finished Jan 21 03:04:55 PM PST 24
Peak memory 209388 kb
Host smart-afd210ff-1c9f-4fa4-883d-78b63e5c1c25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249040510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1249040510
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3205464754
Short name T159
Test name
Test status
Simulation time 12815226893 ps
CPU time 13.89 seconds
Started Jan 21 03:25:40 PM PST 24
Finished Jan 21 03:25:55 PM PST 24
Peak memory 209468 kb
Host smart-87361679-fb5e-4510-a02f-90040ae99fda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205464754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3205464754
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2136709052
Short name T240
Test name
Test status
Simulation time 135165041 ps
CPU time 1.51 seconds
Started Jan 21 03:04:42 PM PST 24
Finished Jan 21 03:04:50 PM PST 24
Peak memory 210388 kb
Host smart-2cd48384-097f-4aae-9730-8708dbd4d233
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136709052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2136709052
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2656343145
Short name T153
Test name
Test status
Simulation time 32542997 ps
CPU time 1.31 seconds
Started Jan 21 03:46:02 PM PST 24
Finished Jan 21 03:46:11 PM PST 24
Peak memory 218876 kb
Host smart-7d662f68-3276-42ce-b654-87c80f387d55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265634
3145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2656343145
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1607781942
Short name T259
Test name
Test status
Simulation time 142565335 ps
CPU time 2.26 seconds
Started Jan 21 03:04:40 PM PST 24
Finished Jan 21 03:04:51 PM PST 24
Peak memory 209428 kb
Host smart-f718ffbb-c7e1-4162-848c-40dc2aca6fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607781942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1607781942
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.590462664
Short name T181
Test name
Test status
Simulation time 27292807 ps
CPU time 1.38 seconds
Started Jan 21 03:26:22 PM PST 24
Finished Jan 21 03:26:24 PM PST 24
Peak memory 209512 kb
Host smart-80623438-4852-496e-b281-4971cfd374c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590462664 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.590462664
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.923957945
Short name T231
Test name
Test status
Simulation time 121099281 ps
CPU time 1.33 seconds
Started Jan 21 03:04:52 PM PST 24
Finished Jan 21 03:04:55 PM PST 24
Peak memory 209392 kb
Host smart-e12f325a-afbf-4bd9-b4e7-789e0d37b623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923957945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.923957945
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2441996709
Short name T248
Test name
Test status
Simulation time 523171478 ps
CPU time 3.41 seconds
Started Jan 21 03:22:08 PM PST 24
Finished Jan 21 03:22:19 PM PST 24
Peak memory 217756 kb
Host smart-1c6902af-6bc5-48c8-a4ee-fc6d8d6cfbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441996709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2441996709
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3002335936
Short name T136
Test name
Test status
Simulation time 1926372080 ps
CPU time 11.11 seconds
Started Jan 21 03:04:40 PM PST 24
Finished Jan 21 03:05:00 PM PST 24
Peak memory 218080 kb
Host smart-4daab480-f306-4a3e-9d72-1086dc9b5dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002335936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3002335936
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2064768798
Short name T285
Test name
Test status
Simulation time 17177864 ps
CPU time 1.32 seconds
Started Jan 21 03:04:57 PM PST 24
Finished Jan 21 03:05:00 PM PST 24
Peak memory 217836 kb
Host smart-abb31cd1-3ae3-4a23-a862-0fedf0631057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064768798 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2064768798
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2330305577
Short name T189
Test name
Test status
Simulation time 80380552 ps
CPU time 0.94 seconds
Started Jan 21 03:05:07 PM PST 24
Finished Jan 21 03:05:10 PM PST 24
Peak memory 209500 kb
Host smart-0e660d94-cb4d-4466-bc17-d0f903704ad9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330305577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2330305577
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3195773472
Short name T106
Test name
Test status
Simulation time 18975989 ps
CPU time 0.98 seconds
Started Jan 21 03:04:50 PM PST 24
Finished Jan 21 03:04:55 PM PST 24
Peak memory 209388 kb
Host smart-174f049b-03d8-47e0-8639-2758bf74a868
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195773472 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3195773472
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1379102965
Short name T223
Test name
Test status
Simulation time 2034393853 ps
CPU time 22.9 seconds
Started Jan 21 03:04:57 PM PST 24
Finished Jan 21 03:05:22 PM PST 24
Peak memory 209436 kb
Host smart-db177338-091d-43ef-a169-ba5e773c1702
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379102965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1379102965
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.596702443
Short name T154
Test name
Test status
Simulation time 1610492833 ps
CPU time 10.83 seconds
Started Jan 21 03:04:49 PM PST 24
Finished Jan 21 03:05:04 PM PST 24
Peak memory 209400 kb
Host smart-70ed1ce7-072a-4acf-8997-7399ae8d5236
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596702443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.596702443
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1008295507
Short name T254
Test name
Test status
Simulation time 86778586 ps
CPU time 1.46 seconds
Started Jan 21 03:04:50 PM PST 24
Finished Jan 21 03:04:55 PM PST 24
Peak memory 218216 kb
Host smart-d60949e4-6022-45a6-adcb-0c2afe23a32f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100829
5507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1008295507
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1441151852
Short name T199
Test name
Test status
Simulation time 168791006 ps
CPU time 2.61 seconds
Started Jan 21 03:04:46 PM PST 24
Finished Jan 21 03:04:52 PM PST 24
Peak memory 209612 kb
Host smart-633a6180-a75d-407e-859c-a3858edd9820
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441151852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1441151852
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.428384307
Short name T221
Test name
Test status
Simulation time 94026663 ps
CPU time 1.14 seconds
Started Jan 21 03:04:49 PM PST 24
Finished Jan 21 03:04:54 PM PST 24
Peak memory 209512 kb
Host smart-174657a6-d460-4d18-b605-19ec7d1d0091
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428384307 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.428384307
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1663049058
Short name T216
Test name
Test status
Simulation time 49138738 ps
CPU time 1.57 seconds
Started Jan 21 03:04:59 PM PST 24
Finished Jan 21 03:05:02 PM PST 24
Peak memory 211172 kb
Host smart-6316fbf3-1f5b-4f45-85f2-b748fc6f80c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663049058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1663049058
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3227216640
Short name T252
Test name
Test status
Simulation time 67740512 ps
CPU time 2.92 seconds
Started Jan 21 04:05:09 PM PST 24
Finished Jan 21 04:05:13 PM PST 24
Peak memory 217744 kb
Host smart-f5c3e0aa-52d2-4802-98b6-378a739054c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227216640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3227216640
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.930787675
Short name T147
Test name
Test status
Simulation time 306845421 ps
CPU time 2.19 seconds
Started Jan 21 03:04:55 PM PST 24
Finished Jan 21 03:05:00 PM PST 24
Peak memory 220856 kb
Host smart-d03cbc73-5026-412d-b4a7-6a0321dd65cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930787675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.930787675
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3862585302
Short name T293
Test name
Test status
Simulation time 30043874 ps
CPU time 1.77 seconds
Started Jan 21 03:05:00 PM PST 24
Finished Jan 21 03:05:03 PM PST 24
Peak memory 218504 kb
Host smart-eee77346-894e-4bad-b233-3cf45f2968e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862585302 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3862585302
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.481235807
Short name T237
Test name
Test status
Simulation time 54721089 ps
CPU time 1.05 seconds
Started Jan 21 03:04:57 PM PST 24
Finished Jan 21 03:05:00 PM PST 24
Peak memory 208584 kb
Host smart-fd8e0ee6-95f6-44d2-add1-294133b6aab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481235807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.481235807
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3831646284
Short name T107
Test name
Test status
Simulation time 61697777 ps
CPU time 2.14 seconds
Started Jan 21 03:05:00 PM PST 24
Finished Jan 21 03:05:03 PM PST 24
Peak memory 209344 kb
Host smart-26ed716b-4e92-410b-becd-2c199c575149
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831646284 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3831646284
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1457653919
Short name T289
Test name
Test status
Simulation time 2567302912 ps
CPU time 15.47 seconds
Started Jan 21 03:05:01 PM PST 24
Finished Jan 21 03:05:17 PM PST 24
Peak memory 209476 kb
Host smart-efa2b654-4a6b-4870-a566-703235c7521d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457653919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1457653919
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3829636745
Short name T227
Test name
Test status
Simulation time 4555755623 ps
CPU time 12.49 seconds
Started Jan 21 03:05:02 PM PST 24
Finished Jan 21 03:05:17 PM PST 24
Peak memory 209416 kb
Host smart-9c96bd34-51b6-40b0-91a1-c98af89f1a14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829636745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3829636745
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.239704083
Short name T243
Test name
Test status
Simulation time 670111560 ps
CPU time 2.08 seconds
Started Jan 21 03:04:59 PM PST 24
Finished Jan 21 03:05:03 PM PST 24
Peak memory 210644 kb
Host smart-66aa3edf-5400-4ce4-979a-c4dbf450b86a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239704083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.239704083
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2575215990
Short name T291
Test name
Test status
Simulation time 66622426 ps
CPU time 1.72 seconds
Started Jan 21 03:05:05 PM PST 24
Finished Jan 21 03:05:08 PM PST 24
Peak memory 217680 kb
Host smart-d8c38b21-7789-4428-b177-afa8fa0be646
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257521
5990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2575215990
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1463184011
Short name T96
Test name
Test status
Simulation time 129860420 ps
CPU time 1.93 seconds
Started Jan 21 03:05:00 PM PST 24
Finished Jan 21 03:05:03 PM PST 24
Peak memory 209396 kb
Host smart-b83e6bb6-847a-4098-b827-c844f7d423c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463184011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1463184011
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1125800246
Short name T249
Test name
Test status
Simulation time 39641199 ps
CPU time 1.49 seconds
Started Jan 21 03:04:58 PM PST 24
Finished Jan 21 03:05:01 PM PST 24
Peak memory 209780 kb
Host smart-1463fcad-0be4-4b99-b494-b8c3a50427d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125800246 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1125800246
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3743138984
Short name T263
Test name
Test status
Simulation time 25682404 ps
CPU time 1.94 seconds
Started Jan 21 03:05:01 PM PST 24
Finished Jan 21 03:05:05 PM PST 24
Peak memory 218744 kb
Host smart-7ff2435b-a987-4ead-9986-b1c7c7d5cae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743138984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3743138984
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1872925218
Short name T145
Test name
Test status
Simulation time 540349373 ps
CPU time 3.03 seconds
Started Jan 21 03:05:02 PM PST 24
Finished Jan 21 03:05:07 PM PST 24
Peak memory 212796 kb
Host smart-8d94c53b-6740-49aa-8acd-ef806ed49b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872925218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1872925218
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1774675779
Short name T246
Test name
Test status
Simulation time 15206137 ps
CPU time 1.01 seconds
Started Jan 21 03:05:04 PM PST 24
Finished Jan 21 03:05:07 PM PST 24
Peak memory 217716 kb
Host smart-7e11b6cb-bce7-436a-9346-7a5ceac9ec28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774675779 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1774675779
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2264789684
Short name T200
Test name
Test status
Simulation time 26879554 ps
CPU time 0.87 seconds
Started Jan 21 03:05:14 PM PST 24
Finished Jan 21 03:05:16 PM PST 24
Peak memory 209328 kb
Host smart-5f9e6623-1307-417e-bbfd-ce12453738b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264789684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2264789684
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.685515564
Short name T244
Test name
Test status
Simulation time 28767529 ps
CPU time 0.97 seconds
Started Jan 21 03:05:08 PM PST 24
Finished Jan 21 03:05:11 PM PST 24
Peak memory 209412 kb
Host smart-bfb28b73-c6f7-4b83-aaf3-23f53e645d47
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685515564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.685515564
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1436562953
Short name T160
Test name
Test status
Simulation time 1833773302 ps
CPU time 10.64 seconds
Started Jan 21 03:05:02 PM PST 24
Finished Jan 21 03:05:15 PM PST 24
Peak memory 208080 kb
Host smart-28b181a1-6843-4065-9938-099ae114cb9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436562953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1436562953
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.999061109
Short name T203
Test name
Test status
Simulation time 1083936143 ps
CPU time 24.88 seconds
Started Jan 21 03:05:04 PM PST 24
Finished Jan 21 03:05:31 PM PST 24
Peak memory 209388 kb
Host smart-53cad637-0e0d-4480-aa2b-8c0def59a4b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999061109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.999061109
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1260322790
Short name T197
Test name
Test status
Simulation time 486239839 ps
CPU time 3.41 seconds
Started Jan 21 03:04:59 PM PST 24
Finished Jan 21 03:05:04 PM PST 24
Peak memory 210692 kb
Host smart-61cba52b-6aca-49dc-bfe3-230f4a4db034
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260322790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1260322790
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1657701754
Short name T290
Test name
Test status
Simulation time 182428820 ps
CPU time 1.33 seconds
Started Jan 21 03:05:01 PM PST 24
Finished Jan 21 03:05:04 PM PST 24
Peak memory 217924 kb
Host smart-43b0ea15-8232-4c72-9ad7-e8e651626b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165770
1754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1657701754
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2639570819
Short name T158
Test name
Test status
Simulation time 115916670 ps
CPU time 1.03 seconds
Started Jan 21 03:05:00 PM PST 24
Finished Jan 21 03:05:02 PM PST 24
Peak memory 209300 kb
Host smart-e6a717fd-ae1c-4cd9-8422-606d2e9e0a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639570819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2639570819
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3714361348
Short name T265
Test name
Test status
Simulation time 88413989 ps
CPU time 1.09 seconds
Started Jan 21 03:05:05 PM PST 24
Finished Jan 21 03:05:07 PM PST 24
Peak memory 209412 kb
Host smart-cca2182f-ff17-45bd-9973-a261463e5228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714361348 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3714361348
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2783070724
Short name T257
Test name
Test status
Simulation time 41918765 ps
CPU time 1.33 seconds
Started Jan 21 03:05:16 PM PST 24
Finished Jan 21 03:05:18 PM PST 24
Peak memory 211276 kb
Host smart-21e710d0-3ba3-4d11-9b00-87e0c773fd42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783070724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2783070724
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2383542701
Short name T132
Test name
Test status
Simulation time 162025816 ps
CPU time 1.92 seconds
Started Jan 21 03:05:12 PM PST 24
Finished Jan 21 03:05:16 PM PST 24
Peak memory 217796 kb
Host smart-efbd094c-4274-4c8a-8fba-88d2010ea802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383542701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2383542701
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4040275826
Short name T139
Test name
Test status
Simulation time 156269636 ps
CPU time 2.02 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:21 PM PST 24
Peak memory 221048 kb
Host smart-c0bd31d5-45c5-41db-87df-3d40e74dcd09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040275826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.4040275826
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1213832719
Short name T245
Test name
Test status
Simulation time 12260488 ps
CPU time 1.09 seconds
Started Jan 21 03:19:36 PM PST 24
Finished Jan 21 03:19:39 PM PST 24
Peak memory 209464 kb
Host smart-3c5201ce-d1a2-4891-8b04-64422c8014e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213832719 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1213832719
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3967985656
Short name T166
Test name
Test status
Simulation time 11812889 ps
CPU time 0.9 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:20 PM PST 24
Peak memory 209288 kb
Host smart-3634fefb-8df4-4755-966f-a7ebe5478bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967985656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3967985656
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.375262377
Short name T272
Test name
Test status
Simulation time 50269165 ps
CPU time 1.05 seconds
Started Jan 21 03:05:08 PM PST 24
Finished Jan 21 03:05:11 PM PST 24
Peak memory 207588 kb
Host smart-686a9588-6a14-4960-9115-bd9a00cfdbeb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375262377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.375262377
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1868060809
Short name T193
Test name
Test status
Simulation time 3781438520 ps
CPU time 10.61 seconds
Started Jan 21 03:05:08 PM PST 24
Finished Jan 21 03:05:20 PM PST 24
Peak memory 209420 kb
Host smart-a9db658e-f39d-4a4a-9e9c-3ef69900e759
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868060809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1868060809
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1841560790
Short name T258
Test name
Test status
Simulation time 4515191962 ps
CPU time 10.64 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:30 PM PST 24
Peak memory 209236 kb
Host smart-1949099f-754c-4336-98c4-b3a9923a7497
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841560790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1841560790
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3286502036
Short name T281
Test name
Test status
Simulation time 60751070 ps
CPU time 2.38 seconds
Started Jan 21 03:05:14 PM PST 24
Finished Jan 21 03:05:17 PM PST 24
Peak memory 218112 kb
Host smart-990cd2f8-0343-45d6-b959-6d2af88d08d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328650
2036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3286502036
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.761974148
Short name T270
Test name
Test status
Simulation time 216830074 ps
CPU time 1.99 seconds
Started Jan 21 03:05:18 PM PST 24
Finished Jan 21 03:05:21 PM PST 24
Peak memory 209084 kb
Host smart-5adecec1-b4be-4767-bb70-afe815fc7930
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761974148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.761974148
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1552653641
Short name T182
Test name
Test status
Simulation time 43897648 ps
CPU time 1.37 seconds
Started Jan 21 03:05:08 PM PST 24
Finished Jan 21 03:05:11 PM PST 24
Peak memory 209576 kb
Host smart-445f1e84-c2ee-48eb-922f-d7ed88f2f4e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552653641 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1552653641
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1450498273
Short name T218
Test name
Test status
Simulation time 137881472 ps
CPU time 1.71 seconds
Started Jan 21 03:05:16 PM PST 24
Finished Jan 21 03:05:18 PM PST 24
Peak memory 211012 kb
Host smart-0320167d-f608-45a8-a3c3-e8fea50d737f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450498273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1450498273
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2442208298
Short name T253
Test name
Test status
Simulation time 550502847 ps
CPU time 3.34 seconds
Started Jan 21 03:05:06 PM PST 24
Finished Jan 21 03:05:11 PM PST 24
Peak memory 217816 kb
Host smart-c67ba71f-5096-4a5f-bcbc-c5b594120f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442208298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2442208298
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.748941624
Short name T577
Test name
Test status
Simulation time 35208772 ps
CPU time 0.83 seconds
Started Jan 21 10:21:17 PM PST 24
Finished Jan 21 10:21:30 PM PST 24
Peak memory 207492 kb
Host smart-22eeab62-d5d5-4f3a-83c5-cb89da623acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748941624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.748941624
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3613670140
Short name T907
Test name
Test status
Simulation time 500701291 ps
CPU time 15 seconds
Started Jan 21 10:21:06 PM PST 24
Finished Jan 21 10:21:32 PM PST 24
Peak memory 225504 kb
Host smart-f325e78f-7d48-4961-b823-2ab9c9e6e143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613670140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3613670140
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1843064331
Short name T435
Test name
Test status
Simulation time 1607044906 ps
CPU time 10.11 seconds
Started Jan 21 10:21:17 PM PST 24
Finished Jan 21 10:21:39 PM PST 24
Peak memory 208960 kb
Host smart-5aad272e-0c44-4528-aa94-8c4ec96d99ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843064331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.1843064331
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.4146700330
Short name T701
Test name
Test status
Simulation time 1088789672 ps
CPU time 34.58 seconds
Started Jan 21 10:21:15 PM PST 24
Finished Jan 21 10:22:03 PM PST 24
Peak memory 217392 kb
Host smart-95fd2abc-657b-4bff-a191-5e4e122a4d7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146700330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.4146700330
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2129876143
Short name T362
Test name
Test status
Simulation time 2340759806 ps
CPU time 14.52 seconds
Started Jan 21 10:21:16 PM PST 24
Finished Jan 21 10:21:43 PM PST 24
Peak memory 217244 kb
Host smart-e0a91298-2da7-433c-8da3-115f0aaa0935
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129876143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.2129876143
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2405334561
Short name T648
Test name
Test status
Simulation time 778749605 ps
CPU time 10.81 seconds
Started Jan 21 10:21:19 PM PST 24
Finished Jan 21 10:21:40 PM PST 24
Peak memory 217464 kb
Host smart-3ba3a46a-2d43-4d29-bf8e-de2487793a50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405334561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2405334561
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4035163982
Short name T576
Test name
Test status
Simulation time 1271194615 ps
CPU time 15.47 seconds
Started Jan 21 10:21:31 PM PST 24
Finished Jan 21 10:21:56 PM PST 24
Peak memory 212204 kb
Host smart-855fefed-795d-476f-8f13-93907a5c05c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035163982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.4035163982
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1013583215
Short name T967
Test name
Test status
Simulation time 1165252780 ps
CPU time 8.75 seconds
Started Jan 21 10:21:20 PM PST 24
Finished Jan 21 10:21:39 PM PST 24
Peak memory 212572 kb
Host smart-14c96242-2e47-4254-bbbc-a7897b33f215
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013583215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1013583215
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2241668464
Short name T886
Test name
Test status
Simulation time 4114280156 ps
CPU time 110.55 seconds
Started Jan 21 10:21:12 PM PST 24
Finished Jan 21 10:23:17 PM PST 24
Peak memory 283180 kb
Host smart-309ce022-0067-4fdc-9540-5cb005a278a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241668464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2241668464
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2720718403
Short name T902
Test name
Test status
Simulation time 3793707506 ps
CPU time 6.78 seconds
Started Jan 21 10:21:12 PM PST 24
Finished Jan 21 10:21:34 PM PST 24
Peak memory 222308 kb
Host smart-950edc7c-1f9a-4f74-8fb2-cd861d20b7e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720718403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2720718403
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2409784059
Short name T610
Test name
Test status
Simulation time 807517625 ps
CPU time 12.18 seconds
Started Jan 21 10:21:12 PM PST 24
Finished Jan 21 10:21:39 PM PST 24
Peak memory 212668 kb
Host smart-c32bb26b-f997-4688-ae65-82863f672ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409784059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2409784059
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.159139887
Short name T116
Test name
Test status
Simulation time 240865426 ps
CPU time 35.04 seconds
Started Jan 21 10:21:17 PM PST 24
Finished Jan 21 10:22:04 PM PST 24
Peak memory 281780 kb
Host smart-c4cd4067-16ac-433b-ac21-29f986bb7fc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159139887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.159139887
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3565175894
Short name T880
Test name
Test status
Simulation time 1195378357 ps
CPU time 13.1 seconds
Started Jan 21 10:21:16 PM PST 24
Finished Jan 21 10:21:42 PM PST 24
Peak memory 218368 kb
Host smart-eb88e231-6998-446d-919b-abfc9b9048d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565175894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3565175894
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1032829801
Short name T298
Test name
Test status
Simulation time 2001831651 ps
CPU time 22.69 seconds
Started Jan 21 10:21:31 PM PST 24
Finished Jan 21 10:22:03 PM PST 24
Peak memory 217272 kb
Host smart-4fabd815-d7a7-4972-8d4e-dd2d2a2de5be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032829801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1032829801
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1806832917
Short name T643
Test name
Test status
Simulation time 319888278 ps
CPU time 9.1 seconds
Started Jan 21 10:21:17 PM PST 24
Finished Jan 21 10:21:38 PM PST 24
Peak memory 217364 kb
Host smart-3dd24db1-5fc2-455c-a87c-28520ff30988
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806832917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
806832917
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1596497780
Short name T78
Test name
Test status
Simulation time 13512123 ps
CPU time 1.15 seconds
Started Jan 21 10:21:07 PM PST 24
Finished Jan 21 10:21:19 PM PST 24
Peak memory 210856 kb
Host smart-86b47fe8-1849-4d37-8a25-f4c3ff30f2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596497780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1596497780
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3969517087
Short name T364
Test name
Test status
Simulation time 658124279 ps
CPU time 18.89 seconds
Started Jan 21 10:21:08 PM PST 24
Finished Jan 21 10:21:39 PM PST 24
Peak memory 250156 kb
Host smart-cc7e7333-382a-4c8b-8fb2-f0b4081b92d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969517087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3969517087
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1879057002
Short name T461
Test name
Test status
Simulation time 89233788 ps
CPU time 8.35 seconds
Started Jan 21 10:21:09 PM PST 24
Finished Jan 21 10:21:30 PM PST 24
Peak memory 245896 kb
Host smart-deb4cd61-ff39-4a18-a657-5f2b3170c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879057002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1879057002
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.967633670
Short name T463
Test name
Test status
Simulation time 7548890684 ps
CPU time 226.69 seconds
Started Jan 21 10:21:16 PM PST 24
Finished Jan 21 10:25:15 PM PST 24
Peak memory 225628 kb
Host smart-43bbfc66-6a07-49df-9933-c23594eaa439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967633670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.967633670
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.957575590
Short name T43
Test name
Test status
Simulation time 77471627 ps
CPU time 0.91 seconds
Started Jan 21 10:21:06 PM PST 24
Finished Jan 21 10:21:18 PM PST 24
Peak memory 210608 kb
Host smart-f77d5f27-4ccb-4443-9818-d507a4ce5c17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957575590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.957575590
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1591413486
Short name T803
Test name
Test status
Simulation time 331193153 ps
CPU time 13.34 seconds
Started Jan 21 10:21:25 PM PST 24
Finished Jan 21 10:21:47 PM PST 24
Peak memory 217364 kb
Host smart-fa734984-d027-477b-8612-46069ecf0fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591413486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1591413486
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1070258090
Short name T589
Test name
Test status
Simulation time 1512054013 ps
CPU time 6.37 seconds
Started Jan 21 10:21:28 PM PST 24
Finished Jan 21 10:21:43 PM PST 24
Peak memory 208476 kb
Host smart-25082d6f-d350-4e18-8da0-4a0daf2d39a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070258090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.1070258090
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.263576253
Short name T102
Test name
Test status
Simulation time 3495826813 ps
CPU time 29.21 seconds
Started Jan 21 10:21:25 PM PST 24
Finished Jan 21 10:22:02 PM PST 24
Peak memory 218408 kb
Host smart-d9216cc5-46a4-440e-b045-8654fff4e830
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263576253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.263576253
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3539104882
Short name T945
Test name
Test status
Simulation time 1565951799 ps
CPU time 2.67 seconds
Started Jan 21 10:21:29 PM PST 24
Finished Jan 21 10:21:41 PM PST 24
Peak memory 209056 kb
Host smart-f4c3c54d-55b9-438d-9491-c6caf7078fc1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539104882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.3539104882
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1684915506
Short name T678
Test name
Test status
Simulation time 185399859 ps
CPU time 3.3 seconds
Started Jan 21 10:21:28 PM PST 24
Finished Jan 21 10:21:40 PM PST 24
Peak memory 217296 kb
Host smart-49f77d83-3cb4-47d0-9e5a-2208ed07eb80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684915506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1684915506
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2874070328
Short name T862
Test name
Test status
Simulation time 874764475 ps
CPU time 23.81 seconds
Started Jan 21 10:21:24 PM PST 24
Finished Jan 21 10:21:56 PM PST 24
Peak memory 212252 kb
Host smart-1f62d438-99aa-4f39-b24b-2b0899b49c53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874070328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2874070328
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3530555556
Short name T77
Test name
Test status
Simulation time 899926583 ps
CPU time 13.17 seconds
Started Jan 21 10:21:28 PM PST 24
Finished Jan 21 10:21:50 PM PST 24
Peak memory 212660 kb
Host smart-01b667f8-c516-4a43-b3bf-085069cdec0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530555556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3530555556
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3970249475
Short name T809
Test name
Test status
Simulation time 1853679253 ps
CPU time 81.95 seconds
Started Jan 21 10:21:30 PM PST 24
Finished Jan 21 10:23:01 PM PST 24
Peak memory 276132 kb
Host smart-b8adafa5-32eb-44cc-94a7-6ae40a72a40c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970249475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3970249475
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1836193997
Short name T527
Test name
Test status
Simulation time 535020134 ps
CPU time 20.6 seconds
Started Jan 21 10:21:30 PM PST 24
Finished Jan 21 10:22:00 PM PST 24
Peak memory 248256 kb
Host smart-f045b43f-f4cb-4539-9a97-e98489f151b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836193997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1836193997
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3967859018
Short name T479
Test name
Test status
Simulation time 857349493 ps
CPU time 3.07 seconds
Started Jan 21 10:21:33 PM PST 24
Finished Jan 21 10:21:46 PM PST 24
Peak memory 217336 kb
Host smart-c28e270b-a71f-4e88-843c-736487abc852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967859018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3967859018
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.4222504458
Short name T734
Test name
Test status
Simulation time 3034264773 ps
CPU time 20.41 seconds
Started Jan 21 10:21:26 PM PST 24
Finished Jan 21 10:21:55 PM PST 24
Peak memory 213256 kb
Host smart-d59b2977-6e63-496d-bb45-ebc6711ce7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222504458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.4222504458
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1786086549
Short name T117
Test name
Test status
Simulation time 477307538 ps
CPU time 34.18 seconds
Started Jan 21 10:21:28 PM PST 24
Finished Jan 21 10:22:11 PM PST 24
Peak memory 268232 kb
Host smart-25c586ed-3de8-4949-baf3-d2c8959a1424
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786086549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1786086549
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.739197383
Short name T625
Test name
Test status
Simulation time 488742051 ps
CPU time 10.07 seconds
Started Jan 21 10:21:26 PM PST 24
Finished Jan 21 10:21:44 PM PST 24
Peak memory 217612 kb
Host smart-26eb3d5c-918e-4e8a-8152-582111a9f37d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739197383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.739197383
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.878169102
Short name T851
Test name
Test status
Simulation time 317468013 ps
CPU time 9.9 seconds
Started Jan 21 10:21:27 PM PST 24
Finished Jan 21 10:21:45 PM PST 24
Peak memory 217332 kb
Host smart-68962e9f-b1ac-4aaa-ba44-95980e764405
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878169102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.878169102
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1119084146
Short name T755
Test name
Test status
Simulation time 346103934 ps
CPU time 13.09 seconds
Started Jan 21 10:21:29 PM PST 24
Finished Jan 21 10:21:51 PM PST 24
Peak memory 217348 kb
Host smart-5004c2e6-a3e3-476c-8354-24f46feda897
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119084146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
119084146
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1778143579
Short name T782
Test name
Test status
Simulation time 346419658 ps
CPU time 13.5 seconds
Started Jan 21 10:21:28 PM PST 24
Finished Jan 21 10:21:51 PM PST 24
Peak memory 217360 kb
Host smart-516645f9-9b80-4550-87ae-cb108c6896b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778143579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1778143579
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2111125282
Short name T315
Test name
Test status
Simulation time 61716511 ps
CPU time 2.4 seconds
Started Jan 21 10:21:17 PM PST 24
Finished Jan 21 10:21:31 PM PST 24
Peak memory 217256 kb
Host smart-888b569e-c3f8-48c3-a332-3c1b7075f92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111125282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2111125282
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3552706797
Short name T424
Test name
Test status
Simulation time 589202467 ps
CPU time 20.4 seconds
Started Jan 21 10:21:27 PM PST 24
Finished Jan 21 10:21:57 PM PST 24
Peak memory 249292 kb
Host smart-c532f675-10e3-4dde-9dc7-a626d0a554e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552706797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3552706797
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1478203300
Short name T679
Test name
Test status
Simulation time 413127104 ps
CPU time 9.17 seconds
Started Jan 21 10:21:24 PM PST 24
Finished Jan 21 10:21:41 PM PST 24
Peak memory 250272 kb
Host smart-8ac92c39-1235-4677-8b89-5be520c08dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478203300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1478203300
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2815793515
Short name T343
Test name
Test status
Simulation time 57730823635 ps
CPU time 185.76 seconds
Started Jan 21 10:21:24 PM PST 24
Finished Jan 21 10:24:38 PM PST 24
Peak memory 250548 kb
Host smart-f1e06b23-9c91-4b73-8c97-b12718331ea9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815793515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2815793515
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3854585817
Short name T699
Test name
Test status
Simulation time 12480422 ps
CPU time 0.78 seconds
Started Jan 21 10:21:27 PM PST 24
Finished Jan 21 10:21:36 PM PST 24
Peak memory 207232 kb
Host smart-556fdde0-0ffb-43bf-bab7-17ed6dde991a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854585817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3854585817
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3185881413
Short name T850
Test name
Test status
Simulation time 31915905 ps
CPU time 1.07 seconds
Started Jan 21 10:23:32 PM PST 24
Finished Jan 21 10:23:38 PM PST 24
Peak memory 207600 kb
Host smart-3761c086-389d-4c4f-b990-bb888cebe039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185881413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3185881413
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.4042131937
Short name T532
Test name
Test status
Simulation time 325185980 ps
CPU time 14.29 seconds
Started Jan 21 10:23:33 PM PST 24
Finished Jan 21 10:23:52 PM PST 24
Peak memory 217368 kb
Host smart-14dc9e05-eb4b-4ae7-ad77-be3a52807496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042131937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.4042131937
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3343574952
Short name T8
Test name
Test status
Simulation time 455819548 ps
CPU time 4.65 seconds
Started Jan 21 10:23:38 PM PST 24
Finished Jan 21 10:23:48 PM PST 24
Peak memory 208944 kb
Host smart-f996bff1-ebeb-4d83-87b7-1128b7767fd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343574952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.3343574952
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2355478005
Short name T975
Test name
Test status
Simulation time 1826406233 ps
CPU time 54.42 seconds
Started Jan 21 10:23:31 PM PST 24
Finished Jan 21 10:24:30 PM PST 24
Peak memory 217304 kb
Host smart-ec4efe45-b591-403f-807e-2bfe48c69030
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355478005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2355478005
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4198773151
Short name T947
Test name
Test status
Simulation time 332697702 ps
CPU time 2.43 seconds
Started Jan 21 10:23:36 PM PST 24
Finished Jan 21 10:23:42 PM PST 24
Peak memory 217236 kb
Host smart-b4218ac1-4d2b-48b1-8008-1dea08cd15f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198773151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4198773151
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2937741194
Short name T88
Test name
Test status
Simulation time 1494154801 ps
CPU time 4.08 seconds
Started Jan 21 10:23:33 PM PST 24
Finished Jan 21 10:23:42 PM PST 24
Peak memory 212124 kb
Host smart-528eb0af-9859-40a0-ad95-8e984615f8fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937741194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2937741194
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3131303795
Short name T128
Test name
Test status
Simulation time 4910587998 ps
CPU time 80.77 seconds
Started Jan 21 10:23:33 PM PST 24
Finished Jan 21 10:24:58 PM PST 24
Peak memory 270940 kb
Host smart-ca90f428-0be2-4bf1-b969-efa3969abf1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131303795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3131303795
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.429912223
Short name T306
Test name
Test status
Simulation time 883339359 ps
CPU time 19.65 seconds
Started Jan 21 10:23:34 PM PST 24
Finished Jan 21 10:23:59 PM PST 24
Peak memory 250368 kb
Host smart-810be7c3-7f70-4c86-b9e3-87e2843fea46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429912223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.429912223
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2731308352
Short name T800
Test name
Test status
Simulation time 126948095 ps
CPU time 2.85 seconds
Started Jan 21 10:23:35 PM PST 24
Finished Jan 21 10:23:42 PM PST 24
Peak memory 217372 kb
Host smart-fbbcfc12-c290-4c18-8900-4c7685ab4982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731308352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2731308352
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2056961959
Short name T741
Test name
Test status
Simulation time 1544345306 ps
CPU time 15.89 seconds
Started Jan 21 10:23:36 PM PST 24
Finished Jan 21 10:23:56 PM PST 24
Peak memory 218392 kb
Host smart-ec384db6-9425-4c81-841b-a3e74ea80b89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056961959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2056961959
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.4020232581
Short name T793
Test name
Test status
Simulation time 949479876 ps
CPU time 10.98 seconds
Started Jan 21 10:23:36 PM PST 24
Finished Jan 21 10:23:51 PM PST 24
Peak memory 217356 kb
Host smart-dbbe57e6-8960-404f-b312-da8d67231cb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020232581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.4020232581
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1456423653
Short name T420
Test name
Test status
Simulation time 6735986560 ps
CPU time 8.48 seconds
Started Jan 21 10:56:15 PM PST 24
Finished Jan 21 10:56:25 PM PST 24
Peak memory 217524 kb
Host smart-4e2154e0-385c-4269-8aa9-e484e428cffc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456423653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1456423653
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1889295141
Short name T302
Test name
Test status
Simulation time 1568210486 ps
CPU time 8.75 seconds
Started Jan 21 10:23:32 PM PST 24
Finished Jan 21 10:23:46 PM PST 24
Peak memory 217352 kb
Host smart-461c2b36-ea1a-4a28-be15-9f4196e447f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889295141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1889295141
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1723230268
Short name T749
Test name
Test status
Simulation time 157230078 ps
CPU time 1.45 seconds
Started Jan 21 11:03:04 PM PST 24
Finished Jan 21 11:03:13 PM PST 24
Peak memory 212364 kb
Host smart-9555a80a-40e6-4542-9aea-11e599619df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723230268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1723230268
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.274641237
Short name T619
Test name
Test status
Simulation time 357104189 ps
CPU time 32.42 seconds
Started Jan 21 10:23:22 PM PST 24
Finished Jan 21 10:24:01 PM PST 24
Peak memory 244980 kb
Host smart-a83f3683-8b54-403a-a650-7a39bb3d5798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274641237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.274641237
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3839635970
Short name T731
Test name
Test status
Simulation time 437432487 ps
CPU time 11.11 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:41 PM PST 24
Peak memory 250180 kb
Host smart-b8667acf-3712-4325-911a-be5850a93c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839635970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3839635970
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.4055230832
Short name T980
Test name
Test status
Simulation time 28556075768 ps
CPU time 550.12 seconds
Started Jan 21 10:23:33 PM PST 24
Finished Jan 21 10:32:48 PM PST 24
Peak memory 252412 kb
Host smart-e61dd03c-709e-4e0b-85ce-acf470a39cc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055230832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.4055230832
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.220002751
Short name T338
Test name
Test status
Simulation time 12334567 ps
CPU time 0.97 seconds
Started Jan 21 10:50:16 PM PST 24
Finished Jan 21 10:50:21 PM PST 24
Peak memory 209040 kb
Host smart-0b0a85ac-6785-4e8b-941e-0f7a69130eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220002751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.220002751
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.139863071
Short name T910
Test name
Test status
Simulation time 390680268 ps
CPU time 12.11 seconds
Started Jan 21 10:49:34 PM PST 24
Finished Jan 21 10:49:47 PM PST 24
Peak memory 217268 kb
Host smart-3a817645-067a-40bb-ac8c-c1410d072f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139863071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.139863071
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1451913081
Short name T954
Test name
Test status
Simulation time 420590322 ps
CPU time 11.27 seconds
Started Jan 21 10:23:39 PM PST 24
Finished Jan 21 10:23:55 PM PST 24
Peak memory 208900 kb
Host smart-ac38aca1-ef83-41eb-8d01-e52b22bd65e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451913081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.1451913081
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2414058562
Short name T368
Test name
Test status
Simulation time 2034925289 ps
CPU time 31.54 seconds
Started Jan 21 10:23:41 PM PST 24
Finished Jan 21 10:24:18 PM PST 24
Peak memory 217284 kb
Host smart-8723d51f-3daa-497f-ad6f-1ffbbec2b5ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414058562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2414058562
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.110373985
Short name T382
Test name
Test status
Simulation time 655462651 ps
CPU time 4.94 seconds
Started Jan 21 10:58:15 PM PST 24
Finished Jan 21 10:58:22 PM PST 24
Peak memory 217280 kb
Host smart-f00e2ee8-3dd8-4454-93b5-4ca6b599dedf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110373985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.110373985
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.553850071
Short name T840
Test name
Test status
Simulation time 280596126 ps
CPU time 2.83 seconds
Started Jan 21 10:56:10 PM PST 24
Finished Jan 21 10:56:14 PM PST 24
Peak memory 212004 kb
Host smart-78346bd9-66fb-4b02-a76c-e99366b9c7a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553850071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
553850071
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.149425288
Short name T635
Test name
Test status
Simulation time 19122317992 ps
CPU time 56.7 seconds
Started Jan 21 10:35:03 PM PST 24
Finished Jan 21 10:36:04 PM PST 24
Peak memory 250424 kb
Host smart-3eacf659-5245-4377-bced-0c1d88da01ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149425288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.149425288
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.638772134
Short name T329
Test name
Test status
Simulation time 2359609306 ps
CPU time 10.18 seconds
Started Jan 21 10:23:38 PM PST 24
Finished Jan 21 10:23:53 PM PST 24
Peak memory 223972 kb
Host smart-6baf9ca5-66bf-4dcd-9787-c9e107132e12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638772134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.638772134
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1565016239
Short name T848
Test name
Test status
Simulation time 307471929 ps
CPU time 3.09 seconds
Started Jan 21 10:54:59 PM PST 24
Finished Jan 21 10:55:09 PM PST 24
Peak memory 217376 kb
Host smart-ee54963c-b493-4cca-8d73-828de4b6560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565016239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1565016239
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2537260030
Short name T896
Test name
Test status
Simulation time 249492715 ps
CPU time 11.02 seconds
Started Jan 21 10:23:40 PM PST 24
Finished Jan 21 10:23:57 PM PST 24
Peak memory 217256 kb
Host smart-09295f11-39b5-431c-af62-06c0bebf7a4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537260030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2537260030
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.486569020
Short name T472
Test name
Test status
Simulation time 1280226945 ps
CPU time 11.41 seconds
Started Jan 21 10:23:45 PM PST 24
Finished Jan 21 10:24:03 PM PST 24
Peak memory 217376 kb
Host smart-282bcc1a-e21f-452f-9c8a-1cb08cf1f81e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486569020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.486569020
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2232647685
Short name T535
Test name
Test status
Simulation time 1989999411 ps
CPU time 11.41 seconds
Started Jan 21 10:23:39 PM PST 24
Finished Jan 21 10:23:56 PM PST 24
Peak memory 217376 kb
Host smart-04fda29d-6710-4c5d-848c-680c9b8ab859
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232647685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2232647685
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.850746567
Short name T68
Test name
Test status
Simulation time 255710189 ps
CPU time 9.85 seconds
Started Jan 21 10:23:39 PM PST 24
Finished Jan 21 10:23:55 PM PST 24
Peak memory 217320 kb
Host smart-25ccc669-2b26-4f87-b6ce-674709c1ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850746567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.850746567
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2602014867
Short name T735
Test name
Test status
Simulation time 38260399 ps
CPU time 1.97 seconds
Started Jan 21 10:23:31 PM PST 24
Finished Jan 21 10:23:38 PM PST 24
Peak memory 212740 kb
Host smart-f93e271e-edbc-4c75-b900-a6ddf603e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602014867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2602014867
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1176434800
Short name T708
Test name
Test status
Simulation time 289932224 ps
CPU time 26.46 seconds
Started Jan 21 10:23:39 PM PST 24
Finished Jan 21 10:24:10 PM PST 24
Peak memory 250344 kb
Host smart-20402fca-0cf2-4e6b-9086-d654c8a23162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176434800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1176434800
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1652771033
Short name T574
Test name
Test status
Simulation time 145425182 ps
CPU time 9.55 seconds
Started Jan 21 10:23:37 PM PST 24
Finished Jan 21 10:23:51 PM PST 24
Peak memory 250016 kb
Host smart-51ba16fb-6778-479b-be77-c395467ca746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652771033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1652771033
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4007202882
Short name T908
Test name
Test status
Simulation time 6477260872 ps
CPU time 137.54 seconds
Started Jan 21 10:23:39 PM PST 24
Finished Jan 21 10:26:03 PM PST 24
Peak memory 272100 kb
Host smart-e7ae452a-33cc-4b91-9e9e-d0f89c07ad9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007202882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4007202882
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2206847924
Short name T682
Test name
Test status
Simulation time 14322062 ps
CPU time 0.83 seconds
Started Jan 21 10:23:39 PM PST 24
Finished Jan 21 10:23:45 PM PST 24
Peak memory 207528 kb
Host smart-d18e8927-c939-4696-b662-ba90c72e676e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206847924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2206847924
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.745490985
Short name T978
Test name
Test status
Simulation time 66672058 ps
CPU time 1.11 seconds
Started Jan 21 10:23:54 PM PST 24
Finished Jan 21 10:23:59 PM PST 24
Peak memory 207632 kb
Host smart-73adc2e9-a434-4574-a390-84295faa7c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745490985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.745490985
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1584473313
Short name T843
Test name
Test status
Simulation time 197957209 ps
CPU time 10.51 seconds
Started Jan 21 11:18:21 PM PST 24
Finished Jan 21 11:18:33 PM PST 24
Peak memory 217440 kb
Host smart-1c4e7ca1-3eb7-43d5-9977-c457148f4c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584473313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1584473313
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.4264161307
Short name T586
Test name
Test status
Simulation time 1831423592 ps
CPU time 22.97 seconds
Started Jan 21 10:23:55 PM PST 24
Finished Jan 21 10:24:23 PM PST 24
Peak memory 208912 kb
Host smart-a9e91e73-518b-4bef-9e7b-73005e4baca4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264161307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_a
ccess.4264161307
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1785089458
Short name T353
Test name
Test status
Simulation time 1305244220 ps
CPU time 42.85 seconds
Started Jan 21 10:23:54 PM PST 24
Finished Jan 21 10:24:39 PM PST 24
Peak memory 217324 kb
Host smart-56a9f52b-6e66-4327-bbeb-a2a04cd4ce4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785089458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1785089458
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1811405804
Short name T515
Test name
Test status
Simulation time 556174146 ps
CPU time 3.73 seconds
Started Jan 21 10:23:54 PM PST 24
Finished Jan 21 10:24:02 PM PST 24
Peak memory 217308 kb
Host smart-db48c76f-fd3b-4f48-bdc5-ba0cac7c7458
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811405804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1811405804
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1213908015
Short name T915
Test name
Test status
Simulation time 194073838 ps
CPU time 6.38 seconds
Started Jan 21 11:11:29 PM PST 24
Finished Jan 21 11:11:36 PM PST 24
Peak memory 212592 kb
Host smart-749b7210-a564-4308-9edf-e448dc5c4f0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213908015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1213908015
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.471752730
Short name T738
Test name
Test status
Simulation time 296730198 ps
CPU time 6.84 seconds
Started Jan 21 10:23:56 PM PST 24
Finished Jan 21 10:24:09 PM PST 24
Peak memory 221804 kb
Host smart-8ed8b96a-59ed-4528-ba99-d7c1e8de8cca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471752730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.471752730
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3096215995
Short name T457
Test name
Test status
Simulation time 41095823 ps
CPU time 2.57 seconds
Started Jan 21 10:23:57 PM PST 24
Finished Jan 21 10:24:06 PM PST 24
Peak memory 217372 kb
Host smart-c70fff9e-1e99-40d4-a8b4-d9a86535b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096215995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3096215995
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3773330991
Short name T671
Test name
Test status
Simulation time 219004708 ps
CPU time 11.03 seconds
Started Jan 21 10:23:58 PM PST 24
Finished Jan 21 10:24:16 PM PST 24
Peak memory 217448 kb
Host smart-7423ebf9-58c0-47be-8fb4-66011eeda9da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773330991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3773330991
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.770849340
Short name T761
Test name
Test status
Simulation time 257851425 ps
CPU time 8.52 seconds
Started Jan 21 10:23:58 PM PST 24
Finished Jan 21 10:24:14 PM PST 24
Peak memory 217336 kb
Host smart-78330b88-2f09-4a51-983b-cd069a2b9e8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770849340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.770849340
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1324023617
Short name T481
Test name
Test status
Simulation time 289288042 ps
CPU time 8.41 seconds
Started Jan 21 10:23:59 PM PST 24
Finished Jan 21 10:24:15 PM PST 24
Peak memory 217380 kb
Host smart-8e5b80a7-a5d5-42c1-8186-c1ee59b18548
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324023617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1324023617
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2080549367
Short name T413
Test name
Test status
Simulation time 915986107 ps
CPU time 9.38 seconds
Started Jan 21 10:23:59 PM PST 24
Finished Jan 21 10:24:15 PM PST 24
Peak memory 217316 kb
Host smart-51453b00-c1e9-405c-99ed-8db455a0394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080549367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2080549367
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3635961247
Short name T375
Test name
Test status
Simulation time 171143008 ps
CPU time 2.34 seconds
Started Jan 21 10:23:59 PM PST 24
Finished Jan 21 10:24:08 PM PST 24
Peak memory 213116 kb
Host smart-31cd45ca-3760-4f4d-81ec-a38ffb7647f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635961247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3635961247
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3642474441
Short name T831
Test name
Test status
Simulation time 379354627 ps
CPU time 19.56 seconds
Started Jan 21 10:23:56 PM PST 24
Finished Jan 21 10:24:21 PM PST 24
Peak memory 250328 kb
Host smart-9974800d-83db-4101-809c-4c518114843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642474441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3642474441
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3921548543
Short name T785
Test name
Test status
Simulation time 53918835 ps
CPU time 5.71 seconds
Started Jan 21 10:51:31 PM PST 24
Finished Jan 21 10:51:38 PM PST 24
Peak memory 245672 kb
Host smart-5ab7f13f-e453-4654-8c37-158d37043728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921548543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3921548543
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3550452970
Short name T952
Test name
Test status
Simulation time 68580839534 ps
CPU time 77.72 seconds
Started Jan 21 10:23:52 PM PST 24
Finished Jan 21 10:25:13 PM PST 24
Peak memory 249336 kb
Host smart-d019bdf5-0981-42f4-ab0a-8a2d06e7f76e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550452970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3550452970
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2680962820
Short name T905
Test name
Test status
Simulation time 31755911 ps
CPU time 0.8 seconds
Started Jan 21 11:40:54 PM PST 24
Finished Jan 21 11:40:56 PM PST 24
Peak memory 207568 kb
Host smart-b5823887-b803-452e-97b1-8cfdb8d153eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680962820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2680962820
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.75166066
Short name T668
Test name
Test status
Simulation time 66819558 ps
CPU time 0.88 seconds
Started Jan 21 10:24:12 PM PST 24
Finished Jan 21 10:24:16 PM PST 24
Peak memory 208820 kb
Host smart-499a9baa-b476-4736-9e47-a36153ba0477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75166066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.75166066
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3182294535
Short name T53
Test name
Test status
Simulation time 613871462 ps
CPU time 13.9 seconds
Started Jan 21 10:23:59 PM PST 24
Finished Jan 21 10:24:20 PM PST 24
Peak memory 217308 kb
Host smart-366216fd-984b-4ed4-a5e8-1a0bce1bc509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182294535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3182294535
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2996083680
Short name T511
Test name
Test status
Simulation time 1842055924 ps
CPU time 10.49 seconds
Started Jan 21 10:24:11 PM PST 24
Finished Jan 21 10:24:25 PM PST 24
Peak memory 208908 kb
Host smart-86d890dc-a621-4512-a839-7fdcfa86e046
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996083680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_a
ccess.2996083680
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2244811384
Short name T742
Test name
Test status
Simulation time 4525163979 ps
CPU time 67.73 seconds
Started Jan 21 10:24:10 PM PST 24
Finished Jan 21 10:25:21 PM PST 24
Peak memory 218444 kb
Host smart-0088b58f-8cb1-4f18-afd1-ca244ce04fee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244811384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2244811384
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1471997061
Short name T537
Test name
Test status
Simulation time 166303771 ps
CPU time 2.06 seconds
Started Jan 21 10:24:14 PM PST 24
Finished Jan 21 10:24:19 PM PST 24
Peak memory 217276 kb
Host smart-e0879ce5-8121-46ca-b3db-f5714df5c15f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471997061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1471997061
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.605287029
Short name T71
Test name
Test status
Simulation time 447897965 ps
CPU time 6.14 seconds
Started Jan 21 10:24:04 PM PST 24
Finished Jan 21 10:24:15 PM PST 24
Peak memory 212576 kb
Host smart-1c20f14f-9535-4c81-ad53-7540f80687fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605287029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
605287029
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3276160530
Short name T600
Test name
Test status
Simulation time 2134348072 ps
CPU time 35.23 seconds
Started Jan 21 10:24:02 PM PST 24
Finished Jan 21 10:24:43 PM PST 24
Peak memory 250252 kb
Host smart-71d64325-599b-467e-8131-29983f26dafe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276160530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3276160530
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.4021405632
Short name T633
Test name
Test status
Simulation time 1684099154 ps
CPU time 11.49 seconds
Started Jan 21 10:23:57 PM PST 24
Finished Jan 21 10:24:16 PM PST 24
Peak memory 249744 kb
Host smart-88bde865-79fc-4d8e-964d-7ae4ac1c217c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021405632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.4021405632
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.180494346
Short name T665
Test name
Test status
Simulation time 152086624 ps
CPU time 2.79 seconds
Started Jan 21 10:24:05 PM PST 24
Finished Jan 21 10:24:13 PM PST 24
Peak memory 217300 kb
Host smart-59e8407a-a0de-4002-aafa-815e537f0ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180494346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.180494346
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1552367282
Short name T566
Test name
Test status
Simulation time 306427369 ps
CPU time 11.49 seconds
Started Jan 21 10:24:08 PM PST 24
Finished Jan 21 10:24:23 PM PST 24
Peak memory 218388 kb
Host smart-41033b21-a8df-411b-ba7e-779d588a7028
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552367282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1552367282
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4024274420
Short name T799
Test name
Test status
Simulation time 306366181 ps
CPU time 12.63 seconds
Started Jan 21 10:24:09 PM PST 24
Finished Jan 21 10:24:25 PM PST 24
Peak memory 217380 kb
Host smart-1fa72cc1-21f1-481d-8c72-86b37786a224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024274420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4024274420
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1930849001
Short name T579
Test name
Test status
Simulation time 2321722192 ps
CPU time 10.52 seconds
Started Jan 21 10:24:08 PM PST 24
Finished Jan 21 10:24:23 PM PST 24
Peak memory 217396 kb
Host smart-5e1b627d-732b-40a1-b248-7bc7cef74297
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930849001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1930849001
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.51868595
Short name T408
Test name
Test status
Simulation time 437351330 ps
CPU time 10.22 seconds
Started Jan 21 10:24:04 PM PST 24
Finished Jan 21 10:24:19 PM PST 24
Peak memory 217368 kb
Host smart-0fe84ba8-949c-479f-b4cd-b61ca9d6f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51868595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.51868595
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1280051296
Short name T971
Test name
Test status
Simulation time 60106005 ps
CPU time 2.7 seconds
Started Jan 21 10:23:57 PM PST 24
Finished Jan 21 10:24:06 PM PST 24
Peak memory 212836 kb
Host smart-abe7f920-67ac-4539-b753-def9c793d62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280051296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1280051296
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.518221217
Short name T867
Test name
Test status
Simulation time 242464402 ps
CPU time 20.26 seconds
Started Jan 21 10:24:03 PM PST 24
Finished Jan 21 10:24:29 PM PST 24
Peak memory 248872 kb
Host smart-778dd4ad-3297-4ad3-aa02-0cb1c0bb7125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518221217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.518221217
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1326437561
Short name T562
Test name
Test status
Simulation time 338300311 ps
CPU time 8.51 seconds
Started Jan 21 10:23:59 PM PST 24
Finished Jan 21 10:24:15 PM PST 24
Peak memory 250416 kb
Host smart-38f44b3d-51b5-4c53-9076-0c8886a56a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326437561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1326437561
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1256762820
Short name T103
Test name
Test status
Simulation time 17356617921 ps
CPU time 247.69 seconds
Started Jan 21 10:24:10 PM PST 24
Finished Jan 21 10:28:21 PM PST 24
Peak memory 283212 kb
Host smart-773366a5-aa74-45b4-b2a4-ac05916b5c43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256762820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1256762820
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.245926683
Short name T876
Test name
Test status
Simulation time 10868025 ps
CPU time 0.91 seconds
Started Jan 21 10:23:55 PM PST 24
Finished Jan 21 10:24:01 PM PST 24
Peak memory 207528 kb
Host smart-c798a7c2-855b-4e37-a032-07555b3a9221
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245926683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.245926683
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2887725014
Short name T336
Test name
Test status
Simulation time 12614977 ps
CPU time 0.97 seconds
Started Jan 21 10:24:23 PM PST 24
Finished Jan 21 10:24:27 PM PST 24
Peak memory 208964 kb
Host smart-3f86ab59-47c2-4a9e-b124-4b28c1ed166b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887725014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2887725014
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.942888056
Short name T621
Test name
Test status
Simulation time 432082741 ps
CPU time 16.93 seconds
Started Jan 21 11:04:35 PM PST 24
Finished Jan 21 11:04:55 PM PST 24
Peak memory 217340 kb
Host smart-6ff61695-7119-41f6-bf0b-b67dc033c0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942888056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.942888056
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2062448213
Short name T590
Test name
Test status
Simulation time 590298414 ps
CPU time 4.2 seconds
Started Jan 21 10:24:23 PM PST 24
Finished Jan 21 10:24:30 PM PST 24
Peak memory 208896 kb
Host smart-4aeae02c-9ab8-4452-be17-6d8043f7ad8e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062448213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_a
ccess.2062448213
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1830871518
Short name T824
Test name
Test status
Simulation time 1550475531 ps
CPU time 28.38 seconds
Started Jan 21 10:24:21 PM PST 24
Finished Jan 21 10:24:51 PM PST 24
Peak memory 217312 kb
Host smart-6de27b6c-ebe7-47dc-b748-1050d1f54fd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830871518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1830871518
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2546234068
Short name T667
Test name
Test status
Simulation time 303293615 ps
CPU time 8.66 seconds
Started Jan 21 10:24:26 PM PST 24
Finished Jan 21 10:24:38 PM PST 24
Peak memory 217212 kb
Host smart-1bd30a1a-768e-4a21-9999-8cd8403d13fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546234068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2546234068
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.427806273
Short name T419
Test name
Test status
Simulation time 290989135 ps
CPU time 4.95 seconds
Started Jan 21 11:05:42 PM PST 24
Finished Jan 21 11:05:48 PM PST 24
Peak memory 212792 kb
Host smart-fd3d93e7-64e4-4549-a131-679eee1b3c54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427806273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
427806273
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.342885121
Short name T505
Test name
Test status
Simulation time 2983602390 ps
CPU time 60.38 seconds
Started Jan 21 10:57:09 PM PST 24
Finished Jan 21 10:58:11 PM PST 24
Peak memory 277288 kb
Host smart-f5204bb8-666e-498c-b627-3942e92b4aad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342885121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.342885121
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.150609570
Short name T759
Test name
Test status
Simulation time 1137932658 ps
CPU time 11.31 seconds
Started Jan 21 10:24:16 PM PST 24
Finished Jan 21 10:24:30 PM PST 24
Peak memory 222912 kb
Host smart-3744bc84-58d4-47ff-aded-7e5bbf7ce751
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150609570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.150609570
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1920639588
Short name T620
Test name
Test status
Simulation time 138486293 ps
CPU time 3.56 seconds
Started Jan 21 10:45:46 PM PST 24
Finished Jan 21 10:45:50 PM PST 24
Peak memory 217380 kb
Host smart-8868e2d8-6748-4e8c-bdb2-83147e446267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920639588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1920639588
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2323240683
Short name T654
Test name
Test status
Simulation time 882985849 ps
CPU time 14.43 seconds
Started Jan 21 10:24:25 PM PST 24
Finished Jan 21 10:24:42 PM PST 24
Peak memory 218276 kb
Host smart-d2beb06b-0882-45d6-9ce3-bfe093b965d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323240683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2323240683
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2663289294
Short name T631
Test name
Test status
Simulation time 863515790 ps
CPU time 14.59 seconds
Started Jan 21 10:24:22 PM PST 24
Finished Jan 21 10:24:39 PM PST 24
Peak memory 217328 kb
Host smart-ea6db641-4709-4142-8a21-685b2ff7ced4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663289294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2663289294
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4004074135
Short name T674
Test name
Test status
Simulation time 741347518 ps
CPU time 14.76 seconds
Started Jan 21 10:24:21 PM PST 24
Finished Jan 21 10:24:38 PM PST 24
Peak memory 217368 kb
Host smart-f9f48f36-e936-42bd-a080-31e375269d95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004074135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
4004074135
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3250644698
Short name T919
Test name
Test status
Simulation time 580750682 ps
CPU time 11.87 seconds
Started Jan 21 10:49:37 PM PST 24
Finished Jan 21 10:49:50 PM PST 24
Peak memory 217352 kb
Host smart-a65658fa-3709-427d-a681-c4bcd6c4e368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250644698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3250644698
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1586121803
Short name T89
Test name
Test status
Simulation time 71747263 ps
CPU time 2.7 seconds
Started Jan 21 10:24:07 PM PST 24
Finished Jan 21 10:24:14 PM PST 24
Peak memory 213180 kb
Host smart-f446a3e8-9f35-4ea5-ada8-067fffc4a295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586121803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1586121803
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1607845347
Short name T883
Test name
Test status
Simulation time 256665180 ps
CPU time 30.84 seconds
Started Jan 21 10:50:00 PM PST 24
Finished Jan 21 10:50:33 PM PST 24
Peak memory 250432 kb
Host smart-3de94dae-56ef-4c4f-af43-5a3daaa803a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607845347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1607845347
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4133338437
Short name T918
Test name
Test status
Simulation time 91303559 ps
CPU time 7.54 seconds
Started Jan 21 10:24:14 PM PST 24
Finished Jan 21 10:24:25 PM PST 24
Peak memory 250428 kb
Host smart-a459143c-a434-42e4-9a1a-77209bd0d74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133338437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4133338437
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3427462490
Short name T82
Test name
Test status
Simulation time 9579859380 ps
CPU time 168.1 seconds
Started Jan 21 10:24:23 PM PST 24
Finished Jan 21 10:27:14 PM PST 24
Peak memory 266892 kb
Host smart-d0dec702-8767-496e-beae-8e361e67610f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427462490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3427462490
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2776483135
Short name T641
Test name
Test status
Simulation time 43447529 ps
CPU time 0.83 seconds
Started Jan 21 10:24:10 PM PST 24
Finished Jan 21 10:24:14 PM PST 24
Peak memory 207244 kb
Host smart-02cab830-879f-423e-87fa-17360f5587ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776483135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2776483135
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3158255966
Short name T421
Test name
Test status
Simulation time 32554649 ps
CPU time 0.91 seconds
Started Jan 21 10:24:34 PM PST 24
Finished Jan 21 10:24:40 PM PST 24
Peak memory 208988 kb
Host smart-39bafbbc-5874-40ae-be61-ca611194dbf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158255966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3158255966
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1603698358
Short name T820
Test name
Test status
Simulation time 269649041 ps
CPU time 11.65 seconds
Started Jan 21 10:24:29 PM PST 24
Finished Jan 21 10:24:44 PM PST 24
Peak memory 217336 kb
Host smart-61b39534-242a-4df3-b1a9-78c7ca5fe2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603698358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1603698358
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2136608174
Short name T423
Test name
Test status
Simulation time 7329578765 ps
CPU time 7.74 seconds
Started Jan 21 10:24:31 PM PST 24
Finished Jan 21 10:24:42 PM PST 24
Peak memory 209096 kb
Host smart-5429a29a-bb3e-426e-b9fb-0febb3dd5750
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136608174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.2136608174
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1347918139
Short name T982
Test name
Test status
Simulation time 7539353915 ps
CPU time 28.69 seconds
Started Jan 21 10:24:30 PM PST 24
Finished Jan 21 10:25:02 PM PST 24
Peak memory 217472 kb
Host smart-c92a4d3a-5f5b-4476-b35b-3d3a038e6510
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347918139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1347918139
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3216324862
Short name T23
Test name
Test status
Simulation time 1477429195 ps
CPU time 12.64 seconds
Started Jan 21 10:50:27 PM PST 24
Finished Jan 21 10:50:40 PM PST 24
Peak memory 217364 kb
Host smart-44a4b809-6cef-4487-97c2-c54af0fcb8ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216324862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3216324862
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2777177381
Short name T784
Test name
Test status
Simulation time 263997221 ps
CPU time 4.84 seconds
Started Jan 21 10:24:30 PM PST 24
Finished Jan 21 10:24:38 PM PST 24
Peak memory 212372 kb
Host smart-5c1af5d8-248b-4992-a73c-c237c939ca7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777177381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2777177381
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.974384283
Short name T685
Test name
Test status
Simulation time 1775370133 ps
CPU time 66.87 seconds
Started Jan 21 10:42:25 PM PST 24
Finished Jan 21 10:43:32 PM PST 24
Peak memory 273168 kb
Host smart-91e1b1dc-0363-4cf7-a123-7513a9ddefdd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974384283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.974384283
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1795784073
Short name T119
Test name
Test status
Simulation time 806734140 ps
CPU time 12.58 seconds
Started Jan 21 10:24:30 PM PST 24
Finished Jan 21 10:24:46 PM PST 24
Peak memory 223960 kb
Host smart-1e636d5f-9b7d-43a5-b394-d66e2e4db90c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795784073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1795784073
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.999061351
Short name T847
Test name
Test status
Simulation time 42414580 ps
CPU time 2.5 seconds
Started Jan 21 10:24:23 PM PST 24
Finished Jan 21 10:24:28 PM PST 24
Peak memory 217376 kb
Host smart-e70dce4c-18c8-44db-97c5-266757c78975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999061351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.999061351
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.378354746
Short name T335
Test name
Test status
Simulation time 440907902 ps
CPU time 8.28 seconds
Started Jan 21 10:24:29 PM PST 24
Finished Jan 21 10:24:41 PM PST 24
Peak memory 217356 kb
Host smart-3757ea0a-1645-4c88-86ba-94c4bded0b11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378354746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.378354746
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2939120141
Short name T817
Test name
Test status
Simulation time 385426949 ps
CPU time 8.5 seconds
Started Jan 21 10:24:32 PM PST 24
Finished Jan 21 10:24:44 PM PST 24
Peak memory 217372 kb
Host smart-a5cec92f-c223-4ac2-9c3f-87090d294935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939120141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2939120141
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2551567473
Short name T385
Test name
Test status
Simulation time 471369601 ps
CPU time 9.73 seconds
Started Jan 21 10:24:30 PM PST 24
Finished Jan 21 10:24:43 PM PST 24
Peak memory 217372 kb
Host smart-cd7c99a1-6080-4b0e-a06f-cf523952c48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551567473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2551567473
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3379635189
Short name T407
Test name
Test status
Simulation time 170073455 ps
CPU time 2.18 seconds
Started Jan 21 10:24:25 PM PST 24
Finished Jan 21 10:24:30 PM PST 24
Peak memory 212660 kb
Host smart-ff5f9ea9-2f2f-4237-91ae-3a769aec18ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379635189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3379635189
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3965742985
Short name T776
Test name
Test status
Simulation time 576085902 ps
CPU time 30.76 seconds
Started Jan 21 10:24:28 PM PST 24
Finished Jan 21 10:25:02 PM PST 24
Peak memory 250084 kb
Host smart-678990f4-f121-4502-b1e6-8272f1d7ba68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965742985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3965742985
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2906963643
Short name T391
Test name
Test status
Simulation time 124652527 ps
CPU time 6.5 seconds
Started Jan 21 10:24:26 PM PST 24
Finished Jan 21 10:24:36 PM PST 24
Peak memory 250192 kb
Host smart-33fe708a-58f9-423c-83ac-9dfef40df683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906963643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2906963643
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3159119076
Short name T402
Test name
Test status
Simulation time 115658783320 ps
CPU time 377.38 seconds
Started Jan 21 10:24:29 PM PST 24
Finished Jan 21 10:30:50 PM PST 24
Peak memory 281964 kb
Host smart-ba253327-8a19-43fa-b77c-7e6e0494a49e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159119076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3159119076
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2794645627
Short name T460
Test name
Test status
Simulation time 35325096 ps
CPU time 0.76 seconds
Started Jan 21 10:55:35 PM PST 24
Finished Jan 21 10:55:38 PM PST 24
Peak memory 207436 kb
Host smart-4d151513-695e-4df9-9900-7bc696b45949
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794645627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2794645627
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1376043693
Short name T861
Test name
Test status
Simulation time 37700260 ps
CPU time 1.17 seconds
Started Jan 21 10:24:42 PM PST 24
Finished Jan 21 10:24:52 PM PST 24
Peak memory 208876 kb
Host smart-0cc86145-a06a-487a-a943-c3b46647ad5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376043693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1376043693
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2656915763
Short name T349
Test name
Test status
Simulation time 1228695466 ps
CPU time 10.95 seconds
Started Jan 21 10:24:50 PM PST 24
Finished Jan 21 10:25:07 PM PST 24
Peak memory 217284 kb
Host smart-f6690da9-1e20-4bba-97e5-dfb068f64c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656915763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2656915763
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1509836254
Short name T356
Test name
Test status
Simulation time 285977428 ps
CPU time 4.1 seconds
Started Jan 21 10:24:40 PM PST 24
Finished Jan 21 10:24:53 PM PST 24
Peak memory 208968 kb
Host smart-102be398-73a8-4634-b657-95b0e7e0337e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509836254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.1509836254
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3791708726
Short name T372
Test name
Test status
Simulation time 7407080620 ps
CPU time 47.57 seconds
Started Jan 21 10:57:26 PM PST 24
Finished Jan 21 10:58:16 PM PST 24
Peak memory 218660 kb
Host smart-572a46c4-77bc-4cfb-84c1-f7e9595fba91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791708726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3791708726
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4039447015
Short name T307
Test name
Test status
Simulation time 128752625 ps
CPU time 5.13 seconds
Started Jan 21 10:24:39 PM PST 24
Finished Jan 21 10:24:52 PM PST 24
Peak memory 217304 kb
Host smart-3b6229d3-a120-4e39-a200-61562bb4f167
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039447015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4039447015
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.844064320
Short name T961
Test name
Test status
Simulation time 390425970 ps
CPU time 5.46 seconds
Started Jan 21 10:24:40 PM PST 24
Finished Jan 21 10:24:54 PM PST 24
Peak memory 217140 kb
Host smart-c315a38d-0eb3-47cd-bb42-fb1c8399fcb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844064320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
844064320
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.793421067
Short name T706
Test name
Test status
Simulation time 15125239921 ps
CPU time 63.69 seconds
Started Jan 21 10:53:38 PM PST 24
Finished Jan 21 10:54:42 PM PST 24
Peak memory 287736 kb
Host smart-728ec252-fc0d-4ca8-b369-530ca58c9a28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793421067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.793421067
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.836614534
Short name T899
Test name
Test status
Simulation time 602284523 ps
CPU time 22.38 seconds
Started Jan 21 10:24:50 PM PST 24
Finished Jan 21 10:25:18 PM PST 24
Peak memory 247776 kb
Host smart-6d17aef8-c678-44b6-8bb6-67399859d671
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836614534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.836614534
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.625640019
Short name T480
Test name
Test status
Simulation time 195818967 ps
CPU time 4.54 seconds
Started Jan 21 10:24:35 PM PST 24
Finished Jan 21 10:24:44 PM PST 24
Peak memory 217364 kb
Host smart-ff2ce547-987d-4e7e-b11e-ee0ed5ec5c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625640019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.625640019
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.306665898
Short name T958
Test name
Test status
Simulation time 1245694126 ps
CPU time 16.85 seconds
Started Jan 21 10:24:44 PM PST 24
Finished Jan 21 10:25:09 PM PST 24
Peak memory 217592 kb
Host smart-b1b5e17f-8436-4e43-9f51-6d2fca0d5560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306665898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.306665898
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2452814820
Short name T328
Test name
Test status
Simulation time 3774270718 ps
CPU time 16.39 seconds
Started Jan 21 10:24:53 PM PST 24
Finished Jan 21 10:25:13 PM PST 24
Peak memory 217424 kb
Host smart-2b9da1c3-20d5-4b98-b773-f6008113c901
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452814820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2452814820
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3992577683
Short name T879
Test name
Test status
Simulation time 390982416 ps
CPU time 13.22 seconds
Started Jan 21 10:24:41 PM PST 24
Finished Jan 21 10:25:03 PM PST 24
Peak memory 217332 kb
Host smart-400b3d2b-c167-476b-82c8-0eb3764ff715
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992577683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3992577683
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2342976670
Short name T536
Test name
Test status
Simulation time 892802253 ps
CPU time 7.35 seconds
Started Jan 21 10:24:53 PM PST 24
Finished Jan 21 10:25:04 PM PST 24
Peak memory 217304 kb
Host smart-d621e9e5-6771-4f5b-8065-1b691b7b8219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342976670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2342976670
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2610941189
Short name T948
Test name
Test status
Simulation time 65198933 ps
CPU time 3.34 seconds
Started Jan 21 10:24:32 PM PST 24
Finished Jan 21 10:24:39 PM PST 24
Peak memory 213636 kb
Host smart-db09eadb-cbcf-4ad8-be0a-c932dd852915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610941189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2610941189
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.718259926
Short name T730
Test name
Test status
Simulation time 294949948 ps
CPU time 24.9 seconds
Started Jan 21 10:24:50 PM PST 24
Finished Jan 21 10:25:21 PM PST 24
Peak memory 250272 kb
Host smart-abb59a4a-e747-42d7-92fb-746ff3b33691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718259926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.718259926
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3977044189
Short name T440
Test name
Test status
Simulation time 195075380 ps
CPU time 6.76 seconds
Started Jan 21 10:24:53 PM PST 24
Finished Jan 21 10:25:03 PM PST 24
Peak memory 249456 kb
Host smart-713b0785-31db-415b-8ec4-a3aaea629cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977044189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3977044189
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3243483301
Short name T725
Test name
Test status
Simulation time 17717223259 ps
CPU time 176.23 seconds
Started Jan 21 10:24:45 PM PST 24
Finished Jan 21 10:27:49 PM PST 24
Peak memory 283240 kb
Host smart-da8146ed-55d5-42c7-bd61-3d3cac2349d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243483301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3243483301
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1322039839
Short name T70
Test name
Test status
Simulation time 17631784 ps
CPU time 0.94 seconds
Started Jan 21 10:24:29 PM PST 24
Finished Jan 21 10:24:34 PM PST 24
Peak memory 210628 kb
Host smart-91e1357b-4a8b-43fe-906f-e69b352d7a03
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322039839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1322039839
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1054209334
Short name T416
Test name
Test status
Simulation time 63447383 ps
CPU time 1.12 seconds
Started Jan 21 10:25:00 PM PST 24
Finished Jan 21 10:25:06 PM PST 24
Peak memory 208992 kb
Host smart-845bca16-d4d0-407d-8602-73f2a5b961c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054209334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1054209334
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2339075863
Short name T712
Test name
Test status
Simulation time 334472001 ps
CPU time 15.77 seconds
Started Jan 21 10:24:53 PM PST 24
Finished Jan 21 10:25:12 PM PST 24
Peak memory 217352 kb
Host smart-eaf34d49-2a76-488a-bfc8-161a3d04fb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339075863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2339075863
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3257315102
Short name T858
Test name
Test status
Simulation time 2176876626 ps
CPU time 8.23 seconds
Started Jan 21 10:25:00 PM PST 24
Finished Jan 21 10:25:14 PM PST 24
Peak memory 209008 kb
Host smart-23517e91-9d20-47ff-a171-5791474cd78a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257315102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.3257315102
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2593781985
Short name T486
Test name
Test status
Simulation time 8317000672 ps
CPU time 30.51 seconds
Started Jan 21 10:24:49 PM PST 24
Finished Jan 21 10:25:26 PM PST 24
Peak memory 218492 kb
Host smart-be61a081-ed30-49c4-b6f5-766ae4c35f9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593781985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2593781985
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3849380507
Short name T314
Test name
Test status
Simulation time 837705213 ps
CPU time 3.49 seconds
Started Jan 21 10:24:50 PM PST 24
Finished Jan 21 10:24:59 PM PST 24
Peak memory 217320 kb
Host smart-46fcf6df-988f-44df-a899-0fff11857069
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849380507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3849380507
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2122812912
Short name T856
Test name
Test status
Simulation time 332237268 ps
CPU time 5.07 seconds
Started Jan 21 10:24:51 PM PST 24
Finished Jan 21 10:25:01 PM PST 24
Peak memory 212424 kb
Host smart-175c0fa6-43a5-4771-94e5-8c90e04ce3f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122812912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2122812912
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.957222547
Short name T661
Test name
Test status
Simulation time 7798884459 ps
CPU time 65.87 seconds
Started Jan 21 10:24:52 PM PST 24
Finished Jan 21 10:26:02 PM PST 24
Peak memory 272956 kb
Host smart-69a932c2-3b57-431b-a00a-fbe41a91a014
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957222547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.957222547
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2644017924
Short name T791
Test name
Test status
Simulation time 2439534363 ps
CPU time 25.74 seconds
Started Jan 21 10:24:55 PM PST 24
Finished Jan 21 10:25:23 PM PST 24
Peak memory 250448 kb
Host smart-946fecb2-83ed-429c-b5dd-b3e4181ff1c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644017924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2644017924
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1214637794
Short name T688
Test name
Test status
Simulation time 61541225 ps
CPU time 2.27 seconds
Started Jan 21 10:24:51 PM PST 24
Finished Jan 21 10:24:58 PM PST 24
Peak memory 217472 kb
Host smart-4014fe91-9bb2-4add-b9c3-7b6d6204a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214637794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1214637794
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.273799467
Short name T686
Test name
Test status
Simulation time 1583345800 ps
CPU time 11.29 seconds
Started Jan 21 10:24:57 PM PST 24
Finished Jan 21 10:25:10 PM PST 24
Peak memory 217356 kb
Host smart-03466273-93c0-4b28-aab7-213ace9d8c7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273799467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.273799467
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2724880066
Short name T715
Test name
Test status
Simulation time 322000858 ps
CPU time 13.76 seconds
Started Jan 21 10:24:58 PM PST 24
Finished Jan 21 10:25:13 PM PST 24
Peak memory 217328 kb
Host smart-9bad3227-8c48-4792-8dbf-d6e65c420366
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724880066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2724880066
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2624045352
Short name T736
Test name
Test status
Simulation time 853462630 ps
CPU time 8.43 seconds
Started Jan 21 10:24:59 PM PST 24
Finished Jan 21 10:25:11 PM PST 24
Peak memory 217340 kb
Host smart-5ddab700-5157-411f-877d-5e5389c2e27f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624045352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2624045352
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3040379506
Short name T91
Test name
Test status
Simulation time 1076707517 ps
CPU time 12.26 seconds
Started Jan 21 10:49:58 PM PST 24
Finished Jan 21 10:50:12 PM PST 24
Peak memory 217376 kb
Host smart-2587701a-69f2-4c38-9f8d-0cf9eabc669e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040379506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3040379506
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2276692342
Short name T827
Test name
Test status
Simulation time 37683755 ps
CPU time 2.14 seconds
Started Jan 21 11:21:16 PM PST 24
Finished Jan 21 11:21:19 PM PST 24
Peak memory 213432 kb
Host smart-ddbebaab-f068-4cf7-bcd4-c93810dd028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276692342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2276692342
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2550431553
Short name T869
Test name
Test status
Simulation time 727379824 ps
CPU time 17.17 seconds
Started Jan 21 10:24:42 PM PST 24
Finished Jan 21 10:25:08 PM PST 24
Peak memory 250228 kb
Host smart-a675a3bb-33a6-4e0a-a75e-4522bf6dc38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550431553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2550431553
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.56646997
Short name T392
Test name
Test status
Simulation time 158830454 ps
CPU time 2.99 seconds
Started Jan 21 11:22:26 PM PST 24
Finished Jan 21 11:22:33 PM PST 24
Peak memory 217440 kb
Host smart-0e349645-24ee-4ef1-bcc3-e042b99b2dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56646997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.56646997
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.4274819236
Short name T591
Test name
Test status
Simulation time 11961791237 ps
CPU time 129.54 seconds
Started Jan 21 10:24:58 PM PST 24
Finished Jan 21 10:27:10 PM PST 24
Peak memory 267328 kb
Host smart-1bb181b9-675b-4b3e-ae10-6ce87d154bdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274819236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.4274819236
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3205812196
Short name T44
Test name
Test status
Simulation time 11654951 ps
CPU time 0.91 seconds
Started Jan 21 10:24:43 PM PST 24
Finished Jan 21 10:24:52 PM PST 24
Peak memory 207340 kb
Host smart-5c6fd4b4-522c-4e37-b5bf-1cffb3b2e679
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205812196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3205812196
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.214238812
Short name T551
Test name
Test status
Simulation time 30344620 ps
CPU time 1.07 seconds
Started Jan 21 10:25:13 PM PST 24
Finished Jan 21 10:25:16 PM PST 24
Peak memory 207576 kb
Host smart-8a8415dc-a7ae-4e37-a4ba-678b0940a772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214238812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.214238812
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3027577956
Short name T300
Test name
Test status
Simulation time 989547650 ps
CPU time 12.21 seconds
Started Jan 21 10:25:06 PM PST 24
Finished Jan 21 10:25:20 PM PST 24
Peak memory 217412 kb
Host smart-7f324ee7-6533-4afb-bd42-f19ccf11faf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027577956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3027577956
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.777181348
Short name T36
Test name
Test status
Simulation time 3701493633 ps
CPU time 6.64 seconds
Started Jan 21 10:25:13 PM PST 24
Finished Jan 21 10:25:21 PM PST 24
Peak memory 209148 kb
Host smart-cd820665-53c9-4ba6-b8d0-01a569f531f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777181348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_ac
cess.777181348
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.54803105
Short name T446
Test name
Test status
Simulation time 7403325387 ps
CPU time 28.97 seconds
Started Jan 21 10:25:06 PM PST 24
Finished Jan 21 10:25:37 PM PST 24
Peak memory 217520 kb
Host smart-82448591-3ffa-4cde-9829-fd88210b8760
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54803105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_err
ors.54803105
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4186126290
Short name T301
Test name
Test status
Simulation time 3252223625 ps
CPU time 10.9 seconds
Started Jan 21 10:25:14 PM PST 24
Finished Jan 21 10:25:27 PM PST 24
Peak memory 217372 kb
Host smart-e44cf416-b16d-4fba-b6ca-2a12e9f51408
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186126290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.4186126290
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2724635239
Short name T75
Test name
Test status
Simulation time 744253793 ps
CPU time 6.03 seconds
Started Jan 21 10:25:15 PM PST 24
Finished Jan 21 10:25:23 PM PST 24
Peak memory 212384 kb
Host smart-0dfcfeb6-0b4a-4e34-8416-3d3b0ccd91bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724635239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2724635239
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.950178914
Short name T717
Test name
Test status
Simulation time 4435544182 ps
CPU time 44.49 seconds
Started Jan 21 10:25:09 PM PST 24
Finished Jan 21 10:25:55 PM PST 24
Peak memory 251836 kb
Host smart-b7a61781-f695-4c97-bb26-209d1543dccf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950178914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.950178914
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3617455402
Short name T325
Test name
Test status
Simulation time 2706554198 ps
CPU time 11.52 seconds
Started Jan 21 10:25:08 PM PST 24
Finished Jan 21 10:25:21 PM PST 24
Peak memory 223280 kb
Host smart-adf90543-211a-49ec-bc73-afcfd1bb8fb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617455402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3617455402
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3168456479
Short name T15
Test name
Test status
Simulation time 372734952 ps
CPU time 3.36 seconds
Started Jan 21 10:25:15 PM PST 24
Finished Jan 21 10:25:20 PM PST 24
Peak memory 217316 kb
Host smart-7ea7a286-a57a-486b-91e0-0e317d919b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168456479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3168456479
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1358668661
Short name T571
Test name
Test status
Simulation time 268973072 ps
CPU time 8.88 seconds
Started Jan 21 10:25:16 PM PST 24
Finished Jan 21 10:25:28 PM PST 24
Peak memory 217368 kb
Host smart-53c24e0c-13e1-4f94-a6e4-3716fe586477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358668661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1358668661
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2502679547
Short name T496
Test name
Test status
Simulation time 1366281389 ps
CPU time 11.78 seconds
Started Jan 21 10:25:08 PM PST 24
Finished Jan 21 10:25:22 PM PST 24
Peak memory 217336 kb
Host smart-2e8bd29a-d51d-4e49-a8d1-958ac23814eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502679547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2502679547
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2045688975
Short name T533
Test name
Test status
Simulation time 353190289 ps
CPU time 9.34 seconds
Started Jan 21 10:25:13 PM PST 24
Finished Jan 21 10:25:24 PM PST 24
Peak memory 217372 kb
Host smart-04ca63ad-5255-4435-9afc-b0b6a2d8c74b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045688975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2045688975
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.699369399
Short name T733
Test name
Test status
Simulation time 571962783 ps
CPU time 7.96 seconds
Started Jan 21 10:25:12 PM PST 24
Finished Jan 21 10:25:22 PM PST 24
Peak memory 217364 kb
Host smart-2b16ad9b-91d6-40c6-bce6-aabebcdc5019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699369399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.699369399
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3463315460
Short name T580
Test name
Test status
Simulation time 113836045 ps
CPU time 2.62 seconds
Started Jan 21 10:25:00 PM PST 24
Finished Jan 21 10:25:08 PM PST 24
Peak memory 213108 kb
Host smart-edb0be58-ee81-4d78-806f-61ffd9488696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463315460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3463315460
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1375322967
Short name T872
Test name
Test status
Simulation time 920050564 ps
CPU time 19.85 seconds
Started Jan 21 10:25:06 PM PST 24
Finished Jan 21 10:25:28 PM PST 24
Peak memory 250224 kb
Host smart-d4da96af-2085-484a-b9f5-a35598b79c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375322967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1375322967
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2693238053
Short name T19
Test name
Test status
Simulation time 267483145 ps
CPU time 6.5 seconds
Started Jan 21 10:25:08 PM PST 24
Finished Jan 21 10:25:17 PM PST 24
Peak memory 250184 kb
Host smart-7385d0a6-b9bb-498d-9926-e873d0d01568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693238053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2693238053
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2953423956
Short name T418
Test name
Test status
Simulation time 10922516365 ps
CPU time 53.85 seconds
Started Jan 21 10:25:13 PM PST 24
Finished Jan 21 10:26:08 PM PST 24
Peak memory 250256 kb
Host smart-a37e7ebf-b72a-4c69-8ce7-ada7b9f6d223
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953423956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2953423956
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.678144102
Short name T467
Test name
Test status
Simulation time 15974631 ps
CPU time 0.83 seconds
Started Jan 21 10:25:06 PM PST 24
Finished Jan 21 10:25:09 PM PST 24
Peak memory 206940 kb
Host smart-d40aa4a8-2afd-4096-b3b1-6951bc0b6993
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678144102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.678144102
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1881443604
Short name T28
Test name
Test status
Simulation time 17525442 ps
CPU time 1.11 seconds
Started Jan 21 11:11:46 PM PST 24
Finished Jan 21 11:11:48 PM PST 24
Peak memory 208956 kb
Host smart-5138bb8a-ab8e-48fe-92a2-368811e3b954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881443604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1881443604
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3594028283
Short name T659
Test name
Test status
Simulation time 2271372532 ps
CPU time 22.86 seconds
Started Jan 21 10:25:23 PM PST 24
Finished Jan 21 10:25:50 PM PST 24
Peak memory 217412 kb
Host smart-41f5a302-d530-42cf-a19a-d56e1c164b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594028283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3594028283
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3468018180
Short name T611
Test name
Test status
Simulation time 1356380246 ps
CPU time 33.02 seconds
Started Jan 21 10:25:18 PM PST 24
Finished Jan 21 10:25:53 PM PST 24
Peak memory 217292 kb
Host smart-988c0da1-c08a-4367-88a9-969c35b911b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468018180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3468018180
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3664714912
Short name T344
Test name
Test status
Simulation time 646016956 ps
CPU time 5.82 seconds
Started Jan 21 10:25:23 PM PST 24
Finished Jan 21 10:25:33 PM PST 24
Peak memory 217288 kb
Host smart-25aa1d25-5bbb-4df0-8ad8-b97b4016de9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664714912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3664714912
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3116044024
Short name T854
Test name
Test status
Simulation time 328308203 ps
CPU time 9.68 seconds
Started Jan 21 10:25:17 PM PST 24
Finished Jan 21 10:25:29 PM PST 24
Peak memory 212620 kb
Host smart-d21bd0d9-fac2-495f-b3f9-644546418c8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116044024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3116044024
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.776123992
Short name T121
Test name
Test status
Simulation time 3124322499 ps
CPU time 61.05 seconds
Started Jan 21 10:25:24 PM PST 24
Finished Jan 21 10:26:29 PM PST 24
Peak memory 272472 kb
Host smart-8c7bf4e6-25c4-4052-adcc-7ab35c8e42b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776123992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.776123992
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.632432346
Short name T762
Test name
Test status
Simulation time 502733020 ps
CPU time 15.58 seconds
Started Jan 21 10:25:23 PM PST 24
Finished Jan 21 10:25:43 PM PST 24
Peak memory 250260 kb
Host smart-6cae2a63-0856-49c1-ae85-e07d8feb5afa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632432346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.632432346
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2551739363
Short name T943
Test name
Test status
Simulation time 72543096 ps
CPU time 3.31 seconds
Started Jan 21 10:25:24 PM PST 24
Finished Jan 21 10:25:31 PM PST 24
Peak memory 217292 kb
Host smart-d1400d01-df3d-422a-bd9f-521216824d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551739363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2551739363
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.659150493
Short name T504
Test name
Test status
Simulation time 1512992109 ps
CPU time 11.61 seconds
Started Jan 21 10:25:23 PM PST 24
Finished Jan 21 10:25:38 PM PST 24
Peak memory 217272 kb
Host smart-e661d1fc-1a8f-4366-9706-015e94d938d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659150493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.659150493
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1848412015
Short name T770
Test name
Test status
Simulation time 2677142843 ps
CPU time 13.49 seconds
Started Jan 21 11:44:32 PM PST 24
Finished Jan 21 11:44:47 PM PST 24
Peak memory 217592 kb
Host smart-9905e764-7153-487b-b229-ff0974c23230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848412015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1848412015
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.4247530679
Short name T704
Test name
Test status
Simulation time 992438826 ps
CPU time 8.09 seconds
Started Jan 21 10:25:24 PM PST 24
Finished Jan 21 10:25:36 PM PST 24
Peak memory 217136 kb
Host smart-5040fbe7-610e-4bcf-b891-53835b96e0e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247530679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
4247530679
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3884044595
Short name T506
Test name
Test status
Simulation time 1316415852 ps
CPU time 7.85 seconds
Started Jan 21 10:25:15 PM PST 24
Finished Jan 21 10:25:25 PM PST 24
Peak memory 217300 kb
Host smart-c2749e81-1e8b-4703-890a-1d6ddb200494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884044595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3884044595
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3981519388
Short name T928
Test name
Test status
Simulation time 239540717 ps
CPU time 5 seconds
Started Jan 21 10:25:23 PM PST 24
Finished Jan 21 10:25:32 PM PST 24
Peak memory 213860 kb
Host smart-85733677-19cd-409f-8c33-a2c27e656794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981519388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3981519388
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3169833829
Short name T377
Test name
Test status
Simulation time 363261973 ps
CPU time 39.59 seconds
Started Jan 21 10:25:18 PM PST 24
Finished Jan 21 10:26:01 PM PST 24
Peak memory 248924 kb
Host smart-76ac5804-e6a4-4963-ad84-063597a9e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169833829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3169833829
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2475888052
Short name T332
Test name
Test status
Simulation time 497488124 ps
CPU time 7.87 seconds
Started Jan 21 10:25:14 PM PST 24
Finished Jan 21 10:25:23 PM PST 24
Peak memory 250328 kb
Host smart-81c06ce1-01e9-4af2-bd12-f1332796bfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475888052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2475888052
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2755582752
Short name T663
Test name
Test status
Simulation time 21234527750 ps
CPU time 89.43 seconds
Started Jan 21 10:25:24 PM PST 24
Finished Jan 21 10:26:57 PM PST 24
Peak memory 269104 kb
Host smart-8c796dc5-bf9c-4bb9-9e08-83e8458c231a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755582752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2755582752
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.648166289
Short name T694
Test name
Test status
Simulation time 11589949 ps
CPU time 0.79 seconds
Started Jan 21 10:25:19 PM PST 24
Finished Jan 21 10:25:23 PM PST 24
Peak memory 207700 kb
Host smart-63721d2a-e2f3-48bb-a1b5-738f57386fe0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648166289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.648166289
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.86470205
Short name T76
Test name
Test status
Simulation time 20292255 ps
CPU time 1.22 seconds
Started Jan 21 10:21:40 PM PST 24
Finished Jan 21 10:21:48 PM PST 24
Peak memory 208988 kb
Host smart-c8388d96-da6e-414b-9f51-6fc56eaf58d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86470205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.86470205
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1792843797
Short name T808
Test name
Test status
Simulation time 14070395 ps
CPU time 0.99 seconds
Started Jan 21 10:21:28 PM PST 24
Finished Jan 21 10:21:38 PM PST 24
Peak memory 208900 kb
Host smart-2f12fe09-5e42-4a98-8130-908331e80424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792843797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1792843797
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.867194754
Short name T938
Test name
Test status
Simulation time 593917681 ps
CPU time 8.26 seconds
Started Jan 21 10:21:31 PM PST 24
Finished Jan 21 10:21:49 PM PST 24
Peak memory 208932 kb
Host smart-87444023-134e-4c63-8be9-0db1329f8cd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867194754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_acc
ess.867194754
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.4185104825
Short name T939
Test name
Test status
Simulation time 1872160788 ps
CPU time 55.13 seconds
Started Jan 21 10:21:37 PM PST 24
Finished Jan 21 10:22:41 PM PST 24
Peak memory 217304 kb
Host smart-9c2e08d4-1346-4cf8-898e-37736600d627
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185104825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.4185104825
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3399300560
Short name T605
Test name
Test status
Simulation time 3665925450 ps
CPU time 12.76 seconds
Started Jan 21 10:21:37 PM PST 24
Finished Jan 21 10:21:58 PM PST 24
Peak memory 217312 kb
Host smart-0a5eee98-81ab-40bc-adc7-2c4f4090934a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399300560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.3399300560
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2548790682
Short name T775
Test name
Test status
Simulation time 563698016 ps
CPU time 2.69 seconds
Started Jan 21 10:21:33 PM PST 24
Finished Jan 21 10:21:46 PM PST 24
Peak memory 217324 kb
Host smart-7bb76ee8-d39d-4d59-a59a-94e310c00aee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548790682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2548790682
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1487634122
Short name T713
Test name
Test status
Simulation time 1273500281 ps
CPU time 31.28 seconds
Started Jan 21 10:21:38 PM PST 24
Finished Jan 21 10:22:18 PM PST 24
Peak memory 212280 kb
Host smart-059f8153-29a9-4ab9-8d73-cb918da88adb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487634122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1487634122
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.333106286
Short name T846
Test name
Test status
Simulation time 937832576 ps
CPU time 4.76 seconds
Started Jan 21 10:21:28 PM PST 24
Finished Jan 21 10:21:42 PM PST 24
Peak memory 212292 kb
Host smart-f599f1ae-e524-4035-be5b-7a2dd2d63b14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333106286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.333106286
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2368181585
Short name T383
Test name
Test status
Simulation time 2687865912 ps
CPU time 48.44 seconds
Started Jan 21 10:21:36 PM PST 24
Finished Jan 21 10:22:34 PM PST 24
Peak memory 250380 kb
Host smart-d3ad2411-4c92-450e-93b1-6811f69029ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368181585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2368181585
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1707787225
Short name T697
Test name
Test status
Simulation time 524262793 ps
CPU time 10.31 seconds
Started Jan 21 10:21:29 PM PST 24
Finished Jan 21 10:21:48 PM PST 24
Peak memory 222828 kb
Host smart-1c6e0575-e8c1-416e-9e3e-ee5665b56829
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707787225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1707787225
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.891671679
Short name T900
Test name
Test status
Simulation time 111887426 ps
CPU time 1.93 seconds
Started Jan 21 10:21:34 PM PST 24
Finished Jan 21 10:21:46 PM PST 24
Peak memory 217332 kb
Host smart-da3368c0-a22d-4200-80f4-e71a31b423f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891671679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.891671679
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2714073562
Short name T794
Test name
Test status
Simulation time 313025309 ps
CPU time 18.22 seconds
Started Jan 21 10:21:33 PM PST 24
Finished Jan 21 10:22:01 PM PST 24
Peak memory 213432 kb
Host smart-dc0e8b67-f350-49dd-91bb-f0af76bfb226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714073562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2714073562
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2875960599
Short name T105
Test name
Test status
Simulation time 945657284 ps
CPU time 24.78 seconds
Started Jan 21 10:21:34 PM PST 24
Finished Jan 21 10:22:09 PM PST 24
Peak memory 280848 kb
Host smart-9689f77e-693f-405d-bae7-dc1eb80019ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875960599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2875960599
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.799312531
Short name T369
Test name
Test status
Simulation time 230548207 ps
CPU time 12.12 seconds
Started Jan 21 10:21:36 PM PST 24
Finished Jan 21 10:21:57 PM PST 24
Peak memory 217344 kb
Host smart-f9f42d57-3d7e-4eba-b00f-25edfe57d69d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799312531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.799312531
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.406485578
Short name T352
Test name
Test status
Simulation time 344692424 ps
CPU time 9.91 seconds
Started Jan 21 10:21:38 PM PST 24
Finished Jan 21 10:21:56 PM PST 24
Peak memory 217300 kb
Host smart-2c184fad-b9c4-46d6-893b-3cfbc088519a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406485578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.406485578
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.808859855
Short name T930
Test name
Test status
Simulation time 7220074439 ps
CPU time 10.12 seconds
Started Jan 21 10:21:33 PM PST 24
Finished Jan 21 10:21:53 PM PST 24
Peak memory 217560 kb
Host smart-3134b085-bf01-419d-9eb5-5d1694e5220b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808859855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.808859855
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.4209145645
Short name T489
Test name
Test status
Simulation time 436932310 ps
CPU time 7.67 seconds
Started Jan 21 11:05:56 PM PST 24
Finished Jan 21 11:06:05 PM PST 24
Peak memory 217436 kb
Host smart-c71c3d64-e267-449d-bc0d-a87f90f74dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209145645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.4209145645
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2996923790
Short name T326
Test name
Test status
Simulation time 141823779 ps
CPU time 2.39 seconds
Started Jan 21 10:21:30 PM PST 24
Finished Jan 21 10:21:41 PM PST 24
Peak memory 213076 kb
Host smart-6e31208b-7816-426c-86a7-0defc7cc3702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996923790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2996923790
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3542276164
Short name T829
Test name
Test status
Simulation time 511312948 ps
CPU time 34.06 seconds
Started Jan 21 10:21:27 PM PST 24
Finished Jan 21 10:22:10 PM PST 24
Peak memory 250336 kb
Host smart-f775a0c2-36e8-4955-90e2-b94f854d3c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542276164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3542276164
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1161273190
Short name T319
Test name
Test status
Simulation time 150614300 ps
CPU time 3.14 seconds
Started Jan 21 10:21:30 PM PST 24
Finished Jan 21 10:21:42 PM PST 24
Peak memory 221420 kb
Host smart-6a0b6cfe-9f88-421f-a3d1-13ec895833e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161273190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1161273190
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4212606303
Short name T47
Test name
Test status
Simulation time 40561222 ps
CPU time 0.75 seconds
Started Jan 21 10:21:27 PM PST 24
Finished Jan 21 10:21:35 PM PST 24
Peak memory 207204 kb
Host smart-30521ada-617e-485b-8b55-d5ff2c020e47
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212606303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4212606303
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1582573230
Short name T570
Test name
Test status
Simulation time 81124006 ps
CPU time 1.31 seconds
Started Jan 21 10:25:35 PM PST 24
Finished Jan 21 10:25:48 PM PST 24
Peak memory 207700 kb
Host smart-f39c6095-ef05-44ad-af4a-100ca5b934c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582573230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1582573230
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.227867031
Short name T903
Test name
Test status
Simulation time 467426776 ps
CPU time 18.66 seconds
Started Jan 21 10:25:35 PM PST 24
Finished Jan 21 10:26:06 PM PST 24
Peak memory 217336 kb
Host smart-21b35db0-cfd0-4683-8b89-02c626681d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227867031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.227867031
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4266150320
Short name T968
Test name
Test status
Simulation time 257936252 ps
CPU time 2.33 seconds
Started Jan 21 10:25:38 PM PST 24
Finished Jan 21 10:25:56 PM PST 24
Peak memory 208948 kb
Host smart-c2107983-d62a-4747-87a2-c0ca24b6de39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266150320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.4266150320
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3716741630
Short name T455
Test name
Test status
Simulation time 99054844 ps
CPU time 3.54 seconds
Started Jan 21 10:25:31 PM PST 24
Finished Jan 21 10:25:37 PM PST 24
Peak memory 217344 kb
Host smart-79eb801c-4995-485b-b9f2-abdef87a0af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716741630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3716741630
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.140486130
Short name T885
Test name
Test status
Simulation time 176830621 ps
CPU time 9.42 seconds
Started Jan 21 10:25:40 PM PST 24
Finished Jan 21 10:26:07 PM PST 24
Peak memory 217368 kb
Host smart-0767783d-e262-4733-988b-ec12286e7769
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140486130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.140486130
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1937423843
Short name T904
Test name
Test status
Simulation time 288240044 ps
CPU time 11.71 seconds
Started Jan 21 10:25:35 PM PST 24
Finished Jan 21 10:25:58 PM PST 24
Peak memory 217376 kb
Host smart-85e04156-e5fe-4ecb-a574-78761b929cd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937423843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1937423843
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1412454520
Short name T750
Test name
Test status
Simulation time 789582984 ps
CPU time 13.87 seconds
Started Jan 21 10:25:41 PM PST 24
Finished Jan 21 10:26:11 PM PST 24
Peak memory 217292 kb
Host smart-d936b26b-aa25-4ba6-8c9f-6939668cfc7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412454520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1412454520
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3141901444
Short name T29
Test name
Test status
Simulation time 216617293 ps
CPU time 7.37 seconds
Started Jan 21 10:25:40 PM PST 24
Finished Jan 21 10:26:05 PM PST 24
Peak memory 217280 kb
Host smart-92e67378-95a3-4bf5-845e-f81d7c1ff1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141901444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3141901444
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3157238014
Short name T778
Test name
Test status
Simulation time 36536713 ps
CPU time 1.8 seconds
Started Jan 21 10:25:24 PM PST 24
Finished Jan 21 10:25:30 PM PST 24
Peak memory 212612 kb
Host smart-4024267b-57d1-4250-ac6c-dc737783fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157238014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3157238014
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2589093567
Short name T881
Test name
Test status
Simulation time 1094030553 ps
CPU time 30.8 seconds
Started Jan 21 10:25:35 PM PST 24
Finished Jan 21 10:26:17 PM PST 24
Peak memory 250316 kb
Host smart-3becaa4e-7a69-435b-be87-a18a8c94af56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589093567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2589093567
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.37232587
Short name T454
Test name
Test status
Simulation time 77538075 ps
CPU time 9.03 seconds
Started Jan 21 10:25:32 PM PST 24
Finished Jan 21 10:25:46 PM PST 24
Peak memory 250400 kb
Host smart-aa19bcb6-d94b-445a-8e0b-acdaad110f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37232587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.37232587
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1350816553
Short name T541
Test name
Test status
Simulation time 1287278753 ps
CPU time 44.03 seconds
Started Jan 21 10:25:38 PM PST 24
Finished Jan 21 10:26:39 PM PST 24
Peak memory 250216 kb
Host smart-7e6b80e9-e251-4160-9a66-2f5e8ab24465
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350816553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1350816553
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3778640311
Short name T960
Test name
Test status
Simulation time 13923128229 ps
CPU time 301.92 seconds
Started Jan 21 10:25:32 PM PST 24
Finished Jan 21 10:30:39 PM PST 24
Peak memory 283424 kb
Host smart-2d047634-abfa-495b-b44c-7cb7ab36c823
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3778640311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.3778640311
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4199819980
Short name T492
Test name
Test status
Simulation time 18389868 ps
CPU time 0.75 seconds
Started Jan 21 10:25:31 PM PST 24
Finished Jan 21 10:25:33 PM PST 24
Peak memory 207372 kb
Host smart-4b427e7e-edd9-4b1d-92d7-cecc6b10ba12
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199819980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.4199819980
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1723314928
Short name T914
Test name
Test status
Simulation time 30708536 ps
CPU time 1.05 seconds
Started Jan 21 10:25:44 PM PST 24
Finished Jan 21 10:25:59 PM PST 24
Peak memory 207280 kb
Host smart-78f67c16-bbdc-499d-b1dd-23948dfe3929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723314928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1723314928
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1431169770
Short name T632
Test name
Test status
Simulation time 1054542953 ps
CPU time 13.51 seconds
Started Jan 21 10:25:37 PM PST 24
Finished Jan 21 10:26:06 PM PST 24
Peak memory 217344 kb
Host smart-9c882c9c-5838-4367-9122-c9815b7f35ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431169770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1431169770
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3613056783
Short name T124
Test name
Test status
Simulation time 1225576252 ps
CPU time 3.46 seconds
Started Jan 21 10:25:43 PM PST 24
Finished Jan 21 10:26:03 PM PST 24
Peak memory 208872 kb
Host smart-06888927-ff38-4153-8625-44962d2d9d05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613056783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.3613056783
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3050554493
Short name T957
Test name
Test status
Simulation time 372561388 ps
CPU time 4.1 seconds
Started Jan 21 10:25:37 PM PST 24
Finished Jan 21 10:25:56 PM PST 24
Peak memory 217368 kb
Host smart-8140074a-a9ca-4ea4-9c8a-e822fe138e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050554493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3050554493
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1953504716
Short name T523
Test name
Test status
Simulation time 440100808 ps
CPU time 8.24 seconds
Started Jan 21 10:25:44 PM PST 24
Finished Jan 21 10:26:06 PM PST 24
Peak memory 217340 kb
Host smart-2712808c-b5eb-4372-bbce-2ec8993a4177
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953504716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1953504716
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3186515757
Short name T587
Test name
Test status
Simulation time 650893218 ps
CPU time 11.06 seconds
Started Jan 21 10:25:44 PM PST 24
Finished Jan 21 10:26:09 PM PST 24
Peak memory 217332 kb
Host smart-3819279e-1558-4192-9877-0891838e9be6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186515757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3186515757
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2094469473
Short name T548
Test name
Test status
Simulation time 1821880759 ps
CPU time 19.65 seconds
Started Jan 21 10:25:39 PM PST 24
Finished Jan 21 10:26:16 PM PST 24
Peak memory 217380 kb
Host smart-95e08233-ef1f-4b4f-90c4-2f4ea27a7d3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094469473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2094469473
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2819793019
Short name T39
Test name
Test status
Simulation time 1048329369 ps
CPU time 7.51 seconds
Started Jan 21 10:25:41 PM PST 24
Finished Jan 21 10:26:05 PM PST 24
Peak memory 217360 kb
Host smart-8a9a4710-3ec0-4a28-8841-f99a77848ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819793019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2819793019
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1272089861
Short name T963
Test name
Test status
Simulation time 92011024 ps
CPU time 3.21 seconds
Started Jan 21 10:25:38 PM PST 24
Finished Jan 21 10:25:58 PM PST 24
Peak memory 213600 kb
Host smart-6125e00b-6ff9-47e3-8689-ac076e160195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272089861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1272089861
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1946985769
Short name T465
Test name
Test status
Simulation time 230877244 ps
CPU time 24.57 seconds
Started Jan 21 10:25:34 PM PST 24
Finished Jan 21 10:26:07 PM PST 24
Peak memory 250204 kb
Host smart-427977e9-1487-404f-a627-9e4c0e66163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946985769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1946985769
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2513010846
Short name T426
Test name
Test status
Simulation time 354259368 ps
CPU time 9.24 seconds
Started Jan 21 10:25:33 PM PST 24
Finished Jan 21 10:25:48 PM PST 24
Peak memory 249960 kb
Host smart-80e22b87-ff74-47ee-9724-e6d119e3e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513010846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2513010846
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1524862484
Short name T564
Test name
Test status
Simulation time 28246364706 ps
CPU time 230.27 seconds
Started Jan 21 10:25:41 PM PST 24
Finished Jan 21 10:29:48 PM PST 24
Peak memory 283352 kb
Host smart-996d6d56-fe9e-4aec-8b49-69946ded029e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524862484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1524862484
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.877757706
Short name T662
Test name
Test status
Simulation time 14655668 ps
CPU time 0.8 seconds
Started Jan 21 10:25:39 PM PST 24
Finished Jan 21 10:25:58 PM PST 24
Peak memory 207504 kb
Host smart-d57a57a1-9e10-4115-bfb9-80fb4bb4145c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877757706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.877757706
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2964396732
Short name T436
Test name
Test status
Simulation time 12604659 ps
CPU time 0.98 seconds
Started Jan 21 10:25:58 PM PST 24
Finished Jan 21 10:26:14 PM PST 24
Peak memory 208984 kb
Host smart-fc3fb766-0f55-4b5a-951d-08911ecdefd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964396732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2964396732
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.593297217
Short name T443
Test name
Test status
Simulation time 482006644 ps
CPU time 10.75 seconds
Started Jan 21 10:25:49 PM PST 24
Finished Jan 21 10:26:15 PM PST 24
Peak memory 217380 kb
Host smart-f598403d-1d24-44f6-8965-2d037b0dd792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593297217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.593297217
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3609103362
Short name T746
Test name
Test status
Simulation time 244322489 ps
CPU time 3.94 seconds
Started Jan 21 10:25:51 PM PST 24
Finished Jan 21 10:26:10 PM PST 24
Peak memory 208920 kb
Host smart-4e0b8c39-2626-4958-8903-1d800a906059
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609103362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.3609103362
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3817899759
Short name T405
Test name
Test status
Simulation time 634703175 ps
CPU time 3.6 seconds
Started Jan 21 10:25:50 PM PST 24
Finished Jan 21 10:26:09 PM PST 24
Peak memory 217324 kb
Host smart-a5593c56-a2a8-4beb-9cca-17b4cff2c573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817899759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3817899759
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3106994736
Short name T616
Test name
Test status
Simulation time 608683083 ps
CPU time 13.12 seconds
Started Jan 21 10:25:46 PM PST 24
Finished Jan 21 10:26:13 PM PST 24
Peak memory 218392 kb
Host smart-e4d17289-aa89-48e8-aab0-657a931de4d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106994736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3106994736
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4080015935
Short name T921
Test name
Test status
Simulation time 311365584 ps
CPU time 9.66 seconds
Started Jan 21 10:25:56 PM PST 24
Finished Jan 21 10:26:21 PM PST 24
Peak memory 217308 kb
Host smart-7159a9e0-1067-48ba-82b0-47b31e1850b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080015935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4080015935
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4210736857
Short name T786
Test name
Test status
Simulation time 1924243416 ps
CPU time 16.67 seconds
Started Jan 21 10:25:52 PM PST 24
Finished Jan 21 10:26:24 PM PST 24
Peak memory 217320 kb
Host smart-5eb85b2c-c8dc-4cc0-9e90-eacc3575e990
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210736857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4210736857
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3366232731
Short name T836
Test name
Test status
Simulation time 1257647592 ps
CPU time 10.01 seconds
Started Jan 21 10:25:51 PM PST 24
Finished Jan 21 10:26:16 PM PST 24
Peak memory 217420 kb
Host smart-7873606e-4af9-46f0-85bc-673821675601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366232731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3366232731
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2125155798
Short name T942
Test name
Test status
Simulation time 235504986 ps
CPU time 2.55 seconds
Started Jan 21 10:25:39 PM PST 24
Finished Jan 21 10:26:00 PM PST 24
Peak memory 213276 kb
Host smart-31f33e8f-fc1b-4fff-83a1-eb1b199423ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125155798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2125155798
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2933094682
Short name T365
Test name
Test status
Simulation time 624926198 ps
CPU time 23.96 seconds
Started Jan 21 10:25:44 PM PST 24
Finished Jan 21 10:26:22 PM PST 24
Peak memory 250016 kb
Host smart-67b20af9-56b9-4401-a959-ee8f8a431ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933094682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2933094682
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3761184466
Short name T410
Test name
Test status
Simulation time 73912035 ps
CPU time 8.13 seconds
Started Jan 21 10:25:46 PM PST 24
Finished Jan 21 10:26:06 PM PST 24
Peak memory 250404 kb
Host smart-e2e3c254-f2fb-4fc2-b8fe-6ac6e171d8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761184466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3761184466
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1434482471
Short name T780
Test name
Test status
Simulation time 1676115420 ps
CPU time 66.85 seconds
Started Jan 21 10:25:56 PM PST 24
Finished Jan 21 10:27:18 PM PST 24
Peak memory 266944 kb
Host smart-276c07b6-8ad3-458d-96af-76288c7e1470
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434482471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1434482471
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1381557600
Short name T651
Test name
Test status
Simulation time 15657453 ps
CPU time 1.05 seconds
Started Jan 21 10:25:46 PM PST 24
Finished Jan 21 10:25:59 PM PST 24
Peak memory 207584 kb
Host smart-68cfc324-f2e6-48d3-a6f7-f19fe0efd0c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381557600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1381557600
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3534967296
Short name T664
Test name
Test status
Simulation time 21500688 ps
CPU time 0.91 seconds
Started Jan 21 10:26:05 PM PST 24
Finished Jan 21 10:26:18 PM PST 24
Peak memory 208996 kb
Host smart-1b29c2e4-61c2-4336-aa96-abb66699d3db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534967296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3534967296
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2456382613
Short name T675
Test name
Test status
Simulation time 1362109163 ps
CPU time 14.63 seconds
Started Jan 21 10:25:56 PM PST 24
Finished Jan 21 10:26:26 PM PST 24
Peak memory 217308 kb
Host smart-99d02f84-b9b4-406f-ba6e-f287966e8ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456382613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2456382613
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3462274599
Short name T649
Test name
Test status
Simulation time 612210800 ps
CPU time 4.89 seconds
Started Jan 21 10:26:00 PM PST 24
Finished Jan 21 10:26:19 PM PST 24
Peak memory 209036 kb
Host smart-a1a1ebc6-c3d3-4562-868f-2b2234b4e470
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462274599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.3462274599
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2009627399
Short name T601
Test name
Test status
Simulation time 150424798 ps
CPU time 3.93 seconds
Started Jan 21 10:26:01 PM PST 24
Finished Jan 21 10:26:18 PM PST 24
Peak memory 217356 kb
Host smart-524f8331-93e7-4f34-bfde-effb78b0183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009627399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2009627399
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2159123243
Short name T866
Test name
Test status
Simulation time 10760133239 ps
CPU time 15.28 seconds
Started Jan 21 10:26:01 PM PST 24
Finished Jan 21 10:26:30 PM PST 24
Peak memory 218500 kb
Host smart-6f439fe1-ab9b-49c1-9659-01e039ddeb72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159123243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2159123243
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2036242284
Short name T340
Test name
Test status
Simulation time 1023383192 ps
CPU time 11.48 seconds
Started Jan 21 10:26:07 PM PST 24
Finished Jan 21 10:26:33 PM PST 24
Peak memory 217308 kb
Host smart-ee1514db-d2dc-409b-945a-4a6be9743a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036242284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2036242284
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2045873176
Short name T613
Test name
Test status
Simulation time 258035990 ps
CPU time 7.86 seconds
Started Jan 21 10:26:00 PM PST 24
Finished Jan 21 10:26:22 PM PST 24
Peak memory 217344 kb
Host smart-32272202-cb5f-45b4-8cd0-6e4f14d06f26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045873176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2045873176
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.900928756
Short name T642
Test name
Test status
Simulation time 241660714 ps
CPU time 7.58 seconds
Started Jan 21 10:26:01 PM PST 24
Finished Jan 21 10:26:22 PM PST 24
Peak memory 217280 kb
Host smart-15312a12-bb06-4e57-b648-8226a2547e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900928756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.900928756
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3201608758
Short name T85
Test name
Test status
Simulation time 59291300 ps
CPU time 1.31 seconds
Started Jan 21 10:25:58 PM PST 24
Finished Jan 21 10:26:14 PM PST 24
Peak memory 212464 kb
Host smart-3796a541-af31-4bc3-9afa-5c4058f5b9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201608758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3201608758
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3112818430
Short name T956
Test name
Test status
Simulation time 677399696 ps
CPU time 12.48 seconds
Started Jan 21 10:26:04 PM PST 24
Finished Jan 21 10:26:29 PM PST 24
Peak memory 249496 kb
Host smart-176f399a-d9d4-4916-92c7-a478be89664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112818430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3112818430
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3837430213
Short name T804
Test name
Test status
Simulation time 949352722 ps
CPU time 7.89 seconds
Started Jan 21 10:25:58 PM PST 24
Finished Jan 21 10:26:21 PM PST 24
Peak memory 249644 kb
Host smart-08668c96-4941-4a5d-9657-8554b6d437a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837430213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3837430213
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3963326398
Short name T544
Test name
Test status
Simulation time 38576622805 ps
CPU time 160.25 seconds
Started Jan 21 10:26:07 PM PST 24
Finished Jan 21 10:29:02 PM PST 24
Peak memory 291500 kb
Host smart-d0f44ff1-8697-4466-bff5-b433f8175a6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963326398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3963326398
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.4198375315
Short name T477
Test name
Test status
Simulation time 15310177 ps
CPU time 0.86 seconds
Started Jan 21 10:25:59 PM PST 24
Finished Jan 21 10:26:14 PM PST 24
Peak memory 207312 kb
Host smart-26785c61-82a0-4ab8-b7bf-6adcf349cade
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198375315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.4198375315
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4223065571
Short name T17
Test name
Test status
Simulation time 59883207 ps
CPU time 1.09 seconds
Started Jan 21 10:26:14 PM PST 24
Finished Jan 21 10:26:31 PM PST 24
Peak memory 208852 kb
Host smart-804acac8-906c-4fbd-a90d-082feca7e8a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223065571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4223065571
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2693666163
Short name T946
Test name
Test status
Simulation time 1261296509 ps
CPU time 20.58 seconds
Started Jan 21 10:26:09 PM PST 24
Finished Jan 21 10:26:46 PM PST 24
Peak memory 217296 kb
Host smart-69a4bad1-8060-4069-97be-1a844c27ee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693666163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2693666163
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3131859283
Short name T431
Test name
Test status
Simulation time 1377010974 ps
CPU time 16.66 seconds
Started Jan 21 10:26:04 PM PST 24
Finished Jan 21 10:26:33 PM PST 24
Peak memory 208980 kb
Host smart-628ffd32-f833-475c-aeb6-272429eb14d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131859283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_a
ccess.3131859283
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.438915225
Short name T557
Test name
Test status
Simulation time 84750981 ps
CPU time 4 seconds
Started Jan 21 10:26:08 PM PST 24
Finished Jan 21 10:26:28 PM PST 24
Peak memory 217324 kb
Host smart-a8767c1f-041b-4755-a8a5-e21c4d0019e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438915225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.438915225
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1982583654
Short name T923
Test name
Test status
Simulation time 599476872 ps
CPU time 10.12 seconds
Started Jan 21 10:26:02 PM PST 24
Finished Jan 21 10:26:25 PM PST 24
Peak memory 217364 kb
Host smart-b4315b39-efd4-4536-98c8-a10d3fbeff47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982583654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1982583654
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2574235435
Short name T871
Test name
Test status
Simulation time 3771726174 ps
CPU time 12.1 seconds
Started Jan 21 10:26:14 PM PST 24
Finished Jan 21 10:26:41 PM PST 24
Peak memory 217456 kb
Host smart-74a09eb0-e393-4b59-929f-7c67d9bea214
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574235435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2574235435
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3362947091
Short name T355
Test name
Test status
Simulation time 270395599 ps
CPU time 10.66 seconds
Started Jan 21 10:26:08 PM PST 24
Finished Jan 21 10:26:33 PM PST 24
Peak memory 217324 kb
Host smart-bf707cd4-188f-4827-af7a-6971f876de19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362947091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3362947091
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2687719597
Short name T491
Test name
Test status
Simulation time 497207809 ps
CPU time 9.89 seconds
Started Jan 21 10:26:03 PM PST 24
Finished Jan 21 10:26:26 PM PST 24
Peak memory 217332 kb
Host smart-503ec6f6-f84e-4d92-933b-7240aacdc8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687719597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2687719597
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3628857070
Short name T64
Test name
Test status
Simulation time 293536590 ps
CPU time 5.38 seconds
Started Jan 21 10:26:09 PM PST 24
Finished Jan 21 10:26:30 PM PST 24
Peak memory 213436 kb
Host smart-ad2d9e70-bd0b-43c9-aeca-29c65ca62ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628857070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3628857070
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4159919828
Short name T888
Test name
Test status
Simulation time 1270173631 ps
CPU time 16.5 seconds
Started Jan 21 10:26:04 PM PST 24
Finished Jan 21 10:26:33 PM PST 24
Peak memory 249612 kb
Host smart-d268ef7a-6808-47fa-a98b-aa86c49bba70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159919828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4159919828
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2821679079
Short name T531
Test name
Test status
Simulation time 455385446 ps
CPU time 7.55 seconds
Started Jan 21 10:26:05 PM PST 24
Finished Jan 21 10:26:24 PM PST 24
Peak memory 250316 kb
Host smart-64e1f14d-c65f-4828-8976-686a8e334ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821679079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2821679079
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1961856054
Short name T538
Test name
Test status
Simulation time 5570252793 ps
CPU time 81.87 seconds
Started Jan 21 10:26:12 PM PST 24
Finished Jan 21 10:27:49 PM PST 24
Peak memory 269664 kb
Host smart-1c1f3a62-6a45-4290-bc6f-57ae883f712a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961856054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1961856054
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.113167802
Short name T563
Test name
Test status
Simulation time 30577610 ps
CPU time 0.96 seconds
Started Jan 21 10:26:04 PM PST 24
Finished Jan 21 10:26:17 PM PST 24
Peak memory 210644 kb
Host smart-18b6ee21-e135-4052-841c-b1b25b68f132
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113167802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.113167802
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1726555546
Short name T330
Test name
Test status
Simulation time 36776196 ps
CPU time 0.87 seconds
Started Jan 21 10:26:19 PM PST 24
Finished Jan 21 10:26:37 PM PST 24
Peak memory 208900 kb
Host smart-57175233-3242-4d42-9500-a296025b9f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726555546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1726555546
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2661664881
Short name T825
Test name
Test status
Simulation time 296352393 ps
CPU time 9.68 seconds
Started Jan 21 10:26:17 PM PST 24
Finished Jan 21 10:26:44 PM PST 24
Peak memory 217212 kb
Host smart-b1a1bb0e-35f9-4a3e-bced-a6a6b462a3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661664881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2661664881
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1044985321
Short name T122
Test name
Test status
Simulation time 498085697 ps
CPU time 2.28 seconds
Started Jan 21 10:26:18 PM PST 24
Finished Jan 21 10:26:37 PM PST 24
Peak memory 208932 kb
Host smart-a3da1e25-d302-4f3a-bcdf-9ed128f87168
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044985321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_a
ccess.1044985321
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2394960204
Short name T434
Test name
Test status
Simulation time 40841074 ps
CPU time 2.5 seconds
Started Jan 21 10:26:15 PM PST 24
Finished Jan 21 10:26:33 PM PST 24
Peak memory 217364 kb
Host smart-a6626a81-2b56-4d74-8d0d-c6fd8e66bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394960204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2394960204
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.766536643
Short name T498
Test name
Test status
Simulation time 466690096 ps
CPU time 13.3 seconds
Started Jan 21 10:26:15 PM PST 24
Finished Jan 21 10:26:45 PM PST 24
Peak memory 217300 kb
Host smart-9f2e77f0-35f3-4eaf-bacc-2cf5cddb9c6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766536643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.766536643
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.442715536
Short name T618
Test name
Test status
Simulation time 957994095 ps
CPU time 16.42 seconds
Started Jan 21 10:26:12 PM PST 24
Finished Jan 21 10:26:44 PM PST 24
Peak memory 217344 kb
Host smart-4acf5db7-78e1-4a83-8493-b8aaff7668eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442715536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.442715536
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3846762023
Short name T830
Test name
Test status
Simulation time 786156299 ps
CPU time 10.06 seconds
Started Jan 21 10:26:14 PM PST 24
Finished Jan 21 10:26:41 PM PST 24
Peak memory 217316 kb
Host smart-fd384b6b-9c2e-4aca-bd7c-58aeadf21fd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846762023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3846762023
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3210323129
Short name T69
Test name
Test status
Simulation time 30123209 ps
CPU time 1.54 seconds
Started Jan 21 10:26:15 PM PST 24
Finished Jan 21 10:26:32 PM PST 24
Peak memory 212536 kb
Host smart-92497cc9-6f50-4392-a18f-90292df31a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210323129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3210323129
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1279809254
Short name T834
Test name
Test status
Simulation time 350455251 ps
CPU time 23.86 seconds
Started Jan 21 10:26:13 PM PST 24
Finished Jan 21 10:26:52 PM PST 24
Peak memory 250328 kb
Host smart-4f76b449-5508-4853-ae52-ba4f31038cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279809254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1279809254
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3987371389
Short name T3
Test name
Test status
Simulation time 387391968 ps
CPU time 3.39 seconds
Started Jan 21 10:26:14 PM PST 24
Finished Jan 21 10:26:34 PM PST 24
Peak memory 221436 kb
Host smart-4428c9e2-3784-4cf4-8ded-bee5569395e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987371389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3987371389
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.661961475
Short name T476
Test name
Test status
Simulation time 620090823 ps
CPU time 34.44 seconds
Started Jan 21 10:26:14 PM PST 24
Finished Jan 21 10:27:05 PM PST 24
Peak memory 250220 kb
Host smart-b61149cf-837e-42e3-b89e-4477b8b55273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661961475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.661961475
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1334995039
Short name T482
Test name
Test status
Simulation time 31441929 ps
CPU time 0.86 seconds
Started Jan 21 10:26:15 PM PST 24
Finished Jan 21 10:26:33 PM PST 24
Peak memory 207480 kb
Host smart-c38e2264-40e7-42c5-a0fa-231cf9bf7952
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334995039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1334995039
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.4235503749
Short name T935
Test name
Test status
Simulation time 61158921 ps
CPU time 0.95 seconds
Started Jan 21 10:26:35 PM PST 24
Finished Jan 21 10:26:54 PM PST 24
Peak memory 207600 kb
Host smart-6d1b1e63-8af9-4cc2-88b1-c0cf928bc4b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235503749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.4235503749
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4294370583
Short name T624
Test name
Test status
Simulation time 431849509 ps
CPU time 16.94 seconds
Started Jan 21 10:26:18 PM PST 24
Finished Jan 21 10:26:52 PM PST 24
Peak memory 217532 kb
Host smart-71dd2d21-aa14-45c8-9ad9-3d59fbcdd007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294370583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4294370583
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.4004535011
Short name T865
Test name
Test status
Simulation time 404398384 ps
CPU time 2.96 seconds
Started Jan 21 11:10:14 PM PST 24
Finished Jan 21 11:10:19 PM PST 24
Peak memory 208964 kb
Host smart-2026f722-4f97-4015-9305-1a3cb27ae879
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004535011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.4004535011
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.334454733
Short name T622
Test name
Test status
Simulation time 25403231 ps
CPU time 1.72 seconds
Started Jan 21 10:26:22 PM PST 24
Finished Jan 21 10:26:42 PM PST 24
Peak memory 217356 kb
Host smart-49b057da-71a6-405f-abd4-791d4577930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334454733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.334454733
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3140913574
Short name T565
Test name
Test status
Simulation time 1687024377 ps
CPU time 14.87 seconds
Started Jan 21 10:26:28 PM PST 24
Finished Jan 21 10:27:03 PM PST 24
Peak memory 218384 kb
Host smart-82c9d826-cb35-401d-8ddf-3426804dc764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140913574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3140913574
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2407149304
Short name T934
Test name
Test status
Simulation time 727668603 ps
CPU time 6.94 seconds
Started Jan 21 10:53:31 PM PST 24
Finished Jan 21 10:53:39 PM PST 24
Peak memory 217336 kb
Host smart-5316e8f7-44bd-40c1-a15f-a509cfb89e1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407149304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2407149304
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1917254574
Short name T764
Test name
Test status
Simulation time 724902403 ps
CPU time 11.87 seconds
Started Jan 21 10:26:26 PM PST 24
Finished Jan 21 10:26:59 PM PST 24
Peak memory 217364 kb
Host smart-8b3604f2-bc67-46e9-9dcc-5da87bdc3d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917254574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1917254574
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1948082233
Short name T388
Test name
Test status
Simulation time 424702556 ps
CPU time 15.66 seconds
Started Jan 21 10:26:19 PM PST 24
Finished Jan 21 10:26:52 PM PST 24
Peak memory 217364 kb
Host smart-8705a333-dc00-4205-8f52-f7b9136e0612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948082233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1948082233
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1727276291
Short name T757
Test name
Test status
Simulation time 56376848 ps
CPU time 1.21 seconds
Started Jan 21 10:26:19 PM PST 24
Finished Jan 21 10:26:37 PM PST 24
Peak memory 212456 kb
Host smart-e42c1930-ff3f-4bdc-8c62-400e23eb8b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727276291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1727276291
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.365983873
Short name T637
Test name
Test status
Simulation time 1536795747 ps
CPU time 30.83 seconds
Started Jan 21 10:26:22 PM PST 24
Finished Jan 21 10:27:11 PM PST 24
Peak memory 250256 kb
Host smart-632ebd43-52a1-4ada-9188-819fdbcfe5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365983873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.365983873
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2727448313
Short name T582
Test name
Test status
Simulation time 91469937 ps
CPU time 7.02 seconds
Started Jan 21 10:26:18 PM PST 24
Finished Jan 21 10:26:42 PM PST 24
Peak memory 249580 kb
Host smart-e82b9088-6191-4884-8405-3803f8e5f777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727448313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2727448313
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.538234275
Short name T941
Test name
Test status
Simulation time 4225239697 ps
CPU time 36.17 seconds
Started Jan 21 10:26:28 PM PST 24
Finished Jan 21 10:27:24 PM PST 24
Peak memory 225584 kb
Host smart-41786527-4473-4542-8d03-ab0331c2118e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538234275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.538234275
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1961077226
Short name T72
Test name
Test status
Simulation time 13819285 ps
CPU time 1.01 seconds
Started Jan 21 10:26:17 PM PST 24
Finished Jan 21 10:26:35 PM PST 24
Peak memory 210576 kb
Host smart-9e0ea83d-34bd-4301-bc73-d935f0471693
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961077226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1961077226
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3202035123
Short name T614
Test name
Test status
Simulation time 65638979 ps
CPU time 1.1 seconds
Started Jan 21 10:26:51 PM PST 24
Finished Jan 21 10:27:09 PM PST 24
Peak memory 208964 kb
Host smart-ee475463-7cc5-4cc3-8581-2b555305bd20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202035123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3202035123
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2398690287
Short name T497
Test name
Test status
Simulation time 928508048 ps
CPU time 15.83 seconds
Started Jan 21 10:26:39 PM PST 24
Finished Jan 21 10:27:12 PM PST 24
Peak memory 217292 kb
Host smart-5c259d1d-2f6e-44ef-972c-ab026b24c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398690287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2398690287
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2496316453
Short name T771
Test name
Test status
Simulation time 774459656 ps
CPU time 10.52 seconds
Started Jan 21 10:26:39 PM PST 24
Finished Jan 21 10:27:07 PM PST 24
Peak memory 208944 kb
Host smart-7f5e3f7c-7737-4cd7-ba7c-789247ca8c4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496316453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.2496316453
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3806509084
Short name T363
Test name
Test status
Simulation time 138220759 ps
CPU time 2.14 seconds
Started Jan 21 10:26:34 PM PST 24
Finished Jan 21 10:26:55 PM PST 24
Peak memory 217540 kb
Host smart-31a4180d-316c-44b1-b55c-02d285e72740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806509084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3806509084
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3564498474
Short name T317
Test name
Test status
Simulation time 420101193 ps
CPU time 16.48 seconds
Started Jan 21 10:26:40 PM PST 24
Finished Jan 21 10:27:13 PM PST 24
Peak memory 218396 kb
Host smart-185c1412-5b58-4fad-a363-dd82d98c8a83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564498474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3564498474
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.197819853
Short name T842
Test name
Test status
Simulation time 941739612 ps
CPU time 10.47 seconds
Started Jan 21 10:26:41 PM PST 24
Finished Jan 21 10:27:09 PM PST 24
Peak memory 217364 kb
Host smart-67788581-802b-4f0e-bd93-9011cf7f947b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197819853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.197819853
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2760753347
Short name T367
Test name
Test status
Simulation time 250019666 ps
CPU time 10.03 seconds
Started Jan 21 11:14:21 PM PST 24
Finished Jan 21 11:14:33 PM PST 24
Peak memory 217388 kb
Host smart-2797dd89-8d4a-4e21-9a54-5c867c50bc3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760753347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2760753347
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4121057177
Short name T427
Test name
Test status
Simulation time 427553890 ps
CPU time 16.1 seconds
Started Jan 21 10:57:30 PM PST 24
Finished Jan 21 10:57:50 PM PST 24
Peak memory 217352 kb
Host smart-919431d4-ed14-41bd-a00e-8e52f4ec31dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121057177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4121057177
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2387669911
Short name T983
Test name
Test status
Simulation time 429047121 ps
CPU time 6.94 seconds
Started Jan 21 10:26:31 PM PST 24
Finished Jan 21 10:26:58 PM PST 24
Peak memory 213428 kb
Host smart-a41378c1-7fc0-4590-82dc-f73a2062337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387669911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2387669911
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1566819148
Short name T873
Test name
Test status
Simulation time 170857950 ps
CPU time 19.98 seconds
Started Jan 21 10:26:33 PM PST 24
Finished Jan 21 10:27:12 PM PST 24
Peak memory 250252 kb
Host smart-c91be52f-2f3c-4f96-9656-9ba2f2e170ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566819148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1566819148
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2641126391
Short name T877
Test name
Test status
Simulation time 93153756 ps
CPU time 7.54 seconds
Started Jan 21 10:26:33 PM PST 24
Finished Jan 21 10:27:00 PM PST 24
Peak memory 245644 kb
Host smart-08cf2bc5-4874-4d43-883c-4b9fe2ef2409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641126391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2641126391
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1969121495
Short name T592
Test name
Test status
Simulation time 18994001256 ps
CPU time 97.63 seconds
Started Jan 21 10:26:51 PM PST 24
Finished Jan 21 10:28:45 PM PST 24
Peak memory 267568 kb
Host smart-38e5041d-f37b-4e83-b066-fc6673ad0b33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969121495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1969121495
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2276215740
Short name T868
Test name
Test status
Simulation time 40836558 ps
CPU time 0.85 seconds
Started Jan 21 10:26:36 PM PST 24
Finished Jan 21 10:26:55 PM PST 24
Peak memory 207756 kb
Host smart-0960eb3f-a134-47f8-8482-ff761f492ed0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276215740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2276215740
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2449759005
Short name T769
Test name
Test status
Simulation time 61252957 ps
CPU time 0.94 seconds
Started Jan 21 10:26:57 PM PST 24
Finished Jan 21 10:27:15 PM PST 24
Peak memory 207564 kb
Host smart-46853a61-77c3-485b-a575-942449e60944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449759005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2449759005
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4205758482
Short name T299
Test name
Test status
Simulation time 1696562820 ps
CPU time 14.74 seconds
Started Jan 21 10:26:51 PM PST 24
Finished Jan 21 10:27:22 PM PST 24
Peak memory 217368 kb
Host smart-d6e7cc6a-511c-4c53-8da0-f1e4212fa085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205758482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4205758482
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2810489061
Short name T9
Test name
Test status
Simulation time 191217229 ps
CPU time 1.9 seconds
Started Jan 21 10:26:55 PM PST 24
Finished Jan 21 10:27:14 PM PST 24
Peak memory 208900 kb
Host smart-9113ab14-36e5-4e60-bd8b-5e8f7974c08f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810489061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.2810489061
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.136005424
Short name T411
Test name
Test status
Simulation time 39055642 ps
CPU time 2.43 seconds
Started Jan 21 10:26:50 PM PST 24
Finished Jan 21 10:27:10 PM PST 24
Peak memory 217332 kb
Host smart-a218398f-b906-49c3-b504-f3836d9bcbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136005424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.136005424
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3160969675
Short name T556
Test name
Test status
Simulation time 1094395018 ps
CPU time 12.44 seconds
Started Jan 21 10:26:59 PM PST 24
Finished Jan 21 10:27:29 PM PST 24
Peak memory 217500 kb
Host smart-b8e7ae02-73f4-46ef-807a-5965fd347c1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160969675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3160969675
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4175614882
Short name T304
Test name
Test status
Simulation time 346756523 ps
CPU time 9.99 seconds
Started Jan 21 10:26:54 PM PST 24
Finished Jan 21 10:27:20 PM PST 24
Peak memory 217328 kb
Host smart-262bc908-231c-4aee-b77d-d8c776f19748
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175614882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4175614882
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2558249408
Short name T959
Test name
Test status
Simulation time 713665026 ps
CPU time 7.09 seconds
Started Jan 21 10:26:55 PM PST 24
Finished Jan 21 10:27:19 PM PST 24
Peak memory 217296 kb
Host smart-d3ca544a-df35-4489-a833-d418646e1edf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558249408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2558249408
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3985165545
Short name T308
Test name
Test status
Simulation time 338487331 ps
CPU time 13.99 seconds
Started Jan 21 10:26:49 PM PST 24
Finished Jan 21 10:27:20 PM PST 24
Peak memory 217348 kb
Host smart-99911c6b-d09a-43e2-8ccc-a69ea92d2df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985165545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3985165545
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3296113884
Short name T80
Test name
Test status
Simulation time 25211776 ps
CPU time 1.14 seconds
Started Jan 21 10:26:51 PM PST 24
Finished Jan 21 10:27:09 PM PST 24
Peak memory 212188 kb
Host smart-fcdd99be-09ea-460c-80b5-32f7bbd61712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296113884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3296113884
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1596793160
Short name T853
Test name
Test status
Simulation time 198458690 ps
CPU time 26.26 seconds
Started Jan 21 10:26:52 PM PST 24
Finished Jan 21 10:27:35 PM PST 24
Peak memory 247952 kb
Host smart-f19e633e-15ff-425c-9c82-4357b14ef761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596793160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1596793160
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2282036834
Short name T819
Test name
Test status
Simulation time 69461336 ps
CPU time 7.38 seconds
Started Jan 21 10:26:52 PM PST 24
Finished Jan 21 10:27:16 PM PST 24
Peak memory 250012 kb
Host smart-6b19784f-ad6d-42d7-8e58-8710403d457c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282036834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2282036834
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2535579892
Short name T687
Test name
Test status
Simulation time 4761899513 ps
CPU time 110.78 seconds
Started Jan 21 10:26:53 PM PST 24
Finished Jan 21 10:29:00 PM PST 24
Peak memory 226964 kb
Host smart-b4ab6584-a891-427e-aa88-5c0bb9557a9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535579892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2535579892
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3647963999
Short name T714
Test name
Test status
Simulation time 14323427 ps
CPU time 0.8 seconds
Started Jan 21 10:26:51 PM PST 24
Finished Jan 21 10:27:09 PM PST 24
Peak memory 207412 kb
Host smart-d1fc3620-2a64-4a01-a4b9-845123829ddf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647963999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3647963999
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.899369404
Short name T513
Test name
Test status
Simulation time 61072064 ps
CPU time 1.05 seconds
Started Jan 21 10:27:07 PM PST 24
Finished Jan 21 10:27:25 PM PST 24
Peak memory 207672 kb
Host smart-dc80d401-cc59-4497-b851-432f1357ee8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899369404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.899369404
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1725633085
Short name T507
Test name
Test status
Simulation time 358373569 ps
CPU time 11.47 seconds
Started Jan 21 10:26:54 PM PST 24
Finished Jan 21 10:27:22 PM PST 24
Peak memory 217324 kb
Host smart-f8976a13-4dbb-4e60-af9b-f72f39834c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725633085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1725633085
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.462534597
Short name T438
Test name
Test status
Simulation time 302829767 ps
CPU time 2.54 seconds
Started Jan 21 10:26:54 PM PST 24
Finished Jan 21 10:27:13 PM PST 24
Peak memory 208980 kb
Host smart-c88812d6-b510-419a-9b47-cf34c5e449a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462534597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_ac
cess.462534597
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2799833993
Short name T495
Test name
Test status
Simulation time 36711452 ps
CPU time 1.95 seconds
Started Jan 21 10:26:53 PM PST 24
Finished Jan 21 10:27:11 PM PST 24
Peak memory 217328 kb
Host smart-d5fd5a65-7025-4a77-8f53-23da457bfaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799833993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2799833993
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2268461653
Short name T51
Test name
Test status
Simulation time 573853269 ps
CPU time 10.25 seconds
Started Jan 21 10:26:53 PM PST 24
Finished Jan 21 10:27:20 PM PST 24
Peak memory 218356 kb
Host smart-44bbf0f6-f9ea-4ccc-bf2b-c13c9a859e2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268461653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2268461653
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1435828022
Short name T711
Test name
Test status
Simulation time 181151359 ps
CPU time 7.51 seconds
Started Jan 21 10:27:06 PM PST 24
Finished Jan 21 10:27:31 PM PST 24
Peak memory 217372 kb
Host smart-4ba28d24-f01c-4825-8293-dc885591ca3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435828022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1435828022
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.923907820
Short name T499
Test name
Test status
Simulation time 1371264484 ps
CPU time 13.37 seconds
Started Jan 21 10:27:08 PM PST 24
Finished Jan 21 10:27:38 PM PST 24
Peak memory 217380 kb
Host smart-6ccf3de1-ffea-4db7-8d86-b04809e6af66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923907820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.923907820
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1766198726
Short name T692
Test name
Test status
Simulation time 207860771 ps
CPU time 6.86 seconds
Started Jan 21 10:26:55 PM PST 24
Finished Jan 21 10:27:19 PM PST 24
Peak memory 217340 kb
Host smart-99aa757a-d2af-4cba-b89f-4ff4397de62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766198726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1766198726
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2851459327
Short name T813
Test name
Test status
Simulation time 24778136 ps
CPU time 1.84 seconds
Started Jan 21 10:26:59 PM PST 24
Finished Jan 21 10:27:18 PM PST 24
Peak memory 212652 kb
Host smart-207168c8-3e12-4a4f-b334-7f5d5fab7ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851459327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2851459327
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.4266196925
Short name T920
Test name
Test status
Simulation time 326232780 ps
CPU time 28.82 seconds
Started Jan 21 10:26:54 PM PST 24
Finished Jan 21 10:27:39 PM PST 24
Peak memory 249288 kb
Host smart-2a597bf8-38c3-4bc7-9eff-dc492430e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266196925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.4266196925
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.560015858
Short name T726
Test name
Test status
Simulation time 214573224 ps
CPU time 6.61 seconds
Started Jan 21 10:26:55 PM PST 24
Finished Jan 21 10:27:18 PM PST 24
Peak memory 249708 kb
Host smart-bb5df600-5b90-4dd5-b482-c3954f2865df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560015858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.560015858
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3813157815
Short name T955
Test name
Test status
Simulation time 13193199285 ps
CPU time 441.5 seconds
Started Jan 21 10:27:12 PM PST 24
Finished Jan 21 10:34:50 PM PST 24
Peak memory 250464 kb
Host smart-ce1e5cb8-9dd1-4599-8a93-be5a562ac2c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813157815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3813157815
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2751790949
Short name T807
Test name
Test status
Simulation time 102309163 ps
CPU time 0.81 seconds
Started Jan 21 10:26:54 PM PST 24
Finished Jan 21 10:27:11 PM PST 24
Peak memory 206936 kb
Host smart-e0f7eb78-31a3-49e4-a950-c832582097cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751790949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2751790949
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.459952107
Short name T572
Test name
Test status
Simulation time 240415674 ps
CPU time 0.98 seconds
Started Jan 21 10:22:15 PM PST 24
Finished Jan 21 10:22:21 PM PST 24
Peak memory 208924 kb
Host smart-4686dec4-158e-4732-a4cc-0ac0b32aeaa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459952107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.459952107
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.154713779
Short name T816
Test name
Test status
Simulation time 25980681 ps
CPU time 0.89 seconds
Started Jan 21 10:21:57 PM PST 24
Finished Jan 21 10:22:00 PM PST 24
Peak memory 207380 kb
Host smart-cc9edfa5-1da5-477a-8c7d-9d77d955ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154713779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.154713779
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1602059392
Short name T360
Test name
Test status
Simulation time 509390310 ps
CPU time 11.87 seconds
Started Jan 21 10:21:50 PM PST 24
Finished Jan 21 10:22:05 PM PST 24
Peak memory 217324 kb
Host smart-fb48f55c-9a15-4b8d-b459-11378e1a174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602059392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1602059392
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3679283274
Short name T33
Test name
Test status
Simulation time 107775594 ps
CPU time 3.43 seconds
Started Jan 21 10:22:04 PM PST 24
Finished Jan 21 10:22:15 PM PST 24
Peak memory 208880 kb
Host smart-e67413f1-50d7-4458-a5ce-5be0932c478e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679283274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.3679283274
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.189930881
Short name T568
Test name
Test status
Simulation time 8914025333 ps
CPU time 28.52 seconds
Started Jan 21 10:22:03 PM PST 24
Finished Jan 21 10:22:39 PM PST 24
Peak memory 217424 kb
Host smart-41b8ef7e-09fa-45d9-ad16-957f9aeb8572
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189930881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.189930881
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1866158412
Short name T607
Test name
Test status
Simulation time 134074388 ps
CPU time 4.37 seconds
Started Jan 21 10:22:07 PM PST 24
Finished Jan 21 10:22:17 PM PST 24
Peak memory 217172 kb
Host smart-097ea4ea-07a8-45ef-b376-7b2ee2f2d441
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866158412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.1866158412
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2539140271
Short name T348
Test name
Test status
Simulation time 1114399253 ps
CPU time 7.86 seconds
Started Jan 21 10:22:07 PM PST 24
Finished Jan 21 10:22:21 PM PST 24
Peak memory 217272 kb
Host smart-8b211798-9dfd-467c-9909-407299e64c1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539140271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2539140271
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1832425159
Short name T6
Test name
Test status
Simulation time 991495466 ps
CPU time 14.71 seconds
Started Jan 21 10:22:03 PM PST 24
Finished Jan 21 10:22:26 PM PST 24
Peak memory 212296 kb
Host smart-7a360e89-51e0-4ef2-b1aa-7e468678f6eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832425159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1832425159
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2275911948
Short name T90
Test name
Test status
Simulation time 469539478 ps
CPU time 2.97 seconds
Started Jan 21 10:21:52 PM PST 24
Finished Jan 21 10:21:57 PM PST 24
Peak memory 211848 kb
Host smart-8cc2c5d1-c80c-4986-b360-eb59031d454e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275911948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2275911948
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1287670296
Short name T437
Test name
Test status
Simulation time 5843969556 ps
CPU time 59.17 seconds
Started Jan 21 10:22:02 PM PST 24
Finished Jan 21 10:23:07 PM PST 24
Peak memory 250788 kb
Host smart-27eefaa0-7a55-45ff-b899-cc8f159265d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287670296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1287670296
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4127316373
Short name T966
Test name
Test status
Simulation time 3047010150 ps
CPU time 13.48 seconds
Started Jan 21 10:22:01 PM PST 24
Finished Jan 21 10:22:21 PM PST 24
Peak memory 246412 kb
Host smart-bc00b806-0175-4a2a-841b-bafacd47a057
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127316373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4127316373
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.432259252
Short name T370
Test name
Test status
Simulation time 90174377 ps
CPU time 1.92 seconds
Started Jan 21 10:21:57 PM PST 24
Finished Jan 21 10:22:02 PM PST 24
Peak memory 217332 kb
Host smart-dc77bfb1-e6e3-474d-8cdd-03b6d65ea17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432259252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.432259252
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1066455127
Short name T303
Test name
Test status
Simulation time 424529195 ps
CPU time 23.33 seconds
Started Jan 21 10:21:54 PM PST 24
Finished Jan 21 10:22:21 PM PST 24
Peak memory 213072 kb
Host smart-181f3f6f-697f-440d-b490-265b296407a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066455127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1066455127
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.150479807
Short name T55
Test name
Test status
Simulation time 1996149124 ps
CPU time 15.32 seconds
Started Jan 21 10:22:04 PM PST 24
Finished Jan 21 10:22:26 PM PST 24
Peak memory 217360 kb
Host smart-92b879ee-4cfb-4d61-b65c-a1a1f14bc409
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150479807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.150479807
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2020846279
Short name T859
Test name
Test status
Simulation time 884643150 ps
CPU time 11.07 seconds
Started Jan 21 10:22:05 PM PST 24
Finished Jan 21 10:22:23 PM PST 24
Peak memory 217304 kb
Host smart-d8f052d4-3c07-484b-ae15-d57e73e80123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020846279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2020846279
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1232169289
Short name T60
Test name
Test status
Simulation time 444723763 ps
CPU time 8.92 seconds
Started Jan 21 10:22:04 PM PST 24
Finished Jan 21 10:22:20 PM PST 24
Peak memory 217328 kb
Host smart-7dee5bc0-3f00-42c2-8346-3ed05a7ef860
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232169289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
232169289
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3622858225
Short name T399
Test name
Test status
Simulation time 323395954 ps
CPU time 13.98 seconds
Started Jan 21 10:21:45 PM PST 24
Finished Jan 21 10:22:04 PM PST 24
Peak memory 217340 kb
Host smart-c5bd5aca-2cd6-4131-b4ee-6290f9731ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622858225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3622858225
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1779684666
Short name T50
Test name
Test status
Simulation time 57357426 ps
CPU time 2.47 seconds
Started Jan 21 10:21:36 PM PST 24
Finished Jan 21 10:21:47 PM PST 24
Peak memory 213012 kb
Host smart-9ecf41ab-9680-4b6a-8594-cfc233551100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779684666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1779684666
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.191082767
Short name T646
Test name
Test status
Simulation time 1386097323 ps
CPU time 29.09 seconds
Started Jan 21 10:21:41 PM PST 24
Finished Jan 21 10:22:16 PM PST 24
Peak memory 250220 kb
Host smart-e549a7bb-d352-4068-a1bd-ea344a5b509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191082767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.191082767
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2646808760
Short name T483
Test name
Test status
Simulation time 115155195 ps
CPU time 9.89 seconds
Started Jan 21 10:21:50 PM PST 24
Finished Jan 21 10:22:03 PM PST 24
Peak memory 250340 kb
Host smart-166fe1df-afaf-4b8d-80fb-4b96f975d9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646808760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2646808760
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2246491053
Short name T485
Test name
Test status
Simulation time 14606349 ps
CPU time 1.01 seconds
Started Jan 21 10:21:41 PM PST 24
Finished Jan 21 10:21:48 PM PST 24
Peak memory 207572 kb
Host smart-5d8c2dfe-4c92-4413-8ec8-d9a8b61ab9e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246491053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2246491053
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.636335969
Short name T672
Test name
Test status
Simulation time 55319660 ps
CPU time 0.88 seconds
Started Jan 21 10:27:10 PM PST 24
Finished Jan 21 10:27:28 PM PST 24
Peak memory 208948 kb
Host smart-4e90c77d-d453-4f26-b894-707944926cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636335969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.636335969
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.4175283404
Short name T530
Test name
Test status
Simulation time 249506692 ps
CPU time 7.97 seconds
Started Jan 21 10:27:09 PM PST 24
Finished Jan 21 10:27:34 PM PST 24
Peak memory 217356 kb
Host smart-642b3208-90a6-4bcc-9996-e4dc30e158fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175283404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.4175283404
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1613102650
Short name T822
Test name
Test status
Simulation time 638228686 ps
CPU time 15.82 seconds
Started Jan 21 10:27:12 PM PST 24
Finished Jan 21 10:27:44 PM PST 24
Peak memory 208900 kb
Host smart-ed2b0726-1695-4d07-a443-5a45d54c0743
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613102650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.1613102650
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2512717696
Short name T487
Test name
Test status
Simulation time 82377784 ps
CPU time 2.64 seconds
Started Jan 21 10:27:10 PM PST 24
Finished Jan 21 10:27:30 PM PST 24
Peak memory 217372 kb
Host smart-840e49d2-c8ae-4312-99b4-c320ae79a3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512717696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2512717696
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3182856448
Short name T501
Test name
Test status
Simulation time 1805969006 ps
CPU time 18.45 seconds
Started Jan 21 10:27:10 PM PST 24
Finished Jan 21 10:27:45 PM PST 24
Peak memory 217400 kb
Host smart-08a468ee-0d17-41ad-acd1-c2e1f1b3cdc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182856448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3182856448
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1834747069
Short name T710
Test name
Test status
Simulation time 3118754063 ps
CPU time 23.96 seconds
Started Jan 21 10:27:10 PM PST 24
Finished Jan 21 10:27:51 PM PST 24
Peak memory 217452 kb
Host smart-392c1a44-6cb4-415e-b6e5-9869521057b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834747069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1834747069
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.500348954
Short name T974
Test name
Test status
Simulation time 277716434 ps
CPU time 10.53 seconds
Started Jan 21 10:27:15 PM PST 24
Finished Jan 21 10:27:42 PM PST 24
Peak memory 217356 kb
Host smart-3d926885-55a8-42ed-b87d-bfde730be57b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500348954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.500348954
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4132903599
Short name T626
Test name
Test status
Simulation time 2164225021 ps
CPU time 17.53 seconds
Started Jan 21 10:27:09 PM PST 24
Finished Jan 21 10:27:44 PM PST 24
Peak memory 217444 kb
Host smart-a0ee4772-5f78-49de-9fa1-493aa0ae6250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132903599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4132903599
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1420653215
Short name T404
Test name
Test status
Simulation time 25451143 ps
CPU time 1.79 seconds
Started Jan 21 10:27:08 PM PST 24
Finished Jan 21 10:27:27 PM PST 24
Peak memory 212440 kb
Host smart-6d18f4fb-6cfe-4995-8425-a97434a26d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420653215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1420653215
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1315590645
Short name T519
Test name
Test status
Simulation time 234205397 ps
CPU time 28.39 seconds
Started Jan 21 10:27:12 PM PST 24
Finished Jan 21 10:27:57 PM PST 24
Peak memory 250300 kb
Host smart-0407cc0f-bdd1-4247-be54-5ecfeaf8b125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315590645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1315590645
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.406944294
Short name T719
Test name
Test status
Simulation time 554630457 ps
CPU time 7.94 seconds
Started Jan 21 10:27:08 PM PST 24
Finished Jan 21 10:27:33 PM PST 24
Peak memory 248948 kb
Host smart-a474bd2d-5efb-4d8c-b292-4f193c1da5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406944294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.406944294
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1604341878
Short name T828
Test name
Test status
Simulation time 12846755965 ps
CPU time 36.23 seconds
Started Jan 21 10:27:13 PM PST 24
Finished Jan 21 10:28:05 PM PST 24
Peak memory 250344 kb
Host smart-6df82d8e-1f01-4fc6-9823-aed029a053fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604341878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1604341878
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.4011241463
Short name T628
Test name
Test status
Simulation time 28318429447 ps
CPU time 311.53 seconds
Started Jan 21 10:27:10 PM PST 24
Finished Jan 21 10:32:38 PM PST 24
Peak memory 277320 kb
Host smart-c31d9db8-039e-42ec-b4b6-6c5d2cf40af9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4011241463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.4011241463
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2201096884
Short name T909
Test name
Test status
Simulation time 35521311 ps
CPU time 0.83 seconds
Started Jan 21 10:27:09 PM PST 24
Finished Jan 21 10:27:27 PM PST 24
Peak memory 207332 kb
Host smart-66cde124-cb97-4ac6-9d9c-962c7dd95527
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201096884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2201096884
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.709353836
Short name T984
Test name
Test status
Simulation time 17969175 ps
CPU time 0.87 seconds
Started Jan 21 10:27:17 PM PST 24
Finished Jan 21 10:27:37 PM PST 24
Peak memory 208972 kb
Host smart-e8dfe18d-1cda-4584-9db0-d85847db288a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709353836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.709353836
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.139420437
Short name T518
Test name
Test status
Simulation time 295476519 ps
CPU time 13.03 seconds
Started Jan 21 10:27:14 PM PST 24
Finished Jan 21 10:27:43 PM PST 24
Peak memory 217324 kb
Host smart-e6a87714-57d5-4541-9e71-be2d7aa6e6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139420437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.139420437
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3169302681
Short name T603
Test name
Test status
Simulation time 183068153 ps
CPU time 5.45 seconds
Started Jan 21 10:27:17 PM PST 24
Finished Jan 21 10:27:41 PM PST 24
Peak memory 208892 kb
Host smart-3465db0e-04d7-4213-af5c-2dc380d7faee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169302681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.3169302681
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1603603051
Short name T312
Test name
Test status
Simulation time 470596537 ps
CPU time 3.54 seconds
Started Jan 21 10:27:13 PM PST 24
Finished Jan 21 10:27:33 PM PST 24
Peak memory 217328 kb
Host smart-41dbab8b-d599-4552-84a4-39e9d812190d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603603051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1603603051
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4040582969
Short name T976
Test name
Test status
Simulation time 1221954536 ps
CPU time 15.48 seconds
Started Jan 21 10:27:16 PM PST 24
Finished Jan 21 10:27:51 PM PST 24
Peak memory 217312 kb
Host smart-d50fc4c0-816d-45fc-a2f4-a0bbe7acb21c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040582969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4040582969
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3999077211
Short name T520
Test name
Test status
Simulation time 436515266 ps
CPU time 11.63 seconds
Started Jan 21 10:27:17 PM PST 24
Finished Jan 21 10:27:47 PM PST 24
Peak memory 217316 kb
Host smart-cbcbcf58-cf63-40fc-ba0b-445f946f8d59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999077211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3999077211
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3673865149
Short name T890
Test name
Test status
Simulation time 273009308 ps
CPU time 7.82 seconds
Started Jan 21 10:27:16 PM PST 24
Finished Jan 21 10:27:42 PM PST 24
Peak memory 217304 kb
Host smart-b6c9b5d7-ca96-4770-b50b-60c17a84f2f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673865149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3673865149
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1978173861
Short name T805
Test name
Test status
Simulation time 886545474 ps
CPU time 9.83 seconds
Started Jan 21 10:27:20 PM PST 24
Finished Jan 21 10:27:49 PM PST 24
Peak memory 217360 kb
Host smart-3882fe36-2992-47d9-9c87-88e3f40a43bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978173861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1978173861
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4261269308
Short name T524
Test name
Test status
Simulation time 113384588 ps
CPU time 1.93 seconds
Started Jan 21 10:27:15 PM PST 24
Finished Jan 21 10:27:33 PM PST 24
Peak memory 212912 kb
Host smart-a17cd360-514c-479f-a7d6-d39c20733879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261269308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4261269308
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3078312870
Short name T545
Test name
Test status
Simulation time 221546537 ps
CPU time 25.36 seconds
Started Jan 21 10:27:13 PM PST 24
Finished Jan 21 10:27:55 PM PST 24
Peak memory 249628 kb
Host smart-077bbbc3-dda3-4252-bf80-0621e3bac7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078312870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3078312870
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1827627741
Short name T313
Test name
Test status
Simulation time 275759749 ps
CPU time 6.33 seconds
Started Jan 21 10:27:14 PM PST 24
Finished Jan 21 10:27:37 PM PST 24
Peak memory 245880 kb
Host smart-a2ad99bc-2e65-48c8-bab1-3d8afe843ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827627741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1827627741
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.4012903245
Short name T24
Test name
Test status
Simulation time 9210889674 ps
CPU time 43.79 seconds
Started Jan 21 11:13:46 PM PST 24
Finished Jan 21 11:14:31 PM PST 24
Peak memory 248180 kb
Host smart-e12e2422-1fcc-4e33-a7d9-4f1f46eca856
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012903245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.4012903245
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1447420329
Short name T48
Test name
Test status
Simulation time 46586932 ps
CPU time 0.77 seconds
Started Jan 21 10:27:13 PM PST 24
Finished Jan 21 10:27:30 PM PST 24
Peak memory 207484 kb
Host smart-f2c5bab9-bc70-4ad3-925d-b880c22082ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447420329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1447420329
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.752163903
Short name T604
Test name
Test status
Simulation time 50974528 ps
CPU time 1.07 seconds
Started Jan 21 10:27:40 PM PST 24
Finished Jan 21 10:27:55 PM PST 24
Peak memory 208856 kb
Host smart-c5b0a358-fa5e-4830-a9de-ba32bab214d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752163903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.752163903
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1424855556
Short name T781
Test name
Test status
Simulation time 1195265559 ps
CPU time 14.35 seconds
Started Jan 21 10:27:26 PM PST 24
Finished Jan 21 10:28:00 PM PST 24
Peak memory 217312 kb
Host smart-72344214-45fb-4117-a200-305ec825646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424855556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1424855556
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.4244386868
Short name T790
Test name
Test status
Simulation time 659503206 ps
CPU time 15.3 seconds
Started Jan 21 10:27:34 PM PST 24
Finished Jan 21 10:28:06 PM PST 24
Peak memory 217168 kb
Host smart-8ae6819d-8d78-46c9-b347-6d5e460f94d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244386868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.4244386868
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2910463432
Short name T898
Test name
Test status
Simulation time 340216402 ps
CPU time 3.79 seconds
Started Jan 21 10:27:32 PM PST 24
Finished Jan 21 10:27:53 PM PST 24
Peak memory 217344 kb
Host smart-1ca4e937-71b7-4e7a-8edb-27363d836091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910463432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2910463432
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3899302293
Short name T444
Test name
Test status
Simulation time 379449359 ps
CPU time 13.14 seconds
Started Jan 21 10:27:36 PM PST 24
Finished Jan 21 10:28:05 PM PST 24
Peak memory 217592 kb
Host smart-c04b3b1b-a63f-43f6-abce-95cf5939df8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899302293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3899302293
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2878061730
Short name T395
Test name
Test status
Simulation time 3745446357 ps
CPU time 11 seconds
Started Jan 21 10:27:38 PM PST 24
Finished Jan 21 10:28:04 PM PST 24
Peak memory 217480 kb
Host smart-7ac84a03-0979-48e0-bcdf-fce970e3fa72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878061730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2878061730
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.99966054
Short name T826
Test name
Test status
Simulation time 1423030754 ps
CPU time 8.95 seconds
Started Jan 21 10:27:31 PM PST 24
Finished Jan 21 10:27:57 PM PST 24
Peak memory 217368 kb
Host smart-a358881f-40b1-4edb-b2eb-bf8c68ecec07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99966054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.99966054
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3452043473
Short name T964
Test name
Test status
Simulation time 309721973 ps
CPU time 9.84 seconds
Started Jan 21 10:27:25 PM PST 24
Finished Jan 21 10:27:55 PM PST 24
Peak memory 217304 kb
Host smart-6f9352ec-c2c3-4e18-954c-6a67fe1c0b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452043473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3452043473
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1889075191
Short name T508
Test name
Test status
Simulation time 429855429 ps
CPU time 3.93 seconds
Started Jan 21 10:27:35 PM PST 24
Finished Jan 21 10:27:55 PM PST 24
Peak memory 213572 kb
Host smart-3c3a6476-817e-4fd0-afad-bfd7f6b59b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889075191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1889075191
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1231217076
Short name T550
Test name
Test status
Simulation time 1167249354 ps
CPU time 26.25 seconds
Started Jan 21 10:27:27 PM PST 24
Finished Jan 21 10:28:13 PM PST 24
Peak memory 250256 kb
Host smart-92040012-0d13-40b4-9644-85f1614e4074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231217076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1231217076
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1875031476
Short name T602
Test name
Test status
Simulation time 125865994 ps
CPU time 8.03 seconds
Started Jan 21 10:27:25 PM PST 24
Finished Jan 21 10:27:53 PM PST 24
Peak memory 247180 kb
Host smart-cb035633-dce4-4b91-91b1-4c046c0b9ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875031476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1875031476
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3896644507
Short name T815
Test name
Test status
Simulation time 20731613865 ps
CPU time 203.19 seconds
Started Jan 21 10:27:28 PM PST 24
Finished Jan 21 10:31:10 PM PST 24
Peak memory 277716 kb
Host smart-05885bce-36d5-4de8-b3c8-037617e0e9a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896644507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3896644507
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1823288478
Short name T747
Test name
Test status
Simulation time 12507018 ps
CPU time 0.95 seconds
Started Jan 21 10:27:30 PM PST 24
Finished Jan 21 10:27:49 PM PST 24
Peak memory 210656 kb
Host smart-3863fa1c-89d7-4283-ac43-f901459ada15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823288478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1823288478
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1621596641
Short name T529
Test name
Test status
Simulation time 40165096 ps
CPU time 0.96 seconds
Started Jan 21 10:27:42 PM PST 24
Finished Jan 21 10:27:56 PM PST 24
Peak memory 207600 kb
Host smart-499a16ce-0f99-44f2-9bee-4392b681f16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621596641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1621596641
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1127861782
Short name T766
Test name
Test status
Simulation time 3304305705 ps
CPU time 11.9 seconds
Started Jan 21 10:27:40 PM PST 24
Finished Jan 21 10:28:06 PM PST 24
Peak memory 217384 kb
Host smart-2c2e7eaa-2c95-4c05-9136-13ffd03e516d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127861782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1127861782
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1023185823
Short name T737
Test name
Test status
Simulation time 701680802 ps
CPU time 17.05 seconds
Started Jan 21 10:27:42 PM PST 24
Finished Jan 21 10:28:12 PM PST 24
Peak memory 208932 kb
Host smart-8c6a7d65-12db-40cd-9ef9-5d76c96a9406
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023185823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.1023185823
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3612817271
Short name T937
Test name
Test status
Simulation time 80298101 ps
CPU time 3.33 seconds
Started Jan 21 10:27:41 PM PST 24
Finished Jan 21 10:27:58 PM PST 24
Peak memory 217324 kb
Host smart-56d72c86-d11e-4f84-94e4-0bd00ba0d8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612817271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3612817271
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.4130698453
Short name T835
Test name
Test status
Simulation time 4595704467 ps
CPU time 11.75 seconds
Started Jan 21 10:27:35 PM PST 24
Finished Jan 21 10:28:03 PM PST 24
Peak memory 218432 kb
Host smart-3b1e5219-4601-4b80-a2af-2b8b1e89d1c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130698453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.4130698453
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4200420824
Short name T655
Test name
Test status
Simulation time 640695126 ps
CPU time 13.62 seconds
Started Jan 21 10:27:39 PM PST 24
Finished Jan 21 10:28:07 PM PST 24
Peak memory 217356 kb
Host smart-90bf31d2-03ab-4c22-9913-a607fdbe90ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200420824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4200420824
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2418926806
Short name T950
Test name
Test status
Simulation time 1363826852 ps
CPU time 8.88 seconds
Started Jan 21 10:27:37 PM PST 24
Finished Jan 21 10:28:01 PM PST 24
Peak memory 217372 kb
Host smart-3192dc75-fda7-46f6-9220-774200fb17d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418926806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2418926806
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3416115518
Short name T977
Test name
Test status
Simulation time 297395594 ps
CPU time 10.49 seconds
Started Jan 21 10:27:42 PM PST 24
Finished Jan 21 10:28:05 PM PST 24
Peak memory 217328 kb
Host smart-38fde754-20dc-46ea-a4da-d26f630c79ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416115518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3416115518
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1881061762
Short name T855
Test name
Test status
Simulation time 84602448 ps
CPU time 3.25 seconds
Started Jan 21 10:27:42 PM PST 24
Finished Jan 21 10:27:58 PM PST 24
Peak memory 213316 kb
Host smart-134407b8-4617-49bc-8e1f-a289038ab978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881061762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1881061762
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.684199247
Short name T432
Test name
Test status
Simulation time 2165646205 ps
CPU time 27.7 seconds
Started Jan 21 10:27:40 PM PST 24
Finished Jan 21 10:28:22 PM PST 24
Peak memory 250144 kb
Host smart-5ce01b7f-9fd5-44b4-967c-f2a9e33dfa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684199247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.684199247
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.941502858
Short name T379
Test name
Test status
Simulation time 162324395 ps
CPU time 3.82 seconds
Started Jan 21 10:27:39 PM PST 24
Finished Jan 21 10:27:57 PM PST 24
Peak memory 217352 kb
Host smart-73c499a7-092b-4e36-aca2-91c99312f73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941502858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.941502858
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4204637321
Short name T677
Test name
Test status
Simulation time 2509310926 ps
CPU time 50.7 seconds
Started Jan 21 10:27:44 PM PST 24
Finished Jan 21 10:28:47 PM PST 24
Peak memory 250240 kb
Host smart-87632d43-da55-41dd-9a9a-dda79cdd63db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204637321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4204637321
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1336155818
Short name T821
Test name
Test status
Simulation time 39612987 ps
CPU time 0.79 seconds
Started Jan 21 10:27:37 PM PST 24
Finished Jan 21 10:27:53 PM PST 24
Peak memory 207464 kb
Host smart-1d3367a9-b48b-4805-958c-492b0a1200cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336155818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1336155818
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.62465001
Short name T38
Test name
Test status
Simulation time 38976598 ps
CPU time 1.03 seconds
Started Jan 21 10:28:01 PM PST 24
Finished Jan 21 10:28:08 PM PST 24
Peak memory 207668 kb
Host smart-202df411-10bf-42db-ac3e-c676ef257589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62465001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.62465001
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.406560437
Short name T845
Test name
Test status
Simulation time 876419723 ps
CPU time 9.8 seconds
Started Jan 21 10:56:47 PM PST 24
Finished Jan 21 10:56:58 PM PST 24
Peak memory 217336 kb
Host smart-2135bbb5-fbd2-4b38-bc33-77491c83cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406560437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.406560437
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.381124143
Short name T32
Test name
Test status
Simulation time 531101845 ps
CPU time 12.7 seconds
Started Jan 21 10:50:57 PM PST 24
Finished Jan 21 10:51:10 PM PST 24
Peak memory 208932 kb
Host smart-be0bdc44-fc27-4a1f-8c7b-d7ffc989f53b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381124143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_ac
cess.381124143
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1368480524
Short name T767
Test name
Test status
Simulation time 207315307 ps
CPU time 2.66 seconds
Started Jan 21 10:27:49 PM PST 24
Finished Jan 21 10:28:04 PM PST 24
Peak memory 217440 kb
Host smart-c3bb9501-ad7a-497c-a422-1e358c3c0523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368480524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1368480524
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4154100142
Short name T841
Test name
Test status
Simulation time 695576238 ps
CPU time 9.88 seconds
Started Jan 21 10:27:51 PM PST 24
Finished Jan 21 10:28:11 PM PST 24
Peak memory 217364 kb
Host smart-c5ea5802-15ce-4931-b443-3e797314d2f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154100142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4154100142
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.388859816
Short name T456
Test name
Test status
Simulation time 1291236437 ps
CPU time 10.72 seconds
Started Jan 21 10:27:55 PM PST 24
Finished Jan 21 10:28:15 PM PST 24
Peak memory 217356 kb
Host smart-63e3c0bf-9b43-494e-a7e9-acd95fbf0082
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388859816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.388859816
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3002550424
Short name T599
Test name
Test status
Simulation time 911762903 ps
CPU time 17.5 seconds
Started Jan 21 10:27:57 PM PST 24
Finished Jan 21 10:28:23 PM PST 24
Peak memory 217340 kb
Host smart-f5b88708-2682-40cc-8f8a-26ef0153ae40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002550424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3002550424
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.203053005
Short name T359
Test name
Test status
Simulation time 1232160085 ps
CPU time 8.18 seconds
Started Jan 21 10:27:50 PM PST 24
Finished Jan 21 10:28:10 PM PST 24
Peak memory 217320 kb
Host smart-1a689589-848f-4c5b-86be-e46f4c7e8e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203053005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.203053005
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4280372658
Short name T547
Test name
Test status
Simulation time 45473712 ps
CPU time 2.33 seconds
Started Jan 21 10:27:46 PM PST 24
Finished Jan 21 10:28:00 PM PST 24
Peak memory 213128 kb
Host smart-e10bcd1c-5b29-4ab0-93f8-d8d10fb66e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280372658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4280372658
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1859360085
Short name T346
Test name
Test status
Simulation time 1882622532 ps
CPU time 34.66 seconds
Started Jan 21 10:27:45 PM PST 24
Finished Jan 21 10:28:32 PM PST 24
Peak memory 250232 kb
Host smart-726cc206-4bb8-42ba-aeeb-c6927f0b2789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859360085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1859360085
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.335656601
Short name T698
Test name
Test status
Simulation time 56388991 ps
CPU time 3.61 seconds
Started Jan 21 11:37:22 PM PST 24
Finished Jan 21 11:37:27 PM PST 24
Peak memory 217480 kb
Host smart-a0682751-5ff8-4ed7-a8a4-96bdf6ec7713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335656601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.335656601
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.231721276
Short name T549
Test name
Test status
Simulation time 2590256371 ps
CPU time 77.95 seconds
Started Jan 21 10:27:57 PM PST 24
Finished Jan 21 10:29:23 PM PST 24
Peak memory 225656 kb
Host smart-05ad6f7b-8a7b-4d34-8218-a5b96d55d1af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231721276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.231721276
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2758603130
Short name T965
Test name
Test status
Simulation time 42232539 ps
CPU time 0.78 seconds
Started Jan 21 10:27:46 PM PST 24
Finished Jan 21 10:27:59 PM PST 24
Peak memory 207460 kb
Host smart-11219c9d-7b03-42f5-b062-15be0d12435e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758603130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2758603130
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1149070603
Short name T911
Test name
Test status
Simulation time 31168301 ps
CPU time 1.14 seconds
Started Jan 21 10:28:06 PM PST 24
Finished Jan 21 10:28:11 PM PST 24
Peak memory 208972 kb
Host smart-c53498d1-8a07-43dd-859b-81ceee5a4593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149070603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1149070603
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2876884072
Short name T555
Test name
Test status
Simulation time 1029636851 ps
CPU time 8.78 seconds
Started Jan 21 10:28:02 PM PST 24
Finished Jan 21 10:28:16 PM PST 24
Peak memory 217364 kb
Host smart-21b30d04-61fe-4bd6-bf81-6851cc7e074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876884072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2876884072
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2145314260
Short name T660
Test name
Test status
Simulation time 379622910 ps
CPU time 4.78 seconds
Started Jan 21 10:28:02 PM PST 24
Finished Jan 21 10:28:12 PM PST 24
Peak memory 208916 kb
Host smart-dff3315e-bafa-4418-a370-6f2baea8fa86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145314260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.2145314260
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4143358320
Short name T913
Test name
Test status
Simulation time 51665769 ps
CPU time 2.83 seconds
Started Jan 21 10:27:56 PM PST 24
Finished Jan 21 10:28:07 PM PST 24
Peak memory 217336 kb
Host smart-7d624e9b-0973-489c-8c09-24585fd4048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143358320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4143358320
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.219752542
Short name T837
Test name
Test status
Simulation time 346927150 ps
CPU time 14.66 seconds
Started Jan 21 10:28:03 PM PST 24
Finished Jan 21 10:28:23 PM PST 24
Peak memory 217432 kb
Host smart-b16a1cf6-bd74-470d-9980-39847d78d74b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219752542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.219752542
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3970916101
Short name T970
Test name
Test status
Simulation time 1835759886 ps
CPU time 8.57 seconds
Started Jan 21 10:28:06 PM PST 24
Finished Jan 21 10:28:18 PM PST 24
Peak memory 217336 kb
Host smart-5f4e8316-d834-4ccd-ad62-3be406751804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970916101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3970916101
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1995031086
Short name T462
Test name
Test status
Simulation time 666749326 ps
CPU time 9.53 seconds
Started Jan 21 10:28:05 PM PST 24
Finished Jan 21 10:28:19 PM PST 24
Peak memory 217368 kb
Host smart-c29682c3-8714-4b86-aef7-bbb066dc3b9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995031086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1995031086
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.397728920
Short name T768
Test name
Test status
Simulation time 35044548 ps
CPU time 2.86 seconds
Started Jan 21 10:27:55 PM PST 24
Finished Jan 21 10:28:07 PM PST 24
Peak memory 213328 kb
Host smart-c3d8bf66-6d0e-4b76-b07c-627738e74894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397728920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.397728920
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1395196878
Short name T123
Test name
Test status
Simulation time 147014496 ps
CPU time 13.85 seconds
Started Jan 21 10:27:57 PM PST 24
Finished Jan 21 10:28:19 PM PST 24
Peak memory 245164 kb
Host smart-0a0d237e-6bb9-42d6-90ad-c3e9403ffd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395196878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1395196878
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2588612016
Short name T630
Test name
Test status
Simulation time 343083057 ps
CPU time 6.58 seconds
Started Jan 21 10:27:55 PM PST 24
Finished Jan 21 10:28:11 PM PST 24
Peak memory 249796 kb
Host smart-166606e4-472b-4bd2-99e1-837d7ffc4d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588612016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2588612016
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.4169591925
Short name T4
Test name
Test status
Simulation time 18413882670 ps
CPU time 82.28 seconds
Started Jan 21 10:28:03 PM PST 24
Finished Jan 21 10:29:30 PM PST 24
Peak memory 250560 kb
Host smart-7c2c364b-d8a5-4f79-b9e2-43aaa21845ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169591925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.4169591925
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1632696064
Short name T484
Test name
Test status
Simulation time 11586315 ps
CPU time 0.98 seconds
Started Jan 21 10:27:55 PM PST 24
Finished Jan 21 10:28:05 PM PST 24
Peak memory 207964 kb
Host smart-f37f6e93-67e7-4d4d-b409-eb5d97d1f50f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632696064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1632696064
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2953142906
Short name T429
Test name
Test status
Simulation time 52199245 ps
CPU time 1.04 seconds
Started Jan 21 10:28:18 PM PST 24
Finished Jan 21 10:28:21 PM PST 24
Peak memory 208940 kb
Host smart-a8710636-13e3-4a3b-929e-bce19d13d3d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953142906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2953142906
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.66060029
Short name T310
Test name
Test status
Simulation time 868470844 ps
CPU time 10.69 seconds
Started Jan 21 10:28:14 PM PST 24
Finished Jan 21 10:28:27 PM PST 24
Peak memory 217368 kb
Host smart-49d3a008-38a3-4681-a65f-df6ceab971e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66060029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.66060029
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1178238858
Short name T581
Test name
Test status
Simulation time 386311023 ps
CPU time 5.38 seconds
Started Jan 21 10:28:15 PM PST 24
Finished Jan 21 10:28:22 PM PST 24
Peak memory 208908 kb
Host smart-207dfdbc-6ff3-48c7-9086-46d379e51570
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178238858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.1178238858
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.242078204
Short name T650
Test name
Test status
Simulation time 119836610 ps
CPU time 2.41 seconds
Started Jan 21 10:28:13 PM PST 24
Finished Jan 21 10:28:18 PM PST 24
Peak memory 217364 kb
Host smart-c1dc5894-2e23-4221-a84b-483822fa99e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242078204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.242078204
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1845320890
Short name T56
Test name
Test status
Simulation time 740300808 ps
CPU time 14.41 seconds
Started Jan 21 11:42:50 PM PST 24
Finished Jan 21 11:43:05 PM PST 24
Peak memory 218428 kb
Host smart-72ed368a-3267-489a-87ae-d5ef08fee220
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845320890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1845320890
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.404216486
Short name T305
Test name
Test status
Simulation time 368174307 ps
CPU time 13.99 seconds
Started Jan 21 10:28:13 PM PST 24
Finished Jan 21 10:28:29 PM PST 24
Peak memory 217316 kb
Host smart-b5172b08-3c8e-4934-9da1-2c6b25fd8e41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404216486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.404216486
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2215935042
Short name T509
Test name
Test status
Simulation time 5446167123 ps
CPU time 9.47 seconds
Started Jan 21 10:28:12 PM PST 24
Finished Jan 21 10:28:23 PM PST 24
Peak memory 217396 kb
Host smart-fadba98d-a155-43fa-b362-5a9616b34617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215935042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2215935042
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1399568786
Short name T559
Test name
Test status
Simulation time 190469900 ps
CPU time 9.93 seconds
Started Jan 21 10:28:14 PM PST 24
Finished Jan 21 10:28:26 PM PST 24
Peak memory 217360 kb
Host smart-55560dd2-b791-4f37-b2a9-0c786e2a9386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399568786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1399568786
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3394537120
Short name T802
Test name
Test status
Simulation time 602454906 ps
CPU time 6.67 seconds
Started Jan 21 10:28:01 PM PST 24
Finished Jan 21 10:28:13 PM PST 24
Peak memory 213684 kb
Host smart-00b33f7d-932a-4140-8789-611ea02bb1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394537120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3394537120
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3280368240
Short name T690
Test name
Test status
Simulation time 2154463791 ps
CPU time 27.32 seconds
Started Jan 21 10:28:02 PM PST 24
Finished Jan 21 10:28:35 PM PST 24
Peak memory 250356 kb
Host smart-780e4d44-debd-4c92-baee-cc1a404f0830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280368240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3280368240
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3102783793
Short name T657
Test name
Test status
Simulation time 93330232 ps
CPU time 6.19 seconds
Started Jan 21 10:28:01 PM PST 24
Finished Jan 21 10:28:13 PM PST 24
Peak memory 250228 kb
Host smart-8bb51287-97d0-496e-95ad-1cc6dfabf5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102783793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3102783793
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.414644090
Short name T906
Test name
Test status
Simulation time 9298383558 ps
CPU time 245.33 seconds
Started Jan 21 10:28:18 PM PST 24
Finished Jan 21 10:32:25 PM PST 24
Peak memory 279276 kb
Host smart-8807d4f5-914c-41e7-940e-d100af1a696a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414644090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.414644090
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1648623928
Short name T539
Test name
Test status
Simulation time 16431391 ps
CPU time 0.74 seconds
Started Jan 21 10:28:03 PM PST 24
Finished Jan 21 10:28:09 PM PST 24
Peak memory 207464 kb
Host smart-41af3ee6-9d02-46b8-9d67-164b8ecdfa79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648623928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1648623928
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.698673021
Short name T464
Test name
Test status
Simulation time 41855339 ps
CPU time 0.98 seconds
Started Jan 21 10:28:31 PM PST 24
Finished Jan 21 10:28:39 PM PST 24
Peak memory 208900 kb
Host smart-b2b40531-30b5-4802-a9fb-f60b75e9b6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698673021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.698673021
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2384897409
Short name T1
Test name
Test status
Simulation time 829101974 ps
CPU time 12.74 seconds
Started Jan 21 10:28:25 PM PST 24
Finished Jan 21 10:28:41 PM PST 24
Peak memory 217464 kb
Host smart-c7751b4a-8990-4fb6-90e7-6ab17804a2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384897409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2384897409
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.348305394
Short name T10
Test name
Test status
Simulation time 4683185570 ps
CPU time 6.48 seconds
Started Jan 21 10:28:23 PM PST 24
Finished Jan 21 10:28:32 PM PST 24
Peak memory 209080 kb
Host smart-f84e7549-85b7-40f5-bfaf-babeca42d247
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348305394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_ac
cess.348305394
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1320950832
Short name T396
Test name
Test status
Simulation time 103506096 ps
CPU time 2.94 seconds
Started Jan 21 10:28:25 PM PST 24
Finished Jan 21 10:28:31 PM PST 24
Peak memory 217364 kb
Host smart-4ff65d9e-3c9b-4a3f-bf1e-d04b0eea718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320950832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1320950832
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2240156903
Short name T54
Test name
Test status
Simulation time 2702180947 ps
CPU time 11.14 seconds
Started Jan 21 10:28:22 PM PST 24
Finished Jan 21 10:28:36 PM PST 24
Peak memory 217516 kb
Host smart-60f5d544-6326-435a-8f73-3abd69504308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240156903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2240156903
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3014229246
Short name T323
Test name
Test status
Simulation time 340539644 ps
CPU time 13.89 seconds
Started Jan 21 10:28:31 PM PST 24
Finished Jan 21 10:28:52 PM PST 24
Peak memory 217316 kb
Host smart-11567a11-8b13-4129-a50c-590259c68611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014229246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3014229246
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2190933556
Short name T875
Test name
Test status
Simulation time 717452834 ps
CPU time 6.42 seconds
Started Jan 21 10:28:21 PM PST 24
Finished Jan 21 10:28:31 PM PST 24
Peak memory 217380 kb
Host smart-3c541547-ee74-4b1c-ac2b-58063ddcc9b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190933556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2190933556
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3936156729
Short name T493
Test name
Test status
Simulation time 422654549 ps
CPU time 12.54 seconds
Started Jan 21 10:28:26 PM PST 24
Finished Jan 21 10:28:42 PM PST 24
Peak memory 217092 kb
Host smart-67515b92-bccd-4f75-b9d0-3eb9ccc732ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936156729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3936156729
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.384272512
Short name T376
Test name
Test status
Simulation time 138069585 ps
CPU time 3.01 seconds
Started Jan 21 10:28:13 PM PST 24
Finished Jan 21 10:28:18 PM PST 24
Peak memory 213524 kb
Host smart-b315a161-d137-441e-9145-4d5309e66d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384272512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.384272512
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1127002428
Short name T751
Test name
Test status
Simulation time 455054531 ps
CPU time 21.73 seconds
Started Jan 21 10:28:26 PM PST 24
Finished Jan 21 10:28:51 PM PST 24
Peak memory 249164 kb
Host smart-c95e82c3-110c-42ce-8358-88b6dba0d821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127002428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1127002428
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3181443987
Short name T645
Test name
Test status
Simulation time 104310872 ps
CPU time 3.59 seconds
Started Jan 21 10:28:23 PM PST 24
Finished Jan 21 10:28:29 PM PST 24
Peak memory 221204 kb
Host smart-b0554a6f-2beb-4f5a-bdad-a0b4060a5a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181443987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3181443987
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1350939063
Short name T87
Test name
Test status
Simulation time 48329126212 ps
CPU time 98.91 seconds
Started Jan 21 10:28:31 PM PST 24
Finished Jan 21 10:30:18 PM PST 24
Peak memory 225668 kb
Host smart-d38d0f61-279d-4c2e-980c-ce115834e9f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350939063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1350939063
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1182149620
Short name T337
Test name
Test status
Simulation time 33021210 ps
CPU time 0.81 seconds
Started Jan 21 10:28:25 PM PST 24
Finished Jan 21 10:28:29 PM PST 24
Peak memory 207324 kb
Host smart-4c9fb580-c5cc-493a-a355-ace1a534f963
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182149620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1182149620
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1843684126
Short name T26
Test name
Test status
Simulation time 19552327 ps
CPU time 1.18 seconds
Started Jan 21 10:28:32 PM PST 24
Finished Jan 21 10:28:40 PM PST 24
Peak memory 207652 kb
Host smart-c987d4d5-052d-4bfb-bbe2-fde1066bdcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843684126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1843684126
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.89834564
Short name T860
Test name
Test status
Simulation time 425644058 ps
CPU time 17.88 seconds
Started Jan 21 10:28:29 PM PST 24
Finished Jan 21 10:28:51 PM PST 24
Peak memory 217368 kb
Host smart-503ed5a4-056f-4a81-a05e-d992469ee876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89834564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.89834564
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1836000393
Short name T448
Test name
Test status
Simulation time 297682432 ps
CPU time 2.48 seconds
Started Jan 21 10:28:26 PM PST 24
Finished Jan 21 10:28:32 PM PST 24
Peak memory 208868 kb
Host smart-aba0999c-ac5a-4d79-88b4-617ad1f7bb99
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836000393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.1836000393
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1083744315
Short name T744
Test name
Test status
Simulation time 49342315 ps
CPU time 2.01 seconds
Started Jan 21 10:28:26 PM PST 24
Finished Jan 21 10:28:32 PM PST 24
Peak memory 217400 kb
Host smart-8c1e6e79-4471-4640-849a-e077e857ed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083744315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1083744315
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.497693179
Short name T473
Test name
Test status
Simulation time 1424723249 ps
CPU time 11.98 seconds
Started Jan 21 10:28:31 PM PST 24
Finished Jan 21 10:28:51 PM PST 24
Peak memory 218376 kb
Host smart-b96ec589-f805-4ba3-b1bf-c1488a653bc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497693179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.497693179
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.361073821
Short name T753
Test name
Test status
Simulation time 3710270300 ps
CPU time 10.17 seconds
Started Jan 21 10:28:38 PM PST 24
Finished Jan 21 10:28:54 PM PST 24
Peak memory 217460 kb
Host smart-9f715ea3-9902-4b97-b192-58b7d24d6dab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361073821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.361073821
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3543962847
Short name T647
Test name
Test status
Simulation time 368896327 ps
CPU time 13.95 seconds
Started Jan 21 10:28:32 PM PST 24
Finished Jan 21 10:28:54 PM PST 24
Peak memory 217360 kb
Host smart-5d3cd158-7008-4d5b-af62-63e9ea42679e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543962847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3543962847
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3862111188
Short name T593
Test name
Test status
Simulation time 1155973043 ps
CPU time 9.81 seconds
Started Jan 21 10:28:31 PM PST 24
Finished Jan 21 10:28:49 PM PST 24
Peak memory 217348 kb
Host smart-27513887-79f7-4d4a-9451-5dacb6083c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862111188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3862111188
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.502524661
Short name T640
Test name
Test status
Simulation time 53562669 ps
CPU time 1.39 seconds
Started Jan 21 10:28:26 PM PST 24
Finished Jan 21 10:28:32 PM PST 24
Peak memory 212392 kb
Host smart-d50804eb-ca7c-4ea9-a8cb-35c1bfa81121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502524661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.502524661
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.777208575
Short name T394
Test name
Test status
Simulation time 1374550011 ps
CPU time 42.39 seconds
Started Jan 21 10:28:28 PM PST 24
Finished Jan 21 10:29:15 PM PST 24
Peak memory 248520 kb
Host smart-f9a5ab3c-b9c2-446b-a061-e9db2123b8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777208575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.777208575
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2309896144
Short name T553
Test name
Test status
Simulation time 55502373 ps
CPU time 7.33 seconds
Started Jan 21 10:28:31 PM PST 24
Finished Jan 21 10:28:46 PM PST 24
Peak memory 250364 kb
Host smart-6b997de9-e15a-496b-9886-55d64a616139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309896144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2309896144
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.583108414
Short name T578
Test name
Test status
Simulation time 1577855419 ps
CPU time 38.53 seconds
Started Jan 21 10:28:36 PM PST 24
Finished Jan 21 10:29:22 PM PST 24
Peak memory 244396 kb
Host smart-86a5c97b-b829-417c-b4c5-e5c9a0b19c91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583108414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.583108414
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2608466648
Short name T542
Test name
Test status
Simulation time 36569004 ps
CPU time 0.75 seconds
Started Jan 21 10:28:32 PM PST 24
Finished Jan 21 10:28:40 PM PST 24
Peak memory 207448 kb
Host smart-60035b14-dabe-494d-a329-e6a5352fcc39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608466648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2608466648
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2154611739
Short name T702
Test name
Test status
Simulation time 24199895 ps
CPU time 0.99 seconds
Started Jan 21 10:28:40 PM PST 24
Finished Jan 21 10:28:50 PM PST 24
Peak memory 208924 kb
Host smart-57a1bfd5-c4e9-4dd2-b34a-23b61b1cbd28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154611739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2154611739
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1778841533
Short name T546
Test name
Test status
Simulation time 1223791220 ps
CPU time 14.22 seconds
Started Jan 21 10:28:35 PM PST 24
Finished Jan 21 10:28:58 PM PST 24
Peak memory 217296 kb
Host smart-fe1190fc-fb96-4d0a-a5fb-2937ec1026be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778841533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1778841533
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1939705499
Short name T34
Test name
Test status
Simulation time 2946605935 ps
CPU time 7.78 seconds
Started Jan 21 10:28:48 PM PST 24
Finished Jan 21 10:29:02 PM PST 24
Peak memory 208996 kb
Host smart-95edeae1-c023-480e-a8f3-3ef1aaeea967
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939705499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.1939705499
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.4184018001
Short name T752
Test name
Test status
Simulation time 105467512 ps
CPU time 3.33 seconds
Started Jan 21 10:28:34 PM PST 24
Finished Jan 21 10:28:47 PM PST 24
Peak memory 217324 kb
Host smart-8494ad4c-8f72-4c83-9662-817c2f8acae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184018001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4184018001
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2143033395
Short name T500
Test name
Test status
Simulation time 596227437 ps
CPU time 9.85 seconds
Started Jan 21 10:28:41 PM PST 24
Finished Jan 21 10:28:59 PM PST 24
Peak memory 218380 kb
Host smart-a8a1a94e-bae1-4026-8dbe-87ff0b36b25b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143033395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2143033395
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.584565616
Short name T597
Test name
Test status
Simulation time 1000786998 ps
CPU time 13.71 seconds
Started Jan 21 10:28:51 PM PST 24
Finished Jan 21 10:29:10 PM PST 24
Peak memory 217300 kb
Host smart-fcb08b91-a482-484b-ac9a-915079c55b4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584565616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.584565616
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.631813981
Short name T417
Test name
Test status
Simulation time 848983294 ps
CPU time 7 seconds
Started Jan 21 10:28:40 PM PST 24
Finished Jan 21 10:28:56 PM PST 24
Peak memory 217360 kb
Host smart-1bb21b9f-8710-451b-97ff-33eaea7703fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631813981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.631813981
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3071872330
Short name T187
Test name
Test status
Simulation time 1822945730 ps
CPU time 10.24 seconds
Started Jan 21 10:28:34 PM PST 24
Finished Jan 21 10:28:53 PM PST 24
Peak memory 217308 kb
Host smart-53ed08e5-9ddd-4e06-a426-e420bb2feb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071872330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3071872330
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1752616504
Short name T517
Test name
Test status
Simulation time 65552472 ps
CPU time 1.32 seconds
Started Jan 21 10:28:35 PM PST 24
Finished Jan 21 10:28:45 PM PST 24
Peak memory 212288 kb
Host smart-49f049b9-641d-46fd-8bc0-88169c69d803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752616504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1752616504
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2715064700
Short name T573
Test name
Test status
Simulation time 970201260 ps
CPU time 32.53 seconds
Started Jan 21 10:28:35 PM PST 24
Finished Jan 21 10:29:16 PM PST 24
Peak memory 250384 kb
Host smart-4f4c9594-51bc-4782-a284-105270ae2d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715064700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2715064700
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.964459135
Short name T972
Test name
Test status
Simulation time 696314842 ps
CPU time 7.39 seconds
Started Jan 21 10:28:34 PM PST 24
Finished Jan 21 10:28:50 PM PST 24
Peak memory 250400 kb
Host smart-fe82652e-65b2-4a7d-976f-4cf563c5e28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964459135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.964459135
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2303558142
Short name T425
Test name
Test status
Simulation time 19347601545 ps
CPU time 56.94 seconds
Started Jan 21 10:28:41 PM PST 24
Finished Jan 21 10:29:47 PM PST 24
Peak memory 250568 kb
Host smart-c0ef9290-f6b6-49c5-ae48-b8c82026a954
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303558142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2303558142
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1114969918
Short name T634
Test name
Test status
Simulation time 14903995 ps
CPU time 1.01 seconds
Started Jan 21 10:28:36 PM PST 24
Finished Jan 21 10:28:45 PM PST 24
Peak memory 210580 kb
Host smart-680a4a0c-ac8f-4f50-bf48-39c6c75884bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114969918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1114969918
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3347822997
Short name T409
Test name
Test status
Simulation time 265811174 ps
CPU time 1.02 seconds
Started Jan 21 10:22:11 PM PST 24
Finished Jan 21 10:22:16 PM PST 24
Peak memory 208972 kb
Host smart-930ec2fd-2648-43aa-979b-3fb1cfbaf0d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347822997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3347822997
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2807395943
Short name T787
Test name
Test status
Simulation time 12142933 ps
CPU time 0.98 seconds
Started Jan 21 10:22:19 PM PST 24
Finished Jan 21 10:22:30 PM PST 24
Peak memory 208836 kb
Host smart-77726566-4c9c-4932-b420-f03b6c58d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807395943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2807395943
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3149928697
Short name T795
Test name
Test status
Simulation time 296739673 ps
CPU time 12.3 seconds
Started Jan 21 10:22:22 PM PST 24
Finished Jan 21 10:22:45 PM PST 24
Peak memory 216720 kb
Host smart-adac13e5-3e30-4e70-8c94-aa112ac3cb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149928697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3149928697
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.120984634
Short name T748
Test name
Test status
Simulation time 361091453 ps
CPU time 6.4 seconds
Started Jan 21 10:22:12 PM PST 24
Finished Jan 21 10:22:22 PM PST 24
Peak memory 208900 kb
Host smart-de3454cc-65ae-4e2d-8fa5-3a93aac11fff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120984634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_acc
ess.120984634
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2129530272
Short name T953
Test name
Test status
Simulation time 9512573100 ps
CPU time 66.02 seconds
Started Jan 21 10:22:19 PM PST 24
Finished Jan 21 10:23:35 PM PST 24
Peak memory 217516 kb
Host smart-77c4c3b8-b2de-4a46-aed6-929fd9d9e0ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129530272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2129530272
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3918617085
Short name T357
Test name
Test status
Simulation time 227410187 ps
CPU time 2.75 seconds
Started Jan 21 10:22:21 PM PST 24
Finished Jan 21 10:22:35 PM PST 24
Peak memory 209004 kb
Host smart-ae203c85-1de9-41b3-a5b6-e59883dc62e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918617085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.3918617085
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1469667698
Short name T852
Test name
Test status
Simulation time 4415926579 ps
CPU time 21.32 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:39 PM PST 24
Peak memory 217576 kb
Host smart-ed9201c2-1133-49e0-b7ba-4911380cf25f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469667698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1469667698
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.590722398
Short name T917
Test name
Test status
Simulation time 908799378 ps
CPU time 28.2 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:45 PM PST 24
Peak memory 212352 kb
Host smart-fc0aa580-0ba4-4373-8bee-39f1e3c9ae0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590722398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.590722398
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2927463262
Short name T371
Test name
Test status
Simulation time 571795304 ps
CPU time 4.51 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:22 PM PST 24
Peak memory 212104 kb
Host smart-fa70466b-b2cb-40a0-8ceb-672a064af2d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927463262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2927463262
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3642341375
Short name T612
Test name
Test status
Simulation time 7487472275 ps
CPU time 73.57 seconds
Started Jan 21 10:22:12 PM PST 24
Finished Jan 21 10:23:29 PM PST 24
Peak memory 271684 kb
Host smart-e8a8f6ec-bf5e-4cfd-9b47-d123f035e5bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642341375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3642341375
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.721927111
Short name T309
Test name
Test status
Simulation time 2913643542 ps
CPU time 6.76 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:25 PM PST 24
Peak memory 221940 kb
Host smart-61356e51-feca-4fd1-9a32-5501674380cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721927111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.721927111
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.943442613
Short name T981
Test name
Test status
Simulation time 149395336 ps
CPU time 3.76 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:21 PM PST 24
Peak memory 217384 kb
Host smart-bc96dd25-3ff7-4906-8d78-744e24d34975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943442613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.943442613
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1169713438
Short name T623
Test name
Test status
Simulation time 552881908 ps
CPU time 6.96 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:24 PM PST 24
Peak memory 221472 kb
Host smart-9081deb0-3cb4-4554-9ca0-913e027e55ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169713438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1169713438
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1049814380
Short name T104
Test name
Test status
Simulation time 1136719113 ps
CPU time 37.67 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:55 PM PST 24
Peak memory 284020 kb
Host smart-3374ca69-f899-4129-b66d-2dfd225dbf2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049814380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1049814380
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1804279846
Short name T669
Test name
Test status
Simulation time 1423786802 ps
CPU time 11.04 seconds
Started Jan 21 10:22:12 PM PST 24
Finished Jan 21 10:22:27 PM PST 24
Peak memory 218352 kb
Host smart-22f04cca-9973-403a-a8fa-ee7eefa925d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804279846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1804279846
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.653606348
Short name T932
Test name
Test status
Simulation time 286891384 ps
CPU time 13.69 seconds
Started Jan 21 10:22:19 PM PST 24
Finished Jan 21 10:22:42 PM PST 24
Peak memory 217364 kb
Host smart-d16c4945-3ea7-4837-bcba-2d8f752d1c12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653606348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.653606348
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1057199309
Short name T892
Test name
Test status
Simulation time 621350062 ps
CPU time 8.21 seconds
Started Jan 21 10:22:14 PM PST 24
Finished Jan 21 10:22:27 PM PST 24
Peak memory 217368 kb
Host smart-e752329e-27ef-4a0c-a216-de3d369989ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057199309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
057199309
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1066125729
Short name T703
Test name
Test status
Simulation time 480491088 ps
CPU time 7.61 seconds
Started Jan 21 10:22:19 PM PST 24
Finished Jan 21 10:22:37 PM PST 24
Peak memory 217360 kb
Host smart-4dac4256-5a81-4c24-8915-346c638cc0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066125729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1066125729
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1923398338
Short name T433
Test name
Test status
Simulation time 36413461 ps
CPU time 2.46 seconds
Started Jan 21 10:22:12 PM PST 24
Finished Jan 21 10:22:18 PM PST 24
Peak memory 213348 kb
Host smart-d02495f0-0e4f-4d1f-a3e7-8b515bc14cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923398338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1923398338
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3633958540
Short name T406
Test name
Test status
Simulation time 414684442 ps
CPU time 22.63 seconds
Started Jan 21 10:22:12 PM PST 24
Finished Jan 21 10:22:38 PM PST 24
Peak memory 244120 kb
Host smart-04b4aa2f-2d21-4d48-8886-fe2558deb54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633958540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3633958540
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2896667693
Short name T345
Test name
Test status
Simulation time 170615839 ps
CPU time 9.01 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:26 PM PST 24
Peak memory 249144 kb
Host smart-148be77a-4e57-414a-b7ce-f45ae6873edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896667693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2896667693
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1362980024
Short name T389
Test name
Test status
Simulation time 8807009630 ps
CPU time 296.75 seconds
Started Jan 21 10:22:15 PM PST 24
Finished Jan 21 10:27:17 PM PST 24
Peak memory 250548 kb
Host smart-9a55e4f4-7a5d-48f9-a797-7b0332c42d77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362980024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1362980024
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4026555826
Short name T459
Test name
Test status
Simulation time 17010387 ps
CPU time 0.86 seconds
Started Jan 21 10:22:13 PM PST 24
Finished Jan 21 10:22:18 PM PST 24
Peak memory 207248 kb
Host smart-84a31f59-4b5b-42d3-ae9e-dd3dfca8097d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026555826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4026555826
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1553818537
Short name T874
Test name
Test status
Simulation time 60296964 ps
CPU time 0.99 seconds
Started Jan 21 10:28:54 PM PST 24
Finished Jan 21 10:29:00 PM PST 24
Peak memory 208948 kb
Host smart-06755327-563d-45de-801f-74a5b3b924be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553818537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1553818537
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2906373242
Short name T922
Test name
Test status
Simulation time 1122264279 ps
CPU time 18.13 seconds
Started Jan 21 10:28:51 PM PST 24
Finished Jan 21 10:29:14 PM PST 24
Peak memory 217264 kb
Host smart-76f8a611-f2de-408d-ae3f-0e3d16bb2d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906373242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2906373242
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3379597214
Short name T466
Test name
Test status
Simulation time 283391902 ps
CPU time 4.44 seconds
Started Jan 21 10:28:51 PM PST 24
Finished Jan 21 10:29:01 PM PST 24
Peak memory 208952 kb
Host smart-ef082038-b4de-44fa-b525-a03cdb34d871
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379597214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.3379597214
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1785438802
Short name T458
Test name
Test status
Simulation time 73372015 ps
CPU time 3.82 seconds
Started Jan 21 10:28:48 PM PST 24
Finished Jan 21 10:28:58 PM PST 24
Peak memory 217292 kb
Host smart-ee37fd17-23eb-44db-90af-644e73b1808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785438802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1785438802
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2263621887
Short name T895
Test name
Test status
Simulation time 4072994658 ps
CPU time 12.06 seconds
Started Jan 21 10:28:51 PM PST 24
Finished Jan 21 10:29:09 PM PST 24
Peak memory 218764 kb
Host smart-1b0e042f-58a4-49e8-ab4e-01a911602270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263621887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2263621887
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.4264052780
Short name T639
Test name
Test status
Simulation time 1478545490 ps
CPU time 19.69 seconds
Started Jan 21 10:28:50 PM PST 24
Finished Jan 21 10:29:16 PM PST 24
Peak memory 217332 kb
Host smart-8a580cfd-4d95-4e10-b51a-3ad98e561f3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264052780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.4264052780
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2464348051
Short name T732
Test name
Test status
Simulation time 495176948 ps
CPU time 11.42 seconds
Started Jan 21 10:28:55 PM PST 24
Finished Jan 21 10:29:10 PM PST 24
Peak memory 217368 kb
Host smart-bc631168-da35-4238-a510-66b8c8ee817e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464348051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2464348051
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.4228225805
Short name T700
Test name
Test status
Simulation time 560845194 ps
CPU time 7.72 seconds
Started Jan 21 10:28:50 PM PST 24
Finished Jan 21 10:29:04 PM PST 24
Peak memory 217328 kb
Host smart-767d0c1d-b532-46bd-9674-e00e936cca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228225805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.4228225805
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3602538225
Short name T615
Test name
Test status
Simulation time 244603032 ps
CPU time 2.94 seconds
Started Jan 21 10:28:48 PM PST 24
Finished Jan 21 10:28:57 PM PST 24
Peak memory 213496 kb
Host smart-adc5023f-61d8-4729-a9b6-e180dd510470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602538225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3602538225
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2025406365
Short name T756
Test name
Test status
Simulation time 813214131 ps
CPU time 23.62 seconds
Started Jan 21 10:28:51 PM PST 24
Finished Jan 21 10:29:20 PM PST 24
Peak memory 250288 kb
Host smart-7b07eb9f-58a2-4f87-8e15-6eeb2282b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025406365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2025406365
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1222517961
Short name T447
Test name
Test status
Simulation time 834499542 ps
CPU time 11.99 seconds
Started Jan 21 10:28:45 PM PST 24
Finished Jan 21 10:29:05 PM PST 24
Peak memory 250412 kb
Host smart-4b143aca-607d-4f72-8f5a-3a9e1d661e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222517961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1222517961
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3313831597
Short name T798
Test name
Test status
Simulation time 2866502278 ps
CPU time 97.26 seconds
Started Jan 21 10:28:53 PM PST 24
Finished Jan 21 10:30:35 PM PST 24
Peak memory 273728 kb
Host smart-49ebb883-bb84-43cc-a72f-1357c4f4f7ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313831597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3313831597
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3711253916
Short name T889
Test name
Test status
Simulation time 20746272 ps
CPU time 0.78 seconds
Started Jan 21 10:28:42 PM PST 24
Finished Jan 21 10:28:52 PM PST 24
Peak memory 207332 kb
Host smart-cb491d03-125e-4f5d-8e6c-e75dbfa36e21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711253916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3711253916
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3572958439
Short name T540
Test name
Test status
Simulation time 19755092 ps
CPU time 1.16 seconds
Started Jan 21 10:29:01 PM PST 24
Finished Jan 21 10:29:13 PM PST 24
Peak memory 207644 kb
Host smart-29aafa9b-2910-4932-bef2-c29f470b1697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572958439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3572958439
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3026345671
Short name T882
Test name
Test status
Simulation time 249517813 ps
CPU time 13.11 seconds
Started Jan 21 10:28:57 PM PST 24
Finished Jan 21 10:29:18 PM PST 24
Peak memory 217340 kb
Host smart-351fcbbd-2f50-4ec4-984e-35f412a7010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026345671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3026345671
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2032376269
Short name T705
Test name
Test status
Simulation time 1383920805 ps
CPU time 4.17 seconds
Started Jan 21 10:29:01 PM PST 24
Finished Jan 21 10:29:16 PM PST 24
Peak memory 208956 kb
Host smart-394de3fb-7551-459c-8e2e-95128f1a0e97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032376269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.2032376269
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2675367502
Short name T65
Test name
Test status
Simulation time 153468739 ps
CPU time 3.79 seconds
Started Jan 21 10:28:57 PM PST 24
Finished Jan 21 10:29:10 PM PST 24
Peak memory 217372 kb
Host smart-78a6a981-2f6c-4b09-bbfd-d6ca2d7e8351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675367502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2675367502
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2648851748
Short name T833
Test name
Test status
Simulation time 2153746536 ps
CPU time 10.29 seconds
Started Jan 21 10:28:58 PM PST 24
Finished Jan 21 10:29:18 PM PST 24
Peak memory 217756 kb
Host smart-d9c36d42-1716-4a8f-a69f-9e038ad7fa67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648851748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2648851748
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.4025652181
Short name T502
Test name
Test status
Simulation time 373992687 ps
CPU time 10.47 seconds
Started Jan 21 10:28:57 PM PST 24
Finished Jan 21 10:29:16 PM PST 24
Peak memory 217260 kb
Host smart-8f9a6428-ce13-4f75-b6a0-df149cb16a97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025652181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.4025652181
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1356501589
Short name T470
Test name
Test status
Simulation time 1031412671 ps
CPU time 11.35 seconds
Started Jan 21 10:28:59 PM PST 24
Finished Jan 21 10:29:20 PM PST 24
Peak memory 217372 kb
Host smart-94ef4d7e-797a-4cd8-b828-9a2b8193ecc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356501589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1356501589
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2568199812
Short name T400
Test name
Test status
Simulation time 1227865783 ps
CPU time 10.73 seconds
Started Jan 21 10:28:59 PM PST 24
Finished Jan 21 10:29:19 PM PST 24
Peak memory 217376 kb
Host smart-54507b0e-7d2c-4654-ace2-6076fde639a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568199812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2568199812
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3369269014
Short name T83
Test name
Test status
Simulation time 527387929 ps
CPU time 3.76 seconds
Started Jan 21 10:28:52 PM PST 24
Finished Jan 21 10:29:01 PM PST 24
Peak memory 212536 kb
Host smart-5b2e294d-4593-4b0e-a550-8cba63c0c377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369269014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3369269014
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3168133526
Short name T318
Test name
Test status
Simulation time 271654132 ps
CPU time 26.4 seconds
Started Jan 21 10:28:50 PM PST 24
Finished Jan 21 10:29:22 PM PST 24
Peak memory 250304 kb
Host smart-33a0546a-8078-4e64-844d-14024140cf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168133526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3168133526
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2653893885
Short name T488
Test name
Test status
Simulation time 235297469 ps
CPU time 3.59 seconds
Started Jan 21 10:28:59 PM PST 24
Finished Jan 21 10:29:12 PM PST 24
Peak memory 217360 kb
Host smart-eebc1d98-0e58-40b3-9e63-528c2aa922ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653893885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2653893885
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1202776347
Short name T779
Test name
Test status
Simulation time 15013515014 ps
CPU time 491.27 seconds
Started Jan 21 10:29:04 PM PST 24
Finished Jan 21 10:37:28 PM PST 24
Peak memory 250708 kb
Host smart-07ba1b69-c566-4463-bf7b-6637ccdc9faa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202776347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1202776347
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4084278247
Short name T596
Test name
Test status
Simulation time 78486907 ps
CPU time 0.77 seconds
Started Jan 21 10:28:52 PM PST 24
Finished Jan 21 10:28:58 PM PST 24
Peak memory 205864 kb
Host smart-09eee4df-6c93-4c79-922d-a44cc283ceca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084278247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4084278247
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1488607524
Short name T774
Test name
Test status
Simulation time 19187208 ps
CPU time 0.89 seconds
Started Jan 21 10:29:07 PM PST 24
Finished Jan 21 10:29:20 PM PST 24
Peak memory 208928 kb
Host smart-a267966e-8e69-4a1d-984a-00ac585935fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488607524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1488607524
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2730620824
Short name T525
Test name
Test status
Simulation time 368265503 ps
CPU time 12.6 seconds
Started Jan 21 10:29:03 PM PST 24
Finished Jan 21 10:29:28 PM PST 24
Peak memory 217336 kb
Host smart-7ccddc10-e089-43ca-b6fb-5217282d1492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730620824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2730620824
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2580691929
Short name T720
Test name
Test status
Simulation time 107440741 ps
CPU time 2.2 seconds
Started Jan 21 10:28:59 PM PST 24
Finished Jan 21 10:29:12 PM PST 24
Peak memory 208980 kb
Host smart-252cc236-9310-40f6-9966-907b4bdbf828
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580691929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.2580691929
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1135328381
Short name T316
Test name
Test status
Simulation time 210383449 ps
CPU time 2.7 seconds
Started Jan 21 10:29:06 PM PST 24
Finished Jan 21 10:29:21 PM PST 24
Peak memory 217364 kb
Host smart-6a1d9855-486c-4baa-a192-788ac05ab6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135328381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1135328381
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1693355255
Short name T864
Test name
Test status
Simulation time 1309766169 ps
CPU time 8.82 seconds
Started Jan 21 10:29:16 PM PST 24
Finished Jan 21 10:29:35 PM PST 24
Peak memory 217324 kb
Host smart-9dcf9cf4-5246-4924-aded-c0117d1281c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693355255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1693355255
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.636125928
Short name T773
Test name
Test status
Simulation time 1971462135 ps
CPU time 11.6 seconds
Started Jan 21 10:29:21 PM PST 24
Finished Jan 21 10:29:44 PM PST 24
Peak memory 217324 kb
Host smart-8a6587cb-3622-473a-83df-66cf46ee2716
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636125928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.636125928
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1002688948
Short name T341
Test name
Test status
Simulation time 680732551 ps
CPU time 8.35 seconds
Started Jan 21 10:29:03 PM PST 24
Finished Jan 21 10:29:24 PM PST 24
Peak memory 217344 kb
Host smart-a9692e54-7747-4c9a-b1aa-c72b3c916c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002688948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1002688948
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1797640253
Short name T494
Test name
Test status
Simulation time 153117655 ps
CPU time 6.83 seconds
Started Jan 21 10:29:02 PM PST 24
Finished Jan 21 10:29:20 PM PST 24
Peak memory 212876 kb
Host smart-7db9ac83-4eec-4b18-8791-e5309f334295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797640253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1797640253
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3133856505
Short name T439
Test name
Test status
Simulation time 563078156 ps
CPU time 25.68 seconds
Started Jan 21 10:29:05 PM PST 24
Finished Jan 21 10:29:43 PM PST 24
Peak memory 250384 kb
Host smart-c52692de-ba0b-4274-8d12-f84b8eb361de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133856505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3133856505
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3088406911
Short name T503
Test name
Test status
Simulation time 240173669 ps
CPU time 11.3 seconds
Started Jan 21 10:29:00 PM PST 24
Finished Jan 21 10:29:23 PM PST 24
Peak memory 250172 kb
Host smart-0dbfb411-9328-44f2-990d-bd3a2a0b8d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088406911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3088406911
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2470335834
Short name T684
Test name
Test status
Simulation time 20034854798 ps
CPU time 79.37 seconds
Started Jan 21 10:29:17 PM PST 24
Finished Jan 21 10:30:47 PM PST 24
Peak memory 250496 kb
Host smart-657b9ef1-537c-42f0-abac-5809f06a7e3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470335834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2470335834
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.809148040
Short name T430
Test name
Test status
Simulation time 38305829 ps
CPU time 0.75 seconds
Started Jan 21 10:29:02 PM PST 24
Finished Jan 21 10:29:16 PM PST 24
Peak memory 207180 kb
Host smart-0f84974c-2fe0-448c-965a-5b2b5032aa50
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809148040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.809148040
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3714979673
Short name T606
Test name
Test status
Simulation time 19961990 ps
CPU time 1.18 seconds
Started Jan 21 10:29:11 PM PST 24
Finished Jan 21 10:29:24 PM PST 24
Peak memory 208852 kb
Host smart-ad7269f8-eafe-4f66-9120-990d28e0c62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714979673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3714979673
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.814421664
Short name T59
Test name
Test status
Simulation time 1753625973 ps
CPU time 13.23 seconds
Started Jan 21 10:29:12 PM PST 24
Finished Jan 21 10:29:36 PM PST 24
Peak memory 217304 kb
Host smart-197a1fa7-46c6-422c-9cd3-164aa34da0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814421664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.814421664
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.758565567
Short name T30
Test name
Test status
Simulation time 2894866674 ps
CPU time 6.87 seconds
Started Jan 21 10:29:13 PM PST 24
Finished Jan 21 10:29:30 PM PST 24
Peak memory 209052 kb
Host smart-eb50c1c6-6926-40a2-b4b4-90c6338ab00c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758565567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_ac
cess.758565567
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2514886827
Short name T670
Test name
Test status
Simulation time 299624185 ps
CPU time 2.25 seconds
Started Jan 21 10:29:03 PM PST 24
Finished Jan 21 10:29:19 PM PST 24
Peak memory 217356 kb
Host smart-80455b66-2951-4b1c-849c-1ad4863a3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514886827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2514886827
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.854109503
Short name T962
Test name
Test status
Simulation time 369319832 ps
CPU time 18.99 seconds
Started Jan 21 10:29:16 PM PST 24
Finished Jan 21 10:29:45 PM PST 24
Peak memory 218328 kb
Host smart-108cd342-6994-42a2-8eb7-ec5748a59927
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854109503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.854109503
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2233054075
Short name T758
Test name
Test status
Simulation time 576073899 ps
CPU time 21.37 seconds
Started Jan 21 10:29:10 PM PST 24
Finished Jan 21 10:29:43 PM PST 24
Peak memory 217380 kb
Host smart-8045fab5-46b3-45dd-a041-12b933187366
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233054075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2233054075
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2951008962
Short name T66
Test name
Test status
Simulation time 1067044636 ps
CPU time 6.92 seconds
Started Jan 21 10:29:13 PM PST 24
Finished Jan 21 10:29:30 PM PST 24
Peak memory 217368 kb
Host smart-bb1308c2-0a11-4114-a174-76345a13e333
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951008962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2951008962
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1787774134
Short name T832
Test name
Test status
Simulation time 296880873 ps
CPU time 10.1 seconds
Started Jan 21 10:29:09 PM PST 24
Finished Jan 21 10:29:31 PM PST 24
Peak memory 217292 kb
Host smart-48c6fcbc-6f66-4884-8683-ae9bf538b886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787774134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1787774134
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3244694488
Short name T381
Test name
Test status
Simulation time 66826570 ps
CPU time 3.66 seconds
Started Jan 21 10:29:08 PM PST 24
Finished Jan 21 10:29:24 PM PST 24
Peak memory 213484 kb
Host smart-57797520-3ca6-4f76-81e8-56c9af305111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244694488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3244694488
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4262031888
Short name T652
Test name
Test status
Simulation time 294699526 ps
CPU time 22.32 seconds
Started Jan 21 10:29:05 PM PST 24
Finished Jan 21 10:29:40 PM PST 24
Peak memory 244372 kb
Host smart-d8bd7692-a960-486e-bcb6-c1306a57f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262031888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4262031888
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2066769656
Short name T387
Test name
Test status
Simulation time 81597351 ps
CPU time 6.79 seconds
Started Jan 21 10:29:17 PM PST 24
Finished Jan 21 10:29:34 PM PST 24
Peak memory 245732 kb
Host smart-ae747554-2e0c-4fad-98b8-e004c46e0f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066769656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2066769656
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2370568058
Short name T949
Test name
Test status
Simulation time 4198809208 ps
CPU time 139.52 seconds
Started Jan 21 10:29:13 PM PST 24
Finished Jan 21 10:31:43 PM PST 24
Peak memory 250404 kb
Host smart-9384cdf8-2a86-48fd-ae62-e31eda8d0149
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370568058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2370568058
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2459810616
Short name T894
Test name
Test status
Simulation time 47422925 ps
CPU time 1.04 seconds
Started Jan 21 10:29:07 PM PST 24
Finished Jan 21 10:29:20 PM PST 24
Peak memory 211808 kb
Host smart-1a4dbd31-6d20-4628-864c-7a8ec64bb7ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459810616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2459810616
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3695344360
Short name T478
Test name
Test status
Simulation time 17862928 ps
CPU time 1.13 seconds
Started Jan 21 10:29:31 PM PST 24
Finished Jan 21 10:29:38 PM PST 24
Peak memory 208944 kb
Host smart-4e0e58b7-cf02-4115-83a8-e0fa912b25d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695344360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3695344360
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2514508487
Short name T311
Test name
Test status
Simulation time 1270874182 ps
CPU time 13.24 seconds
Started Jan 21 10:29:25 PM PST 24
Finished Jan 21 10:29:48 PM PST 24
Peak memory 217328 kb
Host smart-86348725-86c5-4f45-80e9-744e9ca07370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514508487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2514508487
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3915983580
Short name T558
Test name
Test status
Simulation time 964255970 ps
CPU time 6.46 seconds
Started Jan 21 10:29:22 PM PST 24
Finished Jan 21 10:29:40 PM PST 24
Peak memory 208956 kb
Host smart-b02e0407-1ad7-45e8-8a36-f7be73934390
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915983580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.3915983580
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2340943911
Short name T839
Test name
Test status
Simulation time 510566711 ps
CPU time 3.66 seconds
Started Jan 21 10:29:18 PM PST 24
Finished Jan 21 10:29:32 PM PST 24
Peak memory 217364 kb
Host smart-a032afde-e242-45e2-8fcd-75aac4bf7a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340943911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2340943911
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.4080918960
Short name T441
Test name
Test status
Simulation time 927425623 ps
CPU time 8.32 seconds
Started Jan 21 10:29:23 PM PST 24
Finished Jan 21 10:29:42 PM PST 24
Peak memory 217332 kb
Host smart-471dd4b6-69b3-4e84-ae3c-d8b2ef25db48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080918960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4080918960
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.145764780
Short name T636
Test name
Test status
Simulation time 1045131856 ps
CPU time 6.48 seconds
Started Jan 21 10:29:20 PM PST 24
Finished Jan 21 10:29:38 PM PST 24
Peak memory 217456 kb
Host smart-0ac2c3a7-82c6-498b-bdfe-80fab3ebc8e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145764780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.145764780
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1861946961
Short name T707
Test name
Test status
Simulation time 1182494807 ps
CPU time 19.8 seconds
Started Jan 21 10:29:18 PM PST 24
Finished Jan 21 10:29:49 PM PST 24
Peak memory 217276 kb
Host smart-83dd3044-7f29-492a-960b-0b562322f971
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861946961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1861946961
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1299786278
Short name T322
Test name
Test status
Simulation time 5315564397 ps
CPU time 12.42 seconds
Started Jan 21 10:29:17 PM PST 24
Finished Jan 21 10:29:40 PM PST 24
Peak memory 217484 kb
Host smart-4d30d65a-947b-47c5-8412-2cd28fdc0e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299786278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1299786278
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2873573728
Short name T452
Test name
Test status
Simulation time 95271905 ps
CPU time 1.97 seconds
Started Jan 21 10:29:10 PM PST 24
Finished Jan 21 10:29:24 PM PST 24
Peak memory 212872 kb
Host smart-74478129-165e-438e-ae14-89f15d0981a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873573728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2873573728
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.4140052299
Short name T16
Test name
Test status
Simulation time 930769829 ps
CPU time 16.28 seconds
Started Jan 21 10:29:19 PM PST 24
Finished Jan 21 10:29:46 PM PST 24
Peak memory 250292 kb
Host smart-b757d509-817a-4f22-8632-a0eeb7431357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140052299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.4140052299
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3027350445
Short name T870
Test name
Test status
Simulation time 121065989 ps
CPU time 3.74 seconds
Started Jan 21 10:29:17 PM PST 24
Finished Jan 21 10:29:31 PM PST 24
Peak memory 221420 kb
Host smart-7ce011bd-7091-4bf2-99b1-d5b907bfea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027350445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3027350445
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2311415807
Short name T969
Test name
Test status
Simulation time 7058548353 ps
CPU time 257.72 seconds
Started Jan 21 10:29:18 PM PST 24
Finished Jan 21 10:33:46 PM PST 24
Peak memory 279812 kb
Host smart-7faccf4a-d90a-4c7b-aa68-b78af9ea51d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311415807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2311415807
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3946591455
Short name T125
Test name
Test status
Simulation time 72213530610 ps
CPU time 452.63 seconds
Started Jan 21 10:29:17 PM PST 24
Finished Jan 21 10:37:00 PM PST 24
Peak memory 332512 kb
Host smart-0bc8d22b-b962-47e7-8ec8-ec5d0517f9d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3946591455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3946591455
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4060371751
Short name T884
Test name
Test status
Simulation time 112189566 ps
CPU time 0.82 seconds
Started Jan 21 10:29:11 PM PST 24
Finished Jan 21 10:29:23 PM PST 24
Peak memory 207468 kb
Host smart-d847d087-bd32-42b4-8a13-67a9ce3ff8d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060371751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.4060371751
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2829089286
Short name T453
Test name
Test status
Simulation time 47749584 ps
CPU time 1.02 seconds
Started Jan 21 10:29:33 PM PST 24
Finished Jan 21 10:29:38 PM PST 24
Peak memory 208956 kb
Host smart-4e95171c-9f20-43b3-8ee7-1468b33b607f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829089286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2829089286
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1276009462
Short name T893
Test name
Test status
Simulation time 1105669400 ps
CPU time 12.06 seconds
Started Jan 21 10:29:26 PM PST 24
Finished Jan 21 10:29:47 PM PST 24
Peak memory 217268 kb
Host smart-093cc34f-95a3-4a94-aa6c-5e182e6aa555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276009462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1276009462
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3068246904
Short name T680
Test name
Test status
Simulation time 222142002 ps
CPU time 6.52 seconds
Started Jan 21 10:29:35 PM PST 24
Finished Jan 21 10:29:45 PM PST 24
Peak memory 208856 kb
Host smart-02a2c256-8389-439b-a6f9-2306fe716e9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068246904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.3068246904
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.318722036
Short name T401
Test name
Test status
Simulation time 1102074480 ps
CPU time 3.86 seconds
Started Jan 21 10:29:33 PM PST 24
Finished Jan 21 10:29:41 PM PST 24
Peak memory 217324 kb
Host smart-0b7915fc-8682-464b-ac55-031ed8555808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318722036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.318722036
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.957805758
Short name T567
Test name
Test status
Simulation time 253676553 ps
CPU time 8.7 seconds
Started Jan 21 10:29:35 PM PST 24
Finished Jan 21 10:29:47 PM PST 24
Peak memory 217388 kb
Host smart-e7a246fa-e2f3-4967-9601-bae79db64d46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957805758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.957805758
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2745605896
Short name T696
Test name
Test status
Simulation time 320082575 ps
CPU time 7.16 seconds
Started Jan 21 11:40:50 PM PST 24
Finished Jan 21 11:40:58 PM PST 24
Peak memory 217408 kb
Host smart-610074c4-3600-4d78-8042-0ff4c18a7779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745605896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2745605896
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3133226905
Short name T796
Test name
Test status
Simulation time 265834523 ps
CPU time 10 seconds
Started Jan 21 10:29:37 PM PST 24
Finished Jan 21 10:29:49 PM PST 24
Peak memory 217364 kb
Host smart-8e649746-b38c-4fac-94fe-6dabb8def0ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133226905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3133226905
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.717983819
Short name T339
Test name
Test status
Simulation time 842358710 ps
CPU time 15.36 seconds
Started Jan 21 11:20:09 PM PST 24
Finished Jan 21 11:20:26 PM PST 24
Peak memory 217412 kb
Host smart-3012b978-efd1-43ab-8417-7353b913b14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717983819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.717983819
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1459634593
Short name T709
Test name
Test status
Simulation time 145582591 ps
CPU time 2.92 seconds
Started Jan 21 10:29:33 PM PST 24
Finished Jan 21 10:29:40 PM PST 24
Peak memory 212944 kb
Host smart-e344b12f-142c-4bd5-829b-c64f79ad868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459634593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1459634593
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4167044372
Short name T361
Test name
Test status
Simulation time 1486911966 ps
CPU time 31.95 seconds
Started Jan 21 10:29:33 PM PST 24
Finished Jan 21 10:30:09 PM PST 24
Peak memory 250284 kb
Host smart-3e653034-364b-468c-acc7-638ad62833ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167044372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4167044372
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.530054989
Short name T931
Test name
Test status
Simulation time 178965560 ps
CPU time 7.49 seconds
Started Jan 21 10:29:29 PM PST 24
Finished Jan 21 10:29:43 PM PST 24
Peak memory 250324 kb
Host smart-d7050bf9-f6dd-403d-8dd4-89629a091b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530054989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.530054989
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2099781184
Short name T450
Test name
Test status
Simulation time 43822237 ps
CPU time 0.73 seconds
Started Jan 21 10:29:29 PM PST 24
Finished Jan 21 10:29:37 PM PST 24
Peak memory 207268 kb
Host smart-7a65f0b9-1f39-46f2-ab62-b4f191d3a4ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099781184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2099781184
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3752239912
Short name T588
Test name
Test status
Simulation time 72293018 ps
CPU time 1.12 seconds
Started Jan 21 10:45:29 PM PST 24
Finished Jan 21 10:45:34 PM PST 24
Peak memory 208940 kb
Host smart-6f03fb7b-c699-4f3e-9534-7bc9f716737b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752239912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3752239912
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.919737395
Short name T18
Test name
Test status
Simulation time 1081121387 ps
CPU time 17.24 seconds
Started Jan 21 10:29:49 PM PST 24
Finished Jan 21 10:30:08 PM PST 24
Peak memory 216588 kb
Host smart-225d9c20-096d-40bf-8db6-e9acc9b21956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919737395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.919737395
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.224890510
Short name T765
Test name
Test status
Simulation time 1843096355 ps
CPU time 12.29 seconds
Started Jan 21 10:29:43 PM PST 24
Finished Jan 21 10:29:58 PM PST 24
Peak memory 208984 kb
Host smart-9be0301e-6b02-451f-8b95-07da572aa36d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224890510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_ac
cess.224890510
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2370872194
Short name T777
Test name
Test status
Simulation time 398069715 ps
CPU time 4.79 seconds
Started Jan 21 10:29:40 PM PST 24
Finished Jan 21 10:29:47 PM PST 24
Peak memory 217360 kb
Host smart-14a96667-615e-4f44-87dc-f41c8f9e9214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370872194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2370872194
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3893148951
Short name T374
Test name
Test status
Simulation time 399875244 ps
CPU time 12.21 seconds
Started Jan 21 10:29:49 PM PST 24
Finished Jan 21 10:30:03 PM PST 24
Peak memory 217324 kb
Host smart-4635375d-f684-47d9-89d9-67b23982c357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893148951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3893148951
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2209971763
Short name T810
Test name
Test status
Simulation time 364398824 ps
CPU time 10.07 seconds
Started Jan 21 11:11:08 PM PST 24
Finished Jan 21 11:11:19 PM PST 24
Peak memory 217344 kb
Host smart-a6d0e2c2-ea00-4412-90ed-a6890ae44f57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209971763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2209971763
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1514588593
Short name T666
Test name
Test status
Simulation time 193277403 ps
CPU time 8.62 seconds
Started Jan 21 10:29:42 PM PST 24
Finished Jan 21 10:29:53 PM PST 24
Peak memory 217264 kb
Host smart-0444be03-bb19-4939-bb6c-31d21ec3cfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514588593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1514588593
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1836893818
Short name T510
Test name
Test status
Simulation time 25958066 ps
CPU time 1.94 seconds
Started Jan 21 10:29:49 PM PST 24
Finished Jan 21 10:29:53 PM PST 24
Peak memory 211988 kb
Host smart-194a0829-bb50-4037-8181-562620908579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836893818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1836893818
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1045693645
Short name T386
Test name
Test status
Simulation time 387619116 ps
CPU time 27.12 seconds
Started Jan 21 10:29:40 PM PST 24
Finished Jan 21 10:30:09 PM PST 24
Peak memory 250272 kb
Host smart-8ea38112-f720-47e4-99f4-de9f0558cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045693645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1045693645
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.793058023
Short name T380
Test name
Test status
Simulation time 404350053 ps
CPU time 8.36 seconds
Started Jan 21 10:29:45 PM PST 24
Finished Jan 21 10:29:56 PM PST 24
Peak memory 250424 kb
Host smart-10060a01-1a57-454c-99a4-6e5ecc5ead01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793058023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.793058023
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1693539640
Short name T772
Test name
Test status
Simulation time 63085286515 ps
CPU time 126.74 seconds
Started Jan 21 10:57:21 PM PST 24
Finished Jan 21 10:59:33 PM PST 24
Peak memory 277500 kb
Host smart-d353efdc-60b8-46be-a014-7c653e802f67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693539640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1693539640
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2689179608
Short name T46
Test name
Test status
Simulation time 11649223 ps
CPU time 0.81 seconds
Started Jan 21 10:29:45 PM PST 24
Finished Jan 21 10:29:49 PM PST 24
Peak memory 207524 kb
Host smart-3ae3bd40-ffde-4bd9-ad69-0c951cf71907
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689179608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2689179608
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2112493249
Short name T67
Test name
Test status
Simulation time 50778450 ps
CPU time 1.06 seconds
Started Jan 21 10:30:01 PM PST 24
Finished Jan 21 10:30:04 PM PST 24
Peak memory 207628 kb
Host smart-d5b41b16-88fb-4ab6-b330-a7d9cbdea2f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112493249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2112493249
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1406922325
Short name T516
Test name
Test status
Simulation time 901841885 ps
CPU time 9.7 seconds
Started Jan 21 10:29:48 PM PST 24
Finished Jan 21 10:30:00 PM PST 24
Peak memory 217328 kb
Host smart-201c823b-5739-4881-bd3b-e87f25c8df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406922325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1406922325
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1673871652
Short name T474
Test name
Test status
Simulation time 670903521 ps
CPU time 4.69 seconds
Started Jan 21 10:29:49 PM PST 24
Finished Jan 21 10:29:56 PM PST 24
Peak memory 208940 kb
Host smart-e7e64b82-4d60-40b9-8082-1f30845eff12
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673871652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_a
ccess.1673871652
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2499947386
Short name T366
Test name
Test status
Simulation time 243876098 ps
CPU time 3.16 seconds
Started Jan 21 10:29:51 PM PST 24
Finished Jan 21 10:29:56 PM PST 24
Peak memory 217368 kb
Host smart-81363a0c-17dc-4b3c-bfe5-812706497af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499947386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2499947386
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.290419901
Short name T403
Test name
Test status
Simulation time 426749241 ps
CPU time 12.34 seconds
Started Jan 21 10:29:49 PM PST 24
Finished Jan 21 10:30:04 PM PST 24
Peak memory 217304 kb
Host smart-bd66f71c-11c2-4c21-93ab-f2634c75938d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290419901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.290419901
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1380169312
Short name T887
Test name
Test status
Simulation time 1051882231 ps
CPU time 24.62 seconds
Started Jan 21 10:29:51 PM PST 24
Finished Jan 21 10:30:17 PM PST 24
Peak memory 217324 kb
Host smart-603a91f3-654a-46f2-b5c3-dbf8e2906ac6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380169312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1380169312
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.561370726
Short name T656
Test name
Test status
Simulation time 2652485073 ps
CPU time 13.38 seconds
Started Jan 21 10:57:29 PM PST 24
Finished Jan 21 10:57:47 PM PST 24
Peak memory 217496 kb
Host smart-4fdbd163-342b-4850-908d-ee806097a98d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561370726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.561370726
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.634444500
Short name T718
Test name
Test status
Simulation time 312089724 ps
CPU time 9.91 seconds
Started Jan 21 10:29:51 PM PST 24
Finished Jan 21 10:30:03 PM PST 24
Peak memory 217360 kb
Host smart-b9b04d0e-4318-4925-ae44-46ff409cbd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634444500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.634444500
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1404379889
Short name T74
Test name
Test status
Simulation time 66406076 ps
CPU time 3.14 seconds
Started Jan 21 10:29:51 PM PST 24
Finished Jan 21 10:29:56 PM PST 24
Peak memory 213380 kb
Host smart-7b7b75b0-54b7-4917-998c-8679e76fd302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404379889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1404379889
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.988163310
Short name T722
Test name
Test status
Simulation time 370696361 ps
CPU time 23.06 seconds
Started Jan 21 10:55:49 PM PST 24
Finished Jan 21 10:56:13 PM PST 24
Peak memory 250308 kb
Host smart-30c53e61-4653-4da5-aa4b-061eb35c8de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988163310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.988163310
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3311840623
Short name T393
Test name
Test status
Simulation time 333454231 ps
CPU time 9.9 seconds
Started Jan 21 10:29:52 PM PST 24
Finished Jan 21 10:30:03 PM PST 24
Peak memory 250424 kb
Host smart-78016669-c5e5-4423-9f42-8469a94df938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311840623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3311840623
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3086329397
Short name T723
Test name
Test status
Simulation time 4618360603 ps
CPU time 162.25 seconds
Started Jan 21 10:30:04 PM PST 24
Finished Jan 21 10:32:47 PM PST 24
Peak memory 274988 kb
Host smart-cb43315a-923f-4f84-9707-0fe01d66491b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086329397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3086329397
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3690761515
Short name T916
Test name
Test status
Simulation time 18450900 ps
CPU time 0.99 seconds
Started Jan 21 10:29:48 PM PST 24
Finished Jan 21 10:29:51 PM PST 24
Peak memory 210588 kb
Host smart-553c8e5c-ffe0-49a9-bd6b-5b60ac809845
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690761515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3690761515
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.80970316
Short name T727
Test name
Test status
Simulation time 78105498 ps
CPU time 1.24 seconds
Started Jan 21 10:30:07 PM PST 24
Finished Jan 21 10:30:11 PM PST 24
Peak memory 207708 kb
Host smart-caeae3d0-eb31-40d4-9277-577e0f9dfe98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80970316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.80970316
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.71532436
Short name T912
Test name
Test status
Simulation time 3140071809 ps
CPU time 12.6 seconds
Started Jan 21 10:30:02 PM PST 24
Finished Jan 21 10:30:16 PM PST 24
Peak memory 217636 kb
Host smart-b21fb8be-d830-4ee3-862b-cb8f6e00c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71532436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.71532436
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3761174396
Short name T31
Test name
Test status
Simulation time 408039215 ps
CPU time 10.23 seconds
Started Jan 21 10:30:05 PM PST 24
Finished Jan 21 10:30:17 PM PST 24
Peak memory 208964 kb
Host smart-6d30b71d-0cd9-4e67-a3c9-ff2ada3c9e77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761174396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.3761174396
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.265097871
Short name T689
Test name
Test status
Simulation time 56745566 ps
CPU time 2.18 seconds
Started Jan 21 10:50:13 PM PST 24
Finished Jan 21 10:50:20 PM PST 24
Peak memory 217400 kb
Host smart-507e83a8-192a-43e8-ad64-c684afcfae08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265097871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.265097871
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2244594161
Short name T863
Test name
Test status
Simulation time 331694782 ps
CPU time 15.61 seconds
Started Jan 21 10:30:11 PM PST 24
Finished Jan 21 10:30:30 PM PST 24
Peak memory 217360 kb
Host smart-d1c10683-e878-401d-bf32-1daf1c948467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244594161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2244594161
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2517918806
Short name T638
Test name
Test status
Simulation time 556094223 ps
CPU time 14.64 seconds
Started Jan 21 10:30:08 PM PST 24
Finished Jan 21 10:30:24 PM PST 24
Peak memory 217360 kb
Host smart-011a0cb6-2fd7-409d-882d-be418032c069
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517918806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2517918806
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3547741760
Short name T973
Test name
Test status
Simulation time 1139805969 ps
CPU time 8.09 seconds
Started Jan 21 10:30:07 PM PST 24
Finished Jan 21 10:30:18 PM PST 24
Peak memory 217332 kb
Host smart-b586b0b4-d31b-44d4-817a-297b22185956
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547741760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3547741760
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1250813286
Short name T644
Test name
Test status
Simulation time 1162767127 ps
CPU time 12.16 seconds
Started Jan 21 10:30:09 PM PST 24
Finished Jan 21 10:30:23 PM PST 24
Peak memory 217352 kb
Host smart-4d4f269e-6117-4e85-9708-fd92eeddfccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250813286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1250813286
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1630613694
Short name T925
Test name
Test status
Simulation time 486980655 ps
CPU time 2.56 seconds
Started Jan 21 10:30:01 PM PST 24
Finished Jan 21 10:30:06 PM PST 24
Peak memory 212936 kb
Host smart-a216692e-02e8-4805-be15-af701e4f43e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630613694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1630613694
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4088902668
Short name T801
Test name
Test status
Simulation time 504382548 ps
CPU time 24.07 seconds
Started Jan 21 10:30:05 PM PST 24
Finished Jan 21 10:30:30 PM PST 24
Peak memory 249248 kb
Host smart-1c290f9a-5eb3-4f79-bc16-9b8901d6877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088902668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4088902668
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3850009837
Short name T324
Test name
Test status
Simulation time 101833565 ps
CPU time 7.96 seconds
Started Jan 21 10:30:04 PM PST 24
Finished Jan 21 10:30:13 PM PST 24
Peak memory 248968 kb
Host smart-f522e317-ae88-41a3-bd62-047d2839d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850009837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3850009837
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2560060033
Short name T728
Test name
Test status
Simulation time 57602001 ps
CPU time 0.93 seconds
Started Jan 21 10:30:03 PM PST 24
Finished Jan 21 10:30:05 PM PST 24
Peak memory 207460 kb
Host smart-c11abfbd-97ae-44ae-8b6e-0e1e0c981604
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560060033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2560060033
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1947494016
Short name T818
Test name
Test status
Simulation time 14582071 ps
CPU time 0.86 seconds
Started Jan 21 10:30:16 PM PST 24
Finished Jan 21 10:30:28 PM PST 24
Peak memory 207500 kb
Host smart-6d1f26bf-1d67-42f4-a9da-5f0e92233b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947494016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1947494016
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.670346390
Short name T57
Test name
Test status
Simulation time 1671392665 ps
CPU time 14.48 seconds
Started Jan 21 10:30:12 PM PST 24
Finished Jan 21 10:30:35 PM PST 24
Peak memory 224392 kb
Host smart-e7f0d9be-f4b8-48db-b39f-ffd5e4440d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670346390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.670346390
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3118757845
Short name T35
Test name
Test status
Simulation time 601716067 ps
CPU time 3.45 seconds
Started Jan 21 10:30:07 PM PST 24
Finished Jan 21 10:30:12 PM PST 24
Peak memory 208888 kb
Host smart-f5d03d05-c02d-44ec-beca-dc7b37f6812a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118757845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_a
ccess.3118757845
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.791715483
Short name T398
Test name
Test status
Simulation time 184118685 ps
CPU time 2.99 seconds
Started Jan 21 10:30:06 PM PST 24
Finished Jan 21 10:30:10 PM PST 24
Peak memory 217336 kb
Host smart-c186ed34-9ae9-45b9-8db0-f305c3b0faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791715483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.791715483
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3430071213
Short name T342
Test name
Test status
Simulation time 322668049 ps
CPU time 13.31 seconds
Started Jan 21 10:30:06 PM PST 24
Finished Jan 21 10:30:20 PM PST 24
Peak memory 217440 kb
Host smart-4c5463f0-8b59-4a6f-b36d-7b489d366c29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430071213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3430071213
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2790404975
Short name T739
Test name
Test status
Simulation time 297607205 ps
CPU time 10.24 seconds
Started Jan 21 10:30:05 PM PST 24
Finished Jan 21 10:30:16 PM PST 24
Peak memory 217324 kb
Host smart-a709d23e-8461-4974-ab14-e9f8453c7157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790404975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2790404975
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1127427099
Short name T629
Test name
Test status
Simulation time 789596391 ps
CPU time 7.82 seconds
Started Jan 21 10:30:10 PM PST 24
Finished Jan 21 10:30:22 PM PST 24
Peak memory 217372 kb
Host smart-dc265872-380b-41e7-9ffc-3f3fef929034
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127427099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1127427099
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1949945079
Short name T891
Test name
Test status
Simulation time 2566984694 ps
CPU time 9.32 seconds
Started Jan 21 10:30:09 PM PST 24
Finished Jan 21 10:30:21 PM PST 24
Peak memory 217488 kb
Host smart-27623366-797d-4ba6-a60a-53462869be8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949945079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1949945079
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3329120542
Short name T823
Test name
Test status
Simulation time 131788219 ps
CPU time 2.26 seconds
Started Jan 21 10:30:11 PM PST 24
Finished Jan 21 10:30:18 PM PST 24
Peak memory 212744 kb
Host smart-9b3ffc38-cea2-4d14-b8f9-17e276f0c19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329120542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3329120542
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1711212684
Short name T41
Test name
Test status
Simulation time 1139667012 ps
CPU time 30.56 seconds
Started Jan 21 10:30:10 PM PST 24
Finished Jan 21 10:30:44 PM PST 24
Peak memory 250360 kb
Host smart-6ad1f964-63d7-4ebc-a7ff-94964b6ba90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711212684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1711212684
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1520777445
Short name T740
Test name
Test status
Simulation time 311608736 ps
CPU time 2.99 seconds
Started Jan 21 10:30:06 PM PST 24
Finished Jan 21 10:30:10 PM PST 24
Peak memory 221304 kb
Host smart-b0f11752-f0a8-4b26-be4c-fddef9f1273d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520777445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1520777445
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2716982440
Short name T926
Test name
Test status
Simulation time 14727401550 ps
CPU time 94.22 seconds
Started Jan 21 10:55:30 PM PST 24
Finished Jan 21 10:57:08 PM PST 24
Peak memory 225624 kb
Host smart-b21c58a1-a198-44f0-8b94-8115dd9fd1bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716982440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2716982440
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3825752252
Short name T449
Test name
Test status
Simulation time 34286992 ps
CPU time 1.06 seconds
Started Jan 21 10:30:12 PM PST 24
Finished Jan 21 10:30:22 PM PST 24
Peak memory 210676 kb
Host smart-d72a6325-5a85-4426-8732-6543cd220519
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825752252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3825752252
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3804168058
Short name T390
Test name
Test status
Simulation time 21420628 ps
CPU time 1.22 seconds
Started Jan 21 10:22:30 PM PST 24
Finished Jan 21 10:22:41 PM PST 24
Peak memory 207580 kb
Host smart-a6108dd6-085f-4cb3-8946-950962d86b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804168058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3804168058
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2662262848
Short name T184
Test name
Test status
Simulation time 19747021 ps
CPU time 0.8 seconds
Started Jan 21 10:22:21 PM PST 24
Finished Jan 21 10:22:33 PM PST 24
Peak memory 208568 kb
Host smart-657db2cd-effb-4cc5-bf8e-ccefa6d12ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662262848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2662262848
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3718592884
Short name T658
Test name
Test status
Simulation time 1272162922 ps
CPU time 10.12 seconds
Started Jan 21 10:22:24 PM PST 24
Finished Jan 21 10:22:43 PM PST 24
Peak memory 217356 kb
Host smart-5a903b1f-9282-406f-b9ee-d2561aab9fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718592884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3718592884
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.777690750
Short name T878
Test name
Test status
Simulation time 1454430954 ps
CPU time 7.25 seconds
Started Jan 21 10:22:30 PM PST 24
Finished Jan 21 10:22:47 PM PST 24
Peak memory 208884 kb
Host smart-549f12b6-8e13-409e-92f3-4e042364f8d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777690750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_acc
ess.777690750
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1238161604
Short name T940
Test name
Test status
Simulation time 6889916919 ps
CPU time 85.54 seconds
Started Jan 21 10:53:26 PM PST 24
Finished Jan 21 10:54:53 PM PST 24
Peak memory 217760 kb
Host smart-f4ba6b0b-a7ee-4cfb-afca-56fea4e474c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238161604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1238161604
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2862556579
Short name T695
Test name
Test status
Simulation time 1561686516 ps
CPU time 12.62 seconds
Started Jan 21 10:22:28 PM PST 24
Finished Jan 21 10:22:51 PM PST 24
Peak memory 217176 kb
Host smart-ed22fe0b-aef2-45f9-9492-8b5f7c2e1ed0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862556579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.2862556579
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2136853698
Short name T469
Test name
Test status
Simulation time 480438385 ps
CPU time 13.41 seconds
Started Jan 21 10:22:26 PM PST 24
Finished Jan 21 10:22:48 PM PST 24
Peak memory 217276 kb
Host smart-51e2eb83-ff79-480c-85ac-c12f6d1f1bbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136853698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2136853698
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2124420310
Short name T594
Test name
Test status
Simulation time 597282800 ps
CPU time 9.11 seconds
Started Jan 21 10:49:18 PM PST 24
Finished Jan 21 10:49:28 PM PST 24
Peak memory 212008 kb
Host smart-ab116b74-eeae-4cc3-bbe6-8c78187f49c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124420310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2124420310
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3710520216
Short name T691
Test name
Test status
Simulation time 256069383 ps
CPU time 5.02 seconds
Started Jan 21 10:22:22 PM PST 24
Finished Jan 21 10:22:38 PM PST 24
Peak memory 212356 kb
Host smart-af50adb4-88ab-4a60-a2fc-9519c70276af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710520216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3710520216
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3267982719
Short name T944
Test name
Test status
Simulation time 3202955287 ps
CPU time 66.92 seconds
Started Jan 21 10:22:25 PM PST 24
Finished Jan 21 10:23:40 PM PST 24
Peak memory 270000 kb
Host smart-67cc7d4f-1199-4389-953e-57db5db5794d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267982719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3267982719
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3896691728
Short name T560
Test name
Test status
Simulation time 8324171633 ps
CPU time 15.33 seconds
Started Jan 21 10:22:30 PM PST 24
Finished Jan 21 10:22:55 PM PST 24
Peak memory 250348 kb
Host smart-2d6bac9c-3ac3-41df-9249-1b08f12b42dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896691728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3896691728
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1241270385
Short name T585
Test name
Test status
Simulation time 143658630 ps
CPU time 2.74 seconds
Started Jan 21 10:22:21 PM PST 24
Finished Jan 21 10:22:35 PM PST 24
Peak memory 217268 kb
Host smart-54dbee74-7301-48c9-a7b2-0f91afc80c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241270385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1241270385
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.167593538
Short name T428
Test name
Test status
Simulation time 2373124592 ps
CPU time 7.3 seconds
Started Jan 21 10:22:22 PM PST 24
Finished Jan 21 10:22:40 PM PST 24
Peak memory 212828 kb
Host smart-99190166-1476-4a19-a55a-c21bf48c2b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167593538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.167593538
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.545234817
Short name T897
Test name
Test status
Simulation time 1179430006 ps
CPU time 15.37 seconds
Started Jan 21 10:52:41 PM PST 24
Finished Jan 21 10:52:59 PM PST 24
Peak memory 218292 kb
Host smart-df551a4e-1736-41a6-b414-9bf1b6098bbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545234817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.545234817
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1853676860
Short name T792
Test name
Test status
Simulation time 272305865 ps
CPU time 9.46 seconds
Started Jan 21 10:22:27 PM PST 24
Finished Jan 21 10:22:46 PM PST 24
Peak memory 217424 kb
Host smart-5aa71eed-08ba-4827-a82b-f298cb4cf71d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853676860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1853676860
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.885349880
Short name T901
Test name
Test status
Simulation time 1221052169 ps
CPU time 12.95 seconds
Started Jan 21 10:22:28 PM PST 24
Finished Jan 21 10:22:51 PM PST 24
Peak memory 217360 kb
Host smart-3475db83-dfca-418e-8edd-ab20f6f76e6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885349880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.885349880
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3185102793
Short name T543
Test name
Test status
Simulation time 1663124627 ps
CPU time 12.62 seconds
Started Jan 21 10:22:20 PM PST 24
Finished Jan 21 10:22:43 PM PST 24
Peak memory 217320 kb
Host smart-bebb94b2-e8ab-4754-abbf-0fa89d71d979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185102793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3185102793
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4238589938
Short name T384
Test name
Test status
Simulation time 156817145 ps
CPU time 2.19 seconds
Started Jan 21 10:22:34 PM PST 24
Finished Jan 21 10:22:46 PM PST 24
Peak memory 212860 kb
Host smart-ae50a7ac-fff0-4063-ad75-de74695023f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238589938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4238589938
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2854235012
Short name T683
Test name
Test status
Simulation time 205425189 ps
CPU time 21.79 seconds
Started Jan 21 10:22:25 PM PST 24
Finished Jan 21 10:22:55 PM PST 24
Peak memory 250328 kb
Host smart-99d3b852-a73a-4ef2-8092-b9e1c4aa7b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854235012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2854235012
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2718278110
Short name T797
Test name
Test status
Simulation time 177561103 ps
CPU time 3 seconds
Started Jan 21 10:22:23 PM PST 24
Finished Jan 21 10:22:36 PM PST 24
Peak memory 221152 kb
Host smart-b6564b36-4128-4033-97be-8772d293de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718278110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2718278110
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1820583196
Short name T20
Test name
Test status
Simulation time 62181148891 ps
CPU time 124.01 seconds
Started Jan 21 10:22:28 PM PST 24
Finished Jan 21 10:24:42 PM PST 24
Peak memory 275352 kb
Host smart-52ac2dd9-f361-4639-9643-5b26b74981d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820583196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1820583196
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3603012008
Short name T569
Test name
Test status
Simulation time 86474663 ps
CPU time 1.01 seconds
Started Jan 21 10:22:20 PM PST 24
Finished Jan 21 10:22:31 PM PST 24
Peak memory 211712 kb
Host smart-67a9cb37-7ece-437f-8b18-000554a81b38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603012008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3603012008
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.757754719
Short name T979
Test name
Test status
Simulation time 16269237 ps
CPU time 0.88 seconds
Started Jan 21 10:22:44 PM PST 24
Finished Jan 21 10:22:50 PM PST 24
Peak memory 208932 kb
Host smart-e57622a7-f636-4c27-a750-8cae0f000dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757754719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.757754719
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3439338974
Short name T11
Test name
Test status
Simulation time 1267431430 ps
CPU time 14.97 seconds
Started Jan 21 10:22:35 PM PST 24
Finished Jan 21 10:22:59 PM PST 24
Peak memory 217360 kb
Host smart-40fc6d29-123d-40e3-b14b-cd4506013d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439338974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3439338974
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1067013186
Short name T534
Test name
Test status
Simulation time 6024166583 ps
CPU time 20.61 seconds
Started Jan 21 11:14:45 PM PST 24
Finished Jan 21 11:15:08 PM PST 24
Peak memory 209156 kb
Host smart-da4981f4-d48f-4ca8-8125-a1099a4876bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067013186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.1067013186
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3721254052
Short name T561
Test name
Test status
Simulation time 11688222419 ps
CPU time 98.86 seconds
Started Jan 21 10:22:34 PM PST 24
Finished Jan 21 10:24:22 PM PST 24
Peak memory 218724 kb
Host smart-b157f9c2-7448-49ba-81d4-b095ed155958
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721254052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3721254052
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3723834582
Short name T333
Test name
Test status
Simulation time 540734725 ps
CPU time 7.58 seconds
Started Jan 21 10:22:34 PM PST 24
Finished Jan 21 10:22:51 PM PST 24
Peak memory 217228 kb
Host smart-36dd6340-90ae-46c9-b73a-4069ee4f60c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723834582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.3723834582
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3616118771
Short name T844
Test name
Test status
Simulation time 227730661 ps
CPU time 4.53 seconds
Started Jan 21 10:22:32 PM PST 24
Finished Jan 21 10:22:46 PM PST 24
Peak memory 217304 kb
Host smart-d800e902-8774-4b4b-9fb2-0787f0afc392
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616118771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3616118771
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3815309163
Short name T21
Test name
Test status
Simulation time 1871270038 ps
CPU time 28.08 seconds
Started Jan 21 10:22:43 PM PST 24
Finished Jan 21 10:23:17 PM PST 24
Peak memory 212336 kb
Host smart-bef995b4-79e3-44de-98f1-825e1ee7dd4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815309163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3815309163
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3980174004
Short name T84
Test name
Test status
Simulation time 344697252 ps
CPU time 1.54 seconds
Started Jan 21 10:47:03 PM PST 24
Finished Jan 21 10:47:06 PM PST 24
Peak memory 211776 kb
Host smart-d162f45f-c6cf-4c13-82d4-8dbb11ea39a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980174004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3980174004
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3507093617
Short name T445
Test name
Test status
Simulation time 1472535428 ps
CPU time 58.8 seconds
Started Jan 21 10:22:33 PM PST 24
Finished Jan 21 10:23:42 PM PST 24
Peak memory 250356 kb
Host smart-4158ea08-1105-479d-9e7a-fef4feb5355f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507093617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3507093617
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.4143931309
Short name T471
Test name
Test status
Simulation time 1252783831 ps
CPU time 9.12 seconds
Started Jan 21 10:22:34 PM PST 24
Finished Jan 21 10:22:53 PM PST 24
Peak memory 221584 kb
Host smart-9c6a9daf-5f4e-4fd3-b7a5-1b644ccf4ca8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143931309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.4143931309
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1797605486
Short name T351
Test name
Test status
Simulation time 1092979005 ps
CPU time 5.09 seconds
Started Jan 21 10:22:39 PM PST 24
Finished Jan 21 10:22:52 PM PST 24
Peak memory 217464 kb
Host smart-0040d0e5-9193-4b4f-9d9f-a02efc6d1dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797605486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1797605486
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3503473795
Short name T676
Test name
Test status
Simulation time 217957598 ps
CPU time 11.71 seconds
Started Jan 21 10:56:32 PM PST 24
Finished Jan 21 10:56:44 PM PST 24
Peak memory 213260 kb
Host smart-98f976fe-5787-4f02-929e-7fad1f89c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503473795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3503473795
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2058294399
Short name T927
Test name
Test status
Simulation time 2058677125 ps
CPU time 15.99 seconds
Started Jan 21 10:22:42 PM PST 24
Finished Jan 21 10:23:05 PM PST 24
Peak memory 217356 kb
Host smart-b3940228-528c-4f51-b2e8-b7bf155c247a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058294399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2058294399
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4093388014
Short name T37
Test name
Test status
Simulation time 340179511 ps
CPU time 14.23 seconds
Started Jan 21 10:22:44 PM PST 24
Finished Jan 21 10:23:04 PM PST 24
Peak memory 217332 kb
Host smart-b38434b9-554f-4e23-be37-3a949fcb6c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093388014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4093388014
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4145936404
Short name T811
Test name
Test status
Simulation time 279853169 ps
CPU time 10.75 seconds
Started Jan 21 10:22:46 PM PST 24
Finished Jan 21 10:23:04 PM PST 24
Peak memory 217336 kb
Host smart-766e1cbd-e6ae-4b79-a0c4-7171b3c83a80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145936404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
145936404
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2020564804
Short name T724
Test name
Test status
Simulation time 254015288 ps
CPU time 8.1 seconds
Started Jan 21 10:22:38 PM PST 24
Finished Jan 21 10:22:54 PM PST 24
Peak memory 217344 kb
Host smart-901d349a-4ba3-4c46-9347-c5ec8690e7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020564804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2020564804
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.942808977
Short name T673
Test name
Test status
Simulation time 246794779 ps
CPU time 2.72 seconds
Started Jan 21 10:22:34 PM PST 24
Finished Jan 21 10:22:46 PM PST 24
Peak memory 217240 kb
Host smart-3e5bf8ed-8e61-4196-84a7-bf75c6abae0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942808977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.942808977
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1865357914
Short name T118
Test name
Test status
Simulation time 182710023 ps
CPU time 21.1 seconds
Started Jan 21 10:22:33 PM PST 24
Finished Jan 21 10:23:03 PM PST 24
Peak memory 250348 kb
Host smart-c6bc5825-e9d1-45c3-a02b-4dee82c51c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865357914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1865357914
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.548115960
Short name T584
Test name
Test status
Simulation time 301379108 ps
CPU time 6.29 seconds
Started Jan 21 10:22:35 PM PST 24
Finished Jan 21 10:22:51 PM PST 24
Peak memory 242208 kb
Host smart-4908aa6e-33ae-466f-8c5f-671f5ce73163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548115960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.548115960
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3413423085
Short name T127
Test name
Test status
Simulation time 35208398547 ps
CPU time 283.15 seconds
Started Jan 21 10:22:50 PM PST 24
Finished Jan 21 10:27:37 PM PST 24
Peak memory 272736 kb
Host smart-edd96910-de55-4d1c-a106-a27b6ccc879a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413423085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3413423085
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2974985673
Short name T721
Test name
Test status
Simulation time 18989287 ps
CPU time 1.01 seconds
Started Jan 21 10:57:39 PM PST 24
Finished Jan 21 10:57:40 PM PST 24
Peak memory 211620 kb
Host smart-fe9ae28e-0f81-406c-93da-19a97c58f962
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974985673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2974985673
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.4272618432
Short name T583
Test name
Test status
Simulation time 161206968 ps
CPU time 1.17 seconds
Started Jan 21 10:23:01 PM PST 24
Finished Jan 21 10:23:06 PM PST 24
Peak memory 208348 kb
Host smart-8ac0cbe8-d86e-48b5-aea4-0f62da0317b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272618432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.4272618432
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3183304613
Short name T397
Test name
Test status
Simulation time 10916054 ps
CPU time 0.83 seconds
Started Jan 21 10:22:48 PM PST 24
Finished Jan 21 10:22:54 PM PST 24
Peak memory 208712 kb
Host smart-98a639d7-9606-4d4b-9b99-ca5e6af9904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183304613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3183304613
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.570378488
Short name T327
Test name
Test status
Simulation time 397610260 ps
CPU time 20.07 seconds
Started Jan 21 10:22:47 PM PST 24
Finished Jan 21 10:23:13 PM PST 24
Peak memory 217360 kb
Host smart-939fede7-28f4-4a6f-8c66-534eaa0e1154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570378488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.570378488
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2861441962
Short name T617
Test name
Test status
Simulation time 1545341108 ps
CPU time 10.99 seconds
Started Jan 21 10:22:45 PM PST 24
Finished Jan 21 10:23:03 PM PST 24
Peak memory 208948 kb
Host smart-5ae769b5-0c43-4c60-b171-0c8147a8eca4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861441962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.2861441962
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3067823038
Short name T681
Test name
Test status
Simulation time 4939774134 ps
CPU time 21.07 seconds
Started Jan 21 11:06:49 PM PST 24
Finished Jan 21 11:07:12 PM PST 24
Peak memory 217696 kb
Host smart-98f48f48-9fdd-4569-993c-b2bf3474806d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067823038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3067823038
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3430559833
Short name T716
Test name
Test status
Simulation time 2115066641 ps
CPU time 2.56 seconds
Started Jan 21 10:22:45 PM PST 24
Finished Jan 21 10:22:54 PM PST 24
Peak memory 209000 kb
Host smart-ec9e8d91-fe6e-41a8-80a5-45b0c84a03e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430559833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.3430559833
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1132993655
Short name T788
Test name
Test status
Simulation time 1259938617 ps
CPU time 9.24 seconds
Started Jan 21 10:22:46 PM PST 24
Finished Jan 21 10:23:02 PM PST 24
Peak memory 217272 kb
Host smart-87ac5b71-6f6a-4371-bda4-9614abac17da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132993655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1132993655
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1830415101
Short name T415
Test name
Test status
Simulation time 1068996930 ps
CPU time 20.41 seconds
Started Jan 21 10:49:56 PM PST 24
Finished Jan 21 10:50:18 PM PST 24
Peak memory 212372 kb
Host smart-136a846f-865c-4a8c-862b-c14f438d51a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830415101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1830415101
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1800314036
Short name T554
Test name
Test status
Simulation time 573389895 ps
CPU time 4.54 seconds
Started Jan 21 10:22:46 PM PST 24
Finished Jan 21 10:22:57 PM PST 24
Peak memory 212096 kb
Host smart-e601952f-9c2b-4133-ad3c-0628cbae435f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800314036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1800314036
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1450353403
Short name T442
Test name
Test status
Simulation time 8005558596 ps
CPU time 54.02 seconds
Started Jan 21 11:28:54 PM PST 24
Finished Jan 21 11:29:50 PM PST 24
Peak memory 275500 kb
Host smart-bb2b64c5-83a5-4ceb-bea8-c0fa459db4fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450353403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1450353403
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1614798424
Short name T933
Test name
Test status
Simulation time 1430698380 ps
CPU time 18.23 seconds
Started Jan 21 10:22:46 PM PST 24
Finished Jan 21 10:23:11 PM PST 24
Peak memory 248140 kb
Host smart-e3c80a9f-0cbe-45d3-8f4f-cecddce79ffc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614798424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1614798424
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3556308830
Short name T806
Test name
Test status
Simulation time 88262120 ps
CPU time 3.7 seconds
Started Jan 21 10:54:59 PM PST 24
Finished Jan 21 10:55:09 PM PST 24
Peak memory 217384 kb
Host smart-90ff2d0c-a458-420d-8dc1-ba9711633269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556308830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3556308830
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.785619579
Short name T653
Test name
Test status
Simulation time 344503070 ps
CPU time 9.15 seconds
Started Jan 21 10:45:41 PM PST 24
Finished Jan 21 10:45:52 PM PST 24
Peak memory 212868 kb
Host smart-62c34424-f76e-48ad-994b-e997efd6f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785619579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.785619579
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1270186878
Short name T929
Test name
Test status
Simulation time 1411418023 ps
CPU time 28.9 seconds
Started Jan 21 11:23:40 PM PST 24
Finished Jan 21 11:24:10 PM PST 24
Peak memory 217408 kb
Host smart-55536a37-6685-4014-a617-20bd26e0189f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270186878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1270186878
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1165497620
Short name T52
Test name
Test status
Simulation time 887197768 ps
CPU time 21.87 seconds
Started Jan 21 10:22:45 PM PST 24
Finished Jan 21 10:23:13 PM PST 24
Peak memory 217340 kb
Host smart-6cec92da-7e58-476d-a6ba-d0a53ed48888
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165497620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1165497620
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1035461573
Short name T812
Test name
Test status
Simulation time 981654152 ps
CPU time 12.38 seconds
Started Jan 21 10:52:36 PM PST 24
Finished Jan 21 10:52:52 PM PST 24
Peak memory 217328 kb
Host smart-cca59ccf-fc70-4d51-a7d0-0a6ace00450c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035461573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
035461573
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1039802925
Short name T347
Test name
Test status
Simulation time 1112325836 ps
CPU time 11.97 seconds
Started Jan 21 10:22:46 PM PST 24
Finished Jan 21 10:23:04 PM PST 24
Peak memory 217360 kb
Host smart-bdf386af-59c9-4b20-a9e2-3c3234a4dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039802925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1039802925
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1002333263
Short name T468
Test name
Test status
Simulation time 46993088 ps
CPU time 1.93 seconds
Started Jan 21 10:22:44 PM PST 24
Finished Jan 21 10:22:52 PM PST 24
Peak memory 212420 kb
Host smart-99aaff8a-7f38-4dda-9e75-347dbcffd1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002333263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1002333263
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.549764571
Short name T378
Test name
Test status
Simulation time 341758106 ps
CPU time 28.81 seconds
Started Jan 21 10:22:43 PM PST 24
Finished Jan 21 10:23:18 PM PST 24
Peak memory 250308 kb
Host smart-b9b6f944-210c-4c79-869a-653674b19f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549764571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.549764571
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1867727435
Short name T936
Test name
Test status
Simulation time 260410024 ps
CPU time 7.38 seconds
Started Jan 21 10:22:47 PM PST 24
Finished Jan 21 10:23:00 PM PST 24
Peak memory 250040 kb
Host smart-50feecd7-38d6-43fd-9af2-0e3995d9c5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867727435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1867727435
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.157319881
Short name T25
Test name
Test status
Simulation time 5883846002 ps
CPU time 39.27 seconds
Started Jan 21 10:22:59 PM PST 24
Finished Jan 21 10:23:42 PM PST 24
Peak memory 250280 kb
Host smart-0d426a09-abf8-4b9f-a577-776178f19180
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157319881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.157319881
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.933325463
Short name T526
Test name
Test status
Simulation time 14618253 ps
CPU time 0.87 seconds
Started Jan 21 10:23:18 PM PST 24
Finished Jan 21 10:23:24 PM PST 24
Peak memory 208480 kb
Host smart-2ce79132-4d8e-4f84-8cbd-2fdd0c647201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933325463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.933325463
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.495073387
Short name T522
Test name
Test status
Simulation time 33043662 ps
CPU time 0.8 seconds
Started Jan 21 10:23:03 PM PST 24
Finished Jan 21 10:23:08 PM PST 24
Peak memory 207312 kb
Host smart-2f5faf71-2043-4aab-8eaf-ea1998f4f2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495073387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.495073387
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.664546389
Short name T120
Test name
Test status
Simulation time 1821071423 ps
CPU time 13.81 seconds
Started Jan 21 10:23:02 PM PST 24
Finished Jan 21 10:23:19 PM PST 24
Peak memory 217336 kb
Host smart-dd2f4a8f-bdd0-4d9c-8da0-406c44131f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664546389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.664546389
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2642854019
Short name T575
Test name
Test status
Simulation time 1004838998 ps
CPU time 8.96 seconds
Started Jan 21 11:00:08 PM PST 24
Finished Jan 21 11:00:18 PM PST 24
Peak memory 208908 kb
Host smart-2c50017d-f5a6-4de6-ad94-ee472f84bfa0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642854019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.2642854019
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1296303906
Short name T857
Test name
Test status
Simulation time 4930832018 ps
CPU time 37.45 seconds
Started Jan 21 10:46:20 PM PST 24
Finished Jan 21 10:46:58 PM PST 24
Peak memory 218460 kb
Host smart-79bb5b3a-c614-461a-86d0-a54a44ca3df0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296303906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1296303906
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.374024167
Short name T849
Test name
Test status
Simulation time 488276431 ps
CPU time 9.21 seconds
Started Jan 21 10:23:07 PM PST 24
Finished Jan 21 10:23:21 PM PST 24
Peak memory 208980 kb
Host smart-665cbb84-87be-4d67-98c9-149d562549c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374024167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_p
riority.374024167
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1983826953
Short name T814
Test name
Test status
Simulation time 111473463 ps
CPU time 2.52 seconds
Started Jan 21 10:42:15 PM PST 24
Finished Jan 21 10:42:19 PM PST 24
Peak memory 217276 kb
Host smart-46196ea3-3863-405f-8c25-1bb12452f768
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983826953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1983826953
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2921731270
Short name T86
Test name
Test status
Simulation time 4683630534 ps
CPU time 17.35 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:48 PM PST 24
Peak memory 212780 kb
Host smart-9d0a0016-f60c-4479-b8f4-a0813618bccd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921731270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2921731270
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1345044136
Short name T595
Test name
Test status
Simulation time 177211349 ps
CPU time 3.77 seconds
Started Jan 21 10:23:01 PM PST 24
Finished Jan 21 10:23:08 PM PST 24
Peak memory 211684 kb
Host smart-5f0b2d08-13a8-41d2-871f-c892edd7dcc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345044136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1345044136
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1494713829
Short name T475
Test name
Test status
Simulation time 799115154 ps
CPU time 29.9 seconds
Started Jan 21 10:23:06 PM PST 24
Finished Jan 21 10:23:41 PM PST 24
Peak memory 250236 kb
Host smart-e4fccddb-6af3-4a47-9d03-d92927b42ea0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494713829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1494713829
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1462815927
Short name T350
Test name
Test status
Simulation time 1686669966 ps
CPU time 12.79 seconds
Started Jan 21 10:23:08 PM PST 24
Finished Jan 21 10:23:26 PM PST 24
Peak memory 244684 kb
Host smart-e0f9e286-bbad-4c01-9b02-12b2f335062c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462815927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1462815927
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3398266207
Short name T528
Test name
Test status
Simulation time 49224834 ps
CPU time 2.54 seconds
Started Jan 21 10:23:00 PM PST 24
Finished Jan 21 10:23:07 PM PST 24
Peak memory 217380 kb
Host smart-86f23610-3c50-47c6-baa4-4a60c5669684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398266207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3398266207
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3146868906
Short name T838
Test name
Test status
Simulation time 318271562 ps
CPU time 18.19 seconds
Started Jan 21 10:23:00 PM PST 24
Finished Jan 21 10:23:22 PM PST 24
Peak memory 213488 kb
Host smart-82c2ca99-c5c8-458d-8947-8c4231265860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146868906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3146868906
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2456835887
Short name T358
Test name
Test status
Simulation time 995128630 ps
CPU time 14.96 seconds
Started Jan 21 10:23:21 PM PST 24
Finished Jan 21 10:23:42 PM PST 24
Peak memory 217296 kb
Host smart-541e1987-477f-4701-9bd7-181bb2cc350e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456835887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2456835887
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1545302523
Short name T608
Test name
Test status
Simulation time 228757804 ps
CPU time 7.38 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:38 PM PST 24
Peak memory 217272 kb
Host smart-6c874c29-fde8-4c73-8588-604749f72aac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545302523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1545302523
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3452353128
Short name T627
Test name
Test status
Simulation time 418757059 ps
CPU time 10.83 seconds
Started Jan 21 10:23:20 PM PST 24
Finished Jan 21 10:23:37 PM PST 24
Peak memory 217364 kb
Host smart-c58ef10c-3f49-4a41-a92d-3cd744c6ec0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452353128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
452353128
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2070747689
Short name T81
Test name
Test status
Simulation time 539364312 ps
CPU time 7.78 seconds
Started Jan 21 10:23:04 PM PST 24
Finished Jan 21 10:23:15 PM PST 24
Peak memory 217328 kb
Host smart-9c485e1e-d5c2-45c1-af88-925a8e70e44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070747689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2070747689
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2119712145
Short name T951
Test name
Test status
Simulation time 29543994 ps
CPU time 1.12 seconds
Started Jan 21 10:22:55 PM PST 24
Finished Jan 21 10:22:59 PM PST 24
Peak memory 212332 kb
Host smart-513ca08a-5df0-4159-92b4-0bc9032a0b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119712145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2119712145
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2810166993
Short name T27
Test name
Test status
Simulation time 551109584 ps
CPU time 33.68 seconds
Started Jan 21 10:23:00 PM PST 24
Finished Jan 21 10:23:38 PM PST 24
Peak memory 248888 kb
Host smart-466c0b6a-f3aa-492e-ae69-b0a9cf0926d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810166993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2810166993
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.323799168
Short name T422
Test name
Test status
Simulation time 76034975 ps
CPU time 7.64 seconds
Started Jan 21 10:23:00 PM PST 24
Finished Jan 21 10:23:12 PM PST 24
Peak memory 250288 kb
Host smart-0310cb87-6658-4e8d-acf7-e3352e910da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323799168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.323799168
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2317575535
Short name T79
Test name
Test status
Simulation time 3282970328 ps
CPU time 45.82 seconds
Started Jan 21 10:23:19 PM PST 24
Finished Jan 21 10:24:09 PM PST 24
Peak memory 248192 kb
Host smart-7dee2381-3c7d-4974-a3ff-ef2773da8116
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317575535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2317575535
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3898406657
Short name T451
Test name
Test status
Simulation time 18773856 ps
CPU time 0.99 seconds
Started Jan 21 10:22:58 PM PST 24
Finished Jan 21 10:23:01 PM PST 24
Peak memory 211664 kb
Host smart-af3faa29-e4d9-4d1c-aff4-1a95bd18b069
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898406657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3898406657
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1878139631
Short name T598
Test name
Test status
Simulation time 21464946 ps
CPU time 1.14 seconds
Started Jan 21 10:23:22 PM PST 24
Finished Jan 21 10:23:30 PM PST 24
Peak memory 208956 kb
Host smart-fba9b583-78a7-40a4-81b9-fb5b58c12a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878139631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1878139631
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3984428304
Short name T92
Test name
Test status
Simulation time 21005906 ps
CPU time 0.8 seconds
Started Jan 21 10:23:18 PM PST 24
Finished Jan 21 10:23:23 PM PST 24
Peak memory 207300 kb
Host smart-87fa1324-c07e-4438-bfeb-eb8b9ed4a2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984428304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3984428304
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2254000207
Short name T924
Test name
Test status
Simulation time 355797386 ps
CPU time 16.79 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:47 PM PST 24
Peak memory 217364 kb
Host smart-6c503fbc-5a1f-4fa1-87f3-c39d55fe1627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254000207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2254000207
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3709899805
Short name T521
Test name
Test status
Simulation time 121633239 ps
CPU time 3.76 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:33 PM PST 24
Peak memory 208868 kb
Host smart-8873ffb4-8a97-4b66-a4e5-f8167a023006
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709899805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.3709899805
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.812689786
Short name T729
Test name
Test status
Simulation time 7159520724 ps
CPU time 41.26 seconds
Started Jan 21 11:08:38 PM PST 24
Finished Jan 21 11:09:21 PM PST 24
Peak memory 217528 kb
Host smart-1119b926-aa31-411e-bda3-3ed16dca68b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812689786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.812689786
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.290361998
Short name T760
Test name
Test status
Simulation time 1076647608 ps
CPU time 7.84 seconds
Started Jan 21 10:23:28 PM PST 24
Finished Jan 21 10:23:41 PM PST 24
Peak memory 217216 kb
Host smart-360ffba9-b9c9-4607-b49f-5fac5b49db8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290361998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_p
riority.290361998
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2310869212
Short name T693
Test name
Test status
Simulation time 549375195 ps
CPU time 5.35 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:36 PM PST 24
Peak memory 217204 kb
Host smart-4d8952d5-714f-4842-8bd0-973090dcee4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310869212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2310869212
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.481731133
Short name T73
Test name
Test status
Simulation time 9164513615 ps
CPU time 28.77 seconds
Started Jan 21 10:23:29 PM PST 24
Finished Jan 21 10:24:02 PM PST 24
Peak memory 212988 kb
Host smart-ee97e111-e1a1-4b99-bd28-048b5de225b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481731133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.481731133
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3429924728
Short name T414
Test name
Test status
Simulation time 664965992 ps
CPU time 5.56 seconds
Started Jan 21 10:23:18 PM PST 24
Finished Jan 21 10:23:28 PM PST 24
Peak memory 212348 kb
Host smart-ec256a5a-4b0f-453d-b8e6-763123180760
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429924728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3429924728
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3055379017
Short name T514
Test name
Test status
Simulation time 6411284155 ps
CPU time 63.09 seconds
Started Jan 21 10:49:57 PM PST 24
Finished Jan 21 10:51:01 PM PST 24
Peak memory 271584 kb
Host smart-2f1c92a5-8508-4389-9a7b-d2fc9599348b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055379017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3055379017
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2190877305
Short name T373
Test name
Test status
Simulation time 440311548 ps
CPU time 13.98 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:44 PM PST 24
Peak memory 248064 kb
Host smart-dde8ea77-ac82-4baf-8faf-b4c5a6ab3f6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190877305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2190877305
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1654272263
Short name T743
Test name
Test status
Simulation time 67288365 ps
CPU time 2.82 seconds
Started Jan 21 10:23:21 PM PST 24
Finished Jan 21 10:23:30 PM PST 24
Peak memory 217324 kb
Host smart-64faba13-d98f-4375-9f50-1503371bce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654272263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1654272263
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2997233740
Short name T609
Test name
Test status
Simulation time 1313777158 ps
CPU time 8.85 seconds
Started Jan 21 10:23:21 PM PST 24
Finished Jan 21 10:23:36 PM PST 24
Peak memory 217164 kb
Host smart-c3077791-6e6a-440d-8f64-7b2f8a73026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997233740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2997233740
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1411975462
Short name T763
Test name
Test status
Simulation time 523538278 ps
CPU time 13.69 seconds
Started Jan 21 10:42:07 PM PST 24
Finished Jan 21 10:42:22 PM PST 24
Peak memory 217472 kb
Host smart-8659f9c3-156c-4e69-87b6-d605ba127cf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411975462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1411975462
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2403058271
Short name T512
Test name
Test status
Simulation time 389084018 ps
CPU time 10.49 seconds
Started Jan 21 10:23:22 PM PST 24
Finished Jan 21 10:23:39 PM PST 24
Peak memory 217532 kb
Host smart-108fddb7-cefb-48c6-8ce4-1f72b1ca2c65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403058271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2403058271
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2217924588
Short name T783
Test name
Test status
Simulation time 1549532613 ps
CPU time 13.59 seconds
Started Jan 21 10:23:26 PM PST 24
Finished Jan 21 10:23:45 PM PST 24
Peak memory 217356 kb
Host smart-acf5cef3-c39e-43ba-9df4-ba2f8dba58c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217924588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
217924588
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4229606757
Short name T745
Test name
Test status
Simulation time 288759560 ps
CPU time 8.01 seconds
Started Jan 21 10:23:19 PM PST 24
Finished Jan 21 10:23:32 PM PST 24
Peak memory 217308 kb
Host smart-71517c19-142a-421f-87a1-06d7fdf91ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229606757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4229606757
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.108078040
Short name T62
Test name
Test status
Simulation time 65559417 ps
CPU time 2.4 seconds
Started Jan 21 10:23:19 PM PST 24
Finished Jan 21 10:23:27 PM PST 24
Peak memory 212796 kb
Host smart-4aa49d12-f595-4f22-8a81-bf4a756007d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108078040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.108078040
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2982374826
Short name T754
Test name
Test status
Simulation time 1316225830 ps
CPU time 28.92 seconds
Started Jan 21 10:23:18 PM PST 24
Finished Jan 21 10:23:52 PM PST 24
Peak memory 249968 kb
Host smart-8b9f6a9f-bcda-4e10-b570-0e4f4c0d40d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982374826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2982374826
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1522607508
Short name T789
Test name
Test status
Simulation time 374645684 ps
CPU time 8.1 seconds
Started Jan 21 10:23:19 PM PST 24
Finished Jan 21 10:23:33 PM PST 24
Peak memory 250344 kb
Host smart-0146dd67-64fb-4eae-8036-f16e43c6c6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522607508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1522607508
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3159494401
Short name T552
Test name
Test status
Simulation time 8321078713 ps
CPU time 160.28 seconds
Started Jan 21 10:23:29 PM PST 24
Finished Jan 21 10:26:14 PM PST 24
Peak memory 250504 kb
Host smart-3ce11bf8-07f4-4130-a130-84c4e692092d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159494401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3159494401
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1247808371
Short name T45
Test name
Test status
Simulation time 61733787 ps
CPU time 0.79 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:31 PM PST 24
Peak memory 207180 kb
Host smart-46384f73-979c-492b-aa14-f187c0c8b7a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247808371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1247808371
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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