Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39302 |
1 |
|
|
T1 |
397 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
1187 |
1 |
|
|
T1 |
28 |
|
T11 |
14 |
|
T19 |
22 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39705 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
784 |
1 |
|
|
T50 |
9 |
|
T51 |
13 |
|
T30 |
21 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39207 |
1 |
|
|
T1 |
408 |
|
T2 |
73 |
|
T3 |
11 |
auto[1] |
1282 |
1 |
|
|
T1 |
17 |
|
T2 |
14 |
|
T8 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39249 |
1 |
|
|
T1 |
405 |
|
T2 |
73 |
|
T3 |
11 |
auto[1] |
1240 |
1 |
|
|
T1 |
20 |
|
T2 |
14 |
|
T8 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39289 |
1 |
|
|
T1 |
410 |
|
T2 |
79 |
|
T3 |
11 |
auto[1] |
1200 |
1 |
|
|
T1 |
15 |
|
T2 |
8 |
|
T8 |
2 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
37430 |
1 |
|
|
T1 |
393 |
|
T2 |
87 |
|
T3 |
11 |
no_err_inj |
3059 |
1 |
|
|
T1 |
32 |
|
T8 |
7 |
|
T11 |
29 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39302 |
1 |
|
|
T1 |
406 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
1187 |
1 |
|
|
T1 |
19 |
|
T11 |
6 |
|
T19 |
25 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39714 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
775 |
1 |
|
|
T50 |
10 |
|
T51 |
9 |
|
T30 |
15 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
30805 |
1 |
|
|
T1 |
240 |
|
T8 |
14 |
|
T11 |
3 |
auto[1] |
9684 |
1 |
|
|
T1 |
185 |
|
T2 |
87 |
|
T3 |
11 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39271 |
1 |
|
|
T1 |
406 |
|
T2 |
76 |
|
T3 |
11 |
auto[1] |
1218 |
1 |
|
|
T1 |
19 |
|
T2 |
11 |
|
T11 |
3 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39257 |
1 |
|
|
T1 |
413 |
|
T2 |
80 |
|
T3 |
11 |
auto[1] |
1232 |
1 |
|
|
T1 |
12 |
|
T2 |
7 |
|
T8 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39195 |
1 |
|
|
T1 |
402 |
|
T2 |
79 |
|
T3 |
11 |
auto[1] |
1294 |
1 |
|
|
T1 |
23 |
|
T2 |
8 |
|
T11 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39262 |
1 |
|
|
T1 |
403 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
1227 |
1 |
|
|
T1 |
22 |
|
T11 |
15 |
|
T19 |
34 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39089 |
1 |
|
|
T1 |
397 |
|
T2 |
87 |
|
T8 |
14 |
auto[1] |
1400 |
1 |
|
|
T1 |
28 |
|
T3 |
11 |
|
T19 |
6 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39686 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
803 |
1 |
|
|
T50 |
18 |
|
T51 |
23 |
|
T30 |
14 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39723 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
766 |
1 |
|
|
T50 |
14 |
|
T51 |
20 |
|
T30 |
20 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39679 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
810 |
1 |
|
|
T50 |
18 |
|
T51 |
17 |
|
T30 |
18 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38868 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
1621 |
1 |
|
|
T8 |
14 |
|
T11 |
15 |
|
T12 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36907 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
3582 |
1 |
|
|
T17 |
59 |
|
T64 |
75 |
|
T113 |
73 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39229 |
1 |
|
|
T1 |
410 |
|
T2 |
78 |
|
T3 |
11 |
auto[1] |
1260 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T8 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39268 |
1 |
|
|
T1 |
413 |
|
T2 |
79 |
|
T3 |
11 |
auto[1] |
1221 |
1 |
|
|
T1 |
12 |
|
T2 |
8 |
|
T11 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39240 |
1 |
|
|
T1 |
406 |
|
T2 |
79 |
|
T3 |
11 |
auto[1] |
1249 |
1 |
|
|
T1 |
19 |
|
T2 |
8 |
|
T12 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39274 |
1 |
|
|
T1 |
405 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
1215 |
1 |
|
|
T1 |
20 |
|
T11 |
11 |
|
T19 |
27 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35395 |
1 |
|
|
T1 |
393 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
5094 |
1 |
|
|
T1 |
32 |
|
T11 |
11 |
|
T19 |
27 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36834 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
3655 |
1 |
|
|
T44 |
88 |
|
T48 |
50 |
|
T49 |
57 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40489 |
1 |
|
|
T1 |
425 |
|
T2 |
87 |
|
T3 |
11 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39236 |
1 |
|
|
T1 |
390 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
1253 |
1 |
|
|
T1 |
35 |
|
T11 |
10 |
|
T19 |
29 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39273 |
1 |
|
|
T1 |
401 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
1216 |
1 |
|
|
T1 |
24 |
|
T11 |
18 |
|
T19 |
15 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39209 |
1 |
|
|
T1 |
392 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
1280 |
1 |
|
|
T1 |
33 |
|
T11 |
13 |
|
T19 |
31 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
36638 |
1 |
|
|
T1 |
393 |
|
T2 |
87 |
|
T3 |
11 |
auto[0] |
no_err_inj |
2230 |
1 |
|
|
T1 |
32 |
|
T11 |
23 |
|
T15 |
6 |
auto[1] |
err_inj |
792 |
1 |
|
|
T8 |
7 |
|
T11 |
9 |
|
T12 |
6 |
auto[1] |
no_err_inj |
829 |
1 |
|
|
T8 |
7 |
|
T11 |
6 |
|
T12 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37745 |
1 |
|
|
T1 |
413 |
|
T2 |
79 |
|
T3 |
11 |
auto[0] |
auto[1] |
1123 |
1 |
|
|
T1 |
12 |
|
T2 |
8 |
|
T16 |
7 |
auto[1] |
auto[0] |
1523 |
1 |
|
|
T8 |
14 |
|
T11 |
14 |
|
T12 |
12 |
auto[1] |
auto[1] |
98 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T180 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37729 |
1 |
|
|
T1 |
413 |
|
T2 |
80 |
|
T3 |
11 |
auto[0] |
auto[1] |
1139 |
1 |
|
|
T1 |
12 |
|
T2 |
7 |
|
T16 |
9 |
auto[1] |
auto[0] |
1528 |
1 |
|
|
T8 |
12 |
|
T11 |
14 |
|
T12 |
13 |
auto[1] |
auto[1] |
93 |
1 |
|
|
T8 |
2 |
|
T11 |
1 |
|
T19 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37708 |
1 |
|
|
T1 |
406 |
|
T2 |
79 |
|
T3 |
11 |
auto[0] |
auto[1] |
1160 |
1 |
|
|
T1 |
19 |
|
T2 |
8 |
|
T16 |
6 |
auto[1] |
auto[0] |
1532 |
1 |
|
|
T8 |
14 |
|
T11 |
15 |
|
T12 |
12 |
auto[1] |
auto[1] |
89 |
1 |
|
|
T12 |
1 |
|
T19 |
1 |
|
T46 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37712 |
1 |
|
|
T1 |
405 |
|
T2 |
73 |
|
T3 |
11 |
auto[0] |
auto[1] |
1156 |
1 |
|
|
T1 |
20 |
|
T2 |
14 |
|
T16 |
7 |
auto[1] |
auto[0] |
1537 |
1 |
|
|
T8 |
13 |
|
T11 |
13 |
|
T12 |
12 |
auto[1] |
auto[1] |
84 |
1 |
|
|
T8 |
1 |
|
T11 |
2 |
|
T12 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37740 |
1 |
|
|
T1 |
410 |
|
T2 |
79 |
|
T3 |
11 |
auto[0] |
auto[1] |
1128 |
1 |
|
|
T1 |
15 |
|
T2 |
8 |
|
T16 |
6 |
auto[1] |
auto[0] |
1549 |
1 |
|
|
T8 |
12 |
|
T11 |
14 |
|
T12 |
13 |
auto[1] |
auto[1] |
72 |
1 |
|
|
T8 |
2 |
|
T11 |
1 |
|
T21 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37681 |
1 |
|
|
T1 |
408 |
|
T2 |
73 |
|
T3 |
11 |
auto[0] |
auto[1] |
1187 |
1 |
|
|
T1 |
17 |
|
T2 |
14 |
|
T16 |
11 |
auto[1] |
auto[0] |
1526 |
1 |
|
|
T8 |
13 |
|
T11 |
15 |
|
T12 |
12 |
auto[1] |
auto[1] |
95 |
1 |
|
|
T8 |
1 |
|
T12 |
1 |
|
T19 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30075 |
1 |
|
|
T1 |
223 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
730 |
1 |
|
|
T1 |
17 |
|
T19 |
18 |
|
T21 |
11 |
auto[1] |
auto[0] |
9227 |
1 |
|
|
T1 |
174 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
auto[1] |
457 |
1 |
|
|
T1 |
11 |
|
T11 |
14 |
|
T19 |
4 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30069 |
1 |
|
|
T1 |
227 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
736 |
1 |
|
|
T1 |
13 |
|
T19 |
21 |
|
T21 |
19 |
auto[1] |
auto[0] |
9233 |
1 |
|
|
T1 |
179 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
auto[1] |
451 |
1 |
|
|
T1 |
6 |
|
T11 |
6 |
|
T19 |
4 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29995 |
1 |
|
|
T1 |
229 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
810 |
1 |
|
|
T1 |
11 |
|
T181 |
20 |
|
T182 |
6 |
auto[1] |
auto[0] |
9094 |
1 |
|
|
T1 |
168 |
|
T2 |
87 |
|
T11 |
133 |
auto[1] |
auto[1] |
590 |
1 |
|
|
T1 |
17 |
|
T3 |
11 |
|
T19 |
6 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30044 |
1 |
|
|
T1 |
226 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
761 |
1 |
|
|
T1 |
14 |
|
T19 |
21 |
|
T21 |
13 |
auto[1] |
auto[0] |
9218 |
1 |
|
|
T1 |
177 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
auto[1] |
466 |
1 |
|
|
T1 |
8 |
|
T11 |
15 |
|
T19 |
13 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
26157 |
1 |
|
|
T1 |
217 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
4648 |
1 |
|
|
T1 |
23 |
|
T19 |
18 |
|
T39 |
97 |
auto[1] |
auto[0] |
9238 |
1 |
|
|
T1 |
176 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
auto[1] |
446 |
1 |
|
|
T1 |
9 |
|
T11 |
11 |
|
T19 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30025 |
1 |
|
|
T1 |
234 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
780 |
1 |
|
|
T1 |
6 |
|
T12 |
1 |
|
T16 |
7 |
auto[1] |
auto[0] |
9243 |
1 |
|
|
T1 |
179 |
|
T2 |
79 |
|
T3 |
11 |
auto[1] |
auto[1] |
441 |
1 |
|
|
T1 |
6 |
|
T2 |
8 |
|
T11 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29981 |
1 |
|
|
T1 |
230 |
|
T8 |
13 |
|
T11 |
3 |
auto[0] |
auto[1] |
824 |
1 |
|
|
T1 |
10 |
|
T8 |
1 |
|
T16 |
6 |
auto[1] |
auto[0] |
9248 |
1 |
|
|
T1 |
180 |
|
T2 |
78 |
|
T3 |
11 |
auto[1] |
auto[1] |
436 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T19 |
7 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30026 |
1 |
|
|
T1 |
233 |
|
T8 |
12 |
|
T11 |
3 |
auto[0] |
auto[1] |
779 |
1 |
|
|
T1 |
7 |
|
T8 |
2 |
|
T16 |
9 |
auto[1] |
auto[0] |
9231 |
1 |
|
|
T1 |
180 |
|
T2 |
80 |
|
T3 |
11 |
auto[1] |
auto[1] |
453 |
1 |
|
|
T1 |
5 |
|
T2 |
7 |
|
T11 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30036 |
1 |
|
|
T1 |
233 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
769 |
1 |
|
|
T1 |
7 |
|
T12 |
2 |
|
T16 |
10 |
auto[1] |
auto[0] |
9235 |
1 |
|
|
T1 |
173 |
|
T2 |
76 |
|
T3 |
11 |
auto[1] |
auto[1] |
449 |
1 |
|
|
T1 |
12 |
|
T2 |
11 |
|
T11 |
3 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30024 |
1 |
|
|
T1 |
231 |
|
T8 |
13 |
|
T11 |
3 |
auto[0] |
auto[1] |
781 |
1 |
|
|
T1 |
9 |
|
T8 |
1 |
|
T12 |
1 |
auto[1] |
auto[0] |
9225 |
1 |
|
|
T1 |
174 |
|
T2 |
73 |
|
T3 |
11 |
auto[1] |
auto[1] |
459 |
1 |
|
|
T1 |
11 |
|
T2 |
14 |
|
T11 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29982 |
1 |
|
|
T1 |
228 |
|
T8 |
13 |
|
T11 |
3 |
auto[0] |
auto[1] |
823 |
1 |
|
|
T1 |
12 |
|
T8 |
1 |
|
T12 |
1 |
auto[1] |
auto[0] |
9225 |
1 |
|
|
T1 |
180 |
|
T2 |
73 |
|
T3 |
11 |
auto[1] |
auto[1] |
459 |
1 |
|
|
T1 |
5 |
|
T2 |
14 |
|
T19 |
7 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30023 |
1 |
|
|
T1 |
215 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
782 |
1 |
|
|
T1 |
25 |
|
T19 |
25 |
|
T21 |
20 |
auto[1] |
auto[0] |
9186 |
1 |
|
|
T1 |
177 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
auto[1] |
498 |
1 |
|
|
T1 |
8 |
|
T11 |
13 |
|
T19 |
6 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30082 |
1 |
|
|
T1 |
223 |
|
T8 |
14 |
|
T11 |
3 |
auto[0] |
auto[1] |
723 |
1 |
|
|
T1 |
17 |
|
T19 |
12 |
|
T21 |
19 |
auto[1] |
auto[0] |
9191 |
1 |
|
|
T1 |
178 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
auto[1] |
493 |
1 |
|
|
T1 |
7 |
|
T11 |
18 |
|
T19 |
3 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29855 |
1 |
|
|
T1 |
240 |
|
T11 |
3 |
|
T16 |
68 |
auto[0] |
auto[1] |
950 |
1 |
|
|
T8 |
14 |
|
T12 |
13 |
|
T46 |
11 |
auto[1] |
auto[0] |
9013 |
1 |
|
|
T1 |
185 |
|
T2 |
87 |
|
T3 |
11 |
auto[1] |
auto[1] |
671 |
1 |
|
|
T11 |
15 |
|
T19 |
10 |
|
T21 |
14 |