Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61507699

1

T45

2685

T76

3350

T77

8337

auto[1]

1143565

1

T1

9171

T2

3724

T3

490

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61495281

1

T45

2685

T76

3350

T77

8337

auto[1]

1155983

1

T1

9086

T2

4018

T3

588

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5263760	1			T45	185		T76	89		T77	84
auto[IdleSt]	15391097	1			T45	2500		T76	3261		T77	8253
auto[ClkMuxSt]	27994	1			T1	273		T3	11		T8	7
auto[CntIncrSt]	27807	1			T1	272		T3	11		T8	7
auto[CntProgSt]	1701191	1			T1	6682		T3	22		T8	36
auto[TransCheckSt]	22277	1			T1	192		T8	7		T11	92
auto[TokenHashSt]	19424441	1			T1	486993		T8	706		T11	3349
auto[FlashRmaSt]	21452	1			T1	133		T8	13		T11	109
auto[TokenCheck0St]	9758	1			T1	72		T8	7		T11	47
auto[TokenCheck1St]	7060	1			T1	57		T8	7		T11	42
auto[TransProgSt]	365591	1			T1	1794		T8	40		T11	1465
auto[PostTransSt]	8726237	1			T1	91954		T3	13872		T8	1259
auto[ScrapSt]	163360	1			T79	219		T83	484		T96	47178
auto[EscalateSt]	4752003	1			T1	47955		T2	51860		T3	9527
auto[InvalidSt]	6745904	1			T1	74703		T2	168462		T8	484

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1332	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6745904	1			T1	74703		T2	168462		T8	484
EscalateSt	4752003	1			T1	47955		T2	51860		T3	9527
ScrapSt	163360	1			T79	219		T83	484		T96	47178
PostTransSt	8726237	1			T1	91954		T3	13872		T8	1259
TransProgSt	365591	1			T1	1794		T8	40		T11	1465
TokenCheck1St	7060	1			T1	57		T8	7		T11	42
TokenCheck0St	9758	1			T1	72		T8	7		T11	47
FlashRmaSt	21452	1			T1	133		T8	13		T11	109
TokenHashSt	19424441	1			T1	486993		T8	706		T11	3349
TransCheckSt	22277	1			T1	192		T8	7		T11	92
CntProgSt	1701191	1			T1	6682		T3	22		T8	36
CntIncrSt	27807	1			T1	272		T3	11		T8	7
ClkMuxSt	27994	1			T1	273		T3	11		T8	7
IdleSt	15391097	1			T45	2500		T76	3261		T77	8253
ResetSt	5263760	1			T45	185		T76	89		T77	84
arcs[ResetSt=>IdleSt]	41144	1			T45	3		T76	1		T77	1
arcs[IdleSt=>ScrapSt]	229	1			T79	1		T83	1		T96	1
arcs[IdleSt=>ClkMuxSt]	27870	1			T1	272		T3	11		T8	7
arcs[ClkMuxSt=>CntIncrSt]	27807	1			T1	272		T3	11		T8	7
arcs[CntIncrSt=>PostTransSt]	1216	1			T1	24		T11	18		T19	15
arcs[CntIncrSt=>CntProgSt]	26536	1			T1	248		T3	11		T8	7
arcs[CntProgSt=>PostTransSt]	3341	1			T1	56		T3	11		T11	14
arcs[CntProgSt=>TransCheckSt]	22277	1			T1	192		T8	7		T11	92
arcs[TransCheckSt=>PostTransSt]	3110	1			T1	33		T11	13		T19	31
arcs[TransCheckSt=>TokenHashSt]	19025	1			T1	159		T8	7		T11	79
arcs[TokenHashSt=>PostTransSt]	8467	1			T1	87		T11	32		T19	83
arcs[TokenHashSt=>FlashRmaSt]	9851	1			T1	72		T8	7		T11	47
arcs[FlashRmaSt=>TokenCheck0St]	9758	1			T1	72		T8	7		T11	47
arcs[TokenCheck0St=>PostTransSt]	2671	1			T1	15		T11	5		T19	24
arcs[TokenCheck0St=>TokenCheck1St]	7060	1			T1	57		T8	7		T11	42
arcs[TokenCheck1St=>PostTransSt]	587	1			T1	3		T21	1		T46	1
arcs[TransProgSt=>PostTransSt]	5659	1			T1	54		T8	7		T11	42
arcs[IdleSt=>EscalateSt]	201	1			T64	5		T176	5		T177	4
arcs[ClkMuxSt=>EscalateSt]	63	1			T64	3		T114	2		T177	3
arcs[CntIncrSt=>EscalateSt]	55	1			T17	1		T64	1		T114	1
arcs[CntProgSt=>EscalateSt]	918	1			T17	25		T64	12		T113	29
arcs[TransCheckSt=>EscalateSt]	142	1			T64	9		T113	2		T114	1
arcs[TokenHashSt=>EscalateSt]	702	1			T17	3		T64	17		T113	8
arcs[FlashRmaSt=>EscalateSt]	93	1			T17	1		T64	1		T113	1
arcs[TokenCheck0St=>EscalateSt]	27	1			T114	4		T176	1		T178	1
arcs[TokenCheck1St=>EscalateSt]	145	1			T17	3		T64	5		T113	5
arcs[TransProgSt=>EscalateSt]	669	1			T17	19		T64	13		T113	25
arcs[PostTransSt=>EscalateSt]	3646	1			T1	56		T3	11		T11	14
arcs[InvalidSt=>EscalateSt]	10668	1			T1	129		T2	79		T8	7

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5263609	1			T45	185		T76	89		T77	84
auto[0]	auto[IdleSt]	15390967	1			T45	2500		T76	3261		T77	8253
auto[0]	auto[ClkMuxSt]	27953	1			T1	273		T3	11		T8	7
auto[0]	auto[CntIncrSt]	27770	1			T1	272		T3	11		T8	7
auto[0]	auto[CntProgSt]	1700585	1			T1	6682		T3	22		T8	36
auto[0]	auto[TransCheckSt]	22187	1			T1	192		T8	7		T11	92
auto[0]	auto[TokenHashSt]	19423993	1			T1	486993		T8	706		T11	3349
auto[0]	auto[FlashRmaSt]	21394	1			T1	133		T8	13		T11	109
auto[0]	auto[TokenCheck0St]	9737	1			T1	72		T8	7		T11	47
auto[0]	auto[TokenCheck1St]	6967	1			T1	57		T8	7		T11	42
auto[0]	auto[TransProgSt]	365153	1			T1	1794		T8	40		T11	1465
auto[0]	auto[PostTransSt]	8724360	1			T1	91926		T3	13867		T8	1259
auto[0]	auto[ScrapSt]	163319	1			T79	219		T83	484		T96	47178
auto[0]	auto[EscalateSt]	3617810	1			T1	38877		T2	48174		T3	9042
auto[0]	auto[InvalidSt]	6740563	1			T1	74638		T2	168424		T8	481
auto[1]	auto[ResetSt]	151	1			T17	3		T64	3		T113	2
auto[1]	auto[IdleSt]	130	1			T64	3		T176	3		T177	3
auto[1]	auto[ClkMuxSt]	41	1			T64	2		T114	1		T177	2
auto[1]	auto[CntIncrSt]	37	1			T17	1		T114	1		T176	1
auto[1]	auto[CntProgSt]	606	1			T17	14		T64	6		T113	16
auto[1]	auto[TransCheckSt]	90	1			T64	8		T114	1		T176	1
auto[1]	auto[TokenHashSt]	448	1			T17	2		T64	8		T113	4
auto[1]	auto[FlashRmaSt]	58	1			T113	1		T176	1		T178	1
auto[1]	auto[TokenCheck0St]	21	1			T114	2		T176	1		T178	1
auto[1]	auto[TokenCheck1St]	93	1			T17	2		T64	4		T113	3
auto[1]	auto[TransProgSt]	438	1			T17	8		T64	10		T113	19
auto[1]	auto[PostTransSt]	1877	1			T1	28		T3	5		T11	7
auto[1]	auto[ScrapSt]	41	1			T17	1		T114	2		T178	1
auto[1]	auto[EscalateSt]	1134193	1			T1	9078		T2	3686		T3	485
auto[1]	auto[InvalidSt]	5341	1			T1	65		T2	38		T8	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5263612	1			T45	185		T76	89		T77	84
auto[0]	auto[IdleSt]	15390953	1			T45	2500		T76	3261		T77	8253
auto[0]	auto[ClkMuxSt]	27950	1			T1	273		T3	11		T8	7
auto[0]	auto[CntIncrSt]	27771	1			T1	272		T3	11		T8	7
auto[0]	auto[CntProgSt]	1700573	1			T1	6682		T3	22		T8	36
auto[0]	auto[TransCheckSt]	22186	1			T1	192		T8	7		T11	92
auto[0]	auto[TokenHashSt]	19423944	1			T1	486993		T8	706		T11	3349
auto[0]	auto[FlashRmaSt]	21386	1			T1	133		T8	13		T11	109
auto[0]	auto[TokenCheck0St]	9740	1			T1	72		T8	7		T11	47
auto[0]	auto[TokenCheck1St]	6964	1			T1	57		T8	7		T11	42
auto[0]	auto[TransProgSt]	365141	1			T1	1794		T8	40		T11	1465
auto[0]	auto[PostTransSt]	8724371	1			T1	91926		T3	13866		T8	1259
auto[0]	auto[ScrapSt]	163317	1			T79	219		T83	484		T96	47178
auto[0]	auto[EscalateSt]	3605464	1			T1	38961		T2	47883		T3	8945
auto[0]	auto[InvalidSt]	6740577	1			T1	74639		T2	168421		T8	480
auto[1]	auto[ResetSt]	148	1			T17	2		T64	2		T114	5
auto[1]	auto[IdleSt]	144	1			T64	4		T176	2		T177	3
auto[1]	auto[ClkMuxSt]	44	1			T64	2		T114	1		T177	3
auto[1]	auto[CntIncrSt]	36	1			T64	1		T114	1		T177	1
auto[1]	auto[CntProgSt]	618	1			T17	16		T64	11		T113	21
auto[1]	auto[TransCheckSt]	91	1			T64	4		T113	2		T114	1
auto[1]	auto[TokenHashSt]	497	1			T17	3		T64	11		T113	6
auto[1]	auto[FlashRmaSt]	66	1			T17	1		T64	1		T113	1
auto[1]	auto[TokenCheck0St]	18	1			T114	3		T176	1		T178	1
auto[1]	auto[TokenCheck1St]	96	1			T17	2		T64	3		T113	2
auto[1]	auto[TransProgSt]	450	1			T17	16		T64	11		T113	15
auto[1]	auto[PostTransSt]	1866	1			T1	28		T3	6		T11	7
auto[1]	auto[ScrapSt]	43	1			T17	1		T178	1		T179	1
auto[1]	auto[EscalateSt]	1146539	1			T1	8994		T2	3977		T3	582
auto[1]	auto[InvalidSt]	5327	1			T1	64		T2	41		T8	4