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 LINE       1286
 EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T78,T79
1	0	1	Covered	T45,T76,T77
1	1	0	Covered	T123
1	1	1	Covered	T1,T2,T3

 LINE       1287
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T78,T79
1	0	1	Covered	T45,T76,T77
1	1	0	Covered	T83
1	1	1	Covered	T1,T2,T3

 LINE       1288
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T78,T79
1	0	1	Covered	T45,T76,T77
1	1	0	Covered	T129,T119,T91
1	1	1	Covered	T1,T2,T3

 LINE       1289
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T78,T79
1	0	1	Covered	T45,T76,T77
1	1	0	Covered	T79
1	1	1	Covered	T1,T2,T3

 LINE       1290
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T78,T79
1	0	1	Covered	T45,T76,T77
1	1	0	Covered	T93,T123,T121
1	1	1	Covered	T1,T2,T3

 LINE       1291
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T78,T79
1	0	1	Covered	T45,T76,T77
1	1	0	Covered	T119,T122
1	1	1	Covered	T1,T2,T3