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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.38 97.29 95.70 91.98 100.00 95.93 98.73 95.00


Total test records in report: 981
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T755 /workspace/coverage/default/41.lc_ctrl_stress_all.2675827061 Jan 24 08:50:52 PM PST 24 Jan 24 08:52:17 PM PST 24 3125474685 ps
T756 /workspace/coverage/default/26.lc_ctrl_sec_mubi.2662019444 Jan 24 08:46:11 PM PST 24 Jan 24 08:46:28 PM PST 24 314280938 ps
T757 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3064094530 Jan 24 08:42:21 PM PST 24 Jan 24 08:42:34 PM PST 24 1298193135 ps
T758 /workspace/coverage/default/29.lc_ctrl_state_post_trans.2133296246 Jan 24 08:47:14 PM PST 24 Jan 24 08:47:22 PM PST 24 674489725 ps
T759 /workspace/coverage/default/19.lc_ctrl_sec_mubi.2586066767 Jan 24 08:44:29 PM PST 24 Jan 24 08:44:57 PM PST 24 1317663897 ps
T760 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4186984574 Jan 24 09:02:09 PM PST 24 Jan 24 09:02:28 PM PST 24 2544874773 ps
T761 /workspace/coverage/default/31.lc_ctrl_errors.1332089658 Jan 24 08:47:47 PM PST 24 Jan 24 08:48:01 PM PST 24 592168245 ps
T762 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2583561502 Jan 25 01:21:21 AM PST 24 Jan 25 01:21:37 AM PST 24 254242215 ps
T763 /workspace/coverage/default/26.lc_ctrl_alert_test.4107122692 Jan 24 09:43:46 PM PST 24 Jan 24 09:43:50 PM PST 24 36082263 ps
T764 /workspace/coverage/default/21.lc_ctrl_state_post_trans.2454434296 Jan 24 08:44:54 PM PST 24 Jan 24 08:45:04 PM PST 24 281615460 ps
T765 /workspace/coverage/default/2.lc_ctrl_prog_failure.1737194268 Jan 24 11:39:45 PM PST 24 Jan 24 11:39:49 PM PST 24 63410814 ps
T766 /workspace/coverage/default/8.lc_ctrl_state_post_trans.3367211411 Jan 24 08:38:55 PM PST 24 Jan 24 08:39:03 PM PST 24 144978411 ps
T767 /workspace/coverage/default/39.lc_ctrl_smoke.1415787318 Jan 24 08:49:57 PM PST 24 Jan 24 08:50:01 PM PST 24 107369836 ps
T768 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4000611533 Jan 24 08:43:05 PM PST 24 Jan 24 08:43:33 PM PST 24 1358821342 ps
T769 /workspace/coverage/default/2.lc_ctrl_jtag_errors.109789051 Jan 24 09:23:22 PM PST 24 Jan 24 09:24:23 PM PST 24 11912830088 ps
T770 /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2109705610 Jan 25 12:05:45 AM PST 24 Jan 25 12:06:01 AM PST 24 432936967 ps
T771 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1036802667 Jan 24 11:18:51 PM PST 24 Jan 24 11:19:03 PM PST 24 779726318 ps
T772 /workspace/coverage/default/9.lc_ctrl_alert_test.770948293 Jan 24 08:56:17 PM PST 24 Jan 24 08:56:19 PM PST 24 12442426 ps
T773 /workspace/coverage/default/42.lc_ctrl_jtag_access.2927373142 Jan 24 08:50:58 PM PST 24 Jan 24 08:51:02 PM PST 24 792019863 ps
T774 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.237602568 Jan 24 08:45:30 PM PST 24 Jan 24 08:45:42 PM PST 24 8994315682 ps
T775 /workspace/coverage/default/22.lc_ctrl_alert_test.30949961 Jan 24 08:58:14 PM PST 24 Jan 24 08:58:17 PM PST 24 22610096 ps
T776 /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2125276153 Jan 24 08:39:09 PM PST 24 Jan 24 08:39:42 PM PST 24 6367743699 ps
T777 /workspace/coverage/default/36.lc_ctrl_alert_test.3135829804 Jan 24 08:49:16 PM PST 24 Jan 24 08:49:18 PM PST 24 23439045 ps
T778 /workspace/coverage/default/45.lc_ctrl_state_failure.2912462723 Jan 24 09:03:25 PM PST 24 Jan 24 09:03:47 PM PST 24 3947537883 ps
T779 /workspace/coverage/default/23.lc_ctrl_stress_all.2394166893 Jan 24 08:45:36 PM PST 24 Jan 24 08:46:53 PM PST 24 3659296859 ps
T780 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1741152284 Jan 24 08:41:10 PM PST 24 Jan 24 08:41:21 PM PST 24 1032984432 ps
T781 /workspace/coverage/default/18.lc_ctrl_jtag_errors.607736253 Jan 24 08:43:47 PM PST 24 Jan 24 08:44:25 PM PST 24 3913584633 ps
T782 /workspace/coverage/default/6.lc_ctrl_state_failure.1700182220 Jan 24 08:37:11 PM PST 24 Jan 24 08:37:43 PM PST 24 1166664109 ps
T783 /workspace/coverage/default/45.lc_ctrl_smoke.745677471 Jan 24 08:51:46 PM PST 24 Jan 24 08:51:57 PM PST 24 49417380 ps
T784 /workspace/coverage/default/24.lc_ctrl_stress_all.862663870 Jan 24 08:45:57 PM PST 24 Jan 24 08:47:34 PM PST 24 9643582546 ps
T785 /workspace/coverage/default/41.lc_ctrl_sec_mubi.4060961883 Jan 24 08:50:38 PM PST 24 Jan 24 08:50:52 PM PST 24 659859729 ps
T786 /workspace/coverage/default/34.lc_ctrl_smoke.3996644450 Jan 24 08:48:33 PM PST 24 Jan 24 08:48:35 PM PST 24 123685524 ps
T787 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2326552081 Jan 24 08:34:18 PM PST 24 Jan 24 08:34:20 PM PST 24 23269820 ps
T788 /workspace/coverage/default/42.lc_ctrl_security_escalation.1609659654 Jan 24 08:50:57 PM PST 24 Jan 24 08:51:07 PM PST 24 1479499826 ps
T789 /workspace/coverage/default/8.lc_ctrl_smoke.805607837 Jan 24 09:02:00 PM PST 24 Jan 24 09:02:08 PM PST 24 517496773 ps
T790 /workspace/coverage/default/40.lc_ctrl_alert_test.2262233673 Jan 24 08:50:42 PM PST 24 Jan 24 08:50:44 PM PST 24 26143046 ps
T791 /workspace/coverage/default/20.lc_ctrl_jtag_access.3701503460 Jan 24 09:04:14 PM PST 24 Jan 24 09:04:26 PM PST 24 694221720 ps
T792 /workspace/coverage/default/35.lc_ctrl_state_post_trans.1190428795 Jan 24 09:07:22 PM PST 24 Jan 24 09:07:31 PM PST 24 73857677 ps
T793 /workspace/coverage/default/18.lc_ctrl_security_escalation.2062449749 Jan 24 08:43:40 PM PST 24 Jan 24 08:44:04 PM PST 24 1791618581 ps
T794 /workspace/coverage/default/34.lc_ctrl_jtag_access.3795521036 Jan 24 08:48:41 PM PST 24 Jan 24 08:48:47 PM PST 24 1252821959 ps
T795 /workspace/coverage/default/27.lc_ctrl_stress_all.338093609 Jan 24 08:46:31 PM PST 24 Jan 24 08:47:38 PM PST 24 2312689241 ps
T796 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1828726638 Jan 24 09:38:57 PM PST 24 Jan 24 09:39:07 PM PST 24 293641068 ps
T797 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2486650288 Jan 24 09:04:51 PM PST 24 Jan 24 09:05:07 PM PST 24 873836313 ps
T798 /workspace/coverage/default/0.lc_ctrl_alert_test.708850076 Jan 24 08:33:02 PM PST 24 Jan 24 08:33:04 PM PST 24 20271293 ps
T799 /workspace/coverage/default/29.lc_ctrl_sec_mubi.851526891 Jan 24 08:47:16 PM PST 24 Jan 24 08:47:31 PM PST 24 1792964582 ps
T800 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2588879077 Jan 24 10:31:58 PM PST 24 Jan 24 10:32:11 PM PST 24 1866501012 ps
T801 /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.188006084 Jan 24 08:46:40 PM PST 24 Jan 24 08:46:43 PM PST 24 32317506 ps
T802 /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1324557511 Jan 25 03:35:18 AM PST 24 Jan 25 03:35:28 AM PST 24 3630576197 ps
T803 /workspace/coverage/default/48.lc_ctrl_prog_failure.2918388726 Jan 24 09:48:58 PM PST 24 Jan 24 09:49:02 PM PST 24 284034886 ps
T804 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3749895671 Jan 24 08:43:07 PM PST 24 Jan 24 08:44:50 PM PST 24 18474562825 ps
T805 /workspace/coverage/default/32.lc_ctrl_alert_test.1324177592 Jan 25 12:02:37 AM PST 24 Jan 25 12:02:40 AM PST 24 60836124 ps
T806 /workspace/coverage/default/7.lc_ctrl_jtag_access.2145168363 Jan 24 08:38:28 PM PST 24 Jan 24 08:38:40 PM PST 24 2621991413 ps
T807 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1024815444 Jan 24 08:43:17 PM PST 24 Jan 24 08:43:53 PM PST 24 231353125 ps
T808 /workspace/coverage/default/21.lc_ctrl_errors.3484328306 Jan 24 08:44:59 PM PST 24 Jan 24 08:45:17 PM PST 24 562529423 ps
T809 /workspace/coverage/default/23.lc_ctrl_smoke.2652694339 Jan 24 08:57:10 PM PST 24 Jan 24 08:57:17 PM PST 24 70018966 ps
T810 /workspace/coverage/default/20.lc_ctrl_security_escalation.333509913 Jan 24 08:44:43 PM PST 24 Jan 24 08:45:00 PM PST 24 459525854 ps
T811 /workspace/coverage/default/43.lc_ctrl_sec_mubi.2846752304 Jan 24 08:51:13 PM PST 24 Jan 24 08:51:32 PM PST 24 1409219932 ps
T812 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1945471298 Jan 24 08:42:30 PM PST 24 Jan 24 08:42:33 PM PST 24 45090272 ps
T813 /workspace/coverage/default/43.lc_ctrl_stress_all.1042594498 Jan 24 08:51:13 PM PST 24 Jan 24 08:51:32 PM PST 24 2305072932 ps
T814 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1119574209 Jan 24 08:48:43 PM PST 24 Jan 24 08:48:57 PM PST 24 1007793838 ps
T815 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1688634008 Jan 24 08:41:10 PM PST 24 Jan 24 08:41:21 PM PST 24 4666222888 ps
T816 /workspace/coverage/default/33.lc_ctrl_sec_mubi.1933203120 Jan 24 08:48:34 PM PST 24 Jan 24 08:48:51 PM PST 24 1197733620 ps
T817 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3881860339 Jan 24 08:43:08 PM PST 24 Jan 24 08:43:34 PM PST 24 928107841 ps
T818 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2896568478 Jan 24 08:32:34 PM PST 24 Jan 24 08:32:46 PM PST 24 1441590112 ps
T819 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4086863669 Jan 24 08:48:57 PM PST 24 Jan 24 08:49:06 PM PST 24 677950943 ps
T820 /workspace/coverage/default/41.lc_ctrl_prog_failure.2804982147 Jan 24 08:50:43 PM PST 24 Jan 24 08:50:45 PM PST 24 20196014 ps
T821 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2176476597 Jan 24 08:33:43 PM PST 24 Jan 24 08:34:02 PM PST 24 1233252994 ps
T822 /workspace/coverage/default/39.lc_ctrl_prog_failure.1736175555 Jan 24 08:49:55 PM PST 24 Jan 24 08:49:59 PM PST 24 170559835 ps
T823 /workspace/coverage/default/12.lc_ctrl_state_failure.2850782768 Jan 24 08:40:57 PM PST 24 Jan 24 08:41:28 PM PST 24 249520862 ps
T824 /workspace/coverage/default/4.lc_ctrl_smoke.3310094413 Jan 24 08:35:30 PM PST 24 Jan 24 08:35:32 PM PST 24 41525981 ps
T825 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3744301306 Jan 24 09:17:24 PM PST 24 Jan 24 09:17:33 PM PST 24 990857442 ps
T826 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3234821742 Jan 24 08:44:55 PM PST 24 Jan 24 08:44:57 PM PST 24 28527240 ps
T827 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2166954018 Jan 24 08:48:07 PM PST 24 Jan 24 08:48:21 PM PST 24 342040612 ps
T828 /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2681728407 Jan 24 08:47:36 PM PST 24 Jan 24 08:47:38 PM PST 24 40381770 ps
T829 /workspace/coverage/default/20.lc_ctrl_stress_all.3895720898 Jan 24 08:44:56 PM PST 24 Jan 24 08:49:23 PM PST 24 54896625315 ps
T830 /workspace/coverage/default/45.lc_ctrl_sec_mubi.182965393 Jan 24 09:03:58 PM PST 24 Jan 24 09:04:26 PM PST 24 1728412418 ps
T831 /workspace/coverage/default/25.lc_ctrl_errors.1620249464 Jan 25 01:08:41 AM PST 24 Jan 25 01:08:55 AM PST 24 289067349 ps
T832 /workspace/coverage/default/21.lc_ctrl_alert_test.475457104 Jan 24 08:44:59 PM PST 24 Jan 24 08:45:03 PM PST 24 45215364 ps
T833 /workspace/coverage/default/29.lc_ctrl_state_failure.353909472 Jan 24 08:47:11 PM PST 24 Jan 24 08:47:28 PM PST 24 836678598 ps
T834 /workspace/coverage/default/7.lc_ctrl_stress_all.2384630478 Jan 24 10:28:27 PM PST 24 Jan 24 10:37:08 PM PST 24 143977957286 ps
T835 /workspace/coverage/default/43.lc_ctrl_alert_test.390862932 Jan 24 08:51:18 PM PST 24 Jan 24 08:51:20 PM PST 24 44107432 ps
T836 /workspace/coverage/default/47.lc_ctrl_state_post_trans.4150718156 Jan 24 11:24:31 PM PST 24 Jan 24 11:24:39 PM PST 24 387701733 ps
T837 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1692988132 Jan 24 08:42:47 PM PST 24 Jan 24 08:43:04 PM PST 24 721214684 ps
T838 /workspace/coverage/default/48.lc_ctrl_errors.2085152601 Jan 24 09:05:17 PM PST 24 Jan 24 09:05:25 PM PST 24 3223459511 ps
T839 /workspace/coverage/default/11.lc_ctrl_jtag_errors.3550510140 Jan 24 08:40:40 PM PST 24 Jan 24 08:41:32 PM PST 24 1889441298 ps
T840 /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3939772222 Jan 24 08:33:56 PM PST 24 Jan 24 08:34:13 PM PST 24 567605771 ps
T841 /workspace/coverage/default/36.lc_ctrl_errors.2127909092 Jan 24 09:21:57 PM PST 24 Jan 24 09:22:08 PM PST 24 1405242380 ps
T842 /workspace/coverage/default/13.lc_ctrl_state_post_trans.3658633717 Jan 24 09:02:22 PM PST 24 Jan 24 09:02:30 PM PST 24 116559795 ps
T843 /workspace/coverage/default/49.lc_ctrl_jtag_access.3546099858 Jan 24 08:52:58 PM PST 24 Jan 24 08:53:07 PM PST 24 2863496764 ps
T844 /workspace/coverage/default/18.lc_ctrl_sec_mubi.2864611247 Jan 24 08:43:47 PM PST 24 Jan 24 08:44:13 PM PST 24 1743134894 ps
T845 /workspace/coverage/default/21.lc_ctrl_smoke.4075397368 Jan 24 08:44:59 PM PST 24 Jan 24 08:45:05 PM PST 24 519526431 ps
T846 /workspace/coverage/default/20.lc_ctrl_state_failure.1711265000 Jan 24 08:44:44 PM PST 24 Jan 24 08:45:09 PM PST 24 1607914646 ps
T847 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3580570049 Jan 24 08:38:30 PM PST 24 Jan 24 08:38:39 PM PST 24 407140731 ps
T848 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.286958358 Jan 24 08:39:35 PM PST 24 Jan 24 08:39:47 PM PST 24 2261306649 ps
T849 /workspace/coverage/default/4.lc_ctrl_security_escalation.1532283175 Jan 24 08:35:51 PM PST 24 Jan 24 08:36:04 PM PST 24 619346633 ps
T850 /workspace/coverage/default/21.lc_ctrl_jtag_access.572804855 Jan 24 08:44:52 PM PST 24 Jan 24 08:44:55 PM PST 24 400110928 ps
T851 /workspace/coverage/default/13.lc_ctrl_alert_test.112063869 Jan 24 08:41:48 PM PST 24 Jan 24 08:41:50 PM PST 24 224818105 ps
T852 /workspace/coverage/default/15.lc_ctrl_state_failure.358655668 Jan 24 08:54:50 PM PST 24 Jan 24 08:55:15 PM PST 24 282189831 ps
T853 /workspace/coverage/default/37.lc_ctrl_jtag_access.248192381 Jan 24 08:49:25 PM PST 24 Jan 24 08:49:36 PM PST 24 348784954 ps
T854 /workspace/coverage/default/32.lc_ctrl_sec_mubi.55634368 Jan 24 08:48:14 PM PST 24 Jan 24 08:48:27 PM PST 24 401250774 ps
T855 /workspace/coverage/default/36.lc_ctrl_prog_failure.44117437 Jan 24 08:49:19 PM PST 24 Jan 24 08:49:23 PM PST 24 65732537 ps
T856 /workspace/coverage/default/36.lc_ctrl_jtag_access.2259241365 Jan 24 09:06:58 PM PST 24 Jan 24 09:07:16 PM PST 24 4671618683 ps
T857 /workspace/coverage/default/5.lc_ctrl_state_failure.219855858 Jan 24 08:36:22 PM PST 24 Jan 24 08:36:52 PM PST 24 867366187 ps
T858 /workspace/coverage/default/41.lc_ctrl_jtag_access.2104619288 Jan 24 08:50:38 PM PST 24 Jan 24 08:50:57 PM PST 24 2945968676 ps
T859 /workspace/coverage/default/18.lc_ctrl_prog_failure.3653467019 Jan 24 08:43:32 PM PST 24 Jan 24 08:43:57 PM PST 24 821500010 ps
T860 /workspace/coverage/default/22.lc_ctrl_prog_failure.3490118660 Jan 24 08:45:08 PM PST 24 Jan 24 08:45:11 PM PST 24 117016086 ps
T861 /workspace/coverage/default/15.lc_ctrl_state_post_trans.3919525736 Jan 24 08:42:12 PM PST 24 Jan 24 08:42:25 PM PST 24 151893865 ps
T862 /workspace/coverage/default/24.lc_ctrl_sec_mubi.2196167626 Jan 24 08:45:57 PM PST 24 Jan 24 08:46:12 PM PST 24 1038059510 ps
T863 /workspace/coverage/default/18.lc_ctrl_errors.3209119127 Jan 24 08:43:29 PM PST 24 Jan 24 08:44:07 PM PST 24 448335584 ps
T864 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2208266726 Jan 24 08:48:54 PM PST 24 Jan 24 08:48:56 PM PST 24 24013718 ps
T865 /workspace/coverage/default/16.lc_ctrl_sec_mubi.3989413712 Jan 24 08:42:50 PM PST 24 Jan 24 08:43:05 PM PST 24 348969406 ps
T866 /workspace/coverage/default/9.lc_ctrl_errors.2708107266 Jan 24 08:39:25 PM PST 24 Jan 24 08:39:43 PM PST 24 2736800302 ps
T867 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3692934904 Jan 24 08:42:51 PM PST 24 Jan 24 08:43:04 PM PST 24 1708097028 ps
T868 /workspace/coverage/default/23.lc_ctrl_errors.2727212397 Jan 24 09:51:23 PM PST 24 Jan 24 09:51:35 PM PST 24 1005233838 ps
T869 /workspace/coverage/default/1.lc_ctrl_alert_test.3640829043 Jan 24 08:34:05 PM PST 24 Jan 24 08:34:08 PM PST 24 46783138 ps
T870 /workspace/coverage/default/23.lc_ctrl_state_failure.1141046750 Jan 24 08:45:16 PM PST 24 Jan 24 08:45:47 PM PST 24 400481093 ps
T871 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2019034857 Jan 24 08:39:12 PM PST 24 Jan 24 08:39:27 PM PST 24 7082466044 ps
T872 /workspace/coverage/default/23.lc_ctrl_sec_mubi.2629630467 Jan 24 09:14:00 PM PST 24 Jan 24 09:14:26 PM PST 24 4571970132 ps
T873 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2786698653 Jan 24 08:40:12 PM PST 24 Jan 24 08:40:21 PM PST 24 2229253468 ps
T874 /workspace/coverage/default/7.lc_ctrl_jtag_priority.50371196 Jan 24 08:38:32 PM PST 24 Jan 24 08:38:36 PM PST 24 171309295 ps
T875 /workspace/coverage/default/41.lc_ctrl_alert_test.974912140 Jan 24 08:50:54 PM PST 24 Jan 24 08:50:55 PM PST 24 21270837 ps
T876 /workspace/coverage/default/4.lc_ctrl_state_failure.956283811 Jan 24 08:35:38 PM PST 24 Jan 24 08:36:00 PM PST 24 651003793 ps
T877 /workspace/coverage/default/33.lc_ctrl_smoke.2800439840 Jan 24 08:48:19 PM PST 24 Jan 24 08:48:21 PM PST 24 92593300 ps
T878 /workspace/coverage/default/42.lc_ctrl_state_failure.4195984550 Jan 24 08:50:58 PM PST 24 Jan 24 08:51:29 PM PST 24 224694402 ps
T879 /workspace/coverage/default/26.lc_ctrl_jtag_access.123531114 Jan 24 08:46:13 PM PST 24 Jan 24 08:46:24 PM PST 24 300741027 ps
T880 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.220032576 Jan 24 08:38:17 PM PST 24 Jan 24 08:38:23 PM PST 24 2154674455 ps
T881 /workspace/coverage/default/7.lc_ctrl_state_post_trans.2811966414 Jan 24 08:38:20 PM PST 24 Jan 24 08:38:24 PM PST 24 60091013 ps
T882 /workspace/coverage/default/10.lc_ctrl_state_post_trans.2600630146 Jan 24 08:40:03 PM PST 24 Jan 24 08:40:14 PM PST 24 205639525 ps
T883 /workspace/coverage/default/47.lc_ctrl_security_escalation.3637174441 Jan 24 08:52:17 PM PST 24 Jan 24 08:52:30 PM PST 24 526857355 ps
T116 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1445636117 Jan 24 09:17:18 PM PST 24 Jan 24 09:18:29 PM PST 24 6694319559 ps
T884 /workspace/coverage/default/0.lc_ctrl_state_failure.1804903184 Jan 24 08:32:04 PM PST 24 Jan 24 08:32:21 PM PST 24 208347967 ps
T885 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1413777887 Jan 24 08:33:20 PM PST 24 Jan 24 08:33:21 PM PST 24 37678331 ps
T886 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3284221981 Jan 24 08:43:45 PM PST 24 Jan 24 08:44:12 PM PST 24 490861793 ps
T887 /workspace/coverage/default/2.lc_ctrl_stress_all.2710597996 Jan 24 08:34:47 PM PST 24 Jan 24 08:36:59 PM PST 24 22548668924 ps
T888 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1181467298 Jan 24 08:42:09 PM PST 24 Jan 24 08:42:24 PM PST 24 466740361 ps
T889 /workspace/coverage/default/1.lc_ctrl_jtag_access.1408113836 Jan 24 09:20:53 PM PST 24 Jan 24 09:20:55 PM PST 24 42363148 ps
T890 /workspace/coverage/default/25.lc_ctrl_sec_mubi.3547030588 Jan 24 08:46:10 PM PST 24 Jan 24 08:46:27 PM PST 24 2572729182 ps
T891 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4198781483 Jan 24 08:48:02 PM PST 24 Jan 24 08:48:20 PM PST 24 1904335980 ps
T892 /workspace/coverage/default/23.lc_ctrl_alert_test.4005161374 Jan 24 08:45:42 PM PST 24 Jan 24 08:45:45 PM PST 24 28823171 ps
T893 /workspace/coverage/default/12.lc_ctrl_prog_failure.2454348641 Jan 24 08:41:03 PM PST 24 Jan 24 08:41:07 PM PST 24 144847091 ps
T894 /workspace/coverage/default/44.lc_ctrl_security_escalation.2645052648 Jan 24 08:51:29 PM PST 24 Jan 24 08:51:37 PM PST 24 247841795 ps
T895 /workspace/coverage/default/15.lc_ctrl_stress_all.3711871660 Jan 24 08:42:30 PM PST 24 Jan 24 08:43:30 PM PST 24 2677306500 ps
T896 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2242098549 Jan 24 08:51:59 PM PST 24 Jan 24 08:52:11 PM PST 24 1518327519 ps
T897 /workspace/coverage/default/49.lc_ctrl_security_escalation.1523443970 Jan 24 08:52:56 PM PST 24 Jan 24 08:53:07 PM PST 24 457773418 ps
T898 /workspace/coverage/default/26.lc_ctrl_state_failure.144345459 Jan 24 08:46:10 PM PST 24 Jan 24 08:46:38 PM PST 24 467402702 ps
T899 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2998074420 Jan 24 08:51:20 PM PST 24 Jan 24 08:51:22 PM PST 24 32553193 ps
T900 /workspace/coverage/default/48.lc_ctrl_smoke.2144704253 Jan 24 08:52:25 PM PST 24 Jan 24 08:52:29 PM PST 24 446609725 ps
T901 /workspace/coverage/default/13.lc_ctrl_jtag_errors.1530769650 Jan 24 08:41:37 PM PST 24 Jan 24 08:42:43 PM PST 24 9849596972 ps
T902 /workspace/coverage/default/11.lc_ctrl_alert_test.1925016195 Jan 24 08:40:53 PM PST 24 Jan 24 08:40:55 PM PST 24 66662101 ps
T903 /workspace/coverage/default/6.lc_ctrl_sec_mubi.1084612146 Jan 24 08:37:46 PM PST 24 Jan 24 08:38:00 PM PST 24 432937731 ps
T904 /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4131450444 Jan 24 10:20:48 PM PST 24 Jan 24 10:20:54 PM PST 24 322838908 ps
T905 /workspace/coverage/default/39.lc_ctrl_errors.432218840 Jan 24 08:49:54 PM PST 24 Jan 24 08:50:12 PM PST 24 1837037222 ps
T906 /workspace/coverage/default/41.lc_ctrl_security_escalation.524353859 Jan 24 08:50:39 PM PST 24 Jan 24 08:50:49 PM PST 24 733062208 ps
T907 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.980562393 Jan 24 08:40:42 PM PST 24 Jan 24 08:41:32 PM PST 24 2853931223 ps
T908 /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1053975610 Jan 24 08:44:54 PM PST 24 Jan 24 08:53:11 PM PST 24 21663437013 ps
T909 /workspace/coverage/default/7.lc_ctrl_alert_test.861951045 Jan 24 08:38:36 PM PST 24 Jan 24 08:38:38 PM PST 24 46147256 ps
T910 /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4279274008 Jan 24 08:48:06 PM PST 24 Jan 24 08:48:11 PM PST 24 983953978 ps
T911 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2713049269 Jan 24 08:35:14 PM PST 24 Jan 24 08:36:04 PM PST 24 5786693437 ps
T912 /workspace/coverage/default/7.lc_ctrl_jtag_errors.3951504583 Jan 24 08:38:28 PM PST 24 Jan 24 08:38:52 PM PST 24 11085211895 ps
T913 /workspace/coverage/default/10.lc_ctrl_alert_test.1974237972 Jan 24 08:40:21 PM PST 24 Jan 24 08:40:23 PM PST 24 22211005 ps
T914 /workspace/coverage/default/26.lc_ctrl_security_escalation.3830125961 Jan 24 09:52:12 PM PST 24 Jan 24 09:52:25 PM PST 24 2489612614 ps
T915 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1992413668 Jan 24 08:48:59 PM PST 24 Jan 24 08:49:08 PM PST 24 271430259 ps
T916 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1029376251 Jan 24 08:40:40 PM PST 24 Jan 24 08:40:55 PM PST 24 11323941210 ps
T917 /workspace/coverage/default/31.lc_ctrl_smoke.492558021 Jan 24 08:47:34 PM PST 24 Jan 24 08:47:37 PM PST 24 216232122 ps
T918 /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2412620316 Jan 24 08:32:00 PM PST 24 Jan 24 08:32:03 PM PST 24 34878899 ps
T919 /workspace/coverage/default/33.lc_ctrl_state_failure.3948804472 Jan 24 08:48:19 PM PST 24 Jan 24 08:48:43 PM PST 24 1250868667 ps
T920 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1112366633 Jan 24 08:40:48 PM PST 24 Jan 24 08:40:58 PM PST 24 1494351195 ps
T921 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.569626663 Jan 24 08:49:04 PM PST 24 Jan 24 08:49:07 PM PST 24 15566765 ps
T922 /workspace/coverage/default/28.lc_ctrl_state_failure.84339538 Jan 24 08:46:38 PM PST 24 Jan 24 08:47:14 PM PST 24 871695885 ps
T923 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1163155197 Jan 24 08:42:48 PM PST 24 Jan 24 08:43:07 PM PST 24 3313501446 ps
T924 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.4053448627 Jan 24 08:41:55 PM PST 24 Jan 24 08:42:14 PM PST 24 611878252 ps
T925 /workspace/coverage/default/43.lc_ctrl_errors.620644335 Jan 24 08:51:06 PM PST 24 Jan 24 08:51:22 PM PST 24 1242208626 ps
T926 /workspace/coverage/default/46.lc_ctrl_prog_failure.1752377624 Jan 24 08:51:59 PM PST 24 Jan 24 08:52:06 PM PST 24 99781300 ps
T927 /workspace/coverage/default/25.lc_ctrl_state_post_trans.51918857 Jan 24 08:46:13 PM PST 24 Jan 24 08:46:24 PM PST 24 81119037 ps
T928 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2738819344 Jan 24 08:37:49 PM PST 24 Jan 24 08:37:59 PM PST 24 2882777994 ps
T929 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1424902359 Jan 24 08:56:57 PM PST 24 Jan 24 08:57:07 PM PST 24 876830426 ps
T930 /workspace/coverage/default/28.lc_ctrl_errors.2662680476 Jan 24 08:46:49 PM PST 24 Jan 24 08:47:08 PM PST 24 1576856112 ps
T931 /workspace/coverage/default/30.lc_ctrl_errors.3334463737 Jan 24 08:47:24 PM PST 24 Jan 24 08:47:40 PM PST 24 3344270949 ps
T932 /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3463069230 Jan 24 08:43:57 PM PST 24 Jan 24 08:44:06 PM PST 24 42577749 ps
T933 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3744537270 Jan 24 08:45:05 PM PST 24 Jan 24 08:45:14 PM PST 24 258257639 ps
T934 /workspace/coverage/default/41.lc_ctrl_errors.1430316520 Jan 24 08:50:37 PM PST 24 Jan 24 08:50:57 PM PST 24 1371584603 ps
T935 /workspace/coverage/default/44.lc_ctrl_errors.735034922 Jan 24 08:51:21 PM PST 24 Jan 24 08:51:33 PM PST 24 401567036 ps
T936 /workspace/coverage/default/23.lc_ctrl_security_escalation.526355337 Jan 24 08:54:54 PM PST 24 Jan 24 08:55:11 PM PST 24 2163475213 ps
T937 /workspace/coverage/default/29.lc_ctrl_prog_failure.3925784131 Jan 24 08:47:10 PM PST 24 Jan 24 08:47:13 PM PST 24 32304243 ps
T938 /workspace/coverage/default/34.lc_ctrl_errors.2270679731 Jan 24 08:48:40 PM PST 24 Jan 24 08:48:51 PM PST 24 293169856 ps
T939 /workspace/coverage/default/19.lc_ctrl_alert_test.1971801717 Jan 24 08:44:37 PM PST 24 Jan 24 08:44:39 PM PST 24 66378479 ps
T940 /workspace/coverage/default/43.lc_ctrl_smoke.4245668500 Jan 24 08:50:58 PM PST 24 Jan 24 08:51:01 PM PST 24 19167694 ps
T941 /workspace/coverage/default/14.lc_ctrl_smoke.3365949597 Jan 24 08:42:05 PM PST 24 Jan 24 08:42:08 PM PST 24 107852554 ps
T942 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1425559442 Jan 24 08:51:00 PM PST 24 Jan 24 08:51:08 PM PST 24 1981118872 ps
T943 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3893104771 Jan 24 08:43:19 PM PST 24 Jan 24 08:44:07 PM PST 24 539608042 ps
T944 /workspace/coverage/default/14.lc_ctrl_state_failure.558215003 Jan 24 08:41:49 PM PST 24 Jan 24 08:42:19 PM PST 24 277027419 ps
T945 /workspace/coverage/default/24.lc_ctrl_prog_failure.141131546 Jan 24 08:45:55 PM PST 24 Jan 24 08:45:59 PM PST 24 302066626 ps
T946 /workspace/coverage/default/39.lc_ctrl_stress_all.3849337947 Jan 24 08:50:15 PM PST 24 Jan 24 08:54:46 PM PST 24 26472766546 ps
T947 /workspace/coverage/default/47.lc_ctrl_errors.4180986838 Jan 24 08:52:20 PM PST 24 Jan 24 08:52:37 PM PST 24 372624915 ps
T948 /workspace/coverage/default/47.lc_ctrl_stress_all.3541619454 Jan 24 08:52:17 PM PST 24 Jan 24 08:54:30 PM PST 24 27426676487 ps
T949 /workspace/coverage/default/5.lc_ctrl_stress_all.1549548680 Jan 24 08:37:05 PM PST 24 Jan 24 08:37:44 PM PST 24 1019528248 ps
T174 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.189138550 Jan 24 08:36:38 PM PST 24 Jan 24 08:36:39 PM PST 24 20804340 ps
T950 /workspace/coverage/default/1.lc_ctrl_jtag_errors.70801774 Jan 24 08:33:36 PM PST 24 Jan 24 08:34:21 PM PST 24 2972563960 ps
T951 /workspace/coverage/default/25.lc_ctrl_state_failure.3939686146 Jan 24 08:46:11 PM PST 24 Jan 24 08:46:41 PM PST 24 1019355664 ps
T952 /workspace/coverage/default/28.lc_ctrl_stress_all.3323111308 Jan 24 08:47:04 PM PST 24 Jan 24 08:48:04 PM PST 24 2770460251 ps
T953 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1873789930 Jan 24 08:42:47 PM PST 24 Jan 24 08:42:57 PM PST 24 1917296888 ps
T954 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3384393881 Jan 24 08:32:45 PM PST 24 Jan 24 08:33:08 PM PST 24 695647344 ps
T955 /workspace/coverage/default/40.lc_ctrl_security_escalation.777996493 Jan 24 08:50:20 PM PST 24 Jan 24 08:50:32 PM PST 24 1273671105 ps
T956 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2061366907 Jan 24 08:48:19 PM PST 24 Jan 24 08:48:43 PM PST 24 5707293505 ps
T957 /workspace/coverage/default/8.lc_ctrl_sec_mubi.347355092 Jan 24 08:39:11 PM PST 24 Jan 24 08:39:21 PM PST 24 166623486 ps
T958 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.227587059 Jan 24 08:46:33 PM PST 24 Jan 24 08:46:47 PM PST 24 176349541 ps
T959 /workspace/coverage/default/44.lc_ctrl_state_failure.3530288351 Jan 24 08:51:18 PM PST 24 Jan 24 08:51:51 PM PST 24 1345803382 ps
T62 /workspace/coverage/default/15.lc_ctrl_smoke.3724566980 Jan 24 08:54:11 PM PST 24 Jan 24 08:54:13 PM PST 24 38498373 ps
T960 /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2084215553 Jan 24 09:15:28 PM PST 24 Jan 24 09:15:48 PM PST 24 832074389 ps
T961 /workspace/coverage/default/20.lc_ctrl_state_post_trans.3084982245 Jan 24 08:44:43 PM PST 24 Jan 24 08:44:50 PM PST 24 202898895 ps
T63 /workspace/coverage/default/3.lc_ctrl_stress_all.3488299184 Jan 24 08:35:23 PM PST 24 Jan 24 08:37:24 PM PST 24 8535104152 ps
T962 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.50054374 Jan 24 08:52:24 PM PST 24 Jan 24 08:52:26 PM PST 24 84226374 ps
T963 /workspace/coverage/default/9.lc_ctrl_jtag_access.3567521195 Jan 24 08:39:38 PM PST 24 Jan 24 08:39:45 PM PST 24 533265691 ps
T964 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.4141541890 Jan 24 09:20:14 PM PST 24 Jan 24 09:20:26 PM PST 24 377988935 ps
T965 /workspace/coverage/default/4.lc_ctrl_state_post_trans.3876857046 Jan 24 08:35:38 PM PST 24 Jan 24 08:35:46 PM PST 24 78091266 ps
T966 /workspace/coverage/default/45.lc_ctrl_security_escalation.966867175 Jan 24 09:05:16 PM PST 24 Jan 24 09:05:29 PM PST 24 698547649 ps
T967 /workspace/coverage/default/34.lc_ctrl_alert_test.500669970 Jan 24 08:48:42 PM PST 24 Jan 24 08:48:44 PM PST 24 215593499 ps
T968 /workspace/coverage/default/2.lc_ctrl_jtag_access.2756036266 Jan 24 08:58:50 PM PST 24 Jan 24 08:58:58 PM PST 24 281962592 ps
T969 /workspace/coverage/default/48.lc_ctrl_state_post_trans.706669481 Jan 24 09:13:01 PM PST 24 Jan 24 09:13:13 PM PST 24 135278161 ps
T970 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3009926000 Jan 24 08:33:26 PM PST 24 Jan 24 08:33:50 PM PST 24 572422441 ps
T971 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3814444939 Jan 24 08:37:44 PM PST 24 Jan 24 08:37:58 PM PST 24 1474615398 ps
T972 /workspace/coverage/default/6.lc_ctrl_alert_test.40082762 Jan 24 08:38:05 PM PST 24 Jan 24 08:38:06 PM PST 24 163014625 ps
T973 /workspace/coverage/default/0.lc_ctrl_jtag_priority.2150530529 Jan 24 08:32:45 PM PST 24 Jan 24 08:32:54 PM PST 24 902512071 ps
T974 /workspace/coverage/default/4.lc_ctrl_stress_all.4180732081 Jan 24 08:36:11 PM PST 24 Jan 24 08:41:43 PM PST 24 49042398341 ps
T975 /workspace/coverage/default/3.lc_ctrl_jtag_priority.3466677839 Jan 24 08:35:14 PM PST 24 Jan 24 08:35:22 PM PST 24 2603365904 ps
T976 /workspace/coverage/default/2.lc_ctrl_sec_mubi.1187488986 Jan 24 08:34:39 PM PST 24 Jan 24 08:34:55 PM PST 24 1225058830 ps
T977 /workspace/coverage/default/35.lc_ctrl_security_escalation.3113070545 Jan 24 09:15:55 PM PST 24 Jan 24 09:16:09 PM PST 24 331493094 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.809266973 Jan 24 07:31:57 PM PST 24 Jan 24 07:32:09 PM PST 24 239605362 ps
T979 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4212604921 Jan 24 07:44:22 PM PST 24 Jan 24 07:44:24 PM PST 24 29796233 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2266469401 Jan 24 07:29:42 PM PST 24 Jan 24 07:29:46 PM PST 24 57058302 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4040209022 Jan 24 07:30:30 PM PST 24 Jan 24 07:30:37 PM PST 24 2373525149 ps

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.274801347
Short name T45
Test name
Test status
Simulation time 26870332 ps
CPU time 1.42 seconds
Started Jan 24 07:43:06 PM PST 24
Finished Jan 24 07:43:10 PM PST 24
Peak memory 218028 kb
Host smart-76d8eebb-0a17-46d9-ab81-91e3b5245823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274801347 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.274801347
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3269497659
Short name T1
Test name
Test status
Simulation time 8981378125 ps
CPU time 208.54 seconds
Started Jan 24 08:42:13 PM PST 24
Finished Jan 24 08:45:45 PM PST 24
Peak memory 267640 kb
Host smart-4e93fbb3-a9fd-497a-a0bb-d6b05586ba0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269497659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3269497659
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2305409356
Short name T78
Test name
Test status
Simulation time 231507219 ps
CPU time 1.85 seconds
Started Jan 24 07:50:42 PM PST 24
Finished Jan 24 07:50:45 PM PST 24
Peak memory 220908 kb
Host smart-f60276fe-7483-4271-b1d8-da4e3a9cfd04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230540
9356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2305409356
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1938555538
Short name T83
Test name
Test status
Simulation time 105803726 ps
CPU time 2.82 seconds
Started Jan 24 07:32:36 PM PST 24
Finished Jan 24 07:32:41 PM PST 24
Peak memory 212392 kb
Host smart-cb1671e8-502e-46a3-9c11-504422d26f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938555538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1938555538
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.729988057
Short name T31
Test name
Test status
Simulation time 948023399 ps
CPU time 21.78 seconds
Started Jan 24 08:40:50 PM PST 24
Finished Jan 24 08:41:12 PM PST 24
Peak memory 219116 kb
Host smart-8378115c-8a64-448e-91b0-ae3166653e6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729988057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.729988057
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.635832612
Short name T76
Test name
Test status
Simulation time 139687018 ps
CPU time 2.6 seconds
Started Jan 24 07:32:15 PM PST 24
Finished Jan 24 07:32:21 PM PST 24
Peak memory 217392 kb
Host smart-14f7b8cd-7b8a-4bcd-9fbc-86c7ca1be311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635832612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.635832612
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1841542943
Short name T177
Test name
Test status
Simulation time 1388962101 ps
CPU time 10.09 seconds
Started Jan 24 08:44:55 PM PST 24
Finished Jan 24 08:45:08 PM PST 24
Peak memory 218100 kb
Host smart-eef4669f-e7ca-4b45-9ab1-9d1a173f9356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841542943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1841542943
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1345374700
Short name T46
Test name
Test status
Simulation time 11024320338 ps
CPU time 206.93 seconds
Started Jan 24 08:48:49 PM PST 24
Finished Jan 24 08:52:17 PM PST 24
Peak memory 283888 kb
Host smart-2b8ef27d-0c8a-44e2-ab19-93f9e9dc309e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345374700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1345374700
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.887296362
Short name T94
Test name
Test status
Simulation time 51241524 ps
CPU time 1.44 seconds
Started Jan 24 07:30:54 PM PST 24
Finished Jan 24 07:30:57 PM PST 24
Peak memory 209944 kb
Host smart-cd36eb7c-0232-46b9-8016-b027c0b5af68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887296362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.887296362
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1002495626
Short name T34
Test name
Test status
Simulation time 34912450 ps
CPU time 0.91 seconds
Started Jan 24 08:40:01 PM PST 24
Finished Jan 24 08:40:03 PM PST 24
Peak memory 208140 kb
Host smart-e248bf9a-3121-4f1d-9801-c09b07f7450d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002495626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1002495626
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3177956643
Short name T92
Test name
Test status
Simulation time 16093159 ps
CPU time 1.23 seconds
Started Jan 24 07:41:34 PM PST 24
Finished Jan 24 07:41:41 PM PST 24
Peak memory 217192 kb
Host smart-5ba0448f-f1fd-4e2e-ae27-cb278d710ed8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177956643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3177956643
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.477093487
Short name T44
Test name
Test status
Simulation time 637209568 ps
CPU time 11.67 seconds
Started Jan 24 08:42:04 PM PST 24
Finished Jan 24 08:42:17 PM PST 24
Peak memory 218112 kb
Host smart-7e899f7c-dfad-43e4-810c-32e79fc7a58c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477093487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.477093487
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3194913330
Short name T85
Test name
Test status
Simulation time 232027168 ps
CPU time 41.68 seconds
Started Jan 24 08:32:56 PM PST 24
Finished Jan 24 08:33:39 PM PST 24
Peak memory 284164 kb
Host smart-0b1a71b7-a7bd-4e50-a056-6846c3a2cbdc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194913330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3194913330
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3681163199
Short name T19
Test name
Test status
Simulation time 74247222967 ps
CPU time 318.95 seconds
Started Jan 24 08:47:56 PM PST 24
Finished Jan 24 08:53:16 PM PST 24
Peak memory 275828 kb
Host smart-535b1d88-adc0-4c60-99a6-8ab47661c4c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681163199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3681163199
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.188742205
Short name T93
Test name
Test status
Simulation time 82270924 ps
CPU time 3.33 seconds
Started Jan 24 07:31:40 PM PST 24
Finished Jan 24 07:31:54 PM PST 24
Peak memory 217180 kb
Host smart-4eb6cee2-8cdb-41ca-afc5-6860065a6e72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188742205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.188742205
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1557964146
Short name T108
Test name
Test status
Simulation time 100113127 ps
CPU time 1.12 seconds
Started Jan 24 08:42:32 PM PST 24
Finished Jan 24 08:42:37 PM PST 24
Peak memory 209488 kb
Host smart-fb6e53dc-f062-4b30-9fd1-62f63044b7ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557964146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1557964146
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3649858540
Short name T119
Test name
Test status
Simulation time 105643506 ps
CPU time 2.98 seconds
Started Jan 24 07:31:59 PM PST 24
Finished Jan 24 07:32:09 PM PST 24
Peak memory 221120 kb
Host smart-fb8656a7-5e19-4c09-923a-47344aab0f48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649858540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3649858540
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3803766311
Short name T41
Test name
Test status
Simulation time 19826089846 ps
CPU time 81.89 seconds
Started Jan 24 08:40:18 PM PST 24
Finished Jan 24 08:41:41 PM PST 24
Peak memory 226352 kb
Host smart-d920007b-f4d1-4855-9bf7-a17495f6df20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803766311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3803766311
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.951482989
Short name T79
Test name
Test status
Simulation time 173383288 ps
CPU time 3.4 seconds
Started Jan 24 08:45:56 PM PST 24
Finished Jan 24 08:46:00 PM PST 24
Peak memory 217152 kb
Host smart-d2927cd7-5369-44af-bbe8-c859ef4a01d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951482989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.951482989
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.733573723
Short name T4
Test name
Test status
Simulation time 814926736 ps
CPU time 5.13 seconds
Started Jan 24 09:15:47 PM PST 24
Finished Jan 24 09:15:53 PM PST 24
Peak memory 209512 kb
Host smart-cdd0c58d-e7ce-4e97-aef2-a61da2ee37f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733573723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_ac
cess.733573723
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1267076242
Short name T404
Test name
Test status
Simulation time 1106628419 ps
CPU time 30.1 seconds
Started Jan 24 08:42:30 PM PST 24
Finished Jan 24 08:43:02 PM PST 24
Peak memory 251056 kb
Host smart-37fbf648-e22a-44cc-ab8a-64000e96e323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267076242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1267076242
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.705560510
Short name T97
Test name
Test status
Simulation time 55686682 ps
CPU time 1.21 seconds
Started Jan 24 07:30:44 PM PST 24
Finished Jan 24 07:30:46 PM PST 24
Peak memory 210612 kb
Host smart-52532dab-3999-47a2-b7a9-43731e1f3faf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705560510 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.705560510
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2585867060
Short name T98
Test name
Test status
Simulation time 92270625203 ps
CPU time 828.1 seconds
Started Jan 24 08:48:39 PM PST 24
Finished Jan 24 09:02:28 PM PST 24
Peak memory 268044 kb
Host smart-f23be3c1-b4c1-472b-9f7d-f2f2f3087f5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2585867060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2585867060
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1535089774
Short name T120
Test name
Test status
Simulation time 163597899 ps
CPU time 3.6 seconds
Started Jan 24 07:32:16 PM PST 24
Finished Jan 24 07:32:23 PM PST 24
Peak memory 217064 kb
Host smart-17b79675-bd84-4df5-bcf9-8e5f5636ecf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535089774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1535089774
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.167588154
Short name T121
Test name
Test status
Simulation time 786540031 ps
CPU time 4.23 seconds
Started Jan 24 07:31:29 PM PST 24
Finished Jan 24 07:31:41 PM PST 24
Peak memory 212632 kb
Host smart-e2937c9c-fe7b-43aa-8633-9f8c35994b44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167588154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.167588154
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.990993580
Short name T35
Test name
Test status
Simulation time 12375217 ps
CPU time 0.95 seconds
Started Jan 24 08:41:21 PM PST 24
Finished Jan 24 08:41:23 PM PST 24
Peak memory 207936 kb
Host smart-a3c72282-0e81-409f-aef3-7c3c9b555b90
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990993580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.990993580
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.735241118
Short name T146
Test name
Test status
Simulation time 23189324 ps
CPU time 0.84 seconds
Started Jan 24 07:32:25 PM PST 24
Finished Jan 24 07:32:27 PM PST 24
Peak memory 208768 kb
Host smart-3cfcdce7-5659-4339-a8f0-2028a0151f17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735241118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.735241118
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2684609239
Short name T123
Test name
Test status
Simulation time 339208416 ps
CPU time 1.79 seconds
Started Jan 24 07:32:37 PM PST 24
Finished Jan 24 07:32:41 PM PST 24
Peak memory 211820 kb
Host smart-d4d3bccd-84a5-4da9-a26a-b228862cd8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684609239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2684609239
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1519074806
Short name T91
Test name
Test status
Simulation time 317309659 ps
CPU time 3.92 seconds
Started Jan 24 07:32:06 PM PST 24
Finished Jan 24 07:32:16 PM PST 24
Peak memory 217200 kb
Host smart-06ff17b8-d786-4635-b5f1-4d67202a415d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519074806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1519074806
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1980164828
Short name T189
Test name
Test status
Simulation time 91634963 ps
CPU time 1.5 seconds
Started Jan 24 07:29:56 PM PST 24
Finished Jan 24 07:29:58 PM PST 24
Peak memory 217780 kb
Host smart-677999c9-e3f7-4723-a1b7-45d3d51cfbb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980164828 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1980164828
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3131587576
Short name T172
Test name
Test status
Simulation time 11469824 ps
CPU time 1 seconds
Started Jan 24 08:32:16 PM PST 24
Finished Jan 24 08:32:18 PM PST 24
Peak memory 209544 kb
Host smart-5d29bd88-163c-43cc-aaf9-518415388302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131587576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3131587576
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2063467546
Short name T304
Test name
Test status
Simulation time 303429219 ps
CPU time 6.98 seconds
Started Jan 24 09:18:13 PM PST 24
Finished Jan 24 09:18:21 PM PST 24
Peak memory 222588 kb
Host smart-b27d15d7-9500-4753-b477-d7cce41c7c52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063467546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2063467546
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1773303121
Short name T178
Test name
Test status
Simulation time 310301360 ps
CPU time 13.4 seconds
Started Jan 24 08:32:09 PM PST 24
Finished Jan 24 08:32:23 PM PST 24
Peak memory 218116 kb
Host smart-5b802796-b339-44ff-a97a-529690f39634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773303121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1773303121
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3587866340
Short name T173
Test name
Test status
Simulation time 32953944 ps
CPU time 0.84 seconds
Started Jan 24 08:35:06 PM PST 24
Finished Jan 24 08:35:08 PM PST 24
Peak memory 209224 kb
Host smart-f08aea86-2861-46b4-baba-9fa380dbb4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587866340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3587866340
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1879595706
Short name T58
Test name
Test status
Simulation time 69842619 ps
CPU time 0.87 seconds
Started Jan 24 08:38:17 PM PST 24
Finished Jan 24 08:38:18 PM PST 24
Peak memory 209520 kb
Host smart-26cd79ec-86eb-4051-8f54-f9e0f506b719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879595706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1879595706
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1890925943
Short name T175
Test name
Test status
Simulation time 13729407 ps
CPU time 0.79 seconds
Started Jan 24 09:05:16 PM PST 24
Finished Jan 24 09:05:18 PM PST 24
Peak memory 209276 kb
Host smart-0ea05b4d-d738-4a03-afb1-b5dc3f03879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890925943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1890925943
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2633015332
Short name T283
Test name
Test status
Simulation time 110345835 ps
CPU time 1.44 seconds
Started Jan 24 07:30:08 PM PST 24
Finished Jan 24 07:30:10 PM PST 24
Peak memory 208980 kb
Host smart-2de58a2a-c77d-4a02-87e9-f3a88a97736d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633015332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2633015332
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1410288339
Short name T126
Test name
Test status
Simulation time 392786770 ps
CPU time 2.98 seconds
Started Jan 24 09:12:03 PM PST 24
Finished Jan 24 09:12:07 PM PST 24
Peak memory 221272 kb
Host smart-26b3c37e-c106-4713-9fb9-5259b39ff188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410288339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1410288339
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1746440752
Short name T125
Test name
Test status
Simulation time 289014101 ps
CPU time 2.61 seconds
Started Jan 24 07:32:35 PM PST 24
Finished Jan 24 07:32:40 PM PST 24
Peak memory 221216 kb
Host smart-b9a431b5-4b55-437b-aeb0-fec8313c28ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746440752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1746440752
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1172178328
Short name T128
Test name
Test status
Simulation time 76285139 ps
CPU time 2.56 seconds
Started Jan 24 07:32:43 PM PST 24
Finished Jan 24 07:32:46 PM PST 24
Peak memory 217188 kb
Host smart-4c5062fe-f4f9-4fa4-9a28-4e102b6bee4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172178328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1172178328
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2264319864
Short name T122
Test name
Test status
Simulation time 292302785 ps
CPU time 3.18 seconds
Started Jan 24 07:30:32 PM PST 24
Finished Jan 24 07:30:36 PM PST 24
Peak memory 217176 kb
Host smart-2a87b535-290a-4218-951e-eb209cf548a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264319864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2264319864
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3373623871
Short name T82
Test name
Test status
Simulation time 39519300 ps
CPU time 1.13 seconds
Started Jan 24 07:30:08 PM PST 24
Finished Jan 24 07:30:10 PM PST 24
Peak memory 208896 kb
Host smart-3e153938-f590-419d-8af9-53b77bbd8bbe
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373623871 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3373623871
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1645138990
Short name T158
Test name
Test status
Simulation time 50519436 ps
CPU time 1.05 seconds
Started Jan 24 07:29:46 PM PST 24
Finished Jan 24 07:29:48 PM PST 24
Peak memory 208972 kb
Host smart-c88c50bb-8380-4dfc-be6f-1f3865bd74a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645138990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1645138990
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3309816319
Short name T226
Test name
Test status
Simulation time 52943322 ps
CPU time 1.36 seconds
Started Jan 24 07:29:50 PM PST 24
Finished Jan 24 07:29:53 PM PST 24
Peak memory 209032 kb
Host smart-4fb99949-72d0-4a23-8c1b-536b8ecfa341
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309816319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3309816319
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1551639913
Short name T157
Test name
Test status
Simulation time 16870998 ps
CPU time 1.12 seconds
Started Jan 24 07:29:39 PM PST 24
Finished Jan 24 07:29:41 PM PST 24
Peak memory 209116 kb
Host smart-7c43abdc-6a99-4abe-a6ab-f9cf556be388
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551639913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1551639913
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3063319448
Short name T220
Test name
Test status
Simulation time 17408441 ps
CPU time 0.83 seconds
Started Jan 24 07:29:47 PM PST 24
Finished Jan 24 07:29:49 PM PST 24
Peak memory 208976 kb
Host smart-e6a9ee5e-f95c-4bc7-a677-d4cb4e5fb044
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063319448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3063319448
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1069799486
Short name T186
Test name
Test status
Simulation time 109289519 ps
CPU time 0.97 seconds
Started Jan 24 07:29:39 PM PST 24
Finished Jan 24 07:29:41 PM PST 24
Peak memory 208896 kb
Host smart-0e5ac731-0f35-4fe9-8b6a-8923da50f478
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069799486 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1069799486
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1861261398
Short name T215
Test name
Test status
Simulation time 2097394164 ps
CPU time 11.29 seconds
Started Jan 24 07:29:42 PM PST 24
Finished Jan 24 07:29:54 PM PST 24
Peak memory 208896 kb
Host smart-0d102c4f-8d7e-47ae-9b84-5dfc37d74bdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861261398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1861261398
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.850800845
Short name T198
Test name
Test status
Simulation time 806571609 ps
CPU time 9.5 seconds
Started Jan 24 07:29:27 PM PST 24
Finished Jan 24 07:29:38 PM PST 24
Peak memory 208892 kb
Host smart-07328802-3369-45fb-8a2b-fa32d1ecb7a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850800845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.850800845
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.552193205
Short name T281
Test name
Test status
Simulation time 109429530 ps
CPU time 1.54 seconds
Started Jan 24 07:29:22 PM PST 24
Finished Jan 24 07:29:25 PM PST 24
Peak memory 209856 kb
Host smart-74afb645-8268-4d9f-ae87-dec9814d1f3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552193205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.552193205
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2662697706
Short name T258
Test name
Test status
Simulation time 81037689 ps
CPU time 1.47 seconds
Started Jan 24 07:29:39 PM PST 24
Finished Jan 24 07:29:41 PM PST 24
Peak memory 217296 kb
Host smart-37e0ad10-53b8-4834-8433-74c3326d5980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266269
7706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2662697706
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2169015545
Short name T234
Test name
Test status
Simulation time 52331330 ps
CPU time 1.88 seconds
Started Jan 24 07:29:18 PM PST 24
Finished Jan 24 07:29:21 PM PST 24
Peak memory 208880 kb
Host smart-b8325bbc-6edc-4dfe-83e4-9213ee37981f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169015545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2169015545
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1668483629
Short name T154
Test name
Test status
Simulation time 32688016 ps
CPU time 1.16 seconds
Started Jan 24 07:29:40 PM PST 24
Finished Jan 24 07:29:42 PM PST 24
Peak memory 209024 kb
Host smart-ecb694a4-1c94-4c45-8247-612a0e813c88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668483629 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1668483629
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.97917647
Short name T290
Test name
Test status
Simulation time 102819258 ps
CPU time 1.32 seconds
Started Jan 24 07:29:54 PM PST 24
Finished Jan 24 07:29:56 PM PST 24
Peak memory 208968 kb
Host smart-d521eb4c-01ce-493d-9f73-b20abdafdec2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97917647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_s
ame_csr_outstanding.97917647
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3416267407
Short name T232
Test name
Test status
Simulation time 265011478 ps
CPU time 2.02 seconds
Started Jan 24 07:29:42 PM PST 24
Finished Jan 24 07:29:45 PM PST 24
Peak memory 217284 kb
Host smart-fb4b9f40-62e9-4eb1-93f6-f56e5612df70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416267407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3416267407
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2266469401
Short name T980
Test name
Test status
Simulation time 57058302 ps
CPU time 2.51 seconds
Started Jan 24 07:29:42 PM PST 24
Finished Jan 24 07:29:46 PM PST 24
Peak memory 217180 kb
Host smart-bc37c417-0a97-488e-8b37-365e1a469f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266469401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2266469401
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1221111650
Short name T223
Test name
Test status
Simulation time 27650437 ps
CPU time 0.93 seconds
Started Jan 24 07:30:20 PM PST 24
Finished Jan 24 07:30:22 PM PST 24
Peak memory 208036 kb
Host smart-3d9f8983-ef2d-4e96-ac9a-082e423ed9e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221111650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1221111650
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.174877140
Short name T238
Test name
Test status
Simulation time 340572959 ps
CPU time 2.57 seconds
Started Jan 24 07:30:21 PM PST 24
Finished Jan 24 07:30:25 PM PST 24
Peak memory 208992 kb
Host smart-f2a4b5d1-8a65-45ea-aed9-350cf1be8281
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174877140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.174877140
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2657053786
Short name T156
Test name
Test status
Simulation time 167837722 ps
CPU time 1.06 seconds
Started Jan 24 07:30:10 PM PST 24
Finished Jan 24 07:30:12 PM PST 24
Peak memory 210208 kb
Host smart-80e1079f-d6ad-4be4-8031-53e835f81eae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657053786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2657053786
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1392991108
Short name T246
Test name
Test status
Simulation time 83420329 ps
CPU time 1.18 seconds
Started Jan 24 07:30:30 PM PST 24
Finished Jan 24 07:30:31 PM PST 24
Peak memory 218224 kb
Host smart-b9412e8e-10b9-4d11-bdff-72305c55b518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392991108 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1392991108
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.13145725
Short name T162
Test name
Test status
Simulation time 12513533 ps
CPU time 0.99 seconds
Started Jan 24 07:30:13 PM PST 24
Finished Jan 24 07:30:14 PM PST 24
Peak memory 208952 kb
Host smart-c60a78d2-71c6-44ac-9f0f-e2e0a42ee744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13145725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.13145725
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3672434398
Short name T274
Test name
Test status
Simulation time 949433644 ps
CPU time 6.66 seconds
Started Jan 24 07:30:03 PM PST 24
Finished Jan 24 07:30:11 PM PST 24
Peak memory 207396 kb
Host smart-6e0495e9-9ac5-4695-ba3c-d7178e97e882
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672434398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3672434398
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.724511711
Short name T266
Test name
Test status
Simulation time 2674228462 ps
CPU time 50.45 seconds
Started Jan 24 07:30:02 PM PST 24
Finished Jan 24 07:30:54 PM PST 24
Peak memory 208956 kb
Host smart-87084960-036e-4b37-b5a8-61f354249ead
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724511711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.724511711
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.230176795
Short name T239
Test name
Test status
Simulation time 236586941 ps
CPU time 1.72 seconds
Started Jan 24 07:29:53 PM PST 24
Finished Jan 24 07:29:56 PM PST 24
Peak memory 210068 kb
Host smart-7db76851-04a5-4513-9894-85d8d77b6c5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230176795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.230176795
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.838727413
Short name T194
Test name
Test status
Simulation time 69698170 ps
CPU time 1.22 seconds
Started Jan 24 07:30:08 PM PST 24
Finished Jan 24 07:30:10 PM PST 24
Peak memory 217296 kb
Host smart-45210fdb-4240-43ef-ae43-4597688ba140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838727
413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.838727413
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1185223377
Short name T247
Test name
Test status
Simulation time 45611587 ps
CPU time 1.47 seconds
Started Jan 24 07:30:01 PM PST 24
Finished Jan 24 07:30:03 PM PST 24
Peak memory 210572 kb
Host smart-989c4ebb-4662-48e8-9c33-463c7eb25e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185223377 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1185223377
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3307467528
Short name T235
Test name
Test status
Simulation time 19157246 ps
CPU time 1.18 seconds
Started Jan 24 07:30:19 PM PST 24
Finished Jan 24 07:30:21 PM PST 24
Peak memory 210816 kb
Host smart-94264801-8742-4955-8615-5ae06a2149a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307467528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3307467528
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.913722735
Short name T205
Test name
Test status
Simulation time 222585923 ps
CPU time 1.76 seconds
Started Jan 24 07:30:12 PM PST 24
Finished Jan 24 07:30:14 PM PST 24
Peak memory 217304 kb
Host smart-7b11bc99-0e67-471f-a6c8-80757e525f07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913722735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.913722735
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3343744653
Short name T118
Test name
Test status
Simulation time 73560787 ps
CPU time 2.7 seconds
Started Jan 24 07:30:14 PM PST 24
Finished Jan 24 07:30:17 PM PST 24
Peak memory 221436 kb
Host smart-a585c3cf-d973-4b72-b18c-75b338484384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343744653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3343744653
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3036684379
Short name T254
Test name
Test status
Simulation time 50027264 ps
CPU time 1.25 seconds
Started Jan 24 07:32:17 PM PST 24
Finished Jan 24 07:32:21 PM PST 24
Peak memory 218300 kb
Host smart-e72e2d36-c423-4f0a-aa78-dc49e85abe2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036684379 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3036684379
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.670278286
Short name T153
Test name
Test status
Simulation time 15803566 ps
CPU time 0.89 seconds
Started Jan 24 07:41:56 PM PST 24
Finished Jan 24 07:42:04 PM PST 24
Peak memory 208968 kb
Host smart-c42317d3-c85d-4559-8bfe-aae966d1a8e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670278286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.670278286
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3155421614
Short name T213
Test name
Test status
Simulation time 55239158 ps
CPU time 2.22 seconds
Started Jan 24 07:32:09 PM PST 24
Finished Jan 24 07:32:16 PM PST 24
Peak memory 208952 kb
Host smart-ee5d8192-bfaf-44d1-9cf9-238e182f42b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155421614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3155421614
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2746745327
Short name T265
Test name
Test status
Simulation time 70609893 ps
CPU time 1.45 seconds
Started Jan 24 07:32:14 PM PST 24
Finished Jan 24 07:32:18 PM PST 24
Peak memory 217292 kb
Host smart-6d233a2b-8ade-45fa-91a2-38325ac9b94a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746745327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2746745327
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3211791050
Short name T130
Test name
Test status
Simulation time 82146900 ps
CPU time 2.59 seconds
Started Jan 24 07:32:09 PM PST 24
Finished Jan 24 07:32:16 PM PST 24
Peak memory 217168 kb
Host smart-b9b4a4e7-250e-4bee-8666-3672265a5ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211791050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3211791050
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.383654052
Short name T225
Test name
Test status
Simulation time 38391651 ps
CPU time 1.09 seconds
Started Jan 24 07:54:51 PM PST 24
Finished Jan 24 07:54:59 PM PST 24
Peak memory 217512 kb
Host smart-fe5865a3-96c5-41bf-9afa-ab4bbc074762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383654052 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.383654052
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.727324293
Short name T236
Test name
Test status
Simulation time 15629664 ps
CPU time 0.97 seconds
Started Jan 24 11:18:29 PM PST 24
Finished Jan 24 11:18:31 PM PST 24
Peak memory 208816 kb
Host smart-d3a7157c-c308-4e9a-8b9e-4a5fcfbb39d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727324293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.727324293
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.526496341
Short name T255
Test name
Test status
Simulation time 361594635 ps
CPU time 1.47 seconds
Started Jan 24 07:32:15 PM PST 24
Finished Jan 24 07:32:20 PM PST 24
Peak memory 210620 kb
Host smart-f8db2001-f90e-466b-b41e-376150953027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526496341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.526496341
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2676863021
Short name T193
Test name
Test status
Simulation time 58324508 ps
CPU time 1.79 seconds
Started Jan 24 07:32:16 PM PST 24
Finished Jan 24 07:32:21 PM PST 24
Peak memory 217324 kb
Host smart-50a701e2-afa0-4e76-9475-205be4bd82f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676863021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2676863021
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3612654981
Short name T263
Test name
Test status
Simulation time 17677133 ps
CPU time 0.88 seconds
Started Jan 24 07:32:16 PM PST 24
Finished Jan 24 07:32:20 PM PST 24
Peak memory 208408 kb
Host smart-0e1607f1-1f7e-4ffa-ba79-4e24b8d43968
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612654981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3612654981
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1126792605
Short name T278
Test name
Test status
Simulation time 188760187 ps
CPU time 1.99 seconds
Started Jan 24 07:32:17 PM PST 24
Finished Jan 24 07:32:22 PM PST 24
Peak memory 208864 kb
Host smart-8b7fc076-443a-4ca5-85fb-195998232fa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126792605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1126792605
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.756907953
Short name T249
Test name
Test status
Simulation time 68428419 ps
CPU time 2.36 seconds
Started Jan 24 07:32:16 PM PST 24
Finished Jan 24 07:32:22 PM PST 24
Peak memory 217216 kb
Host smart-ef12b9f0-b1d6-47af-a8b9-fe2fcefac88a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756907953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.756907953
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2077662240
Short name T142
Test name
Test status
Simulation time 14454390 ps
CPU time 1.09 seconds
Started Jan 24 07:32:28 PM PST 24
Finished Jan 24 07:32:31 PM PST 24
Peak memory 218804 kb
Host smart-f3ab7c51-3570-4436-a90e-2dfec4194cb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077662240 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2077662240
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.565845830
Short name T280
Test name
Test status
Simulation time 97169450 ps
CPU time 1.2 seconds
Started Jan 24 07:32:25 PM PST 24
Finished Jan 24 07:32:27 PM PST 24
Peak memory 208948 kb
Host smart-90d5fa1c-f178-4551-b3b7-b4955f66273a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565845830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.565845830
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2772391941
Short name T287
Test name
Test status
Simulation time 47741952 ps
CPU time 1.1 seconds
Started Jan 24 07:32:35 PM PST 24
Finished Jan 24 07:32:38 PM PST 24
Peak memory 217112 kb
Host smart-5c499208-4e38-4b3d-969a-0d03eecd65e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772391941 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2772391941
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3778272978
Short name T167
Test name
Test status
Simulation time 14235496 ps
CPU time 0.97 seconds
Started Jan 24 07:32:34 PM PST 24
Finished Jan 24 07:32:36 PM PST 24
Peak memory 208972 kb
Host smart-4d7aaebf-6714-49aa-a108-12434f35bfad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778272978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3778272978
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.233067933
Short name T144
Test name
Test status
Simulation time 91040564 ps
CPU time 1.35 seconds
Started Jan 24 07:32:35 PM PST 24
Finished Jan 24 07:32:39 PM PST 24
Peak memory 208892 kb
Host smart-f35c8ff2-71df-4f80-86e9-59dadf787482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233067933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.233067933
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1760425232
Short name T259
Test name
Test status
Simulation time 227614425 ps
CPU time 2.18 seconds
Started Jan 24 07:32:36 PM PST 24
Finished Jan 24 07:32:40 PM PST 24
Peak memory 217624 kb
Host smart-07f3994b-d932-43f9-80cb-3a79c0effdd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760425232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1760425232
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.224393650
Short name T221
Test name
Test status
Simulation time 17890289 ps
CPU time 1.29 seconds
Started Jan 24 07:32:36 PM PST 24
Finished Jan 24 07:32:39 PM PST 24
Peak memory 217580 kb
Host smart-a92c62b9-42e0-48a3-b1a2-58e98029f953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224393650 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.224393650
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1145500250
Short name T227
Test name
Test status
Simulation time 14273004 ps
CPU time 1.02 seconds
Started Jan 24 07:32:34 PM PST 24
Finished Jan 24 07:32:36 PM PST 24
Peak memory 208976 kb
Host smart-14e54617-3813-4bf2-a283-4f01351a6b00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145500250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1145500250
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2172084098
Short name T252
Test name
Test status
Simulation time 133956310 ps
CPU time 1.32 seconds
Started Jan 24 07:32:34 PM PST 24
Finished Jan 24 07:32:37 PM PST 24
Peak memory 208952 kb
Host smart-eacf35a3-d13b-44e8-abfa-cbe9ca145fd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172084098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2172084098
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2741643343
Short name T277
Test name
Test status
Simulation time 475855553 ps
CPU time 3.41 seconds
Started Jan 24 07:32:36 PM PST 24
Finished Jan 24 07:32:42 PM PST 24
Peak memory 217296 kb
Host smart-36ffb22b-2b36-489a-86ed-d08311088af7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741643343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2741643343
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4201377848
Short name T147
Test name
Test status
Simulation time 21029046 ps
CPU time 1.15 seconds
Started Jan 24 07:32:48 PM PST 24
Finished Jan 24 07:32:50 PM PST 24
Peak memory 217648 kb
Host smart-b646bab4-2390-410d-aa4c-59dcac14c95d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201377848 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4201377848
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1297410440
Short name T163
Test name
Test status
Simulation time 53825855 ps
CPU time 0.85 seconds
Started Jan 24 07:32:45 PM PST 24
Finished Jan 24 07:32:47 PM PST 24
Peak memory 208812 kb
Host smart-c9742cc4-0c66-4c56-8578-b25a32dc9c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297410440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1297410440
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3358366560
Short name T209
Test name
Test status
Simulation time 31892836 ps
CPU time 1.16 seconds
Started Jan 24 07:32:49 PM PST 24
Finished Jan 24 07:32:52 PM PST 24
Peak memory 208988 kb
Host smart-0bdb3b20-93ac-4b17-ba56-843b0775533e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358366560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3358366560
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2335414135
Short name T212
Test name
Test status
Simulation time 66880846 ps
CPU time 2.14 seconds
Started Jan 24 07:32:34 PM PST 24
Finished Jan 24 07:32:37 PM PST 24
Peak memory 217324 kb
Host smart-aa39d800-eab3-4c68-b85d-2ab4e643f3b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335414135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2335414135
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2961679916
Short name T288
Test name
Test status
Simulation time 39634476 ps
CPU time 1.13 seconds
Started Jan 24 07:32:44 PM PST 24
Finished Jan 24 07:32:46 PM PST 24
Peak memory 217848 kb
Host smart-22dbd233-dcb8-4a8a-bd79-1865d76cd1de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961679916 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2961679916
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3698824447
Short name T159
Test name
Test status
Simulation time 158881473 ps
CPU time 0.88 seconds
Started Jan 24 07:32:44 PM PST 24
Finished Jan 24 07:32:46 PM PST 24
Peak memory 208916 kb
Host smart-4dbbd2bd-abf1-4e56-b0c4-91b49b219bce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698824447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3698824447
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2271853013
Short name T276
Test name
Test status
Simulation time 135653323 ps
CPU time 1.08 seconds
Started Jan 24 07:32:44 PM PST 24
Finished Jan 24 07:32:46 PM PST 24
Peak memory 208928 kb
Host smart-26d73c71-ceca-40d3-9f85-35b2f7670b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271853013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2271853013
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1073541149
Short name T237
Test name
Test status
Simulation time 100046371 ps
CPU time 3.02 seconds
Started Jan 24 07:32:47 PM PST 24
Finished Jan 24 07:32:51 PM PST 24
Peak memory 217280 kb
Host smart-db76a3a3-a6bc-4af6-a9ec-6cf9c4e6fede
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073541149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1073541149
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2840886117
Short name T150
Test name
Test status
Simulation time 24635149 ps
CPU time 1.63 seconds
Started Jan 24 07:32:45 PM PST 24
Finished Jan 24 07:32:48 PM PST 24
Peak memory 217196 kb
Host smart-bbda49a5-8a6a-44c7-afe3-846823a798cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840886117 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2840886117
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3733787290
Short name T155
Test name
Test status
Simulation time 124017957 ps
CPU time 0.98 seconds
Started Jan 24 07:32:47 PM PST 24
Finished Jan 24 07:32:49 PM PST 24
Peak memory 208956 kb
Host smart-372cf6d0-a257-4e61-b525-cfbbe1062ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733787290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3733787290
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2279820700
Short name T166
Test name
Test status
Simulation time 93360388 ps
CPU time 1.6 seconds
Started Jan 24 07:53:57 PM PST 24
Finished Jan 24 07:54:01 PM PST 24
Peak memory 210620 kb
Host smart-2556e649-d475-4d16-8143-a3d39a0ee69b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279820700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2279820700
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1404823486
Short name T184
Test name
Test status
Simulation time 139171750 ps
CPU time 2.52 seconds
Started Jan 24 07:32:44 PM PST 24
Finished Jan 24 07:32:47 PM PST 24
Peak memory 217256 kb
Host smart-3cee5722-2bc8-4f80-b4a1-cd787e63f812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404823486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1404823486
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1738227071
Short name T131
Test name
Test status
Simulation time 441510929 ps
CPU time 2.81 seconds
Started Jan 24 07:32:44 PM PST 24
Finished Jan 24 07:32:48 PM PST 24
Peak memory 220572 kb
Host smart-6957bd33-10ff-4934-b8ae-ad20f0a85e21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738227071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1738227071
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2494586772
Short name T244
Test name
Test status
Simulation time 59182826 ps
CPU time 2.45 seconds
Started Jan 24 07:32:54 PM PST 24
Finished Jan 24 07:32:57 PM PST 24
Peak memory 218452 kb
Host smart-3482cb8e-c0f3-4464-82b1-1775ea17f396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494586772 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2494586772
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3095955752
Short name T229
Test name
Test status
Simulation time 13739810 ps
CPU time 1.12 seconds
Started Jan 24 07:32:48 PM PST 24
Finished Jan 24 07:32:50 PM PST 24
Peak memory 208316 kb
Host smart-6b3401d1-1dd8-428e-8b43-6fa4d7e4d0dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095955752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3095955752
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.588880038
Short name T218
Test name
Test status
Simulation time 48037777 ps
CPU time 2.02 seconds
Started Jan 24 07:32:49 PM PST 24
Finished Jan 24 07:32:53 PM PST 24
Peak memory 210656 kb
Host smart-3faf64fe-a2a4-4054-adac-020e2e7b0135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588880038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.588880038
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.220823887
Short name T191
Test name
Test status
Simulation time 147258810 ps
CPU time 1.63 seconds
Started Jan 24 07:32:43 PM PST 24
Finished Jan 24 07:32:46 PM PST 24
Peak memory 217296 kb
Host smart-11e8be85-2d66-41c1-900f-35d61769eb7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220823887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.220823887
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2121264475
Short name T124
Test name
Test status
Simulation time 173025851 ps
CPU time 2.34 seconds
Started Jan 24 07:32:47 PM PST 24
Finished Jan 24 07:32:50 PM PST 24
Peak memory 217152 kb
Host smart-dd634e7e-cddf-459e-83a6-0ab6fce279c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121264475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2121264475
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2834104086
Short name T161
Test name
Test status
Simulation time 21435677 ps
CPU time 1 seconds
Started Jan 24 07:30:48 PM PST 24
Finished Jan 24 07:30:49 PM PST 24
Peak memory 207860 kb
Host smart-3aa9b090-a950-4f3a-a262-519cc939deda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834104086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2834104086
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3901054064
Short name T195
Test name
Test status
Simulation time 27330412 ps
CPU time 1.82 seconds
Started Jan 24 07:30:39 PM PST 24
Finished Jan 24 07:30:42 PM PST 24
Peak memory 208936 kb
Host smart-4358fa10-5c42-4cd0-934e-2925d9d9336f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901054064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3901054064
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2405479139
Short name T169
Test name
Test status
Simulation time 22651552 ps
CPU time 0.84 seconds
Started Jan 24 07:30:33 PM PST 24
Finished Jan 24 07:30:34 PM PST 24
Peak memory 208808 kb
Host smart-44f97e55-8fe3-411f-a222-aec2dfd6169b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405479139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2405479139
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1266255571
Short name T282
Test name
Test status
Simulation time 26679488 ps
CPU time 2.01 seconds
Started Jan 24 07:30:44 PM PST 24
Finished Jan 24 07:30:47 PM PST 24
Peak memory 218900 kb
Host smart-a7fd540f-15f2-45fa-b04f-40c4ffd748d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266255571 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1266255571
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3239563366
Short name T269
Test name
Test status
Simulation time 63761025 ps
CPU time 0.95 seconds
Started Jan 24 07:30:39 PM PST 24
Finished Jan 24 07:30:41 PM PST 24
Peak memory 208928 kb
Host smart-ab6558d0-c641-45ab-8c60-5e5780f7da69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239563366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3239563366
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4119732156
Short name T196
Test name
Test status
Simulation time 165282107 ps
CPU time 1.63 seconds
Started Jan 24 07:30:37 PM PST 24
Finished Jan 24 07:30:39 PM PST 24
Peak memory 207244 kb
Host smart-37127645-3c31-42f0-8758-619fb9c9c5fd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119732156 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4119732156
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2766991269
Short name T201
Test name
Test status
Simulation time 1716249841 ps
CPU time 4.77 seconds
Started Jan 24 07:30:24 PM PST 24
Finished Jan 24 07:30:29 PM PST 24
Peak memory 207760 kb
Host smart-081f7a23-c24a-408d-8cc4-021320797d1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766991269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2766991269
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4040209022
Short name T981
Test name
Test status
Simulation time 2373525149 ps
CPU time 6.05 seconds
Started Jan 24 07:30:30 PM PST 24
Finished Jan 24 07:30:37 PM PST 24
Peak memory 208960 kb
Host smart-10732266-ea98-4bde-ab69-d3296a0df9b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040209022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4040209022
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.985102715
Short name T188
Test name
Test status
Simulation time 267374580 ps
CPU time 1.38 seconds
Started Jan 24 07:30:29 PM PST 24
Finished Jan 24 07:30:32 PM PST 24
Peak memory 209964 kb
Host smart-04634a20-aaf8-4278-ab49-814cea3bfee2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985102715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.985102715
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.604478692
Short name T138
Test name
Test status
Simulation time 79058639 ps
CPU time 1.81 seconds
Started Jan 24 07:30:34 PM PST 24
Finished Jan 24 07:30:36 PM PST 24
Peak memory 218008 kb
Host smart-4e3bc03d-3200-439e-90d3-e0f585bbec78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604478
692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.604478692
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.797924140
Short name T214
Test name
Test status
Simulation time 237864114 ps
CPU time 1.37 seconds
Started Jan 24 07:30:31 PM PST 24
Finished Jan 24 07:30:33 PM PST 24
Peak memory 208896 kb
Host smart-c3b8c148-5fd8-4279-b2ab-e2dca637fe3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797924140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.797924140
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1901419165
Short name T260
Test name
Test status
Simulation time 17878680 ps
CPU time 1.05 seconds
Started Jan 24 07:30:26 PM PST 24
Finished Jan 24 07:30:29 PM PST 24
Peak memory 208948 kb
Host smart-cf1c39fa-aae9-4618-96a5-a6c7ab84ca87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901419165 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1901419165
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3657628856
Short name T289
Test name
Test status
Simulation time 73122518 ps
CPU time 1.28 seconds
Started Jan 24 07:30:42 PM PST 24
Finished Jan 24 07:30:45 PM PST 24
Peak memory 208968 kb
Host smart-967f330c-8a5c-4830-9865-dbdb5a6470b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657628856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3657628856
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3227143713
Short name T127
Test name
Test status
Simulation time 107384212 ps
CPU time 3.86 seconds
Started Jan 24 07:30:35 PM PST 24
Finished Jan 24 07:30:40 PM PST 24
Peak memory 217424 kb
Host smart-af3ff64e-5d21-4507-8631-b32edef697aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227143713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3227143713
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.172025406
Short name T152
Test name
Test status
Simulation time 17954684 ps
CPU time 1.02 seconds
Started Jan 24 09:22:33 PM PST 24
Finished Jan 24 09:22:35 PM PST 24
Peak memory 209024 kb
Host smart-e0ccf052-650c-4807-8fc0-ad0fad6149b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172025406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.172025406
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4143954524
Short name T253
Test name
Test status
Simulation time 359203804 ps
CPU time 2.01 seconds
Started Jan 24 07:31:03 PM PST 24
Finished Jan 24 07:31:08 PM PST 24
Peak memory 208996 kb
Host smart-7fec6170-8b54-4c77-abd2-473a16d22cdd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143954524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.4143954524
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3531780239
Short name T270
Test name
Test status
Simulation time 19635324 ps
CPU time 1.19 seconds
Started Jan 24 07:30:54 PM PST 24
Finished Jan 24 07:30:56 PM PST 24
Peak memory 210800 kb
Host smart-4550051c-8b20-43c9-ade9-419939fcf47d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531780239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3531780239
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3636449366
Short name T95
Test name
Test status
Simulation time 29395646 ps
CPU time 2.19 seconds
Started Jan 24 07:31:03 PM PST 24
Finished Jan 24 07:31:08 PM PST 24
Peak memory 218608 kb
Host smart-8961ba6f-b307-4505-b030-f1cc8b4cb62e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636449366 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3636449366
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3004968493
Short name T222
Test name
Test status
Simulation time 24801582 ps
CPU time 0.9 seconds
Started Jan 24 07:31:05 PM PST 24
Finished Jan 24 07:31:08 PM PST 24
Peak memory 207836 kb
Host smart-d97b42dc-842c-4b1e-9cc0-c39d730bf6cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004968493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3004968493
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.255112048
Short name T134
Test name
Test status
Simulation time 131117538 ps
CPU time 1.25 seconds
Started Jan 24 07:30:52 PM PST 24
Finished Jan 24 07:30:53 PM PST 24
Peak memory 208896 kb
Host smart-2542e6fb-d6c2-4741-9057-447960ee9de3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255112048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.255112048
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3496580084
Short name T286
Test name
Test status
Simulation time 640936770 ps
CPU time 5.79 seconds
Started Jan 24 07:30:47 PM PST 24
Finished Jan 24 07:30:53 PM PST 24
Peak memory 208972 kb
Host smart-f28f8c85-9fa3-4595-8e38-3a4f3707b981
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496580084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3496580084
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2532860381
Short name T96
Test name
Test status
Simulation time 1891544816 ps
CPU time 12.47 seconds
Started Jan 24 07:30:45 PM PST 24
Finished Jan 24 07:30:59 PM PST 24
Peak memory 208840 kb
Host smart-99fceeda-937d-45b2-a845-bda078d88d4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532860381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2532860381
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1438924812
Short name T133
Test name
Test status
Simulation time 110497661 ps
CPU time 3.26 seconds
Started Jan 24 08:25:34 PM PST 24
Finished Jan 24 08:25:38 PM PST 24
Peak memory 217240 kb
Host smart-efdc330d-c83f-45b3-9ccc-2d0502b2e893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143892
4812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1438924812
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3664278887
Short name T267
Test name
Test status
Simulation time 74480477 ps
CPU time 1.39 seconds
Started Jan 24 07:30:52 PM PST 24
Finished Jan 24 07:30:54 PM PST 24
Peak memory 208812 kb
Host smart-e17ced47-1929-492d-b1b1-a2db6b2bd113
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664278887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3664278887
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1618492616
Short name T248
Test name
Test status
Simulation time 203174710 ps
CPU time 1.39 seconds
Started Jan 24 08:28:25 PM PST 24
Finished Jan 24 08:28:27 PM PST 24
Peak memory 208940 kb
Host smart-5d17f095-c17d-47d1-afac-58218f67e1ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618492616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1618492616
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3816074425
Short name T251
Test name
Test status
Simulation time 405490200 ps
CPU time 4.08 seconds
Started Jan 24 07:31:02 PM PST 24
Finished Jan 24 07:31:10 PM PST 24
Peak memory 217300 kb
Host smart-ed69d690-f410-4cec-b19b-36f6871a9745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816074425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3816074425
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2958679312
Short name T129
Test name
Test status
Simulation time 424085466 ps
CPU time 4.13 seconds
Started Jan 24 07:30:56 PM PST 24
Finished Jan 24 07:31:01 PM PST 24
Peak memory 212432 kb
Host smart-c50384a8-4057-449f-add4-a15bd2835ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958679312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2958679312
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3521612126
Short name T211
Test name
Test status
Simulation time 22685412 ps
CPU time 1.04 seconds
Started Jan 24 07:41:16 PM PST 24
Finished Jan 24 07:41:18 PM PST 24
Peak memory 208916 kb
Host smart-ed4ac4aa-a8b6-4e29-bc7e-3cbbc90c2bcf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521612126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3521612126
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2045052145
Short name T268
Test name
Test status
Simulation time 93409143 ps
CPU time 1.82 seconds
Started Jan 24 07:31:09 PM PST 24
Finished Jan 24 07:31:14 PM PST 24
Peak memory 207784 kb
Host smart-b06d333a-98f1-4932-8e69-4ffaf1e32557
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045052145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2045052145
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.396640945
Short name T203
Test name
Test status
Simulation time 17632375 ps
CPU time 0.95 seconds
Started Jan 24 07:31:26 PM PST 24
Finished Jan 24 07:31:28 PM PST 24
Peak memory 217244 kb
Host smart-d9b24cee-ca00-46ee-b381-2c6d647c5836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396640945 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.396640945
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2232296264
Short name T170
Test name
Test status
Simulation time 18837098 ps
CPU time 1.18 seconds
Started Jan 24 07:31:12 PM PST 24
Finished Jan 24 07:31:15 PM PST 24
Peak memory 208956 kb
Host smart-0077b3e7-2f35-4db5-bb18-7d349d550675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232296264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2232296264
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3682183188
Short name T257
Test name
Test status
Simulation time 108493635 ps
CPU time 1.78 seconds
Started Jan 24 07:31:02 PM PST 24
Finished Jan 24 07:31:07 PM PST 24
Peak memory 208884 kb
Host smart-f77ced51-a964-4562-9c5b-d1e3a569a09c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682183188 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3682183188
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3603998543
Short name T135
Test name
Test status
Simulation time 2177844781 ps
CPU time 16.91 seconds
Started Jan 24 07:31:01 PM PST 24
Finished Jan 24 07:31:21 PM PST 24
Peak memory 207824 kb
Host smart-bd887504-6cb1-4f4e-acde-63cd2020e1e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603998543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3603998543
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3829018367
Short name T187
Test name
Test status
Simulation time 939091530 ps
CPU time 9.23 seconds
Started Jan 24 07:31:06 PM PST 24
Finished Jan 24 07:31:17 PM PST 24
Peak memory 208848 kb
Host smart-78708607-ea50-418a-b587-9edc82ba3074
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829018367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3829018367
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3895344290
Short name T140
Test name
Test status
Simulation time 566861250 ps
CPU time 1.88 seconds
Started Jan 24 07:31:07 PM PST 24
Finished Jan 24 07:31:13 PM PST 24
Peak memory 210276 kb
Host smart-bc83a559-f1a8-4bbe-9b59-a03b4b24c83d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895344290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3895344290
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3252991932
Short name T284
Test name
Test status
Simulation time 618305028 ps
CPU time 2.82 seconds
Started Jan 24 08:50:14 PM PST 24
Finished Jan 24 08:50:18 PM PST 24
Peak memory 217276 kb
Host smart-77d63e14-3c15-4cf6-8421-446122ee7eb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325299
1932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3252991932
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3586725937
Short name T137
Test name
Test status
Simulation time 95318974 ps
CPU time 1.73 seconds
Started Jan 24 07:42:45 PM PST 24
Finished Jan 24 07:42:47 PM PST 24
Peak memory 207840 kb
Host smart-ee204cc6-a8ff-422c-baad-0960dada19a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586725937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3586725937
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.147855313
Short name T271
Test name
Test status
Simulation time 146909862 ps
CPU time 1.75 seconds
Started Jan 24 07:43:58 PM PST 24
Finished Jan 24 07:44:00 PM PST 24
Peak memory 210944 kb
Host smart-ff35e601-e089-41ec-a7b7-482c92274a3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147855313 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.147855313
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1256108713
Short name T231
Test name
Test status
Simulation time 48267081 ps
CPU time 2.05 seconds
Started Jan 24 07:31:25 PM PST 24
Finished Jan 24 07:31:29 PM PST 24
Peak memory 210564 kb
Host smart-99b5ba8c-888d-4259-8d80-191593a22e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256108713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1256108713
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2477021297
Short name T80
Test name
Test status
Simulation time 279761253 ps
CPU time 3.22 seconds
Started Jan 24 07:31:05 PM PST 24
Finished Jan 24 07:31:10 PM PST 24
Peak memory 217244 kb
Host smart-6263d883-34d3-42e4-b90f-25c6a8702152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477021297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2477021297
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1913262770
Short name T250
Test name
Test status
Simulation time 390655318 ps
CPU time 2.17 seconds
Started Jan 24 07:31:16 PM PST 24
Finished Jan 24 07:31:19 PM PST 24
Peak memory 221000 kb
Host smart-30f24e17-a593-4cbf-be74-13f8ca4c8c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913262770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1913262770
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2941200888
Short name T190
Test name
Test status
Simulation time 118892912 ps
CPU time 1.51 seconds
Started Jan 24 07:31:32 PM PST 24
Finished Jan 24 07:31:46 PM PST 24
Peak memory 218536 kb
Host smart-cb325d23-e638-4a5a-a6ff-fd0d95a767b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941200888 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2941200888
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3351540777
Short name T143
Test name
Test status
Simulation time 60526943 ps
CPU time 0.79 seconds
Started Jan 24 07:31:32 PM PST 24
Finished Jan 24 07:31:44 PM PST 24
Peak memory 208816 kb
Host smart-c46f4242-7b92-401f-b385-ef7472143971
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351540777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3351540777
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2338258904
Short name T208
Test name
Test status
Simulation time 284492092 ps
CPU time 2.35 seconds
Started Jan 24 07:31:23 PM PST 24
Finished Jan 24 07:31:26 PM PST 24
Peak memory 208860 kb
Host smart-5ed93196-0fd0-437f-aa84-92005382a310
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338258904 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2338258904
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3479764532
Short name T207
Test name
Test status
Simulation time 1054681093 ps
CPU time 3.62 seconds
Started Jan 24 07:31:20 PM PST 24
Finished Jan 24 07:31:25 PM PST 24
Peak memory 208904 kb
Host smart-7b73ec4a-ae70-4abf-aa65-78b5a320b053
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479764532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3479764532
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1806930048
Short name T241
Test name
Test status
Simulation time 2461158423 ps
CPU time 8.52 seconds
Started Jan 24 07:31:27 PM PST 24
Finished Jan 24 07:31:39 PM PST 24
Peak memory 207860 kb
Host smart-1d1d7ff1-f68e-48b2-95da-800ca0e178c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806930048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1806930048
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.322629003
Short name T264
Test name
Test status
Simulation time 445681281 ps
CPU time 1.89 seconds
Started Jan 24 07:31:22 PM PST 24
Finished Jan 24 07:31:24 PM PST 24
Peak memory 210184 kb
Host smart-639b641d-6af6-4582-b519-89d02d3ff17a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322629003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.322629003
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2721143251
Short name T200
Test name
Test status
Simulation time 344949092 ps
CPU time 1.34 seconds
Started Jan 24 07:31:21 PM PST 24
Finished Jan 24 07:31:24 PM PST 24
Peak memory 208816 kb
Host smart-bdf82d14-018d-4d08-90c4-6db842514834
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721143251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2721143251
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3245224260
Short name T151
Test name
Test status
Simulation time 87576654 ps
CPU time 1.11 seconds
Started Jan 24 07:31:21 PM PST 24
Finished Jan 24 07:31:23 PM PST 24
Peak memory 208288 kb
Host smart-ee307c16-434b-4279-a1df-b8e2b0ad8455
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245224260 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3245224260
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4212604921
Short name T979
Test name
Test status
Simulation time 29796233 ps
CPU time 1.52 seconds
Started Jan 24 07:44:22 PM PST 24
Finished Jan 24 07:44:24 PM PST 24
Peak memory 208984 kb
Host smart-2a0b9979-c300-4792-b8a9-00e2bb1ef4fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212604921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.4212604921
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1297512636
Short name T84
Test name
Test status
Simulation time 49037699 ps
CPU time 2.2 seconds
Started Jan 24 07:39:09 PM PST 24
Finished Jan 24 07:39:13 PM PST 24
Peak memory 217300 kb
Host smart-61f224ff-8be3-46d1-8a91-0d26d1dd100b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297512636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1297512636
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2886537776
Short name T81
Test name
Test status
Simulation time 21177493 ps
CPU time 1.68 seconds
Started Jan 24 07:31:48 PM PST 24
Finished Jan 24 07:31:55 PM PST 24
Peak memory 218636 kb
Host smart-96e9d6d8-00ca-41a1-921e-5ecdcb2f1de6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886537776 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2886537776
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2232024761
Short name T160
Test name
Test status
Simulation time 37215311 ps
CPU time 0.86 seconds
Started Jan 24 07:31:40 PM PST 24
Finished Jan 24 07:31:52 PM PST 24
Peak memory 208804 kb
Host smart-40f8dea2-4036-468f-b7fa-195dc7a17f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232024761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2232024761
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1618132388
Short name T262
Test name
Test status
Simulation time 324657650 ps
CPU time 1.18 seconds
Started Jan 24 07:44:36 PM PST 24
Finished Jan 24 07:44:38 PM PST 24
Peak memory 208888 kb
Host smart-2b3bf5ff-0728-4ccd-9943-5767e5274f91
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618132388 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1618132388
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3110743367
Short name T206
Test name
Test status
Simulation time 933562767 ps
CPU time 20.51 seconds
Started Jan 24 07:31:32 PM PST 24
Finished Jan 24 07:32:04 PM PST 24
Peak memory 208844 kb
Host smart-6658c814-62bd-49e4-914e-6a5f7fea5b47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110743367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3110743367
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.932541194
Short name T273
Test name
Test status
Simulation time 4841004955 ps
CPU time 13.39 seconds
Started Jan 24 07:31:32 PM PST 24
Finished Jan 24 07:31:58 PM PST 24
Peak memory 207608 kb
Host smart-6e6077bc-d41a-41ff-9f84-0b597fd68b2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932541194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.932541194
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1966910967
Short name T204
Test name
Test status
Simulation time 1352249377 ps
CPU time 2.62 seconds
Started Jan 24 07:31:32 PM PST 24
Finished Jan 24 07:31:47 PM PST 24
Peak memory 209608 kb
Host smart-5afefe82-3d0b-46fa-9aee-5697a11b6a76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966910967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1966910967
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097767314
Short name T197
Test name
Test status
Simulation time 128314728 ps
CPU time 2.1 seconds
Started Jan 24 09:01:33 PM PST 24
Finished Jan 24 09:01:37 PM PST 24
Peak memory 218324 kb
Host smart-9f2e5202-8768-4d03-92ed-e1c8b6b7ed0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209776
7314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097767314
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1180654084
Short name T279
Test name
Test status
Simulation time 800440645 ps
CPU time 4.19 seconds
Started Jan 24 07:31:35 PM PST 24
Finished Jan 24 07:31:49 PM PST 24
Peak memory 208732 kb
Host smart-640c8094-c5d7-46b0-9664-52ab0135544d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180654084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1180654084
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2588794688
Short name T164
Test name
Test status
Simulation time 13934727 ps
CPU time 1.14 seconds
Started Jan 24 07:31:37 PM PST 24
Finished Jan 24 07:31:46 PM PST 24
Peak memory 208940 kb
Host smart-307f759f-d19e-429c-a3ec-b937629516e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588794688 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2588794688
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.607411776
Short name T168
Test name
Test status
Simulation time 311920948 ps
CPU time 1.31 seconds
Started Jan 24 07:31:43 PM PST 24
Finished Jan 24 07:31:52 PM PST 24
Peak memory 208944 kb
Host smart-a449ca25-e0bc-4264-ae4a-a9f9a4ab37e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607411776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.607411776
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2855126682
Short name T185
Test name
Test status
Simulation time 555420635 ps
CPU time 3.79 seconds
Started Jan 24 08:16:39 PM PST 24
Finished Jan 24 08:16:44 PM PST 24
Peak memory 217316 kb
Host smart-6cf72121-29ad-4be8-ab6b-0c50663770dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855126682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2855126682
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3865865413
Short name T242
Test name
Test status
Simulation time 50225388 ps
CPU time 2.52 seconds
Started Jan 24 07:31:37 PM PST 24
Finished Jan 24 07:31:47 PM PST 24
Peak memory 217264 kb
Host smart-f680e7c7-12db-4826-8209-c9501658af19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865865413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3865865413
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3635998056
Short name T192
Test name
Test status
Simulation time 26066796 ps
CPU time 1.01 seconds
Started Jan 24 07:31:52 PM PST 24
Finished Jan 24 07:31:58 PM PST 24
Peak memory 208912 kb
Host smart-5fdd48f3-6e20-4096-b64e-b623c9076e0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635998056 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3635998056
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.555288100
Short name T230
Test name
Test status
Simulation time 13931194 ps
CPU time 0.92 seconds
Started Jan 24 07:31:43 PM PST 24
Finished Jan 24 07:31:52 PM PST 24
Peak memory 208104 kb
Host smart-67496c35-6f9e-4407-98f7-d5284350183d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555288100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.555288100
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2491833134
Short name T89
Test name
Test status
Simulation time 45057555 ps
CPU time 1.17 seconds
Started Jan 24 07:31:37 PM PST 24
Finished Jan 24 07:31:46 PM PST 24
Peak memory 208896 kb
Host smart-d31010f3-b393-46f6-bc9c-621db91789db
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491833134 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2491833134
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1143682532
Short name T272
Test name
Test status
Simulation time 1454853324 ps
CPU time 11.43 seconds
Started Jan 24 07:31:42 PM PST 24
Finished Jan 24 07:32:02 PM PST 24
Peak memory 207660 kb
Host smart-c541f83b-ea7f-4cdf-9f89-bfce35ddf111
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143682532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1143682532
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.836085585
Short name T275
Test name
Test status
Simulation time 28946114051 ps
CPU time 38.43 seconds
Started Jan 24 07:31:39 PM PST 24
Finished Jan 24 07:32:27 PM PST 24
Peak memory 208956 kb
Host smart-605b57a9-c2e0-4205-a28d-32413b303eb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836085585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.836085585
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.218596705
Short name T139
Test name
Test status
Simulation time 155699642 ps
CPU time 2.66 seconds
Started Jan 24 07:31:48 PM PST 24
Finished Jan 24 07:31:56 PM PST 24
Peak memory 210216 kb
Host smart-09dbabc3-e5c8-4ede-aa9b-9e02ff712b54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218596705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.218596705
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.222672870
Short name T210
Test name
Test status
Simulation time 67613326 ps
CPU time 2.02 seconds
Started Jan 24 07:31:48 PM PST 24
Finished Jan 24 07:31:55 PM PST 24
Peak memory 218240 kb
Host smart-1875847f-e6df-4b99-872d-579b8d2d30aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222672
870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.222672870
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2055845470
Short name T285
Test name
Test status
Simulation time 230482326 ps
CPU time 3.14 seconds
Started Jan 24 07:31:47 PM PST 24
Finished Jan 24 07:31:56 PM PST 24
Peak memory 208864 kb
Host smart-9879cde5-c462-485e-addb-906544efdc03
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055845470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2055845470
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3084824874
Short name T219
Test name
Test status
Simulation time 31986165 ps
CPU time 1.44 seconds
Started Jan 24 07:31:42 PM PST 24
Finished Jan 24 07:31:53 PM PST 24
Peak memory 208852 kb
Host smart-64a69748-483f-4c78-8684-e56ba76eb9d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084824874 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3084824874
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.535900525
Short name T165
Test name
Test status
Simulation time 42031657 ps
CPU time 1.31 seconds
Started Jan 24 07:31:50 PM PST 24
Finished Jan 24 07:31:56 PM PST 24
Peak memory 208960 kb
Host smart-ad04ad61-8ed6-4452-8ef8-12f61f24c366
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535900525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.535900525
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2021712720
Short name T77
Test name
Test status
Simulation time 86879573 ps
CPU time 3.36 seconds
Started Jan 24 07:31:48 PM PST 24
Finished Jan 24 07:31:57 PM PST 24
Peak memory 217292 kb
Host smart-beb7d55a-6c5e-4d82-97ec-5f725c65bf08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021712720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2021712720
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.419374251
Short name T217
Test name
Test status
Simulation time 106265254 ps
CPU time 1.39 seconds
Started Jan 24 07:32:05 PM PST 24
Finished Jan 24 07:32:12 PM PST 24
Peak memory 218716 kb
Host smart-8e1682db-a707-4d82-93bf-ba11ea46b973
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419374251 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.419374251
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1000155151
Short name T136
Test name
Test status
Simulation time 152500944 ps
CPU time 0.85 seconds
Started Jan 24 07:31:58 PM PST 24
Finished Jan 24 07:32:07 PM PST 24
Peak memory 208820 kb
Host smart-99b13b6d-eca9-4dfa-8422-991f5807b763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000155151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1000155151
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3492022356
Short name T202
Test name
Test status
Simulation time 43187255 ps
CPU time 1.67 seconds
Started Jan 24 07:31:57 PM PST 24
Finished Jan 24 07:32:07 PM PST 24
Peak memory 207324 kb
Host smart-c3900134-68be-46a2-bfe3-2b4dea3584a6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492022356 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3492022356
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.784384260
Short name T199
Test name
Test status
Simulation time 354309860 ps
CPU time 6.26 seconds
Started Jan 24 07:31:46 PM PST 24
Finished Jan 24 07:31:58 PM PST 24
Peak memory 207768 kb
Host smart-bf5a1b12-a593-442a-b3d1-f6e1da16c02f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784384260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.784384260
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1885281839
Short name T228
Test name
Test status
Simulation time 1341820120 ps
CPU time 9.01 seconds
Started Jan 24 07:46:54 PM PST 24
Finished Jan 24 07:47:04 PM PST 24
Peak memory 207776 kb
Host smart-5a78562c-c75b-4363-93ce-460dc00c9fab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885281839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1885281839
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.967709667
Short name T141
Test name
Test status
Simulation time 583925528 ps
CPU time 1.67 seconds
Started Jan 24 07:31:48 PM PST 24
Finished Jan 24 07:31:55 PM PST 24
Peak memory 210212 kb
Host smart-94887760-c259-4caf-8041-836abf3b6316
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967709667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.967709667
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2910498798
Short name T224
Test name
Test status
Simulation time 48724439 ps
CPU time 2.21 seconds
Started Jan 24 07:31:57 PM PST 24
Finished Jan 24 07:32:09 PM PST 24
Peak memory 218328 kb
Host smart-bed53f2f-f001-4103-8860-8360d674bc70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291049
8798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2910498798
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1047354235
Short name T132
Test name
Test status
Simulation time 616378137 ps
CPU time 3.94 seconds
Started Jan 24 07:31:54 PM PST 24
Finished Jan 24 07:32:01 PM PST 24
Peak memory 208932 kb
Host smart-0737817f-965e-4022-ac8b-03dcdab94fd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047354235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1047354235
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.36000775
Short name T245
Test name
Test status
Simulation time 16238762 ps
CPU time 1.06 seconds
Started Jan 24 07:42:12 PM PST 24
Finished Jan 24 07:42:16 PM PST 24
Peak memory 208960 kb
Host smart-b57c8d8a-6960-4e5f-bab7-54ebad352ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36000775 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.36000775
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1915676206
Short name T240
Test name
Test status
Simulation time 49080074 ps
CPU time 1.38 seconds
Started Jan 24 07:32:03 PM PST 24
Finished Jan 24 07:32:11 PM PST 24
Peak memory 209056 kb
Host smart-41221b25-c213-45e7-8739-d0cd66ed33be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915676206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1915676206
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1606011810
Short name T149
Test name
Test status
Simulation time 84954734 ps
CPU time 2.67 seconds
Started Jan 24 07:31:56 PM PST 24
Finished Jan 24 07:32:06 PM PST 24
Peak memory 217312 kb
Host smart-4c5b15d5-fab4-49ac-b752-e41f60d00d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606011810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1606011810
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1078323628
Short name T148
Test name
Test status
Simulation time 29407517 ps
CPU time 1.84 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:15:38 PM PST 24
Peak memory 217544 kb
Host smart-ae24751d-c31c-468e-8453-14dd184bd224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078323628 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1078323628
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.656575045
Short name T216
Test name
Test status
Simulation time 12827957 ps
CPU time 1.02 seconds
Started Jan 24 07:32:13 PM PST 24
Finished Jan 24 07:32:17 PM PST 24
Peak memory 208928 kb
Host smart-5470df6a-1e7b-4731-a849-df5ab98cbb1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656575045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.656575045
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2093416924
Short name T261
Test name
Test status
Simulation time 72812830 ps
CPU time 1.35 seconds
Started Jan 24 07:32:09 PM PST 24
Finished Jan 24 07:32:15 PM PST 24
Peak memory 208844 kb
Host smart-c5682464-2a94-454f-80aa-809a6f276dba
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093416924 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2093416924
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.397314325
Short name T90
Test name
Test status
Simulation time 679499304 ps
CPU time 3.4 seconds
Started Jan 24 07:32:08 PM PST 24
Finished Jan 24 07:32:17 PM PST 24
Peak memory 208848 kb
Host smart-fc2c8ec3-d8f8-4aeb-8768-0a53a14ac35b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397314325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.397314325
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4184922613
Short name T117
Test name
Test status
Simulation time 4287240399 ps
CPU time 25.4 seconds
Started Jan 24 07:32:00 PM PST 24
Finished Jan 24 07:32:32 PM PST 24
Peak memory 208948 kb
Host smart-5f295e94-5a10-452a-ae48-8d1cfe10b637
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184922613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4184922613
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3968150654
Short name T233
Test name
Test status
Simulation time 88122152 ps
CPU time 1.68 seconds
Started Jan 24 07:31:55 PM PST 24
Finished Jan 24 07:32:04 PM PST 24
Peak memory 210240 kb
Host smart-ab88b037-5dcc-4e66-8dfc-8d138bc4cdf2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968150654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3968150654
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4140379588
Short name T243
Test name
Test status
Simulation time 60777610 ps
CPU time 1.36 seconds
Started Jan 24 07:32:06 PM PST 24
Finished Jan 24 07:32:14 PM PST 24
Peak memory 219188 kb
Host smart-efacaad3-b63b-4157-a810-e2cbe3de56be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414037
9588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4140379588
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.809266973
Short name T978
Test name
Test status
Simulation time 239605362 ps
CPU time 2.13 seconds
Started Jan 24 07:31:57 PM PST 24
Finished Jan 24 07:32:09 PM PST 24
Peak memory 208900 kb
Host smart-a6017a8b-e15e-4d42-8a4a-c0582b5baf44
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809266973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.809266973
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3555173045
Short name T256
Test name
Test status
Simulation time 83543110 ps
CPU time 1.42 seconds
Started Jan 24 07:32:07 PM PST 24
Finished Jan 24 07:32:15 PM PST 24
Peak memory 208908 kb
Host smart-1c06f044-1d63-4ab3-a064-1d81fdc15636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555173045 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3555173045
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3448372293
Short name T145
Test name
Test status
Simulation time 43018174 ps
CPU time 1.45 seconds
Started Jan 24 07:38:54 PM PST 24
Finished Jan 24 07:39:02 PM PST 24
Peak memory 208980 kb
Host smart-f2de1172-ffe0-4630-ab07-2f176281a8ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448372293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3448372293
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3989270138
Short name T183
Test name
Test status
Simulation time 39772222 ps
CPU time 2.5 seconds
Started Jan 24 07:32:10 PM PST 24
Finished Jan 24 07:32:16 PM PST 24
Peak memory 218308 kb
Host smart-3999612a-3fb7-40cb-aad8-0d50a2ec7c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989270138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3989270138
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.708850076
Short name T798
Test name
Test status
Simulation time 20271293 ps
CPU time 1.18 seconds
Started Jan 24 08:33:02 PM PST 24
Finished Jan 24 08:33:04 PM PST 24
Peak memory 209480 kb
Host smart-968f79f5-1eb5-44a7-814d-4e3ae4301a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708850076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.708850076
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.569999278
Short name T320
Test name
Test status
Simulation time 1368231226 ps
CPU time 11.14 seconds
Started Jan 24 08:32:04 PM PST 24
Finished Jan 24 08:32:16 PM PST 24
Peak memory 218116 kb
Host smart-eaea4400-6a15-49e3-b275-fb4a76be31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569999278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.569999278
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.4002041461
Short name T403
Test name
Test status
Simulation time 125207495 ps
CPU time 2.12 seconds
Started Jan 24 08:32:44 PM PST 24
Finished Jan 24 08:32:46 PM PST 24
Peak memory 209500 kb
Host smart-4f6334a5-f922-4306-84de-a6796dcfddfc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002041461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.4002041461
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1422366938
Short name T513
Test name
Test status
Simulation time 14065937541 ps
CPU time 92.54 seconds
Started Jan 24 09:10:35 PM PST 24
Finished Jan 24 09:12:15 PM PST 24
Peak memory 218376 kb
Host smart-72da311c-1bf0-4881-898e-868ab4b34de4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422366938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1422366938
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2150530529
Short name T973
Test name
Test status
Simulation time 902512071 ps
CPU time 7.44 seconds
Started Jan 24 08:32:45 PM PST 24
Finished Jan 24 08:32:54 PM PST 24
Peak memory 217784 kb
Host smart-1c928e5e-8791-4044-8a07-920ece2f820b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150530529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.2150530529
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2896568478
Short name T818
Test name
Test status
Simulation time 1441590112 ps
CPU time 10.91 seconds
Started Jan 24 08:32:34 PM PST 24
Finished Jan 24 08:32:46 PM PST 24
Peak memory 218052 kb
Host smart-6abe3b68-c875-4a4a-9216-6c47961f187d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896568478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2896568478
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1275184287
Short name T529
Test name
Test status
Simulation time 3241401316 ps
CPU time 36.28 seconds
Started Jan 24 08:32:49 PM PST 24
Finished Jan 24 08:33:26 PM PST 24
Peak memory 213752 kb
Host smart-81d7cf4b-aa1e-4ca1-95d3-7cf4f76844f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275184287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1275184287
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1403054000
Short name T370
Test name
Test status
Simulation time 399979497 ps
CPU time 3.45 seconds
Started Jan 24 08:32:17 PM PST 24
Finished Jan 24 08:32:22 PM PST 24
Peak memory 212804 kb
Host smart-b38df52d-3609-4374-ab38-0b37d083c21e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403054000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1403054000
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1083599896
Short name T531
Test name
Test status
Simulation time 4767086662 ps
CPU time 87.38 seconds
Started Jan 24 10:48:50 PM PST 24
Finished Jan 24 10:50:18 PM PST 24
Peak memory 281840 kb
Host smart-704fcf43-f936-42da-98e1-cc35310930f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083599896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1083599896
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2489180272
Short name T376
Test name
Test status
Simulation time 160871161 ps
CPU time 5.16 seconds
Started Jan 24 08:32:02 PM PST 24
Finished Jan 24 08:32:08 PM PST 24
Peak memory 218072 kb
Host smart-1279e23c-0aa2-4e44-ad5e-3add43f56928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489180272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2489180272
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1605134495
Short name T383
Test name
Test status
Simulation time 411077957 ps
CPU time 8.45 seconds
Started Jan 24 08:32:17 PM PST 24
Finished Jan 24 08:32:26 PM PST 24
Peak memory 213968 kb
Host smart-e27990f6-dff7-40ab-868e-52093883d706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605134495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1605134495
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2624585428
Short name T356
Test name
Test status
Simulation time 1160340429 ps
CPU time 15.86 seconds
Started Jan 24 08:32:46 PM PST 24
Finished Jan 24 08:33:03 PM PST 24
Peak memory 219120 kb
Host smart-95dbaf9a-a3a9-4204-9554-a3b9e620d106
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624585428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2624585428
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2575450510
Short name T405
Test name
Test status
Simulation time 328105596 ps
CPU time 10.51 seconds
Started Jan 24 08:54:00 PM PST 24
Finished Jan 24 08:54:12 PM PST 24
Peak memory 218112 kb
Host smart-df389e9e-271d-4500-a9dd-260a1a30d8c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575450510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2575450510
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3384393881
Short name T954
Test name
Test status
Simulation time 695647344 ps
CPU time 22.46 seconds
Started Jan 24 08:32:45 PM PST 24
Finished Jan 24 08:33:08 PM PST 24
Peak memory 218112 kb
Host smart-c526cea2-edbe-4752-bc1a-f1e9597d0f55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384393881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
384393881
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1573610828
Short name T584
Test name
Test status
Simulation time 56197129 ps
CPU time 1.96 seconds
Started Jan 24 08:31:49 PM PST 24
Finished Jan 24 08:31:52 PM PST 24
Peak memory 213368 kb
Host smart-ab4ec1f5-e1d3-489a-8d35-8c9ce5502e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573610828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1573610828
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1804903184
Short name T884
Test name
Test status
Simulation time 208347967 ps
CPU time 16.18 seconds
Started Jan 24 08:32:04 PM PST 24
Finished Jan 24 08:32:21 PM PST 24
Peak memory 250828 kb
Host smart-77ba1aff-ffe3-401e-8284-d0db538517c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804903184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1804903184
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1440490933
Short name T630
Test name
Test status
Simulation time 556408210 ps
CPU time 6.69 seconds
Started Jan 24 08:32:03 PM PST 24
Finished Jan 24 08:32:11 PM PST 24
Peak memory 249964 kb
Host smart-20e36a96-e62c-4193-a9b0-a92c1219caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440490933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1440490933
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1301476267
Short name T66
Test name
Test status
Simulation time 8607880644 ps
CPU time 45.56 seconds
Started Jan 24 08:32:56 PM PST 24
Finished Jan 24 08:33:43 PM PST 24
Peak memory 226352 kb
Host smart-44863983-556d-4eea-b16a-146538d0f6f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301476267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1301476267
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2412620316
Short name T918
Test name
Test status
Simulation time 34878899 ps
CPU time 0.9 seconds
Started Jan 24 08:32:00 PM PST 24
Finished Jan 24 08:32:03 PM PST 24
Peak memory 207904 kb
Host smart-39d6525b-94c7-45d1-9c36-14233c843dd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412620316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2412620316
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3640829043
Short name T869
Test name
Test status
Simulation time 46783138 ps
CPU time 0.86 seconds
Started Jan 24 08:34:05 PM PST 24
Finished Jan 24 08:34:08 PM PST 24
Peak memory 207864 kb
Host smart-638e5ae4-5c05-433f-8e76-9277c7e6a365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640829043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3640829043
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1413777887
Short name T885
Test name
Test status
Simulation time 37678331 ps
CPU time 0.78 seconds
Started Jan 24 08:33:20 PM PST 24
Finished Jan 24 08:33:21 PM PST 24
Peak memory 209248 kb
Host smart-7a998b22-3f55-452d-917c-ebd9a53623c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413777887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1413777887
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3805028968
Short name T571
Test name
Test status
Simulation time 457630321 ps
CPU time 11.07 seconds
Started Jan 24 08:33:15 PM PST 24
Finished Jan 24 08:33:27 PM PST 24
Peak memory 218104 kb
Host smart-935e18b3-2a8e-4a3f-86fd-84ba22a4341a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805028968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3805028968
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1408113836
Short name T889
Test name
Test status
Simulation time 42363148 ps
CPU time 1.72 seconds
Started Jan 24 09:20:53 PM PST 24
Finished Jan 24 09:20:55 PM PST 24
Peak memory 209452 kb
Host smart-bbec7ed0-69fb-47cc-9dbb-6e45d90946ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408113836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.1408113836
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.70801774
Short name T950
Test name
Test status
Simulation time 2972563960 ps
CPU time 44.02 seconds
Started Jan 24 08:33:36 PM PST 24
Finished Jan 24 08:34:21 PM PST 24
Peak memory 218156 kb
Host smart-d7c82779-3e8c-45d9-9cc3-da580a01564e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70801774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_erro
rs.70801774
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1807066678
Short name T712
Test name
Test status
Simulation time 4103703093 ps
CPU time 11 seconds
Started Jan 24 08:33:35 PM PST 24
Finished Jan 24 08:33:46 PM PST 24
Peak memory 217848 kb
Host smart-44be0e91-91d2-42cc-83fc-70f8a1244492
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807066678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.1807066678
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.756697613
Short name T562
Test name
Test status
Simulation time 3840025393 ps
CPU time 8.15 seconds
Started Jan 24 09:01:35 PM PST 24
Finished Jan 24 09:01:45 PM PST 24
Peak memory 218120 kb
Host smart-c7434171-eefe-4c8c-8909-f5a8a1d35a5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756697613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.756697613
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2176476597
Short name T821
Test name
Test status
Simulation time 1233252994 ps
CPU time 18.42 seconds
Started Jan 24 08:33:43 PM PST 24
Finished Jan 24 08:34:02 PM PST 24
Peak memory 213024 kb
Host smart-c04f2907-8443-436b-9f2b-ee3cb396134c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176476597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2176476597
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3699692617
Short name T595
Test name
Test status
Simulation time 88239837 ps
CPU time 2.08 seconds
Started Jan 24 08:33:26 PM PST 24
Finished Jan 24 08:33:31 PM PST 24
Peak memory 212544 kb
Host smart-f99dbb96-7b49-4644-96c4-a75d722c5f89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699692617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3699692617
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3903291872
Short name T676
Test name
Test status
Simulation time 5838596302 ps
CPU time 31.12 seconds
Started Jan 24 08:33:26 PM PST 24
Finished Jan 24 08:34:00 PM PST 24
Peak memory 251012 kb
Host smart-38aafd5a-2110-479b-af40-6fb3556ad00c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903291872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3903291872
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3009926000
Short name T970
Test name
Test status
Simulation time 572422441 ps
CPU time 21.3 seconds
Started Jan 24 08:33:26 PM PST 24
Finished Jan 24 08:33:50 PM PST 24
Peak memory 247920 kb
Host smart-95d4722a-06d9-4b99-bbe0-39f9939bc211
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009926000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3009926000
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2626671625
Short name T619
Test name
Test status
Simulation time 26263647 ps
CPU time 1.8 seconds
Started Jan 24 08:33:11 PM PST 24
Finished Jan 24 08:33:14 PM PST 24
Peak memory 218108 kb
Host smart-ffc9e6da-e531-475f-9ac2-e1fb38eaae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626671625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2626671625
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2745614976
Short name T570
Test name
Test status
Simulation time 4654590501 ps
CPU time 9.5 seconds
Started Jan 24 08:33:13 PM PST 24
Finished Jan 24 08:33:23 PM PST 24
Peak memory 214736 kb
Host smart-f206c764-c494-4c4c-847f-a7630bc0af68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745614976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2745614976
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2895192390
Short name T87
Test name
Test status
Simulation time 1691294054 ps
CPU time 40.52 seconds
Started Jan 24 08:33:59 PM PST 24
Finished Jan 24 08:34:43 PM PST 24
Peak memory 281064 kb
Host smart-4432333a-e38f-4e0e-8d56-936165fa5b6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895192390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2895192390
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.827309479
Short name T575
Test name
Test status
Simulation time 712242451 ps
CPU time 15.55 seconds
Started Jan 24 08:33:56 PM PST 24
Finished Jan 24 08:34:16 PM PST 24
Peak memory 218104 kb
Host smart-1cd03d65-8736-4a57-9dbb-1ff3c5addb55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827309479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.827309479
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2868485374
Short name T393
Test name
Test status
Simulation time 1455460885 ps
CPU time 14.07 seconds
Started Jan 24 08:33:58 PM PST 24
Finished Jan 24 08:34:16 PM PST 24
Peak memory 218092 kb
Host smart-33c96eb9-114d-49fa-8aa4-ea76fd671381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868485374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2868485374
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3939772222
Short name T840
Test name
Test status
Simulation time 567605771 ps
CPU time 12.58 seconds
Started Jan 24 08:33:56 PM PST 24
Finished Jan 24 08:34:13 PM PST 24
Peak memory 218088 kb
Host smart-09f7ed4d-3bff-40a1-b57b-5bfe9092646c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939772222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
939772222
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4238746353
Short name T544
Test name
Test status
Simulation time 4097383192 ps
CPU time 9.78 seconds
Started Jan 24 08:33:10 PM PST 24
Finished Jan 24 08:33:21 PM PST 24
Peak memory 218168 kb
Host smart-c4da22ed-36a7-4ed4-a012-e9b54866ba89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238746353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4238746353
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.719255357
Short name T74
Test name
Test status
Simulation time 71324960 ps
CPU time 2.19 seconds
Started Jan 24 08:33:04 PM PST 24
Finished Jan 24 08:33:07 PM PST 24
Peak memory 213588 kb
Host smart-08ffe425-f6f3-4652-bdd5-f53b2f8255ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719255357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.719255357
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2738907764
Short name T672
Test name
Test status
Simulation time 502760520 ps
CPU time 25.48 seconds
Started Jan 24 08:33:00 PM PST 24
Finished Jan 24 08:33:27 PM PST 24
Peak memory 251048 kb
Host smart-c0a93a83-71b0-4cb6-a00f-0333d12a9004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738907764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2738907764
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3335320729
Short name T387
Test name
Test status
Simulation time 317561857 ps
CPU time 6.96 seconds
Started Jan 24 08:33:03 PM PST 24
Finished Jan 24 08:33:10 PM PST 24
Peak memory 249604 kb
Host smart-72c61eaa-b71e-49b2-82de-df73ebd31fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335320729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3335320729
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3311955424
Short name T732
Test name
Test status
Simulation time 53592937546 ps
CPU time 234.46 seconds
Started Jan 24 08:33:58 PM PST 24
Finished Jan 24 08:37:56 PM PST 24
Peak memory 251160 kb
Host smart-91e8c4e6-a229-45db-af3e-fe955cc3c82f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311955424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3311955424
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3203430858
Short name T633
Test name
Test status
Simulation time 26381620 ps
CPU time 0.8 seconds
Started Jan 24 08:33:04 PM PST 24
Finished Jan 24 08:33:07 PM PST 24
Peak memory 208340 kb
Host smart-e8750be9-3f8d-4e7a-b990-7045b52e827e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203430858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3203430858
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1974237972
Short name T913
Test name
Test status
Simulation time 22211005 ps
CPU time 1.05 seconds
Started Jan 24 08:40:21 PM PST 24
Finished Jan 24 08:40:23 PM PST 24
Peak memory 208148 kb
Host smart-55d1470b-b178-459c-b937-3604f368c5c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974237972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1974237972
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1613618179
Short name T717
Test name
Test status
Simulation time 2929338352 ps
CPU time 20.75 seconds
Started Jan 24 08:40:14 PM PST 24
Finished Jan 24 08:40:36 PM PST 24
Peak memory 218216 kb
Host smart-4c9e284f-0ff3-4dec-a0ae-68491504592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613618179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1613618179
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.4086034413
Short name T330
Test name
Test status
Simulation time 468354626 ps
CPU time 5.99 seconds
Started Jan 24 08:40:11 PM PST 24
Finished Jan 24 08:40:18 PM PST 24
Peak memory 209492 kb
Host smart-badb03d5-35fb-4044-8a64-b2f4edbe70ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086034413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.4086034413
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2189248178
Short name T560
Test name
Test status
Simulation time 1970263696 ps
CPU time 50.87 seconds
Started Jan 24 08:40:12 PM PST 24
Finished Jan 24 08:41:04 PM PST 24
Peak memory 218000 kb
Host smart-b133c815-0c6a-4e95-a4c6-d9352592cb6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189248178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2189248178
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3288008718
Short name T467
Test name
Test status
Simulation time 480171980 ps
CPU time 7.47 seconds
Started Jan 24 08:40:12 PM PST 24
Finished Jan 24 08:40:21 PM PST 24
Peak memory 218000 kb
Host smart-26b3a68b-9812-402f-8837-ce6ba6c81f14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288008718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3288008718
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2786698653
Short name T873
Test name
Test status
Simulation time 2229253468 ps
CPU time 7.42 seconds
Started Jan 24 08:40:12 PM PST 24
Finished Jan 24 08:40:21 PM PST 24
Peak memory 212976 kb
Host smart-e484fd6e-4dea-42a6-a0c0-20ddf876cc92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786698653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2786698653
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2875385517
Short name T396
Test name
Test status
Simulation time 2954479488 ps
CPU time 68.46 seconds
Started Jan 24 08:40:14 PM PST 24
Finished Jan 24 08:41:24 PM PST 24
Peak memory 253496 kb
Host smart-400744c5-9f86-4737-9640-1b59e806fb54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875385517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2875385517
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4087211671
Short name T427
Test name
Test status
Simulation time 4495990882 ps
CPU time 20.53 seconds
Started Jan 24 08:40:14 PM PST 24
Finished Jan 24 08:40:36 PM PST 24
Peak memory 251108 kb
Host smart-a4a73104-80f4-4a4e-9d19-ffa0b343896a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087211671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.4087211671
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2835658860
Short name T380
Test name
Test status
Simulation time 157232235 ps
CPU time 2.75 seconds
Started Jan 24 08:40:15 PM PST 24
Finished Jan 24 08:40:19 PM PST 24
Peak memory 218124 kb
Host smart-54c1f763-02a4-439d-9f5f-1c84f07555d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835658860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2835658860
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.829060227
Short name T721
Test name
Test status
Simulation time 1344248930 ps
CPU time 11.62 seconds
Started Jan 24 08:40:14 PM PST 24
Finished Jan 24 08:40:26 PM PST 24
Peak memory 218620 kb
Host smart-8206d40e-f0ce-4d5e-aa63-bea1d5a3b5aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829060227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.829060227
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1289252159
Short name T718
Test name
Test status
Simulation time 1953918471 ps
CPU time 27.83 seconds
Started Jan 24 08:40:21 PM PST 24
Finished Jan 24 08:40:50 PM PST 24
Peak memory 218096 kb
Host smart-2a08525d-32ed-4f6f-8cb0-d4e5d9f1e9a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289252159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1289252159
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3030175042
Short name T661
Test name
Test status
Simulation time 686744429 ps
CPU time 10.58 seconds
Started Jan 24 08:40:19 PM PST 24
Finished Jan 24 08:40:31 PM PST 24
Peak memory 218100 kb
Host smart-6c63e718-9463-4368-9724-12deb82af7dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030175042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3030175042
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.169726016
Short name T422
Test name
Test status
Simulation time 1405120481 ps
CPU time 10.23 seconds
Started Jan 24 08:40:10 PM PST 24
Finished Jan 24 08:40:21 PM PST 24
Peak memory 218108 kb
Host smart-98604c70-d98c-490c-8ed9-fabd48687c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169726016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.169726016
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2041088261
Short name T582
Test name
Test status
Simulation time 53779746 ps
CPU time 1.2 seconds
Started Jan 24 08:40:05 PM PST 24
Finished Jan 24 08:40:07 PM PST 24
Peak memory 212516 kb
Host smart-cab7cd6d-336b-47e9-a0ed-3dedd37a8e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041088261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2041088261
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.580489994
Short name T557
Test name
Test status
Simulation time 913647331 ps
CPU time 31.49 seconds
Started Jan 24 08:40:03 PM PST 24
Finished Jan 24 08:40:36 PM PST 24
Peak memory 250776 kb
Host smart-eabb73eb-5efe-4ed8-968e-963e6749a436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580489994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.580489994
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2600630146
Short name T882
Test name
Test status
Simulation time 205639525 ps
CPU time 9.82 seconds
Started Jan 24 08:40:03 PM PST 24
Finished Jan 24 08:40:14 PM PST 24
Peak memory 251096 kb
Host smart-adde3c69-f6a3-47c2-b7a3-d1b604f4a743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600630146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2600630146
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1925016195
Short name T902
Test name
Test status
Simulation time 66662101 ps
CPU time 0.95 seconds
Started Jan 24 08:40:53 PM PST 24
Finished Jan 24 08:40:55 PM PST 24
Peak memory 209472 kb
Host smart-01d09835-72ca-4633-8289-4269a95b89a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925016195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1925016195
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3003730565
Short name T483
Test name
Test status
Simulation time 689677521 ps
CPU time 16.24 seconds
Started Jan 24 08:40:31 PM PST 24
Finished Jan 24 08:40:48 PM PST 24
Peak memory 218064 kb
Host smart-c38dd2a7-4545-42bd-8f3a-a65ea2d94282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003730565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3003730565
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2965258951
Short name T28
Test name
Test status
Simulation time 1472734963 ps
CPU time 5.51 seconds
Started Jan 24 08:40:41 PM PST 24
Finished Jan 24 08:40:47 PM PST 24
Peak memory 209504 kb
Host smart-837b7ca5-8d92-4941-bace-d9e33ac7b7cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965258951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.2965258951
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3550510140
Short name T839
Test name
Test status
Simulation time 1889441298 ps
CPU time 51.42 seconds
Started Jan 24 08:40:40 PM PST 24
Finished Jan 24 08:41:32 PM PST 24
Peak memory 218064 kb
Host smart-0aa9f881-1bb9-46eb-b6a4-aaf1f509470d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550510140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3550510140
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2945236590
Short name T665
Test name
Test status
Simulation time 639660427 ps
CPU time 10.05 seconds
Started Jan 24 08:40:39 PM PST 24
Finished Jan 24 08:40:50 PM PST 24
Peak memory 218068 kb
Host smart-32221bea-19e3-490c-81ec-53f0af7cb93a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945236590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2945236590
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1171953187
Short name T750
Test name
Test status
Simulation time 270604058 ps
CPU time 2.55 seconds
Started Jan 24 11:11:45 PM PST 24
Finished Jan 24 11:11:50 PM PST 24
Peak memory 217784 kb
Host smart-5301a4e9-01a2-4ef2-9f95-dccbe8a634a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171953187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1171953187
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.980562393
Short name T907
Test name
Test status
Simulation time 2853931223 ps
CPU time 49.17 seconds
Started Jan 24 08:40:42 PM PST 24
Finished Jan 24 08:41:32 PM PST 24
Peak memory 267436 kb
Host smart-e54fed15-3a27-452c-9018-72bdb819a559
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980562393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.980562393
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1029376251
Short name T916
Test name
Test status
Simulation time 11323941210 ps
CPU time 14.13 seconds
Started Jan 24 08:40:40 PM PST 24
Finished Jan 24 08:40:55 PM PST 24
Peak memory 251148 kb
Host smart-59717dbe-a56c-4790-a85c-038b1f255c41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029376251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1029376251
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3192338201
Short name T315
Test name
Test status
Simulation time 51285799 ps
CPU time 2.74 seconds
Started Jan 24 08:40:29 PM PST 24
Finished Jan 24 08:40:32 PM PST 24
Peak memory 218108 kb
Host smart-69028d17-fbb5-4a92-9db9-a4ed483f5ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192338201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3192338201
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1058322553
Short name T597
Test name
Test status
Simulation time 295160724 ps
CPU time 12.46 seconds
Started Jan 24 08:40:48 PM PST 24
Finished Jan 24 08:41:01 PM PST 24
Peak memory 218108 kb
Host smart-754c6132-fe02-49f2-94a8-4c0f4f72bfaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058322553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1058322553
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1112366633
Short name T920
Test name
Test status
Simulation time 1494351195 ps
CPU time 8.96 seconds
Started Jan 24 08:40:48 PM PST 24
Finished Jan 24 08:40:58 PM PST 24
Peak memory 218120 kb
Host smart-19978380-445f-417f-9664-b4c46dbf9b1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112366633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1112366633
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1049184571
Short name T64
Test name
Test status
Simulation time 1580317302 ps
CPU time 8.81 seconds
Started Jan 24 08:40:27 PM PST 24
Finished Jan 24 08:40:37 PM PST 24
Peak memory 218116 kb
Host smart-ef373872-fce3-41a2-95af-e224ab820151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049184571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1049184571
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1136333249
Short name T434
Test name
Test status
Simulation time 80787149 ps
CPU time 1.89 seconds
Started Jan 24 08:40:20 PM PST 24
Finished Jan 24 08:40:23 PM PST 24
Peak memory 213536 kb
Host smart-f0dc366b-f56b-4d3d-9fca-9f6c926ba836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136333249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1136333249
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1913068814
Short name T580
Test name
Test status
Simulation time 1447937439 ps
CPU time 41.8 seconds
Started Jan 24 08:40:20 PM PST 24
Finished Jan 24 08:41:03 PM PST 24
Peak memory 249532 kb
Host smart-d6cf07a9-44e5-4e68-8fa5-c97f9780f75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913068814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1913068814
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2586416754
Short name T358
Test name
Test status
Simulation time 208554664 ps
CPU time 10.11 seconds
Started Jan 24 08:40:28 PM PST 24
Finished Jan 24 08:40:40 PM PST 24
Peak memory 251092 kb
Host smart-17582721-5fe1-41d1-a402-86fddd2e1fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586416754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2586416754
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3715478852
Short name T423
Test name
Test status
Simulation time 9487181004 ps
CPU time 85.2 seconds
Started Jan 24 08:40:49 PM PST 24
Finished Jan 24 08:42:15 PM PST 24
Peak memory 251056 kb
Host smart-38392983-8cdd-4155-b3a7-cb318cc27543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715478852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3715478852
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.769134073
Short name T37
Test name
Test status
Simulation time 47984246 ps
CPU time 0.83 seconds
Started Jan 24 08:40:20 PM PST 24
Finished Jan 24 08:40:22 PM PST 24
Peak memory 208140 kb
Host smart-32f873bc-44a7-4861-931c-273c1020dc61
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769134073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.769134073
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.749079972
Short name T696
Test name
Test status
Simulation time 46628904 ps
CPU time 1.11 seconds
Started Jan 24 08:41:22 PM PST 24
Finished Jan 24 08:41:24 PM PST 24
Peak memory 209568 kb
Host smart-4796c1b2-6a62-4032-9b58-29d418dafe78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749079972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.749079972
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3599984475
Short name T649
Test name
Test status
Simulation time 787636413 ps
CPU time 9.38 seconds
Started Jan 24 08:41:11 PM PST 24
Finished Jan 24 08:41:22 PM PST 24
Peak memory 218084 kb
Host smart-3ffd6c6d-40eb-45c6-b7ef-6847ca11d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599984475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3599984475
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1886729683
Short name T754
Test name
Test status
Simulation time 623597756 ps
CPU time 15.13 seconds
Started Jan 24 08:41:16 PM PST 24
Finished Jan 24 08:41:32 PM PST 24
Peak memory 209472 kb
Host smart-a29301bf-6d28-445d-a272-12b3faf48225
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886729683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_a
ccess.1886729683
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4045323874
Short name T715
Test name
Test status
Simulation time 8421850572 ps
CPU time 67.16 seconds
Started Jan 25 01:32:50 AM PST 24
Finished Jan 25 01:34:01 AM PST 24
Peak memory 219156 kb
Host smart-b26b90a2-569e-43a4-aa9a-2e6402ff5009
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045323874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4045323874
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.148953681
Short name T465
Test name
Test status
Simulation time 278476687 ps
CPU time 5.58 seconds
Started Jan 24 08:41:13 PM PST 24
Finished Jan 24 08:41:19 PM PST 24
Peak memory 218040 kb
Host smart-e069375b-bf22-4146-abe7-46d143e5a5b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148953681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.148953681
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3430093029
Short name T15
Test name
Test status
Simulation time 427098547 ps
CPU time 2.42 seconds
Started Jan 24 08:41:10 PM PST 24
Finished Jan 24 08:41:13 PM PST 24
Peak memory 212796 kb
Host smart-94db31cb-8183-4fdf-b92e-ef784edbb59e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430093029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3430093029
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1290132878
Short name T713
Test name
Test status
Simulation time 1606844118 ps
CPU time 44.38 seconds
Started Jan 24 08:41:12 PM PST 24
Finished Jan 24 08:41:57 PM PST 24
Peak memory 268516 kb
Host smart-d2066533-bb8a-4188-9daf-790d891fcf77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290132878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1290132878
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1688634008
Short name T815
Test name
Test status
Simulation time 4666222888 ps
CPU time 10.18 seconds
Started Jan 24 08:41:10 PM PST 24
Finished Jan 24 08:41:21 PM PST 24
Peak memory 223924 kb
Host smart-3eebbedc-b7ac-4ce5-9c85-a7c3b46f146f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688634008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1688634008
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2454348641
Short name T893
Test name
Test status
Simulation time 144847091 ps
CPU time 2.79 seconds
Started Jan 24 08:41:03 PM PST 24
Finished Jan 24 08:41:07 PM PST 24
Peak memory 218124 kb
Host smart-15d9e540-3054-450d-888d-02e6704b3f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454348641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2454348641
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1950759115
Short name T622
Test name
Test status
Simulation time 388461982 ps
CPU time 17.33 seconds
Started Jan 24 08:41:11 PM PST 24
Finished Jan 24 08:41:29 PM PST 24
Peak memory 219120 kb
Host smart-61d48b64-3f31-48f5-8252-64f8ed984acf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950759115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1950759115
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.4053352687
Short name T378
Test name
Test status
Simulation time 470012264 ps
CPU time 12.49 seconds
Started Jan 24 08:41:25 PM PST 24
Finished Jan 24 08:41:38 PM PST 24
Peak memory 218128 kb
Host smart-adb10c3b-2fb8-44f3-bbe3-586e4c28ff90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053352687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.4053352687
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1741152284
Short name T780
Test name
Test status
Simulation time 1032984432 ps
CPU time 10.01 seconds
Started Jan 24 08:41:10 PM PST 24
Finished Jan 24 08:41:21 PM PST 24
Peak memory 218112 kb
Host smart-c5b6c1c8-ea58-41dd-93bf-3f289a8a6da6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741152284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1741152284
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1604750563
Short name T681
Test name
Test status
Simulation time 525366916 ps
CPU time 10.18 seconds
Started Jan 24 09:15:40 PM PST 24
Finished Jan 24 09:15:52 PM PST 24
Peak memory 218112 kb
Host smart-5da277bc-e2b9-4c0b-bc1f-30224b4465a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604750563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1604750563
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2542560782
Short name T439
Test name
Test status
Simulation time 87728812 ps
CPU time 2.53 seconds
Started Jan 24 08:40:57 PM PST 24
Finished Jan 24 08:41:00 PM PST 24
Peak memory 213732 kb
Host smart-316026ec-cd94-49a9-add1-ca0e33f92470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542560782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2542560782
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2850782768
Short name T823
Test name
Test status
Simulation time 249520862 ps
CPU time 29.51 seconds
Started Jan 24 08:40:57 PM PST 24
Finished Jan 24 08:41:28 PM PST 24
Peak memory 251056 kb
Host smart-e02b46d7-506b-4128-8b78-fa34e40a1780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850782768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2850782768
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1175024997
Short name T663
Test name
Test status
Simulation time 73771978 ps
CPU time 8.34 seconds
Started Jan 24 08:41:06 PM PST 24
Finished Jan 24 08:41:16 PM PST 24
Peak memory 246128 kb
Host smart-0b71e944-d89e-4d38-8656-58b653aad7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175024997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1175024997
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.345647089
Short name T588
Test name
Test status
Simulation time 5329233192 ps
CPU time 51.34 seconds
Started Jan 24 08:41:21 PM PST 24
Finished Jan 24 08:42:13 PM PST 24
Peak memory 251188 kb
Host smart-44025550-74e2-4857-bcd9-8e6f754c5f69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345647089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.345647089
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4024435806
Short name T368
Test name
Test status
Simulation time 13871633 ps
CPU time 0.97 seconds
Started Jan 24 08:40:53 PM PST 24
Finished Jan 24 08:40:54 PM PST 24
Peak memory 208224 kb
Host smart-f55a0d7f-6b87-4e7f-ac2d-502c3c890908
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024435806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4024435806
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.112063869
Short name T851
Test name
Test status
Simulation time 224818105 ps
CPU time 1.15 seconds
Started Jan 24 08:41:48 PM PST 24
Finished Jan 24 08:41:50 PM PST 24
Peak memory 209540 kb
Host smart-f6f20685-37ec-44c0-ae01-ac9f776b6e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112063869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.112063869
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2447731905
Short name T638
Test name
Test status
Simulation time 654006918 ps
CPU time 14.84 seconds
Started Jan 24 08:57:53 PM PST 24
Finished Jan 24 08:58:11 PM PST 24
Peak memory 218124 kb
Host smart-1ce8c29a-86c3-4e90-9506-fdd1a2b45844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447731905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2447731905
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.123936053
Short name T27
Test name
Test status
Simulation time 967719861 ps
CPU time 6.69 seconds
Started Jan 24 08:41:38 PM PST 24
Finished Jan 24 08:41:45 PM PST 24
Peak memory 209528 kb
Host smart-8cd41f6b-c387-4391-8139-27b074a48526
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123936053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ac
cess.123936053
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1530769650
Short name T901
Test name
Test status
Simulation time 9849596972 ps
CPU time 65.57 seconds
Started Jan 24 08:41:37 PM PST 24
Finished Jan 24 08:42:43 PM PST 24
Peak memory 218100 kb
Host smart-20c76ea7-2b13-4fc4-aec2-523c6d258dcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530769650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1530769650
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1828726638
Short name T796
Test name
Test status
Simulation time 293641068 ps
CPU time 9.53 seconds
Started Jan 24 09:38:57 PM PST 24
Finished Jan 24 09:39:07 PM PST 24
Peak memory 218056 kb
Host smart-093d54d0-764e-42d8-8f0c-de094ff68a93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828726638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1828726638
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.380034720
Short name T447
Test name
Test status
Simulation time 499728524 ps
CPU time 3.99 seconds
Started Jan 24 09:40:44 PM PST 24
Finished Jan 24 09:40:48 PM PST 24
Peak memory 212944 kb
Host smart-756f4089-3676-4743-bb76-22197fc39b6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380034720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
380034720
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.990926107
Short name T609
Test name
Test status
Simulation time 2101554799 ps
CPU time 48.86 seconds
Started Jan 24 08:41:30 PM PST 24
Finished Jan 24 08:42:20 PM PST 24
Peak memory 251932 kb
Host smart-482cb9ea-611d-4687-9fec-e745aa329ebb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990926107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.990926107
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.246251866
Short name T300
Test name
Test status
Simulation time 939129272 ps
CPU time 13.23 seconds
Started Jan 24 08:41:30 PM PST 24
Finished Jan 24 08:41:44 PM PST 24
Peak memory 251012 kb
Host smart-5d1c77ed-73cd-43ac-9fc4-e3b0a4285f48
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246251866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.246251866
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1582476105
Short name T413
Test name
Test status
Simulation time 37360873 ps
CPU time 2.52 seconds
Started Jan 24 08:41:31 PM PST 24
Finished Jan 24 08:41:34 PM PST 24
Peak memory 218092 kb
Host smart-dbb88e74-9b12-4dc8-9f72-d5aeaf8bc42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582476105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1582476105
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1061737308
Short name T51
Test name
Test status
Simulation time 1047039713 ps
CPU time 13.23 seconds
Started Jan 24 08:41:38 PM PST 24
Finished Jan 24 08:41:52 PM PST 24
Peak memory 218064 kb
Host smart-1b5d9227-9278-44be-9414-02fdafddc421
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061737308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1061737308
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3744301306
Short name T825
Test name
Test status
Simulation time 990857442 ps
CPU time 7.97 seconds
Started Jan 24 09:17:24 PM PST 24
Finished Jan 24 09:17:33 PM PST 24
Peak memory 218116 kb
Host smart-2bf03e25-c7df-4603-8509-b87332017804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744301306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3744301306
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3654225768
Short name T526
Test name
Test status
Simulation time 305893149 ps
CPU time 13.41 seconds
Started Jan 24 09:35:32 PM PST 24
Finished Jan 24 09:35:48 PM PST 24
Peak memory 218132 kb
Host smart-ab94c5a5-38a1-4671-96dc-c38f3487399b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654225768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3654225768
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.4023934156
Short name T472
Test name
Test status
Simulation time 542759195 ps
CPU time 8.14 seconds
Started Jan 24 08:41:34 PM PST 24
Finished Jan 24 08:41:42 PM PST 24
Peak memory 218108 kb
Host smart-6688fbf0-623b-43aa-8ff0-43cd7817b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023934156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.4023934156
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2349506745
Short name T653
Test name
Test status
Simulation time 25147976 ps
CPU time 2.16 seconds
Started Jan 24 08:57:56 PM PST 24
Finished Jan 24 08:58:02 PM PST 24
Peak memory 213672 kb
Host smart-20b93fca-658a-4f12-80c7-5a5ca3870f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349506745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2349506745
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1519493005
Short name T542
Test name
Test status
Simulation time 2410695022 ps
CPU time 23.76 seconds
Started Jan 24 08:41:25 PM PST 24
Finished Jan 24 08:41:50 PM PST 24
Peak memory 251188 kb
Host smart-9556218f-2f93-4bcd-9520-3e2928c1397b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519493005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1519493005
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3658633717
Short name T842
Test name
Test status
Simulation time 116559795 ps
CPU time 7.92 seconds
Started Jan 24 09:02:22 PM PST 24
Finished Jan 24 09:02:30 PM PST 24
Peak memory 251132 kb
Host smart-18da9550-9b03-4e2f-a672-39b86344b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658633717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3658633717
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2279434401
Short name T581
Test name
Test status
Simulation time 32166044 ps
CPU time 0.89 seconds
Started Jan 24 09:09:44 PM PST 24
Finished Jan 24 09:09:45 PM PST 24
Peak memory 209484 kb
Host smart-bd6b5f1e-3501-43ba-bf08-f5d51f65da53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279434401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2279434401
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3492953043
Short name T43
Test name
Test status
Simulation time 854549283 ps
CPU time 8.69 seconds
Started Jan 24 10:33:36 PM PST 24
Finished Jan 24 10:33:46 PM PST 24
Peak memory 218120 kb
Host smart-4bf2160a-f0f5-4b94-a393-d2d93c8494f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492953043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3492953043
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2446206643
Short name T350
Test name
Test status
Simulation time 2435231241 ps
CPU time 11.96 seconds
Started Jan 24 08:59:16 PM PST 24
Finished Jan 24 08:59:29 PM PST 24
Peak memory 209664 kb
Host smart-81814b34-73ae-4259-92d4-5480099074a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446206643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_a
ccess.2446206643
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2744249068
Short name T738
Test name
Test status
Simulation time 4538399875 ps
CPU time 55 seconds
Started Jan 24 09:53:11 PM PST 24
Finished Jan 24 09:54:07 PM PST 24
Peak memory 218296 kb
Host smart-c65ddb96-041e-49c1-8ff2-ff659a7aa041
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744249068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2744249068
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.4053448627
Short name T924
Test name
Test status
Simulation time 611878252 ps
CPU time 17.25 seconds
Started Jan 24 08:41:55 PM PST 24
Finished Jan 24 08:42:14 PM PST 24
Peak memory 218072 kb
Host smart-3bb2bf88-07f8-4893-92c5-1e95aad29c73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053448627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.4053448627
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1378392175
Short name T56
Test name
Test status
Simulation time 433624870 ps
CPU time 4.12 seconds
Started Jan 24 08:41:55 PM PST 24
Finished Jan 24 08:42:00 PM PST 24
Peak memory 212848 kb
Host smart-f2947f4d-418b-47d3-983d-d903f692d8f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378392175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1378392175
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3916033152
Short name T328
Test name
Test status
Simulation time 1304914605 ps
CPU time 37.4 seconds
Started Jan 24 08:41:55 PM PST 24
Finished Jan 24 08:42:33 PM PST 24
Peak memory 252192 kb
Host smart-d6f61816-20d7-421f-8c09-41e9ab38a254
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916033152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3916033152
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2084215553
Short name T960
Test name
Test status
Simulation time 832074389 ps
CPU time 18.75 seconds
Started Jan 24 09:15:28 PM PST 24
Finished Jan 24 09:15:48 PM PST 24
Peak memory 244780 kb
Host smart-8e8e93b2-b163-4439-a8ef-1401df0556bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084215553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2084215553
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3115966127
Short name T552
Test name
Test status
Simulation time 136661765 ps
CPU time 2.84 seconds
Started Jan 24 09:29:36 PM PST 24
Finished Jan 24 09:29:39 PM PST 24
Peak memory 218120 kb
Host smart-88aa34a9-dc0f-4486-9f03-28108c77e79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115966127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3115966127
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1770216418
Short name T623
Test name
Test status
Simulation time 1572041991 ps
CPU time 13.05 seconds
Started Jan 24 08:42:05 PM PST 24
Finished Jan 24 08:42:19 PM PST 24
Peak memory 219128 kb
Host smart-754ac17b-18d0-49cd-b58e-b8051848d69e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770216418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1770216418
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1181467298
Short name T888
Test name
Test status
Simulation time 466740361 ps
CPU time 11.73 seconds
Started Jan 24 08:42:09 PM PST 24
Finished Jan 24 08:42:24 PM PST 24
Peak memory 218116 kb
Host smart-82b341ad-5a5a-4c49-9270-f438c3b7679e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181467298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1181467298
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2184353755
Short name T692
Test name
Test status
Simulation time 5236235960 ps
CPU time 12.74 seconds
Started Jan 24 08:41:56 PM PST 24
Finished Jan 24 08:42:11 PM PST 24
Peak memory 218172 kb
Host smart-a5d4a1ea-0671-4bae-80b0-660953348db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184353755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2184353755
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3365949597
Short name T941
Test name
Test status
Simulation time 107852554 ps
CPU time 2.29 seconds
Started Jan 24 08:42:05 PM PST 24
Finished Jan 24 08:42:08 PM PST 24
Peak memory 213696 kb
Host smart-da4b6712-64c6-4387-b3f6-fe19f56d0104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365949597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3365949597
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.558215003
Short name T944
Test name
Test status
Simulation time 277027419 ps
CPU time 27.9 seconds
Started Jan 24 08:41:49 PM PST 24
Finished Jan 24 08:42:19 PM PST 24
Peak memory 251132 kb
Host smart-0ca878c8-121e-4853-b455-87e2bf89005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558215003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.558215003
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1165711564
Short name T435
Test name
Test status
Simulation time 169486867 ps
CPU time 7.26 seconds
Started Jan 24 08:41:51 PM PST 24
Finished Jan 24 08:42:02 PM PST 24
Peak memory 245828 kb
Host smart-fde85fd3-db03-470a-be54-bf6252ab6cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165711564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1165711564
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1029473217
Short name T628
Test name
Test status
Simulation time 14350262 ps
CPU time 0.87 seconds
Started Jan 24 08:41:48 PM PST 24
Finished Jan 24 08:41:49 PM PST 24
Peak memory 208116 kb
Host smart-5667fe47-e43a-455f-a474-c32b4d7f5a9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029473217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1029473217
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2130452107
Short name T751
Test name
Test status
Simulation time 501980519 ps
CPU time 15.63 seconds
Started Jan 24 08:55:29 PM PST 24
Finished Jan 24 08:55:46 PM PST 24
Peak memory 218120 kb
Host smart-d952564c-7928-445d-a00a-6d3d6ae8d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130452107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2130452107
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3665774987
Short name T585
Test name
Test status
Simulation time 426105972 ps
CPU time 3.56 seconds
Started Jan 24 08:42:20 PM PST 24
Finished Jan 24 08:42:25 PM PST 24
Peak memory 209560 kb
Host smart-9b316876-7192-4635-973c-0145c956ed1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665774987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.3665774987
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2584775274
Short name T611
Test name
Test status
Simulation time 1108002023 ps
CPU time 34.4 seconds
Started Jan 24 08:42:23 PM PST 24
Finished Jan 24 08:42:58 PM PST 24
Peak memory 218060 kb
Host smart-cb55c837-3cfe-469a-8190-26391d9c220c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584775274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2584775274
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4186984574
Short name T760
Test name
Test status
Simulation time 2544874773 ps
CPU time 16.64 seconds
Started Jan 24 09:02:09 PM PST 24
Finished Jan 24 09:02:28 PM PST 24
Peak memory 218132 kb
Host smart-b60630e7-bea2-4dad-82e6-a8ba9a68298a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186984574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4186984574
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1683246820
Short name T415
Test name
Test status
Simulation time 525916861 ps
CPU time 4.69 seconds
Started Jan 24 08:42:11 PM PST 24
Finished Jan 24 08:42:20 PM PST 24
Peak memory 213008 kb
Host smart-5791dd0b-69ba-4bc6-8b1c-52c4d58c2f16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683246820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1683246820
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.339773310
Short name T115
Test name
Test status
Simulation time 12037115321 ps
CPU time 85.69 seconds
Started Jan 24 08:42:24 PM PST 24
Finished Jan 24 08:43:51 PM PST 24
Peak memory 251036 kb
Host smart-59b73859-b380-4a1b-8036-69528c14c6f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339773310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.339773310
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2109705610
Short name T770
Test name
Test status
Simulation time 432936967 ps
CPU time 14.64 seconds
Started Jan 25 12:05:45 AM PST 24
Finished Jan 25 12:06:01 AM PST 24
Peak memory 251100 kb
Host smart-b6a76a9e-272f-44ab-8305-d95f2a206a4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109705610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2109705610
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1169109281
Short name T578
Test name
Test status
Simulation time 32955188 ps
CPU time 1.95 seconds
Started Jan 24 08:42:11 PM PST 24
Finished Jan 24 08:42:15 PM PST 24
Peak memory 218064 kb
Host smart-c467f989-a91c-450c-8411-bb2c030b98c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169109281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1169109281
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2303244551
Short name T576
Test name
Test status
Simulation time 982274575 ps
CPU time 11.21 seconds
Started Jan 24 08:42:22 PM PST 24
Finished Jan 24 08:42:34 PM PST 24
Peak memory 218124 kb
Host smart-0c1bee93-c15f-446c-a69b-049d5e1bb7c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303244551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2303244551
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2166954018
Short name T827
Test name
Test status
Simulation time 342040612 ps
CPU time 13.94 seconds
Started Jan 24 08:48:07 PM PST 24
Finished Jan 24 08:48:21 PM PST 24
Peak memory 218128 kb
Host smart-f5c1dda1-68b5-472a-b663-6672e4e8ddbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166954018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2166954018
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3064094530
Short name T757
Test name
Test status
Simulation time 1298193135 ps
CPU time 12.2 seconds
Started Jan 24 08:42:21 PM PST 24
Finished Jan 24 08:42:34 PM PST 24
Peak memory 218116 kb
Host smart-8e6507c7-bff6-4be4-988d-0d065c0f6d13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064094530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3064094530
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2691430035
Short name T113
Test name
Test status
Simulation time 1299568050 ps
CPU time 10.77 seconds
Started Jan 24 08:42:14 PM PST 24
Finished Jan 24 08:42:28 PM PST 24
Peak memory 218092 kb
Host smart-736a6c44-c72c-4758-ad23-1ffd4e30dcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691430035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2691430035
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3724566980
Short name T62
Test name
Test status
Simulation time 38498373 ps
CPU time 1.03 seconds
Started Jan 24 08:54:11 PM PST 24
Finished Jan 24 08:54:13 PM PST 24
Peak memory 211692 kb
Host smart-c87c916d-4439-4f38-bccd-837b0805cc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724566980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3724566980
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.358655668
Short name T852
Test name
Test status
Simulation time 282189831 ps
CPU time 19.01 seconds
Started Jan 24 08:54:50 PM PST 24
Finished Jan 24 08:55:15 PM PST 24
Peak memory 251044 kb
Host smart-a36e3dc5-755c-4b3e-adce-d1dca7ddc9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358655668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.358655668
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3919525736
Short name T861
Test name
Test status
Simulation time 151893865 ps
CPU time 8.78 seconds
Started Jan 24 08:42:12 PM PST 24
Finished Jan 24 08:42:25 PM PST 24
Peak memory 251124 kb
Host smart-36b05077-1227-466e-a554-ec963bba264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919525736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3919525736
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3711871660
Short name T895
Test name
Test status
Simulation time 2677306500 ps
CPU time 57.76 seconds
Started Jan 24 08:42:30 PM PST 24
Finished Jan 24 08:43:30 PM PST 24
Peak memory 251180 kb
Host smart-a95c2821-6341-4255-8a99-46020125626a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711871660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3711871660
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.65587839
Short name T349
Test name
Test status
Simulation time 39709528 ps
CPU time 1.03 seconds
Started Jan 24 08:42:15 PM PST 24
Finished Jan 24 08:42:18 PM PST 24
Peak memory 211232 kb
Host smart-23f5d2db-4916-48b4-9f17-bd82660b878c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65587839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_volatile_unlock_smoke.65587839
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1716652953
Short name T593
Test name
Test status
Simulation time 25683039 ps
CPU time 0.95 seconds
Started Jan 24 08:42:53 PM PST 24
Finished Jan 24 08:42:54 PM PST 24
Peak memory 209496 kb
Host smart-20f54e78-ce7a-4332-a490-6c449d5ba8d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716652953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1716652953
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3907596173
Short name T314
Test name
Test status
Simulation time 390860573 ps
CPU time 16.42 seconds
Started Jan 24 08:42:44 PM PST 24
Finished Jan 24 08:43:01 PM PST 24
Peak memory 218108 kb
Host smart-dd2ba77d-4bd4-4eef-b925-6ef8fb7ff7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907596173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3907596173
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.906818111
Short name T677
Test name
Test status
Simulation time 3060299318 ps
CPU time 6.05 seconds
Started Jan 24 08:42:51 PM PST 24
Finished Jan 24 08:42:58 PM PST 24
Peak memory 209564 kb
Host smart-62cd013b-7a4b-4a0e-95e3-2a49824313c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906818111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_ac
cess.906818111
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1355052212
Short name T478
Test name
Test status
Simulation time 7457944853 ps
CPU time 27.67 seconds
Started Jan 24 08:42:55 PM PST 24
Finished Jan 24 08:43:24 PM PST 24
Peak memory 218156 kb
Host smart-3348713d-6bef-438e-b242-bc21b915d507
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355052212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1355052212
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.237602568
Short name T774
Test name
Test status
Simulation time 8994315682 ps
CPU time 11.34 seconds
Started Jan 24 08:45:30 PM PST 24
Finished Jan 24 08:45:42 PM PST 24
Peak memory 218068 kb
Host smart-4792ed1f-ca00-42b5-ba4d-e2febf176ecf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237602568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.237602568
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1873789930
Short name T953
Test name
Test status
Simulation time 1917296888 ps
CPU time 9.6 seconds
Started Jan 24 08:42:47 PM PST 24
Finished Jan 24 08:42:57 PM PST 24
Peak memory 213460 kb
Host smart-de3c9d6b-4d31-465a-a62c-4457a1c49e3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873789930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1873789930
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1664914677
Short name T375
Test name
Test status
Simulation time 2812046140 ps
CPU time 38.12 seconds
Started Jan 24 08:42:44 PM PST 24
Finished Jan 24 08:43:24 PM PST 24
Peak memory 267528 kb
Host smart-d534c6b2-98fa-4025-8c3d-7c25a1a9dbdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664914677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1664914677
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1692988132
Short name T837
Test name
Test status
Simulation time 721214684 ps
CPU time 15.28 seconds
Started Jan 24 08:42:47 PM PST 24
Finished Jan 24 08:43:04 PM PST 24
Peak memory 250268 kb
Host smart-a6fc7a73-2bfc-45a0-b2db-63b5c2726cdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692988132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1692988132
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1185691629
Short name T182
Test name
Test status
Simulation time 32298771 ps
CPU time 2.03 seconds
Started Jan 24 08:42:42 PM PST 24
Finished Jan 24 08:42:45 PM PST 24
Peak memory 218148 kb
Host smart-60cba2b1-3bb8-407c-a1b7-8ac5bc5cd1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185691629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1185691629
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3989413712
Short name T865
Test name
Test status
Simulation time 348969406 ps
CPU time 14.21 seconds
Started Jan 24 08:42:50 PM PST 24
Finished Jan 24 08:43:05 PM PST 24
Peak memory 218092 kb
Host smart-da94b6ca-5be8-4377-a616-b21fc6296e41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989413712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3989413712
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3692934904
Short name T867
Test name
Test status
Simulation time 1708097028 ps
CPU time 12.03 seconds
Started Jan 24 08:42:51 PM PST 24
Finished Jan 24 08:43:04 PM PST 24
Peak memory 218100 kb
Host smart-cd995926-26d2-441c-89c4-aba92490921e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692934904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3692934904
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1163155197
Short name T923
Test name
Test status
Simulation time 3313501446 ps
CPU time 17.68 seconds
Started Jan 24 08:42:48 PM PST 24
Finished Jan 24 08:43:07 PM PST 24
Peak memory 218184 kb
Host smart-541d7346-211a-400b-bcb2-6749761bca2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163155197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1163155197
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2329453930
Short name T497
Test name
Test status
Simulation time 1546065744 ps
CPU time 14.28 seconds
Started Jan 24 08:42:45 PM PST 24
Finished Jan 24 08:43:00 PM PST 24
Peak memory 218100 kb
Host smart-31f9069f-ad23-4859-bd55-d67cd501c0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329453930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2329453930
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2916029626
Short name T740
Test name
Test status
Simulation time 117508524 ps
CPU time 1.79 seconds
Started Jan 24 08:42:30 PM PST 24
Finished Jan 24 08:42:33 PM PST 24
Peak memory 213224 kb
Host smart-cc4efa1f-dd2c-4e16-8295-1a7464caf855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916029626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2916029626
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1457120266
Short name T481
Test name
Test status
Simulation time 208526787 ps
CPU time 6.16 seconds
Started Jan 24 08:42:31 PM PST 24
Finished Jan 24 08:42:38 PM PST 24
Peak memory 246064 kb
Host smart-a8cb2ef6-47ee-406e-9327-f6d1b3395b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457120266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1457120266
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1959778741
Short name T461
Test name
Test status
Simulation time 59129939479 ps
CPU time 430.52 seconds
Started Jan 24 08:42:51 PM PST 24
Finished Jan 24 08:50:03 PM PST 24
Peak memory 283896 kb
Host smart-37aa0ea9-059d-4313-b201-293ed00288a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959778741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1959778741
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1945471298
Short name T812
Test name
Test status
Simulation time 45090272 ps
CPU time 0.95 seconds
Started Jan 24 08:42:30 PM PST 24
Finished Jan 24 08:42:33 PM PST 24
Peak memory 208172 kb
Host smart-2b6112a9-37b8-46ed-b263-2875c827a35d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945471298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1945471298
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2128874452
Short name T515
Test name
Test status
Simulation time 21390551 ps
CPU time 0.99 seconds
Started Jan 24 08:43:31 PM PST 24
Finished Jan 24 08:43:55 PM PST 24
Peak memory 209456 kb
Host smart-92795813-38ac-41e1-90fa-8f03d5682419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128874452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2128874452
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1489189835
Short name T318
Test name
Test status
Simulation time 217791587 ps
CPU time 11.13 seconds
Started Jan 24 08:43:10 PM PST 24
Finished Jan 24 08:43:43 PM PST 24
Peak memory 218064 kb
Host smart-2a512039-4bf7-472f-91dc-a2d8d4e6e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489189835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1489189835
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1289122776
Short name T401
Test name
Test status
Simulation time 3110868476 ps
CPU time 12.9 seconds
Started Jan 24 08:43:24 PM PST 24
Finished Jan 24 08:44:04 PM PST 24
Peak memory 209596 kb
Host smart-1e12519a-4402-488a-a954-c995e6d32c73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289122776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.1289122776
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4284959440
Short name T354
Test name
Test status
Simulation time 3846815962 ps
CPU time 29.4 seconds
Started Jan 24 08:43:17 PM PST 24
Finished Jan 24 08:44:16 PM PST 24
Peak memory 218140 kb
Host smart-7c229a8b-e92d-40ba-a012-2b58f9d3d652
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284959440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4284959440
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.309669815
Short name T3
Test name
Test status
Simulation time 8333426090 ps
CPU time 17.13 seconds
Started Jan 24 08:43:17 PM PST 24
Finished Jan 24 08:44:03 PM PST 24
Peak memory 218128 kb
Host smart-d12f411f-0b85-491b-96ab-59d89254432b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309669815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.309669815
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3881860339
Short name T817
Test name
Test status
Simulation time 928107841 ps
CPU time 7.08 seconds
Started Jan 24 08:43:08 PM PST 24
Finished Jan 24 08:43:34 PM PST 24
Peak memory 213444 kb
Host smart-03d8bffe-83dd-41b5-b817-8065fcaae2e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881860339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3881860339
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3749895671
Short name T804
Test name
Test status
Simulation time 18474562825 ps
CPU time 85.28 seconds
Started Jan 24 08:43:07 PM PST 24
Finished Jan 24 08:44:50 PM PST 24
Peak memory 283832 kb
Host smart-24d3728f-ee6f-4cd5-ac4a-d492404d3ded
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749895671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3749895671
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4000611533
Short name T768
Test name
Test status
Simulation time 1358821342 ps
CPU time 12.06 seconds
Started Jan 24 08:43:05 PM PST 24
Finished Jan 24 08:43:33 PM PST 24
Peak memory 251040 kb
Host smart-0d11be33-eac8-4428-854a-975313028b87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000611533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.4000611533
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2745254286
Short name T426
Test name
Test status
Simulation time 39689264 ps
CPU time 1.69 seconds
Started Jan 24 08:43:06 PM PST 24
Finished Jan 24 08:43:23 PM PST 24
Peak memory 218184 kb
Host smart-252cc412-a4e6-4dee-80c9-5df32fafc9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745254286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2745254286
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4092017711
Short name T30
Test name
Test status
Simulation time 2284063962 ps
CPU time 20.04 seconds
Started Jan 24 08:43:19 PM PST 24
Finished Jan 24 08:44:08 PM PST 24
Peak memory 219184 kb
Host smart-e70130fe-4554-4566-9c0c-8b786be316fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092017711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4092017711
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3893104771
Short name T943
Test name
Test status
Simulation time 539608042 ps
CPU time 18.39 seconds
Started Jan 24 08:43:19 PM PST 24
Finished Jan 24 08:44:07 PM PST 24
Peak memory 218104 kb
Host smart-6115aca0-d920-4acf-a75b-cb19d764b16d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893104771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3893104771
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1024815444
Short name T807
Test name
Test status
Simulation time 231353125 ps
CPU time 6.75 seconds
Started Jan 24 08:43:17 PM PST 24
Finished Jan 24 08:43:53 PM PST 24
Peak memory 218096 kb
Host smart-5c1fc7ee-cf18-4737-91ad-090b40228239
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024815444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1024815444
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3763765131
Short name T748
Test name
Test status
Simulation time 256180333 ps
CPU time 10.71 seconds
Started Jan 24 08:43:11 PM PST 24
Finished Jan 24 08:43:43 PM PST 24
Peak memory 218080 kb
Host smart-69e48260-50d9-430f-9b7e-00ef1ce01e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763765131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3763765131
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3471149184
Short name T695
Test name
Test status
Simulation time 30606266 ps
CPU time 2.04 seconds
Started Jan 24 08:43:09 PM PST 24
Finished Jan 24 08:43:33 PM PST 24
Peak memory 213508 kb
Host smart-85f311c2-0290-4f1d-bff6-843ffae9299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471149184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3471149184
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1204682115
Short name T446
Test name
Test status
Simulation time 728044055 ps
CPU time 19.73 seconds
Started Jan 24 08:43:10 PM PST 24
Finished Jan 24 08:43:51 PM PST 24
Peak memory 250972 kb
Host smart-71ea8a29-9ff2-4cf1-ada7-a2d0e99b6f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204682115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1204682115
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1376431419
Short name T603
Test name
Test status
Simulation time 400592612 ps
CPU time 6.98 seconds
Started Jan 24 08:43:10 PM PST 24
Finished Jan 24 08:43:38 PM PST 24
Peak memory 250500 kb
Host smart-d706dc6c-4702-46b0-8ea0-5e7338b4f848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376431419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1376431419
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2145262875
Short name T666
Test name
Test status
Simulation time 5054602696 ps
CPU time 34.02 seconds
Started Jan 24 08:43:20 PM PST 24
Finished Jan 24 08:44:23 PM PST 24
Peak memory 251148 kb
Host smart-d37946b5-7334-4949-9d83-78fa54638878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145262875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2145262875
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4195127016
Short name T470
Test name
Test status
Simulation time 19612317 ps
CPU time 0.75 seconds
Started Jan 24 08:43:07 PM PST 24
Finished Jan 24 08:43:27 PM PST 24
Peak memory 207960 kb
Host smart-81f0d31b-a376-4d68-a4d3-b186868acf17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195127016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4195127016
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3593805227
Short name T295
Test name
Test status
Simulation time 42098479 ps
CPU time 0.84 seconds
Started Jan 24 08:43:55 PM PST 24
Finished Jan 24 08:44:05 PM PST 24
Peak memory 209348 kb
Host smart-5996650e-b3d5-42c0-91ef-83371b885546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593805227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3593805227
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3209119127
Short name T863
Test name
Test status
Simulation time 448335584 ps
CPU time 13.97 seconds
Started Jan 24 08:43:29 PM PST 24
Finished Jan 24 08:44:07 PM PST 24
Peak memory 218100 kb
Host smart-26544867-413e-43e8-ba8a-d9bfb3a20d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209119127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3209119127
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.256319178
Short name T392
Test name
Test status
Simulation time 659423239 ps
CPU time 2.62 seconds
Started Jan 24 08:43:48 PM PST 24
Finished Jan 24 08:44:03 PM PST 24
Peak memory 209464 kb
Host smart-6a9e9d3d-8886-4dc1-9d03-48b42e318e74
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256319178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_ac
cess.256319178
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.607736253
Short name T781
Test name
Test status
Simulation time 3913584633 ps
CPU time 25.14 seconds
Started Jan 24 08:43:47 PM PST 24
Finished Jan 24 08:44:25 PM PST 24
Peak memory 218208 kb
Host smart-eea530e4-19e6-43a2-a82d-ad85bf8a403c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607736253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.607736253
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.58933697
Short name T294
Test name
Test status
Simulation time 195605446 ps
CPU time 3.91 seconds
Started Jan 24 08:43:53 PM PST 24
Finished Jan 24 08:44:07 PM PST 24
Peak memory 218060 kb
Host smart-277b0793-8fb3-4053-a1a0-9004e5bdcf99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58933697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_
prog_failure.58933697
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.632586537
Short name T535
Test name
Test status
Simulation time 93647477 ps
CPU time 2.19 seconds
Started Jan 24 08:43:39 PM PST 24
Finished Jan 24 08:43:59 PM PST 24
Peak memory 212548 kb
Host smart-e9614a8f-02fc-4575-b6cf-62d35c80a54e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632586537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
632586537
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4034027422
Short name T2
Test name
Test status
Simulation time 5558817776 ps
CPU time 92.31 seconds
Started Jan 24 08:43:46 PM PST 24
Finished Jan 24 08:45:32 PM PST 24
Peak memory 251056 kb
Host smart-3dbdb5b4-a64f-413f-9aea-4c8f92fdc4f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034027422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.4034027422
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2101667486
Short name T678
Test name
Test status
Simulation time 3337733044 ps
CPU time 18.63 seconds
Started Jan 24 08:43:48 PM PST 24
Finished Jan 24 08:44:19 PM PST 24
Peak memory 251132 kb
Host smart-c9cffa55-5bd6-4ca8-b038-f7339bef217c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101667486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2101667486
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3653467019
Short name T859
Test name
Test status
Simulation time 821500010 ps
CPU time 3.43 seconds
Started Jan 24 08:43:32 PM PST 24
Finished Jan 24 08:43:57 PM PST 24
Peak memory 218092 kb
Host smart-4ffd94bd-4aa6-4052-b5f7-90829299e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653467019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3653467019
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2864611247
Short name T844
Test name
Test status
Simulation time 1743134894 ps
CPU time 13.11 seconds
Started Jan 24 08:43:47 PM PST 24
Finished Jan 24 08:44:13 PM PST 24
Peak memory 218088 kb
Host smart-9d9c21d8-07cc-459a-a47e-2bf6b718302a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864611247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2864611247
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3284221981
Short name T886
Test name
Test status
Simulation time 490861793 ps
CPU time 12.69 seconds
Started Jan 24 08:43:45 PM PST 24
Finished Jan 24 08:44:12 PM PST 24
Peak memory 218124 kb
Host smart-e89f1e66-4804-4009-9573-f3d413474ca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284221981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3284221981
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1725264392
Short name T48
Test name
Test status
Simulation time 201698224 ps
CPU time 6.96 seconds
Started Jan 24 08:43:46 PM PST 24
Finished Jan 24 08:44:07 PM PST 24
Peak memory 218092 kb
Host smart-2f6ad7d5-d181-4486-b16e-eda71e03d8ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725264392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1725264392
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2062449749
Short name T793
Test name
Test status
Simulation time 1791618581 ps
CPU time 6.52 seconds
Started Jan 24 08:43:40 PM PST 24
Finished Jan 24 08:44:04 PM PST 24
Peak memory 218088 kb
Host smart-b74ebc05-8755-45c6-8119-a5ad1bc01ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062449749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2062449749
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1016705528
Short name T73
Test name
Test status
Simulation time 1365545093 ps
CPU time 10.5 seconds
Started Jan 24 08:43:31 PM PST 24
Finished Jan 24 08:44:04 PM PST 24
Peak memory 214248 kb
Host smart-3efd7b1c-d192-491e-b2c3-8a639a9a9116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016705528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1016705528
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1727007766
Short name T548
Test name
Test status
Simulation time 283437573 ps
CPU time 24.84 seconds
Started Jan 24 08:43:28 PM PST 24
Finished Jan 24 08:44:18 PM PST 24
Peak memory 251020 kb
Host smart-f4c18d88-fae8-455e-85aa-827f308ad6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727007766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1727007766
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2581042381
Short name T645
Test name
Test status
Simulation time 74258878 ps
CPU time 7.28 seconds
Started Jan 24 08:43:28 PM PST 24
Finished Jan 24 08:44:00 PM PST 24
Peak memory 251132 kb
Host smart-9d9980be-8be1-4aab-b000-fedf257473ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581042381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2581042381
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.206693604
Short name T635
Test name
Test status
Simulation time 43997304133 ps
CPU time 198.74 seconds
Started Jan 24 08:43:56 PM PST 24
Finished Jan 24 08:47:23 PM PST 24
Peak memory 248672 kb
Host smart-35c48b03-87e6-4d3b-b84e-8d8472701c37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206693604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.206693604
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1282789125
Short name T36
Test name
Test status
Simulation time 30449383 ps
CPU time 0.75 seconds
Started Jan 24 08:43:30 PM PST 24
Finished Jan 24 08:43:54 PM PST 24
Peak memory 207740 kb
Host smart-39561bd3-8a70-44b3-801c-4cf5417b3812
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282789125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1282789125
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1971801717
Short name T939
Test name
Test status
Simulation time 66378479 ps
CPU time 0.97 seconds
Started Jan 24 08:44:37 PM PST 24
Finished Jan 24 08:44:39 PM PST 24
Peak memory 209456 kb
Host smart-d0240683-1307-47ec-9204-6b34f76683c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971801717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1971801717
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1502150661
Short name T353
Test name
Test status
Simulation time 1440080543 ps
CPU time 14.24 seconds
Started Jan 24 08:44:04 PM PST 24
Finished Jan 24 08:44:23 PM PST 24
Peak memory 218096 kb
Host smart-5eef373e-1d4f-4262-9208-ef0d9a8f10a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502150661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1502150661
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1100792276
Short name T519
Test name
Test status
Simulation time 301583618 ps
CPU time 1.68 seconds
Started Jan 24 08:44:25 PM PST 24
Finished Jan 24 08:44:28 PM PST 24
Peak memory 209516 kb
Host smart-edc4c250-bcdf-46a8-9d02-d4929c27222c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100792276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.1100792276
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1947390362
Short name T344
Test name
Test status
Simulation time 1677166534 ps
CPU time 30.04 seconds
Started Jan 24 08:44:18 PM PST 24
Finished Jan 24 08:44:50 PM PST 24
Peak memory 218060 kb
Host smart-57dc3168-c6b7-4d8d-8c94-bb202598fcf4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947390362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1947390362
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.537015989
Short name T331
Test name
Test status
Simulation time 475978835 ps
CPU time 7.77 seconds
Started Jan 24 08:44:19 PM PST 24
Finished Jan 24 08:44:29 PM PST 24
Peak memory 218040 kb
Host smart-436460dd-5583-40e3-9579-67dd58849eb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537015989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.537015989
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3547339564
Short name T52
Test name
Test status
Simulation time 369466422 ps
CPU time 2.45 seconds
Started Jan 24 08:44:10 PM PST 24
Finished Jan 24 08:44:16 PM PST 24
Peak memory 212572 kb
Host smart-39ff242b-4e95-4f60-bf44-9ad5c6906f42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547339564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3547339564
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1500341784
Short name T667
Test name
Test status
Simulation time 3065765839 ps
CPU time 62.55 seconds
Started Jan 24 08:44:09 PM PST 24
Finished Jan 24 08:45:15 PM PST 24
Peak memory 283812 kb
Host smart-753cf43b-eafb-4062-81bc-4947e62e344d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500341784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1500341784
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.583394109
Short name T452
Test name
Test status
Simulation time 4570687812 ps
CPU time 16.52 seconds
Started Jan 24 09:20:08 PM PST 24
Finished Jan 24 09:20:25 PM PST 24
Peak memory 226548 kb
Host smart-66d65e8b-1314-48b2-8530-0c8989ce8586
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583394109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.583394109
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.389425187
Short name T716
Test name
Test status
Simulation time 101007731 ps
CPU time 3.16 seconds
Started Jan 24 09:08:20 PM PST 24
Finished Jan 24 09:08:25 PM PST 24
Peak memory 218116 kb
Host smart-85e21282-186a-4127-86d1-824a401b1de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389425187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.389425187
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2586066767
Short name T759
Test name
Test status
Simulation time 1317663897 ps
CPU time 27.12 seconds
Started Jan 24 08:44:29 PM PST 24
Finished Jan 24 08:44:57 PM PST 24
Peak memory 218104 kb
Host smart-1ab51877-88b9-42ed-8525-9fada9d37aa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586066767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2586066767
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2102150914
Short name T371
Test name
Test status
Simulation time 1684421088 ps
CPU time 14.31 seconds
Started Jan 25 01:31:33 AM PST 24
Finished Jan 25 01:31:48 AM PST 24
Peak memory 218116 kb
Host smart-7297b64e-207f-43f8-8cab-74bd563d7eaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102150914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2102150914
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3983993825
Short name T651
Test name
Test status
Simulation time 1732053959 ps
CPU time 9.69 seconds
Started Jan 24 08:44:29 PM PST 24
Finished Jan 24 08:44:40 PM PST 24
Peak memory 218112 kb
Host smart-17b1399a-d3ab-4260-b15c-9af3d6ad3f88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983993825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3983993825
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2998019808
Short name T372
Test name
Test status
Simulation time 944243153 ps
CPU time 6.49 seconds
Started Jan 24 08:44:09 PM PST 24
Finished Jan 24 08:44:19 PM PST 24
Peak memory 218112 kb
Host smart-ffd97cca-c60e-46a6-ad22-518e843d45a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998019808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2998019808
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2706241801
Short name T679
Test name
Test status
Simulation time 20625515 ps
CPU time 1.2 seconds
Started Jan 24 08:43:59 PM PST 24
Finished Jan 24 08:44:07 PM PST 24
Peak memory 212956 kb
Host smart-eb551aaa-5bd4-4030-99cd-dda7722c7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706241801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2706241801
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2534399285
Short name T722
Test name
Test status
Simulation time 2104517858 ps
CPU time 20.06 seconds
Started Jan 24 09:37:58 PM PST 24
Finished Jan 24 09:38:19 PM PST 24
Peak memory 251048 kb
Host smart-ac9cfe42-c2e7-4f33-829c-323186442e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534399285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2534399285
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2021970089
Short name T402
Test name
Test status
Simulation time 213837556 ps
CPU time 6.65 seconds
Started Jan 24 08:44:05 PM PST 24
Finished Jan 24 08:44:16 PM PST 24
Peak memory 250080 kb
Host smart-76a11455-7c45-4351-a982-0466f075fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021970089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2021970089
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3332290465
Short name T412
Test name
Test status
Simulation time 6737591835 ps
CPU time 127.26 seconds
Started Jan 24 08:44:25 PM PST 24
Finished Jan 24 08:46:33 PM PST 24
Peak memory 251112 kb
Host smart-17a8a760-6a0b-4be7-9348-6f460dc3ab65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332290465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3332290465
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3463069230
Short name T932
Test name
Test status
Simulation time 42577749 ps
CPU time 0.75 seconds
Started Jan 24 08:43:57 PM PST 24
Finished Jan 24 08:44:06 PM PST 24
Peak memory 207956 kb
Host smart-b61c0dbd-8646-4e0e-b3dd-b6b4f4439d0c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463069230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3463069230
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2562328148
Short name T57
Test name
Test status
Simulation time 17880538 ps
CPU time 0.92 seconds
Started Jan 24 08:50:54 PM PST 24
Finished Jan 24 08:50:56 PM PST 24
Peak memory 209512 kb
Host smart-4202db52-359c-4d1c-9574-045537b25fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562328148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2562328148
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2326552081
Short name T787
Test name
Test status
Simulation time 23269820 ps
CPU time 1 seconds
Started Jan 24 08:34:18 PM PST 24
Finished Jan 24 08:34:20 PM PST 24
Peak memory 209392 kb
Host smart-a246d2d0-cd46-4f9a-ad9f-1819aaca7a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326552081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2326552081
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3621519609
Short name T329
Test name
Test status
Simulation time 264263449 ps
CPU time 10.73 seconds
Started Jan 24 08:34:14 PM PST 24
Finished Jan 24 08:34:26 PM PST 24
Peak memory 226288 kb
Host smart-ec159db4-3d84-4137-8bb5-37999a38fca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621519609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3621519609
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2756036266
Short name T968
Test name
Test status
Simulation time 281962592 ps
CPU time 4.42 seconds
Started Jan 24 08:58:50 PM PST 24
Finished Jan 24 08:58:58 PM PST 24
Peak memory 209536 kb
Host smart-cc44a156-0529-49f7-b180-46eb2dcfe005
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756036266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ac
cess.2756036266
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.109789051
Short name T769
Test name
Test status
Simulation time 11912830088 ps
CPU time 60.05 seconds
Started Jan 24 09:23:22 PM PST 24
Finished Jan 24 09:24:23 PM PST 24
Peak memory 221240 kb
Host smart-e1ab13b0-c7d4-489d-bd29-ab4437c3673a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109789051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.109789051
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.270105671
Short name T5
Test name
Test status
Simulation time 370174639 ps
CPU time 5.43 seconds
Started Jan 24 08:34:30 PM PST 24
Finished Jan 24 08:34:37 PM PST 24
Peak memory 217888 kb
Host smart-735cb3a0-94b5-4bcc-86cb-b72fcc31829f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270105671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_p
riority.270105671
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1036802667
Short name T771
Test name
Test status
Simulation time 779726318 ps
CPU time 8.92 seconds
Started Jan 24 11:18:51 PM PST 24
Finished Jan 24 11:19:03 PM PST 24
Peak memory 218068 kb
Host smart-d61965fb-4f27-4393-932a-c257ed4ac8bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036802667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1036802667
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3196302779
Short name T632
Test name
Test status
Simulation time 2528064136 ps
CPU time 33.72 seconds
Started Jan 24 08:34:41 PM PST 24
Finished Jan 24 08:35:15 PM PST 24
Peak memory 213248 kb
Host smart-72df0a13-9968-41dc-9939-4530d3522495
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196302779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3196302779
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.644601618
Short name T72
Test name
Test status
Simulation time 449683606 ps
CPU time 4.37 seconds
Started Jan 25 12:00:29 AM PST 24
Finished Jan 25 12:00:35 AM PST 24
Peak memory 213056 kb
Host smart-dece94ed-7a4c-4e65-b51c-10acdbc756b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644601618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.644601618
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3071046439
Short name T714
Test name
Test status
Simulation time 2268023970 ps
CPU time 49.53 seconds
Started Jan 24 09:39:26 PM PST 24
Finished Jan 24 09:40:16 PM PST 24
Peak memory 267444 kb
Host smart-4da8d90d-726e-463b-9040-dbebc1c2de83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071046439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3071046439
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3709534512
Short name T297
Test name
Test status
Simulation time 437606999 ps
CPU time 16.74 seconds
Started Jan 24 08:34:22 PM PST 24
Finished Jan 24 08:34:44 PM PST 24
Peak memory 250568 kb
Host smart-0b8f96cf-2d88-4107-863b-813232966ba9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709534512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3709534512
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1737194268
Short name T765
Test name
Test status
Simulation time 63410814 ps
CPU time 2.73 seconds
Started Jan 24 11:39:45 PM PST 24
Finished Jan 24 11:39:49 PM PST 24
Peak memory 218108 kb
Host smart-d123c091-701c-4500-af33-7c0345e92912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737194268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1737194268
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3346853603
Short name T682
Test name
Test status
Simulation time 560022958 ps
CPU time 15.36 seconds
Started Jan 24 09:30:30 PM PST 24
Finished Jan 24 09:30:47 PM PST 24
Peak memory 217840 kb
Host smart-79252f1b-9881-4502-b580-d981dc122908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346853603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3346853603
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1560771394
Short name T59
Test name
Test status
Simulation time 477881798 ps
CPU time 35.76 seconds
Started Jan 24 08:34:47 PM PST 24
Finished Jan 24 08:35:24 PM PST 24
Peak memory 281500 kb
Host smart-11a8e5b1-6f9a-458f-88fc-702a74726c8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560771394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1560771394
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1187488986
Short name T976
Test name
Test status
Simulation time 1225058830 ps
CPU time 14.94 seconds
Started Jan 24 08:34:39 PM PST 24
Finished Jan 24 08:34:55 PM PST 24
Peak memory 218184 kb
Host smart-939f062b-2a1c-46c0-aac7-f0cb0356eae5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187488986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1187488986
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1891951587
Short name T493
Test name
Test status
Simulation time 1121217392 ps
CPU time 8.51 seconds
Started Jan 24 08:34:38 PM PST 24
Finished Jan 24 08:34:47 PM PST 24
Peak memory 218096 kb
Host smart-fd85b515-ba82-4116-bd83-f43f95640c84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891951587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1891951587
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1903531398
Short name T347
Test name
Test status
Simulation time 311403557 ps
CPU time 11.61 seconds
Started Jan 24 08:34:41 PM PST 24
Finished Jan 24 08:34:53 PM PST 24
Peak memory 218064 kb
Host smart-1fd37ca8-e7f6-40a9-8dff-5dc10d130b3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903531398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
903531398
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.809860517
Short name T549
Test name
Test status
Simulation time 1415950032 ps
CPU time 10.77 seconds
Started Jan 24 08:54:55 PM PST 24
Finished Jan 24 08:55:09 PM PST 24
Peak memory 218228 kb
Host smart-9a5ebfee-8563-4c5e-bd63-ceabf7aed727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809860517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.809860517
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2894761914
Short name T18
Test name
Test status
Simulation time 58408468 ps
CPU time 2.5 seconds
Started Jan 24 08:34:04 PM PST 24
Finished Jan 24 08:34:07 PM PST 24
Peak memory 213960 kb
Host smart-adb3efc2-d916-4407-a4c5-b9a11a526aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894761914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2894761914
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.421554576
Short name T477
Test name
Test status
Simulation time 259574224 ps
CPU time 22.02 seconds
Started Jan 24 10:32:21 PM PST 24
Finished Jan 24 10:32:44 PM PST 24
Peak memory 251056 kb
Host smart-d93fb4ca-305d-433f-85a8-59d86ccb4638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421554576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.421554576
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2696842835
Short name T600
Test name
Test status
Simulation time 311232550 ps
CPU time 7.27 seconds
Started Jan 24 08:34:16 PM PST 24
Finished Jan 24 08:34:25 PM PST 24
Peak memory 246552 kb
Host smart-4eabbcb4-026a-40eb-828f-43c1a2371ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696842835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2696842835
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2710597996
Short name T887
Test name
Test status
Simulation time 22548668924 ps
CPU time 131.95 seconds
Started Jan 24 08:34:47 PM PST 24
Finished Jan 24 08:36:59 PM PST 24
Peak memory 283888 kb
Host smart-9a7700ab-ba28-4e9b-9c11-06fa9d4f0606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710597996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2710597996
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1958018454
Short name T473
Test name
Test status
Simulation time 13406438 ps
CPU time 0.86 seconds
Started Jan 24 08:34:04 PM PST 24
Finished Jan 24 08:34:05 PM PST 24
Peak memory 208116 kb
Host smart-74484bf5-a0fb-4fcb-985c-5e254f4b7133
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958018454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1958018454
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1933679695
Short name T662
Test name
Test status
Simulation time 36482525 ps
CPU time 1.01 seconds
Started Jan 24 08:45:06 PM PST 24
Finished Jan 24 08:45:09 PM PST 24
Peak memory 208092 kb
Host smart-97dbd77b-46c6-47c1-9a0c-a11384f9fd9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933679695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1933679695
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1930984591
Short name T656
Test name
Test status
Simulation time 593268097 ps
CPU time 17.4 seconds
Started Jan 24 11:31:05 PM PST 24
Finished Jan 24 11:31:25 PM PST 24
Peak memory 218116 kb
Host smart-2118b6ba-4c30-4c2f-8da1-0ea4913737ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930984591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1930984591
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3701503460
Short name T791
Test name
Test status
Simulation time 694221720 ps
CPU time 2.96 seconds
Started Jan 24 09:04:14 PM PST 24
Finished Jan 24 09:04:26 PM PST 24
Peak memory 209556 kb
Host smart-4a42180b-85a4-48e8-b74d-94b25de19fb4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701503460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.3701503460
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2776006641
Short name T428
Test name
Test status
Simulation time 152281907 ps
CPU time 2.41 seconds
Started Jan 24 08:44:43 PM PST 24
Finished Jan 24 08:44:47 PM PST 24
Peak memory 218148 kb
Host smart-5c9089d2-f98b-49a2-a89b-4da33b651a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776006641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2776006641
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1017270651
Short name T406
Test name
Test status
Simulation time 621823504 ps
CPU time 12.89 seconds
Started Jan 24 08:45:01 PM PST 24
Finished Jan 24 08:45:17 PM PST 24
Peak memory 219116 kb
Host smart-65038f75-1e07-40e2-9b25-8c708cc4138b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017270651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1017270651
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.4282825556
Short name T388
Test name
Test status
Simulation time 2412365485 ps
CPU time 14.77 seconds
Started Jan 24 08:44:56 PM PST 24
Finished Jan 24 08:45:13 PM PST 24
Peak memory 218164 kb
Host smart-ee3c55dc-688e-4be7-b54f-3552b9bd565a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282825556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.4282825556
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3917475524
Short name T620
Test name
Test status
Simulation time 2183320109 ps
CPU time 10.34 seconds
Started Jan 24 08:44:55 PM PST 24
Finished Jan 24 08:45:07 PM PST 24
Peak memory 218164 kb
Host smart-864e141f-ce72-41a4-802e-1bb00d72836a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917475524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3917475524
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.333509913
Short name T810
Test name
Test status
Simulation time 459525854 ps
CPU time 15.81 seconds
Started Jan 24 08:44:43 PM PST 24
Finished Jan 24 08:45:00 PM PST 24
Peak memory 218092 kb
Host smart-35a4f41c-2ff6-407e-9170-4fbbe98f6e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333509913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.333509913
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1256560467
Short name T618
Test name
Test status
Simulation time 204807588 ps
CPU time 2.13 seconds
Started Jan 24 09:54:07 PM PST 24
Finished Jan 24 09:54:10 PM PST 24
Peak memory 213560 kb
Host smart-134b7a2a-8818-468a-a331-452cbf0d2a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256560467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1256560467
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1711265000
Short name T846
Test name
Test status
Simulation time 1607914646 ps
CPU time 23.73 seconds
Started Jan 24 08:44:44 PM PST 24
Finished Jan 24 08:45:09 PM PST 24
Peak memory 251028 kb
Host smart-7fc65118-05ff-44a0-8531-fe3e9c159fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711265000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1711265000
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3084982245
Short name T961
Test name
Test status
Simulation time 202898895 ps
CPU time 5.83 seconds
Started Jan 24 08:44:43 PM PST 24
Finished Jan 24 08:44:50 PM PST 24
Peak memory 250844 kb
Host smart-332f5b44-4a04-4b95-91b9-dc53bbb72a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084982245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3084982245
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3895720898
Short name T829
Test name
Test status
Simulation time 54896625315 ps
CPU time 264.38 seconds
Started Jan 24 08:44:56 PM PST 24
Finished Jan 24 08:49:23 PM PST 24
Peak memory 277780 kb
Host smart-074159b2-4b73-4c0e-a2e5-3c628a62d4f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895720898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3895720898
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1053975610
Short name T908
Test name
Test status
Simulation time 21663437013 ps
CPU time 495.46 seconds
Started Jan 24 08:44:54 PM PST 24
Finished Jan 24 08:53:11 PM PST 24
Peak memory 332828 kb
Host smart-ade9bc03-2515-45dd-9a1d-7b502134e627
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1053975610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1053975610
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4260662807
Short name T456
Test name
Test status
Simulation time 14698904 ps
CPU time 1.17 seconds
Started Jan 24 09:02:14 PM PST 24
Finished Jan 24 09:02:16 PM PST 24
Peak memory 211228 kb
Host smart-1ee3ca4a-c61a-4b22-8cea-fd825339762b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260662807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.4260662807
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.475457104
Short name T832
Test name
Test status
Simulation time 45215364 ps
CPU time 0.98 seconds
Started Jan 24 08:44:59 PM PST 24
Finished Jan 24 08:45:03 PM PST 24
Peak memory 209496 kb
Host smart-8c484853-537a-4773-967f-6c1229a120ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475457104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.475457104
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3484328306
Short name T808
Test name
Test status
Simulation time 562529423 ps
CPU time 14.88 seconds
Started Jan 24 08:44:59 PM PST 24
Finished Jan 24 08:45:17 PM PST 24
Peak memory 218104 kb
Host smart-b8ee600c-12e5-46d6-81f8-6a736783b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484328306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3484328306
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.572804855
Short name T850
Test name
Test status
Simulation time 400110928 ps
CPU time 1.97 seconds
Started Jan 24 08:44:52 PM PST 24
Finished Jan 24 08:44:55 PM PST 24
Peak memory 209492 kb
Host smart-c691c27a-461a-4377-94de-cb835519456e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572804855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_ac
cess.572804855
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3132997336
Short name T468
Test name
Test status
Simulation time 21418718 ps
CPU time 1.64 seconds
Started Jan 24 08:44:59 PM PST 24
Finished Jan 24 08:45:03 PM PST 24
Peak memory 218128 kb
Host smart-b775ead3-6721-488d-9fe3-d098a042478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132997336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3132997336
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.4120545850
Short name T106
Test name
Test status
Simulation time 633311737 ps
CPU time 16.56 seconds
Started Jan 24 08:45:00 PM PST 24
Finished Jan 24 08:45:19 PM PST 24
Peak memory 218092 kb
Host smart-d8901fe1-b4df-4e43-b1a6-453b1eaef643
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120545850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.4120545850
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2779549309
Short name T587
Test name
Test status
Simulation time 5070866838 ps
CPU time 13.68 seconds
Started Jan 24 08:45:03 PM PST 24
Finished Jan 24 08:45:20 PM PST 24
Peak memory 218172 kb
Host smart-8526043b-3362-470d-b3ea-ec6740ac6ee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779549309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2779549309
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2304666532
Short name T605
Test name
Test status
Simulation time 304512924 ps
CPU time 12.58 seconds
Started Jan 24 08:44:55 PM PST 24
Finished Jan 24 08:45:10 PM PST 24
Peak memory 218172 kb
Host smart-4f2e7b6f-9110-4775-ada5-c6c007c802bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304666532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2304666532
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4075397368
Short name T845
Test name
Test status
Simulation time 519526431 ps
CPU time 2.69 seconds
Started Jan 24 08:44:59 PM PST 24
Finished Jan 24 08:45:05 PM PST 24
Peak memory 213812 kb
Host smart-84a9a700-2610-4f79-a2b0-9a4291d150e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075397368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4075397368
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.657988535
Short name T450
Test name
Test status
Simulation time 384486799 ps
CPU time 29.06 seconds
Started Jan 24 10:03:54 PM PST 24
Finished Jan 24 10:04:32 PM PST 24
Peak memory 250676 kb
Host smart-e5157c8a-a45a-4d3a-9787-2d5e6674bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657988535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.657988535
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2454434296
Short name T764
Test name
Test status
Simulation time 281615460 ps
CPU time 8.34 seconds
Started Jan 24 08:44:54 PM PST 24
Finished Jan 24 08:45:04 PM PST 24
Peak memory 251080 kb
Host smart-5c1fece1-94f6-45cc-b80b-020502dc9968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454434296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2454434296
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1693855571
Short name T707
Test name
Test status
Simulation time 14831592794 ps
CPU time 231.3 seconds
Started Jan 24 08:45:04 PM PST 24
Finished Jan 24 08:48:58 PM PST 24
Peak memory 219548 kb
Host smart-4ed14b96-1074-4959-9ded-0cbc055bab90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693855571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1693855571
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.991656801
Short name T13
Test name
Test status
Simulation time 18146710 ps
CPU time 0.97 seconds
Started Jan 24 08:44:59 PM PST 24
Finished Jan 24 08:45:03 PM PST 24
Peak memory 211220 kb
Host smart-5bf9ac39-f867-495e-8838-0e2b653bd4b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991656801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.991656801
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.30949961
Short name T775
Test name
Test status
Simulation time 22610096 ps
CPU time 1.04 seconds
Started Jan 24 08:58:14 PM PST 24
Finished Jan 24 08:58:17 PM PST 24
Peak memory 208160 kb
Host smart-a44e3f57-9da9-421b-988b-904d836f7e5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30949961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.30949961
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1389947838
Short name T729
Test name
Test status
Simulation time 574038519 ps
CPU time 13.34 seconds
Started Jan 24 08:45:03 PM PST 24
Finished Jan 24 08:45:20 PM PST 24
Peak memory 218108 kb
Host smart-c2f4331c-28ff-432d-94f1-238e3eb8b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389947838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1389947838
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.4276317205
Short name T501
Test name
Test status
Simulation time 310259260 ps
CPU time 5.51 seconds
Started Jan 24 08:45:10 PM PST 24
Finished Jan 24 08:45:17 PM PST 24
Peak memory 209472 kb
Host smart-fde6360a-080b-4b7e-9050-794238e6c92e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276317205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.4276317205
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3490118660
Short name T860
Test name
Test status
Simulation time 117016086 ps
CPU time 1.94 seconds
Started Jan 24 08:45:08 PM PST 24
Finished Jan 24 08:45:11 PM PST 24
Peak memory 218104 kb
Host smart-0796291d-2b8f-4340-a402-5deda5ba1c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490118660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3490118660
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2551339084
Short name T625
Test name
Test status
Simulation time 1805653623 ps
CPU time 17.2 seconds
Started Jan 24 08:45:04 PM PST 24
Finished Jan 24 08:45:24 PM PST 24
Peak memory 218096 kb
Host smart-bd7c5a5f-a903-4be1-86e4-63c522e475f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551339084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2551339084
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2143982923
Short name T536
Test name
Test status
Simulation time 362478557 ps
CPU time 10.65 seconds
Started Jan 24 08:45:10 PM PST 24
Finished Jan 24 08:45:22 PM PST 24
Peak memory 218060 kb
Host smart-d23d2ea2-fb77-405a-9278-c8032d924129
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143982923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2143982923
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3744537270
Short name T933
Test name
Test status
Simulation time 258257639 ps
CPU time 6.79 seconds
Started Jan 24 08:45:05 PM PST 24
Finished Jan 24 08:45:14 PM PST 24
Peak memory 218096 kb
Host smart-ee3d45ff-1461-4e41-b496-f38db3de7078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744537270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3744537270
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.169540226
Short name T17
Test name
Test status
Simulation time 219747425 ps
CPU time 8.74 seconds
Started Jan 24 08:45:05 PM PST 24
Finished Jan 24 08:45:16 PM PST 24
Peak memory 218128 kb
Host smart-3047dd56-5e8e-42fa-8712-b4b262d23207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169540226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.169540226
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2946642716
Short name T648
Test name
Test status
Simulation time 21488197 ps
CPU time 1.34 seconds
Started Jan 24 08:44:56 PM PST 24
Finished Jan 24 08:45:00 PM PST 24
Peak memory 212960 kb
Host smart-c6aa7a6e-c509-4c76-8510-6e125ead5a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946642716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2946642716
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.156695198
Short name T709
Test name
Test status
Simulation time 187221405 ps
CPU time 24.3 seconds
Started Jan 24 08:44:54 PM PST 24
Finished Jan 24 08:45:19 PM PST 24
Peak memory 251052 kb
Host smart-d390755e-8430-4e3b-8326-558c61300431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156695198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.156695198
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.806923777
Short name T462
Test name
Test status
Simulation time 199276674 ps
CPU time 7.86 seconds
Started Jan 24 09:47:16 PM PST 24
Finished Jan 24 09:47:25 PM PST 24
Peak memory 251052 kb
Host smart-252c7340-fe33-4d2d-8ded-3a955e719c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806923777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.806923777
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1545867328
Short name T486
Test name
Test status
Simulation time 9198147482 ps
CPU time 260.17 seconds
Started Jan 24 08:45:04 PM PST 24
Finished Jan 24 08:49:27 PM PST 24
Peak memory 251172 kb
Host smart-5d2eb454-f018-42dd-9493-4904d474b338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545867328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1545867328
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3234821742
Short name T826
Test name
Test status
Simulation time 28527240 ps
CPU time 0.72 seconds
Started Jan 24 08:44:55 PM PST 24
Finished Jan 24 08:44:57 PM PST 24
Peak memory 207712 kb
Host smart-6df9ea25-8ff8-4b74-9cfa-3afc7e58f9f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234821742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3234821742
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.4005161374
Short name T892
Test name
Test status
Simulation time 28823171 ps
CPU time 0.98 seconds
Started Jan 24 08:45:42 PM PST 24
Finished Jan 24 08:45:45 PM PST 24
Peak memory 209476 kb
Host smart-971cb169-3093-438a-a320-ebda2cbf9e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005161374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4005161374
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2727212397
Short name T868
Test name
Test status
Simulation time 1005233838 ps
CPU time 11.04 seconds
Started Jan 24 09:51:23 PM PST 24
Finished Jan 24 09:51:35 PM PST 24
Peak memory 218112 kb
Host smart-9428d0a2-d875-4b10-a0f4-897266f5cef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727212397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2727212397
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2792278947
Short name T432
Test name
Test status
Simulation time 513272694 ps
CPU time 12.49 seconds
Started Jan 24 08:45:22 PM PST 24
Finished Jan 24 08:45:36 PM PST 24
Peak memory 209508 kb
Host smart-75196516-f6d6-40bf-8009-f8d2f5f8f5f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792278947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.2792278947
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3433792367
Short name T494
Test name
Test status
Simulation time 73751092 ps
CPU time 3.22 seconds
Started Jan 24 08:45:16 PM PST 24
Finished Jan 24 08:45:21 PM PST 24
Peak memory 218108 kb
Host smart-56936e47-855a-48da-9d4e-fe9afb0ce046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433792367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3433792367
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2629630467
Short name T872
Test name
Test status
Simulation time 4571970132 ps
CPU time 25.11 seconds
Started Jan 24 09:14:00 PM PST 24
Finished Jan 24 09:14:26 PM PST 24
Peak memory 220260 kb
Host smart-e753cbd0-01c5-4446-bd2b-a1343af52795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629630467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2629630467
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2207443818
Short name T296
Test name
Test status
Simulation time 3203260061 ps
CPU time 12 seconds
Started Jan 24 08:45:31 PM PST 24
Finished Jan 24 08:45:44 PM PST 24
Peak memory 218160 kb
Host smart-ecfb69b0-512e-4927-a9f8-08984a4f677a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207443818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2207443818
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3660311811
Short name T624
Test name
Test status
Simulation time 478790075 ps
CPU time 13.81 seconds
Started Jan 24 08:45:31 PM PST 24
Finished Jan 24 08:45:46 PM PST 24
Peak memory 218120 kb
Host smart-d0d27ee7-7b7e-48c8-8854-56b7e2cb853a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660311811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3660311811
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.526355337
Short name T936
Test name
Test status
Simulation time 2163475213 ps
CPU time 12.7 seconds
Started Jan 24 08:54:54 PM PST 24
Finished Jan 24 08:55:11 PM PST 24
Peak memory 218180 kb
Host smart-564caba7-ddfa-4e8e-836a-a2939f887997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526355337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.526355337
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2652694339
Short name T809
Test name
Test status
Simulation time 70018966 ps
CPU time 2.53 seconds
Started Jan 24 08:57:10 PM PST 24
Finished Jan 24 08:57:17 PM PST 24
Peak memory 213560 kb
Host smart-f2369092-f420-47a0-87b5-9f0631be97e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652694339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2652694339
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1141046750
Short name T870
Test name
Test status
Simulation time 400481093 ps
CPU time 28.93 seconds
Started Jan 24 08:45:16 PM PST 24
Finished Jan 24 08:45:47 PM PST 24
Peak memory 249940 kb
Host smart-3ffc588e-6fe9-4729-ae0c-b6de056fe1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141046750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1141046750
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.242804102
Short name T604
Test name
Test status
Simulation time 114956806 ps
CPU time 6.99 seconds
Started Jan 24 08:45:16 PM PST 24
Finished Jan 24 08:45:24 PM PST 24
Peak memory 250848 kb
Host smart-4f04ef4d-4569-4927-8628-a56196a8cb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242804102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.242804102
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2394166893
Short name T779
Test name
Test status
Simulation time 3659296859 ps
CPU time 76 seconds
Started Jan 24 08:45:36 PM PST 24
Finished Jan 24 08:46:53 PM PST 24
Peak memory 278316 kb
Host smart-cce82f1b-adc3-4ab4-8d56-7b96246ea106
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394166893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2394166893
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3587592097
Short name T341
Test name
Test status
Simulation time 31215164 ps
CPU time 0.94 seconds
Started Jan 24 08:45:12 PM PST 24
Finished Jan 24 08:45:14 PM PST 24
Peak memory 211200 kb
Host smart-86247aba-dad1-4125-8790-cd42bde26c04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587592097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3587592097
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1063838452
Short name T558
Test name
Test status
Simulation time 68001487 ps
CPU time 1.1 seconds
Started Jan 24 08:45:57 PM PST 24
Finished Jan 24 08:45:59 PM PST 24
Peak memory 208792 kb
Host smart-0ca393ad-ed5a-465a-a51c-13cf151c9d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063838452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1063838452
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3336056151
Short name T753
Test name
Test status
Simulation time 3043211517 ps
CPU time 18.46 seconds
Started Jan 24 08:45:55 PM PST 24
Finished Jan 24 08:46:14 PM PST 24
Peak memory 218156 kb
Host smart-e65fefa2-cc85-41d6-944b-dc5ac494189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336056151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3336056151
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.209829509
Short name T669
Test name
Test status
Simulation time 57003578 ps
CPU time 2.15 seconds
Started Jan 24 08:45:57 PM PST 24
Finished Jan 24 08:46:00 PM PST 24
Peak memory 209508 kb
Host smart-e4d8edc9-40c3-428e-acd9-328d9c22ac63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209829509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_ac
cess.209829509
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.141131546
Short name T945
Test name
Test status
Simulation time 302066626 ps
CPU time 2.92 seconds
Started Jan 24 08:45:55 PM PST 24
Finished Jan 24 08:45:59 PM PST 24
Peak memory 218108 kb
Host smart-4839a684-c173-4301-bcf5-15e7c83376e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141131546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.141131546
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2196167626
Short name T862
Test name
Test status
Simulation time 1038059510 ps
CPU time 14.26 seconds
Started Jan 24 08:45:57 PM PST 24
Finished Jan 24 08:46:12 PM PST 24
Peak memory 219124 kb
Host smart-fef19d00-1b31-4866-b2e7-e29e4e32cc4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196167626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2196167626
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3140010594
Short name T321
Test name
Test status
Simulation time 700489356 ps
CPU time 11.21 seconds
Started Jan 24 08:45:56 PM PST 24
Finished Jan 24 08:46:08 PM PST 24
Peak memory 218120 kb
Host smart-056e7fdf-f492-4d5d-b939-dd85d66556ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140010594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3140010594
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1609388528
Short name T498
Test name
Test status
Simulation time 512883431 ps
CPU time 9.73 seconds
Started Jan 24 08:45:53 PM PST 24
Finished Jan 24 08:46:04 PM PST 24
Peak memory 218088 kb
Host smart-bc60f523-2777-4720-8df0-e1f0b83afd88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609388528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1609388528
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3967752455
Short name T726
Test name
Test status
Simulation time 340387010 ps
CPU time 9.6 seconds
Started Jan 24 08:45:58 PM PST 24
Finished Jan 24 08:46:09 PM PST 24
Peak memory 218124 kb
Host smart-fb7cda46-2a0d-42b8-a093-dda59a696e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967752455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3967752455
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.174454000
Short name T65
Test name
Test status
Simulation time 119490797 ps
CPU time 2.16 seconds
Started Jan 24 08:45:39 PM PST 24
Finished Jan 24 08:45:42 PM PST 24
Peak memory 213564 kb
Host smart-5fd22c86-8492-4f56-92e2-42420cbbb14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174454000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.174454000
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1611261533
Short name T345
Test name
Test status
Simulation time 324357109 ps
CPU time 34.95 seconds
Started Jan 24 08:45:57 PM PST 24
Finished Jan 24 08:46:33 PM PST 24
Peak memory 250380 kb
Host smart-442289e9-893a-46e4-a359-91e7f17e1a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611261533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1611261533
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1882337325
Short name T745
Test name
Test status
Simulation time 112298856 ps
CPU time 3.69 seconds
Started Jan 24 08:45:56 PM PST 24
Finished Jan 24 08:46:00 PM PST 24
Peak memory 221792 kb
Host smart-9045d4c4-f011-4733-bd52-8956d1aa11b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882337325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1882337325
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.862663870
Short name T784
Test name
Test status
Simulation time 9643582546 ps
CPU time 95.51 seconds
Started Jan 24 08:45:57 PM PST 24
Finished Jan 24 08:47:34 PM PST 24
Peak memory 271096 kb
Host smart-9032cefd-35df-4091-be75-1fda7349d78f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862663870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.862663870
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3390876576
Short name T686
Test name
Test status
Simulation time 13819288 ps
CPU time 0.94 seconds
Started Jan 24 08:45:41 PM PST 24
Finished Jan 24 08:45:43 PM PST 24
Peak memory 208000 kb
Host smart-033ae11f-f5a7-47dd-adf7-e25bd2c6a3ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390876576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3390876576
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3934376815
Short name T512
Test name
Test status
Simulation time 31088748 ps
CPU time 1.06 seconds
Started Jan 24 08:46:13 PM PST 24
Finished Jan 24 08:46:16 PM PST 24
Peak memory 209484 kb
Host smart-8db7dd55-c910-4fdc-84a3-08951cba30e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934376815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3934376815
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1620249464
Short name T831
Test name
Test status
Simulation time 289067349 ps
CPU time 13.43 seconds
Started Jan 25 01:08:41 AM PST 24
Finished Jan 25 01:08:55 AM PST 24
Peak memory 218144 kb
Host smart-43c884a6-3d53-444b-8efa-a9af58af4960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620249464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1620249464
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1521324798
Short name T577
Test name
Test status
Simulation time 131282599 ps
CPU time 1.54 seconds
Started Jan 24 08:46:12 PM PST 24
Finished Jan 24 08:46:16 PM PST 24
Peak memory 209492 kb
Host smart-f6f46864-c612-483d-9807-3a870c6b7205
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521324798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_a
ccess.1521324798
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1463112114
Short name T636
Test name
Test status
Simulation time 104569939 ps
CPU time 2 seconds
Started Jan 24 08:46:13 PM PST 24
Finished Jan 24 08:46:17 PM PST 24
Peak memory 218120 kb
Host smart-0c8080cf-b699-48df-afbf-0142ae697a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463112114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1463112114
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3547030588
Short name T890
Test name
Test status
Simulation time 2572729182 ps
CPU time 13.38 seconds
Started Jan 24 08:46:10 PM PST 24
Finished Jan 24 08:46:27 PM PST 24
Peak memory 219540 kb
Host smart-ad717cd4-6628-4d57-a958-7bc91527b745
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547030588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3547030588
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1122316223
Short name T639
Test name
Test status
Simulation time 1622785315 ps
CPU time 12.3 seconds
Started Jan 24 08:46:10 PM PST 24
Finished Jan 24 08:46:26 PM PST 24
Peak memory 218108 kb
Host smart-0d16d888-3711-4652-808a-cd67c5aa7c56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122316223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1122316223
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2776523125
Short name T525
Test name
Test status
Simulation time 1631075863 ps
CPU time 9.31 seconds
Started Jan 24 10:34:09 PM PST 24
Finished Jan 24 10:34:22 PM PST 24
Peak memory 218132 kb
Host smart-c7038817-ac64-4bde-bc19-fe6506302b21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776523125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2776523125
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1377998277
Short name T420
Test name
Test status
Simulation time 302534533 ps
CPU time 9.7 seconds
Started Jan 24 08:46:14 PM PST 24
Finished Jan 24 08:46:25 PM PST 24
Peak memory 218096 kb
Host smart-c9544e4c-8155-4651-ab7a-ece7e5ec0d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377998277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1377998277
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1969628415
Short name T614
Test name
Test status
Simulation time 34801603 ps
CPU time 1.67 seconds
Started Jan 24 08:46:12 PM PST 24
Finished Jan 24 08:46:16 PM PST 24
Peak memory 218172 kb
Host smart-f9a1355e-5aa0-4de7-bd5c-c618de3e2695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969628415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1969628415
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3939686146
Short name T951
Test name
Test status
Simulation time 1019355664 ps
CPU time 26.63 seconds
Started Jan 24 08:46:11 PM PST 24
Finished Jan 24 08:46:41 PM PST 24
Peak memory 251036 kb
Host smart-6e4d78d2-3caf-4ad5-81af-876a22de6a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939686146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3939686146
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.51918857
Short name T927
Test name
Test status
Simulation time 81119037 ps
CPU time 8.89 seconds
Started Jan 24 08:46:13 PM PST 24
Finished Jan 24 08:46:24 PM PST 24
Peak memory 251092 kb
Host smart-98977a4f-f048-4b39-aa2f-9a4779d34afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51918857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.51918857
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1815886465
Short name T674
Test name
Test status
Simulation time 12441114798 ps
CPU time 135.98 seconds
Started Jan 24 08:46:14 PM PST 24
Finished Jan 24 08:48:31 PM PST 24
Peak memory 283684 kb
Host smart-014c34cc-35b2-4179-8ae6-914b1c892342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815886465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1815886465
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.915441452
Short name T703
Test name
Test status
Simulation time 40103974 ps
CPU time 0.89 seconds
Started Jan 24 08:46:10 PM PST 24
Finished Jan 24 08:46:15 PM PST 24
Peak memory 211172 kb
Host smart-ab0cd52f-1428-4825-bd0d-9bc3fdfa360a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915441452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.915441452
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.4107122692
Short name T763
Test name
Test status
Simulation time 36082263 ps
CPU time 1.16 seconds
Started Jan 24 09:43:46 PM PST 24
Finished Jan 24 09:43:50 PM PST 24
Peak memory 209512 kb
Host smart-6c65b550-ffd1-4578-8294-949ffed448a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107122692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.4107122692
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3122565296
Short name T573
Test name
Test status
Simulation time 2094307526 ps
CPU time 25.01 seconds
Started Jan 24 09:12:56 PM PST 24
Finished Jan 24 09:13:24 PM PST 24
Peak memory 218104 kb
Host smart-fbc5442c-3988-4a22-8bde-f5fa6d76009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122565296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3122565296
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.123531114
Short name T879
Test name
Test status
Simulation time 300741027 ps
CPU time 8.66 seconds
Started Jan 24 08:46:13 PM PST 24
Finished Jan 24 08:46:24 PM PST 24
Peak memory 209500 kb
Host smart-58f31912-5c0f-4d47-9188-cb5d0e862a03
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123531114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_ac
cess.123531114
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2659295429
Short name T306
Test name
Test status
Simulation time 135132025 ps
CPU time 2.99 seconds
Started Jan 24 08:46:11 PM PST 24
Finished Jan 24 08:46:17 PM PST 24
Peak memory 218064 kb
Host smart-7f98c1a7-6d58-4a6c-8224-dee730d5249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659295429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2659295429
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2662019444
Short name T756
Test name
Test status
Simulation time 314280938 ps
CPU time 13.68 seconds
Started Jan 24 08:46:11 PM PST 24
Finished Jan 24 08:46:28 PM PST 24
Peak memory 219084 kb
Host smart-2a3e8d5b-c151-4d48-8666-39ae74356f92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662019444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2662019444
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3747129134
Short name T697
Test name
Test status
Simulation time 5556323412 ps
CPU time 13.64 seconds
Started Jan 24 11:31:28 PM PST 24
Finished Jan 24 11:31:42 PM PST 24
Peak memory 218176 kb
Host smart-7e584150-ad75-45af-a4a7-25f1f6b3f3d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747129134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3747129134
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.243597501
Short name T429
Test name
Test status
Simulation time 918334429 ps
CPU time 15.86 seconds
Started Jan 24 10:28:28 PM PST 24
Finished Jan 24 10:28:44 PM PST 24
Peak memory 218116 kb
Host smart-160987ab-5cab-475b-8536-dfabcad8d817
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243597501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.243597501
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3830125961
Short name T914
Test name
Test status
Simulation time 2489612614 ps
CPU time 10.86 seconds
Started Jan 24 09:52:12 PM PST 24
Finished Jan 24 09:52:25 PM PST 24
Peak memory 218176 kb
Host smart-ec5efd09-c87a-4c22-8a0c-6b82d4942a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830125961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3830125961
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2161252698
Short name T599
Test name
Test status
Simulation time 92679138 ps
CPU time 4.86 seconds
Started Jan 24 08:46:14 PM PST 24
Finished Jan 24 08:46:20 PM PST 24
Peak memory 213916 kb
Host smart-a0d69749-dc4a-472b-a54a-a5b9f8c31beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161252698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2161252698
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.144345459
Short name T898
Test name
Test status
Simulation time 467402702 ps
CPU time 24.34 seconds
Started Jan 24 08:46:10 PM PST 24
Finished Jan 24 08:46:38 PM PST 24
Peak memory 251048 kb
Host smart-015acdad-7ac2-4980-b72b-4d1bfc9dc535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144345459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.144345459
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3061547636
Short name T482
Test name
Test status
Simulation time 129894762 ps
CPU time 7.45 seconds
Started Jan 24 08:46:11 PM PST 24
Finished Jan 24 08:46:22 PM PST 24
Peak memory 250616 kb
Host smart-5e70133f-a9f9-4266-a3c7-b5dc77379a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061547636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3061547636
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2297855153
Short name T673
Test name
Test status
Simulation time 2242534582 ps
CPU time 75.09 seconds
Started Jan 24 09:03:09 PM PST 24
Finished Jan 24 09:04:24 PM PST 24
Peak memory 268472 kb
Host smart-3bd7e618-a17b-48d1-ab00-12b9516e347f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297855153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2297855153
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1270423281
Short name T502
Test name
Test status
Simulation time 20905597 ps
CPU time 1 seconds
Started Jan 24 08:46:11 PM PST 24
Finished Jan 24 08:46:15 PM PST 24
Peak memory 211344 kb
Host smart-8c08eb0b-af2d-416c-86fd-ad77f31aa420
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270423281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1270423281
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3922900569
Short name T291
Test name
Test status
Simulation time 38356776 ps
CPU time 0.99 seconds
Started Jan 24 08:46:30 PM PST 24
Finished Jan 24 08:46:36 PM PST 24
Peak memory 209476 kb
Host smart-757d894a-7c12-46de-865d-f208e38e8dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922900569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3922900569
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3361639280
Short name T40
Test name
Test status
Simulation time 2058253151 ps
CPU time 9.33 seconds
Started Jan 24 08:46:24 PM PST 24
Finished Jan 24 08:46:36 PM PST 24
Peak memory 218096 kb
Host smart-f6b7f9b5-a1ab-4592-87c1-a6d98ffe112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361639280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3361639280
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2162693390
Short name T708
Test name
Test status
Simulation time 752582880 ps
CPU time 4.6 seconds
Started Jan 24 09:30:01 PM PST 24
Finished Jan 24 09:30:07 PM PST 24
Peak memory 217696 kb
Host smart-fdd6001e-20da-47af-a64f-3a0367b9639b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162693390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.2162693390
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3900400313
Short name T685
Test name
Test status
Simulation time 113720140 ps
CPU time 1.68 seconds
Started Jan 24 08:46:28 PM PST 24
Finished Jan 24 08:46:38 PM PST 24
Peak memory 218064 kb
Host smart-3bb89db8-d0a8-42fd-8049-7d6d6e506a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900400313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3900400313
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2947377279
Short name T731
Test name
Test status
Simulation time 1665814088 ps
CPU time 21.91 seconds
Started Jan 24 08:46:29 PM PST 24
Finished Jan 24 08:46:58 PM PST 24
Peak memory 218224 kb
Host smart-29bed015-6d6f-444f-9f1b-0a5a16d00c8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947377279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2947377279
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2565163545
Short name T103
Test name
Test status
Simulation time 980884024 ps
CPU time 13.25 seconds
Started Jan 24 10:29:38 PM PST 24
Finished Jan 24 10:29:53 PM PST 24
Peak memory 218116 kb
Host smart-e26691ba-4e62-4f16-b588-ae0fdf6432b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565163545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2565163545
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.227587059
Short name T958
Test name
Test status
Simulation time 176349541 ps
CPU time 8.09 seconds
Started Jan 24 08:46:33 PM PST 24
Finished Jan 24 08:46:47 PM PST 24
Peak memory 218112 kb
Host smart-dd021daf-a877-4e34-964d-1a1717bcf283
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227587059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.227587059
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1857638809
Short name T568
Test name
Test status
Simulation time 1187043884 ps
CPU time 7.82 seconds
Started Jan 24 09:20:49 PM PST 24
Finished Jan 24 09:20:58 PM PST 24
Peak memory 218108 kb
Host smart-594c4bc0-d768-417f-8f0e-f6c961aa172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857638809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1857638809
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2706064938
Short name T631
Test name
Test status
Simulation time 140108858 ps
CPU time 3.82 seconds
Started Jan 24 09:21:06 PM PST 24
Finished Jan 24 09:21:10 PM PST 24
Peak memory 214408 kb
Host smart-31675dcf-d276-431e-b878-e45bf0e8e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706064938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2706064938
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1578215195
Short name T693
Test name
Test status
Simulation time 322491157 ps
CPU time 22.38 seconds
Started Jan 24 10:01:25 PM PST 24
Finished Jan 24 10:01:51 PM PST 24
Peak memory 251112 kb
Host smart-dd292b19-d73b-481c-89ec-09f6645262a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578215195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1578215195
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2748681246
Short name T537
Test name
Test status
Simulation time 955294738 ps
CPU time 8.37 seconds
Started Jan 24 08:54:13 PM PST 24
Finished Jan 24 08:54:22 PM PST 24
Peak memory 246384 kb
Host smart-afc508a5-654b-44ab-a155-e9d780e0998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748681246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2748681246
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.338093609
Short name T795
Test name
Test status
Simulation time 2312689241 ps
CPU time 61.66 seconds
Started Jan 24 08:46:31 PM PST 24
Finished Jan 24 08:47:38 PM PST 24
Peak memory 277172 kb
Host smart-562ef506-1c8c-468c-82cc-079e5fc2947b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338093609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.338093609
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.530777273
Short name T112
Test name
Test status
Simulation time 101475801784 ps
CPU time 639.29 seconds
Started Jan 24 08:46:30 PM PST 24
Finished Jan 24 08:57:15 PM PST 24
Peak memory 496964 kb
Host smart-0a1b9f22-7414-4e9b-bb4b-b5d8b2746882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=530777273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.530777273
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2706097447
Short name T492
Test name
Test status
Simulation time 31698485 ps
CPU time 0.86 seconds
Started Jan 24 10:27:09 PM PST 24
Finished Jan 24 10:27:10 PM PST 24
Peak memory 208152 kb
Host smart-ce9b58d0-8d59-4f3b-80a6-22756177eade
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706097447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2706097447
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3362785573
Short name T469
Test name
Test status
Simulation time 12462806 ps
CPU time 0.83 seconds
Started Jan 24 08:47:04 PM PST 24
Finished Jan 24 08:47:05 PM PST 24
Peak memory 207896 kb
Host smart-380cd557-c7e9-4ec8-a714-b7a4b7452606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362785573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3362785573
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2662680476
Short name T930
Test name
Test status
Simulation time 1576856112 ps
CPU time 16.89 seconds
Started Jan 24 08:46:49 PM PST 24
Finished Jan 24 08:47:08 PM PST 24
Peak memory 218124 kb
Host smart-1f342b84-eb25-48f1-9964-7605145f2cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662680476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2662680476
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3784852236
Short name T564
Test name
Test status
Simulation time 3886533465 ps
CPU time 7.73 seconds
Started Jan 24 08:46:51 PM PST 24
Finished Jan 24 08:46:59 PM PST 24
Peak memory 209556 kb
Host smart-c1a9c071-c2f6-4a75-b8db-20f9b79fd7fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784852236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.3784852236
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3762116096
Short name T664
Test name
Test status
Simulation time 93844273 ps
CPU time 2.28 seconds
Started Jan 24 08:46:49 PM PST 24
Finished Jan 24 08:46:53 PM PST 24
Peak memory 218104 kb
Host smart-5dc9b3cb-ce03-464b-8e1d-1b8a5c757c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762116096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3762116096
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2842306521
Short name T100
Test name
Test status
Simulation time 844360962 ps
CPU time 20.75 seconds
Started Jan 24 08:46:48 PM PST 24
Finished Jan 24 08:47:09 PM PST 24
Peak memory 219120 kb
Host smart-e4e614da-1404-4494-9577-ad2e1eabc340
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842306521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2842306521
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3486390176
Short name T680
Test name
Test status
Simulation time 392291370 ps
CPU time 11.77 seconds
Started Jan 24 08:47:04 PM PST 24
Finished Jan 24 08:47:17 PM PST 24
Peak memory 218124 kb
Host smart-03af6c13-b722-46ad-aa03-9696116a6d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486390176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3486390176
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3287219329
Short name T374
Test name
Test status
Simulation time 1089261552 ps
CPU time 9.64 seconds
Started Jan 24 08:46:51 PM PST 24
Finished Jan 24 08:47:02 PM PST 24
Peak memory 218088 kb
Host smart-ff73884e-bf20-454f-bad2-de3d1ab872e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287219329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3287219329
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1895268577
Short name T508
Test name
Test status
Simulation time 1252460701 ps
CPU time 10.07 seconds
Started Jan 24 08:46:48 PM PST 24
Finished Jan 24 08:47:00 PM PST 24
Peak memory 218124 kb
Host smart-003bb5a4-cd2d-4ba5-a828-e548c7d54b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895268577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1895268577
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2182713754
Short name T47
Test name
Test status
Simulation time 94868996 ps
CPU time 3.25 seconds
Started Jan 24 08:46:40 PM PST 24
Finished Jan 24 08:46:45 PM PST 24
Peak memory 213776 kb
Host smart-b41ea64a-dc97-4171-b501-8f08b44a9715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182713754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2182713754
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.84339538
Short name T922
Test name
Test status
Simulation time 871695885 ps
CPU time 32.63 seconds
Started Jan 24 08:46:38 PM PST 24
Finished Jan 24 08:47:14 PM PST 24
Peak memory 251020 kb
Host smart-7fc1bd61-04d3-44d8-9b79-923e3daeccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84339538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.84339538
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.406512114
Short name T466
Test name
Test status
Simulation time 58817712 ps
CPU time 3.55 seconds
Started Jan 24 08:46:40 PM PST 24
Finished Jan 24 08:46:46 PM PST 24
Peak memory 222004 kb
Host smart-9f06a422-46bc-495a-9d2c-347881f13af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406512114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.406512114
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3323111308
Short name T952
Test name
Test status
Simulation time 2770460251 ps
CPU time 59.19 seconds
Started Jan 24 08:47:04 PM PST 24
Finished Jan 24 08:48:04 PM PST 24
Peak memory 275936 kb
Host smart-82981ff5-0f6a-4904-a3e8-b96c08eb1a3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323111308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3323111308
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.188006084
Short name T801
Test name
Test status
Simulation time 32317506 ps
CPU time 0.76 seconds
Started Jan 24 08:46:40 PM PST 24
Finished Jan 24 08:46:43 PM PST 24
Peak memory 207716 kb
Host smart-822e760b-9e1d-49ea-848b-a9e79a6f537a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188006084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.188006084
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.529861817
Short name T88
Test name
Test status
Simulation time 14530518 ps
CPU time 1.02 seconds
Started Jan 24 08:47:16 PM PST 24
Finished Jan 24 08:47:19 PM PST 24
Peak memory 208128 kb
Host smart-199ef5d1-21b0-4021-b28d-87c84fa0cc37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529861817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.529861817
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4058679180
Short name T445
Test name
Test status
Simulation time 192158709 ps
CPU time 8.76 seconds
Started Jan 24 08:47:11 PM PST 24
Finished Jan 24 08:47:22 PM PST 24
Peak memory 218228 kb
Host smart-99ccc32a-2a44-4128-9767-e2e84be23f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058679180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4058679180
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.719370424
Short name T397
Test name
Test status
Simulation time 5968469509 ps
CPU time 5.03 seconds
Started Jan 24 08:47:11 PM PST 24
Finished Jan 24 08:47:17 PM PST 24
Peak memory 209568 kb
Host smart-4c50538b-dc62-4f08-ac4f-10c9d4767baf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719370424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_ac
cess.719370424
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3925784131
Short name T937
Test name
Test status
Simulation time 32304243 ps
CPU time 1.41 seconds
Started Jan 24 08:47:10 PM PST 24
Finished Jan 24 08:47:13 PM PST 24
Peak memory 218128 kb
Host smart-4c4fa23a-dfc6-432c-b696-187a22a3884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925784131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3925784131
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.851526891
Short name T799
Test name
Test status
Simulation time 1792964582 ps
CPU time 14.03 seconds
Started Jan 24 08:47:16 PM PST 24
Finished Jan 24 08:47:31 PM PST 24
Peak memory 218132 kb
Host smart-9f5a5aa0-7e4b-43d3-a8d5-279fc84261a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851526891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.851526891
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1182879074
Short name T292
Test name
Test status
Simulation time 256528888 ps
CPU time 8.29 seconds
Started Jan 24 08:47:11 PM PST 24
Finished Jan 24 08:47:21 PM PST 24
Peak memory 218068 kb
Host smart-dd86eab3-d364-41e1-beb6-16cc02aab091
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182879074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1182879074
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1513755643
Short name T499
Test name
Test status
Simulation time 828462038 ps
CPU time 16.49 seconds
Started Jan 24 08:47:16 PM PST 24
Finished Jan 24 08:47:35 PM PST 24
Peak memory 218100 kb
Host smart-4d6abee1-a2ac-4784-a6f6-2a61e5d308f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513755643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1513755643
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4007251845
Short name T706
Test name
Test status
Simulation time 431860671 ps
CPU time 7.39 seconds
Started Jan 24 08:47:15 PM PST 24
Finished Jan 24 08:47:23 PM PST 24
Peak memory 218088 kb
Host smart-126645c8-11ec-4af4-8ca2-0aa14e0a428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007251845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4007251845
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1457472351
Short name T749
Test name
Test status
Simulation time 55267510 ps
CPU time 2.5 seconds
Started Jan 24 08:47:00 PM PST 24
Finished Jan 24 08:47:03 PM PST 24
Peak memory 213816 kb
Host smart-dc94d5bd-5802-4717-9ba0-145521ffbd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457472351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1457472351
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.353909472
Short name T833
Test name
Test status
Simulation time 836678598 ps
CPU time 16.39 seconds
Started Jan 24 08:47:11 PM PST 24
Finished Jan 24 08:47:28 PM PST 24
Peak memory 251112 kb
Host smart-b2bbeb5e-7df0-4588-b5f4-842a31b641c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353909472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.353909472
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2133296246
Short name T758
Test name
Test status
Simulation time 674489725 ps
CPU time 6.16 seconds
Started Jan 24 08:47:14 PM PST 24
Finished Jan 24 08:47:22 PM PST 24
Peak memory 249896 kb
Host smart-a5f92ee5-cfe1-4e3f-97e0-f128dc8095a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133296246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2133296246
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1204040263
Short name T336
Test name
Test status
Simulation time 8892282109 ps
CPU time 169.08 seconds
Started Jan 24 08:47:16 PM PST 24
Finished Jan 24 08:50:06 PM PST 24
Peak memory 251192 kb
Host smart-16c626fc-980a-4c4d-9ccd-1ae3314f1592
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204040263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1204040263
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1618881460
Short name T111
Test name
Test status
Simulation time 104527114804 ps
CPU time 523.03 seconds
Started Jan 24 08:47:12 PM PST 24
Finished Jan 24 08:55:56 PM PST 24
Peak memory 316776 kb
Host smart-aa2a451a-c8d9-4888-997c-4778f891bcd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1618881460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1618881460
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3176417189
Short name T659
Test name
Test status
Simulation time 16375817 ps
CPU time 1.04 seconds
Started Jan 24 08:47:04 PM PST 24
Finished Jan 24 08:47:06 PM PST 24
Peak memory 208168 kb
Host smart-8c00d9b4-c2ee-4c0b-b853-da768f95ba0c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176417189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3176417189
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1844469950
Short name T543
Test name
Test status
Simulation time 31233695 ps
CPU time 1.42 seconds
Started Jan 24 08:59:11 PM PST 24
Finished Jan 24 08:59:14 PM PST 24
Peak memory 209496 kb
Host smart-7c1ac4a5-6a9c-479c-af71-f6bfd3b260ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844469950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1844469950
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3475278911
Short name T487
Test name
Test status
Simulation time 712875238 ps
CPU time 16 seconds
Started Jan 24 08:35:04 PM PST 24
Finished Jan 24 08:35:21 PM PST 24
Peak memory 218112 kb
Host smart-439792f9-ee95-4249-9fef-ed7343a2aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475278911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3475278911
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2470047835
Short name T744
Test name
Test status
Simulation time 429949137 ps
CPU time 5.7 seconds
Started Jan 24 08:35:16 PM PST 24
Finished Jan 24 08:35:23 PM PST 24
Peak memory 209504 kb
Host smart-8fee672a-fd34-4946-8a91-4897ff7e5f01
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470047835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.2470047835
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2127239204
Short name T457
Test name
Test status
Simulation time 2582315899 ps
CPU time 21.05 seconds
Started Jan 24 09:33:08 PM PST 24
Finished Jan 24 09:33:30 PM PST 24
Peak memory 218148 kb
Host smart-d48c98f8-c9ee-4280-a277-2a055885f681
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127239204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2127239204
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3466677839
Short name T975
Test name
Test status
Simulation time 2603365904 ps
CPU time 7.24 seconds
Started Jan 24 08:35:14 PM PST 24
Finished Jan 24 08:35:22 PM PST 24
Peak memory 209656 kb
Host smart-3f653568-2c9b-4458-adf9-90843f76fdca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466677839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.3466677839
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3442202533
Short name T476
Test name
Test status
Simulation time 993163072 ps
CPU time 25.77 seconds
Started Jan 24 08:56:54 PM PST 24
Finished Jan 24 08:57:22 PM PST 24
Peak memory 213024 kb
Host smart-cd23aa2e-a6eb-45a5-b8db-83fc6b5dff09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442202533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3442202533
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4215549295
Short name T640
Test name
Test status
Simulation time 191831795 ps
CPU time 1.59 seconds
Started Jan 24 11:35:48 PM PST 24
Finished Jan 24 11:35:51 PM PST 24
Peak memory 212340 kb
Host smart-8070d3d3-00ad-4236-9dd6-eed77db21d6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215549295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4215549295
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2713049269
Short name T911
Test name
Test status
Simulation time 5786693437 ps
CPU time 48.81 seconds
Started Jan 24 08:35:14 PM PST 24
Finished Jan 24 08:36:04 PM PST 24
Peak memory 267780 kb
Host smart-20862817-7fd4-433d-9e3f-6410cb6fdca5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713049269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2713049269
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.52966556
Short name T398
Test name
Test status
Simulation time 497466353 ps
CPU time 19.76 seconds
Started Jan 24 08:35:14 PM PST 24
Finished Jan 24 08:35:34 PM PST 24
Peak memory 251036 kb
Host smart-e6bed9f9-560a-4bad-ba73-7bf321d40ecd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52966556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_state_post_trans.52966556
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1632333573
Short name T181
Test name
Test status
Simulation time 97953583 ps
CPU time 4.39 seconds
Started Jan 24 10:07:12 PM PST 24
Finished Jan 24 10:07:26 PM PST 24
Peak memory 218128 kb
Host smart-89d7659a-21eb-4d11-8d4f-990eb3926d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632333573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1632333573
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.385811879
Short name T418
Test name
Test status
Simulation time 1693289333 ps
CPU time 11.89 seconds
Started Jan 24 08:35:05 PM PST 24
Finished Jan 24 08:35:19 PM PST 24
Peak memory 213924 kb
Host smart-abba932d-b796-46de-9d5f-8c9192bc991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385811879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.385811879
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1369684636
Short name T86
Test name
Test status
Simulation time 432210248 ps
CPU time 40.52 seconds
Started Jan 24 08:51:44 PM PST 24
Finished Jan 24 08:52:27 PM PST 24
Peak memory 269180 kb
Host smart-b2838158-9b2d-4266-8127-c3eeb58b2f8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369684636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1369684636
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2554538058
Short name T409
Test name
Test status
Simulation time 226934834 ps
CPU time 10.18 seconds
Started Jan 24 08:35:22 PM PST 24
Finished Jan 24 08:35:33 PM PST 24
Peak memory 218116 kb
Host smart-70b73d02-01ff-42d5-ab09-4e8e944c146c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554538058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2554538058
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3358367443
Short name T312
Test name
Test status
Simulation time 1229811255 ps
CPU time 11.98 seconds
Started Jan 24 08:35:21 PM PST 24
Finished Jan 24 08:35:34 PM PST 24
Peak memory 218092 kb
Host smart-ca118b40-34ff-4a4e-befe-878317bbaa3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358367443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3358367443
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4122083936
Short name T323
Test name
Test status
Simulation time 1262464936 ps
CPU time 11.38 seconds
Started Jan 24 08:35:23 PM PST 24
Finished Jan 24 08:35:35 PM PST 24
Peak memory 218128 kb
Host smart-48a9de7a-7b43-4ed5-8bf9-f202785f29e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122083936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
122083936
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.528806422
Short name T523
Test name
Test status
Simulation time 1961151095 ps
CPU time 8.97 seconds
Started Jan 24 09:21:22 PM PST 24
Finished Jan 24 09:21:32 PM PST 24
Peak memory 218112 kb
Host smart-a2990a9c-fd7b-4d37-8f5a-95dc25dc7db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528806422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.528806422
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.167991689
Short name T591
Test name
Test status
Simulation time 151123292 ps
CPU time 2.56 seconds
Started Jan 24 08:34:47 PM PST 24
Finished Jan 24 08:34:51 PM PST 24
Peak memory 213880 kb
Host smart-e9c688dd-3112-4012-9535-e44c6c4d486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167991689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.167991689
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2063338911
Short name T727
Test name
Test status
Simulation time 955426809 ps
CPU time 22.79 seconds
Started Jan 24 08:34:55 PM PST 24
Finished Jan 24 08:35:22 PM PST 24
Peak memory 251048 kb
Host smart-62b1fa6d-9e1d-4ddb-be30-989a9353b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063338911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2063338911
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.65399965
Short name T8
Test name
Test status
Simulation time 126766604 ps
CPU time 7.47 seconds
Started Jan 24 08:34:56 PM PST 24
Finished Jan 24 08:35:06 PM PST 24
Peak memory 251104 kb
Host smart-10800e55-7848-4caa-90ea-02e4e9fd8a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65399965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.65399965
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3488299184
Short name T63
Test name
Test status
Simulation time 8535104152 ps
CPU time 120.85 seconds
Started Jan 24 08:35:23 PM PST 24
Finished Jan 24 08:37:24 PM PST 24
Peak memory 272248 kb
Host smart-f0d15993-99f7-4b38-bc0b-9b391d917808
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488299184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3488299184
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2202175616
Short name T444
Test name
Test status
Simulation time 34671810 ps
CPU time 0.79 seconds
Started Jan 24 09:14:25 PM PST 24
Finished Jan 24 09:14:26 PM PST 24
Peak memory 207976 kb
Host smart-5335137f-37f6-4531-93ff-15692cf2fbfc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202175616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2202175616
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2945043759
Short name T506
Test name
Test status
Simulation time 49309934 ps
CPU time 0.99 seconds
Started Jan 24 08:47:37 PM PST 24
Finished Jan 24 08:47:39 PM PST 24
Peak memory 209484 kb
Host smart-d70ebf04-b434-4d9d-a09a-403bb87942f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945043759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2945043759
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3334463737
Short name T931
Test name
Test status
Simulation time 3344270949 ps
CPU time 15.57 seconds
Started Jan 24 08:47:24 PM PST 24
Finished Jan 24 08:47:40 PM PST 24
Peak memory 225464 kb
Host smart-6cc718fc-67d1-43d7-8ae5-de9cfac2e370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334463737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3334463737
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.853992002
Short name T26
Test name
Test status
Simulation time 861446513 ps
CPU time 5.73 seconds
Started Jan 24 08:47:23 PM PST 24
Finished Jan 24 08:47:29 PM PST 24
Peak memory 209500 kb
Host smart-c95b8524-e8d3-4fe6-b184-3f4583612beb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853992002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_ac
cess.853992002
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.801358249
Short name T711
Test name
Test status
Simulation time 75375776 ps
CPU time 3.16 seconds
Started Jan 24 08:47:28 PM PST 24
Finished Jan 24 08:47:32 PM PST 24
Peak memory 218104 kb
Host smart-9d9a8c32-14bf-49e3-947b-900067b231e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801358249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.801358249
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1858544813
Short name T379
Test name
Test status
Simulation time 1533822001 ps
CPU time 12.09 seconds
Started Jan 24 08:47:37 PM PST 24
Finished Jan 24 08:47:50 PM PST 24
Peak memory 218164 kb
Host smart-842be9ab-a74a-4973-ba91-1385442f4563
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858544813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1858544813
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4000137940
Short name T352
Test name
Test status
Simulation time 781365641 ps
CPU time 8.72 seconds
Started Jan 24 08:47:42 PM PST 24
Finished Jan 24 08:47:52 PM PST 24
Peak memory 218120 kb
Host smart-a457afb2-b31a-4e94-9bf9-3cdc14800b7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000137940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4000137940
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2036956431
Short name T629
Test name
Test status
Simulation time 832916559 ps
CPU time 6.05 seconds
Started Jan 24 08:50:18 PM PST 24
Finished Jan 24 08:50:25 PM PST 24
Peak memory 218068 kb
Host smart-e6f964d6-a6b2-44d8-9a8a-fd3a0fcd7916
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036956431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2036956431
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3452435374
Short name T448
Test name
Test status
Simulation time 299227729 ps
CPU time 7.77 seconds
Started Jan 24 08:53:26 PM PST 24
Finished Jan 24 08:53:35 PM PST 24
Peak memory 218112 kb
Host smart-cbf13a8b-aebc-4d18-8b9b-b0f99990843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452435374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3452435374
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.433108524
Short name T743
Test name
Test status
Simulation time 32775887 ps
CPU time 1.88 seconds
Started Jan 24 08:47:13 PM PST 24
Finished Jan 24 08:47:16 PM PST 24
Peak memory 213260 kb
Host smart-ae3456a8-9cd5-45e8-aca9-4b9e12428071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433108524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.433108524
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.684385023
Short name T16
Test name
Test status
Simulation time 1091450796 ps
CPU time 26.33 seconds
Started Jan 24 09:09:57 PM PST 24
Finished Jan 24 09:10:26 PM PST 24
Peak memory 245476 kb
Host smart-662384af-7761-47ac-8919-8708794a7c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684385023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.684385023
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.786650831
Short name T417
Test name
Test status
Simulation time 189867477 ps
CPU time 3.54 seconds
Started Jan 24 08:47:28 PM PST 24
Finished Jan 24 08:47:32 PM PST 24
Peak memory 222104 kb
Host smart-be138e98-5787-4599-8e1f-42613ae72634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786650831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.786650831
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.4198585438
Short name T437
Test name
Test status
Simulation time 3293546852 ps
CPU time 60.32 seconds
Started Jan 24 08:47:34 PM PST 24
Finished Jan 24 08:48:36 PM PST 24
Peak memory 250872 kb
Host smart-5c8a6050-3ed2-48b5-84b0-abd7593b9591
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198585438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.4198585438
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3159519371
Short name T514
Test name
Test status
Simulation time 11707372 ps
CPU time 1.05 seconds
Started Jan 24 09:22:40 PM PST 24
Finished Jan 24 09:22:42 PM PST 24
Peak memory 211208 kb
Host smart-2f6ad3ab-88b9-45b7-966b-c0c9ad85af19
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159519371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3159519371
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1971610359
Short name T99
Test name
Test status
Simulation time 49372654 ps
CPU time 0.85 seconds
Started Jan 24 08:47:56 PM PST 24
Finished Jan 24 08:47:58 PM PST 24
Peak memory 209472 kb
Host smart-40b03b33-58a9-400b-87c9-4d83f4eb5bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971610359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1971610359
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1332089658
Short name T761
Test name
Test status
Simulation time 592168245 ps
CPU time 13.25 seconds
Started Jan 24 08:47:47 PM PST 24
Finished Jan 24 08:48:01 PM PST 24
Peak memory 218096 kb
Host smart-56f9a10d-2864-4a43-bc39-d6be183b8cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332089658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1332089658
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.4159218860
Short name T24
Test name
Test status
Simulation time 910696928 ps
CPU time 12.43 seconds
Started Jan 24 08:47:46 PM PST 24
Finished Jan 24 08:47:59 PM PST 24
Peak memory 209472 kb
Host smart-de50ef81-7e59-449e-9c6e-5e90e971fbe8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159218860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.4159218860
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1839392540
Short name T484
Test name
Test status
Simulation time 209829796 ps
CPU time 3.37 seconds
Started Jan 24 08:47:35 PM PST 24
Finished Jan 24 08:47:40 PM PST 24
Peak memory 218120 kb
Host smart-79718164-0266-4477-bdfe-af78a6f313ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839392540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1839392540
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4036245753
Short name T524
Test name
Test status
Simulation time 475654429 ps
CPU time 19.26 seconds
Started Jan 24 08:47:56 PM PST 24
Finished Jan 24 08:48:17 PM PST 24
Peak memory 219144 kb
Host smart-753265f2-48a4-497e-ae97-6a5ec361df8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036245753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4036245753
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4198781483
Short name T891
Test name
Test status
Simulation time 1904335980 ps
CPU time 16.83 seconds
Started Jan 24 08:48:02 PM PST 24
Finished Jan 24 08:48:20 PM PST 24
Peak memory 218128 kb
Host smart-2c23b73d-3da6-4184-81f5-8dd519f2885c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198781483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.4198781483
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2400354426
Short name T395
Test name
Test status
Simulation time 1881357524 ps
CPU time 8.87 seconds
Started Jan 24 08:47:58 PM PST 24
Finished Jan 24 08:48:08 PM PST 24
Peak memory 218092 kb
Host smart-33d9239a-8d12-4eea-8e44-41e12f0225a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400354426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2400354426
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1230173510
Short name T730
Test name
Test status
Simulation time 1096013078 ps
CPU time 7.29 seconds
Started Jan 24 08:47:45 PM PST 24
Finished Jan 24 08:47:53 PM PST 24
Peak memory 218128 kb
Host smart-d4ed2645-63b9-4730-b338-eaea028b2b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230173510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1230173510
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.492558021
Short name T917
Test name
Test status
Simulation time 216232122 ps
CPU time 1.36 seconds
Started Jan 24 08:47:34 PM PST 24
Finished Jan 24 08:47:37 PM PST 24
Peak memory 213060 kb
Host smart-5388ece1-1bb6-4ff3-a7fa-7dd85a1b3845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492558021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.492558021
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2899589454
Short name T532
Test name
Test status
Simulation time 5554403619 ps
CPU time 36.82 seconds
Started Jan 24 08:47:36 PM PST 24
Finished Jan 24 08:48:14 PM PST 24
Peak memory 251052 kb
Host smart-e5ce900a-c271-44b3-aaf8-adeea949d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899589454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2899589454
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3659802536
Short name T527
Test name
Test status
Simulation time 158103906 ps
CPU time 4.71 seconds
Started Jan 24 08:47:35 PM PST 24
Finished Jan 24 08:47:41 PM PST 24
Peak memory 222460 kb
Host smart-d1655a27-d44d-4c1a-b586-78b90bfd3974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659802536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3659802536
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2681728407
Short name T828
Test name
Test status
Simulation time 40381770 ps
CPU time 0.82 seconds
Started Jan 24 08:47:36 PM PST 24
Finished Jan 24 08:47:38 PM PST 24
Peak memory 207788 kb
Host smart-25867f84-89b3-42d2-9d22-7dd3b71abe2b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681728407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2681728407
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1324177592
Short name T805
Test name
Test status
Simulation time 60836124 ps
CPU time 0.91 seconds
Started Jan 25 12:02:37 AM PST 24
Finished Jan 25 12:02:40 AM PST 24
Peak memory 209488 kb
Host smart-1397ffaa-c925-48fd-a595-52a95098d980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324177592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1324177592
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1115564366
Short name T101
Test name
Test status
Simulation time 625966891 ps
CPU time 10.92 seconds
Started Jan 24 08:48:15 PM PST 24
Finished Jan 24 08:48:27 PM PST 24
Peak memory 218056 kb
Host smart-d83213b8-1d2b-45f3-9923-11f2fd3c0942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115564366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1115564366
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.73974112
Short name T546
Test name
Test status
Simulation time 1071813470 ps
CPU time 7.62 seconds
Started Jan 24 08:48:17 PM PST 24
Finished Jan 24 08:48:25 PM PST 24
Peak memory 209536 kb
Host smart-df7ab38b-fac6-43e9-8ae0-e59e3757effb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73974112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_acc
ess.73974112
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3670037688
Short name T339
Test name
Test status
Simulation time 59262845 ps
CPU time 2.86 seconds
Started Jan 24 08:47:57 PM PST 24
Finished Jan 24 08:48:01 PM PST 24
Peak memory 218064 kb
Host smart-718ce8aa-d4e5-489a-9cda-94b60214cd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670037688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3670037688
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.55634368
Short name T854
Test name
Test status
Simulation time 401250774 ps
CPU time 12.2 seconds
Started Jan 24 08:48:14 PM PST 24
Finished Jan 24 08:48:27 PM PST 24
Peak memory 219144 kb
Host smart-1c331218-a6c0-4e27-8f31-10916d7222d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55634368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.55634368
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2061366907
Short name T956
Test name
Test status
Simulation time 5707293505 ps
CPU time 22.7 seconds
Started Jan 24 08:48:19 PM PST 24
Finished Jan 24 08:48:43 PM PST 24
Peak memory 218156 kb
Host smart-2172d32a-9695-42c9-a3f1-d9d31fd58fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061366907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2061366907
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.415573884
Short name T366
Test name
Test status
Simulation time 1764277581 ps
CPU time 10.41 seconds
Started Jan 24 10:06:36 PM PST 24
Finished Jan 24 10:06:48 PM PST 24
Peak memory 218124 kb
Host smart-68fb6a65-1eab-4526-a699-67221de61432
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415573884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.415573884
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1936575446
Short name T574
Test name
Test status
Simulation time 388213877 ps
CPU time 11.26 seconds
Started Jan 24 08:48:17 PM PST 24
Finished Jan 24 08:48:29 PM PST 24
Peak memory 218120 kb
Host smart-f6a413c9-1edc-4fce-914b-4fa572df8c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936575446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1936575446
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3066493555
Short name T67
Test name
Test status
Simulation time 25452211 ps
CPU time 1.91 seconds
Started Jan 24 08:54:35 PM PST 24
Finished Jan 24 08:54:38 PM PST 24
Peak memory 213536 kb
Host smart-583b5e29-d6e5-4507-aedf-efaeb8e5fdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066493555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3066493555
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1659914481
Short name T504
Test name
Test status
Simulation time 227243923 ps
CPU time 20.66 seconds
Started Jan 24 08:48:00 PM PST 24
Finished Jan 24 08:48:21 PM PST 24
Peak memory 251132 kb
Host smart-a7c85358-8c2a-4f87-9a05-023ff1d3f9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659914481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1659914481
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3026524592
Short name T734
Test name
Test status
Simulation time 220374094 ps
CPU time 8.21 seconds
Started Jan 24 08:47:58 PM PST 24
Finished Jan 24 08:48:07 PM PST 24
Peak memory 251056 kb
Host smart-ef47f0a8-06ed-4868-a2f4-8191740f05ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026524592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3026524592
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.548943201
Short name T68
Test name
Test status
Simulation time 1029167518 ps
CPU time 80.17 seconds
Started Jan 24 08:48:15 PM PST 24
Finished Jan 24 08:49:36 PM PST 24
Peak memory 251104 kb
Host smart-700f5632-d386-43af-beab-2bfab3a5748d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548943201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.548943201
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1091036853
Short name T322
Test name
Test status
Simulation time 22129083 ps
CPU time 1 seconds
Started Jan 24 08:47:56 PM PST 24
Finished Jan 24 08:47:58 PM PST 24
Peak memory 211252 kb
Host smart-6beecffb-31ff-4662-be9d-7c919de8f5a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091036853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1091036853
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3068156202
Short name T637
Test name
Test status
Simulation time 82332711 ps
CPU time 0.87 seconds
Started Jan 24 08:52:43 PM PST 24
Finished Jan 24 08:52:47 PM PST 24
Peak memory 209336 kb
Host smart-f1e0dcec-295f-4321-b0c3-7204da51a215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068156202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3068156202
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2479636614
Short name T313
Test name
Test status
Simulation time 262245538 ps
CPU time 10.74 seconds
Started Jan 24 08:48:30 PM PST 24
Finished Jan 24 08:48:42 PM PST 24
Peak memory 218112 kb
Host smart-bbce4d60-56a3-4ce7-8ee4-c8240c1910d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479636614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2479636614
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1756668387
Short name T346
Test name
Test status
Simulation time 6563477677 ps
CPU time 4.76 seconds
Started Jan 24 08:48:32 PM PST 24
Finished Jan 24 08:48:37 PM PST 24
Peak memory 209684 kb
Host smart-e14ec840-f173-4f94-8a0f-9fd07b5487ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756668387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.1756668387
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1760768379
Short name T690
Test name
Test status
Simulation time 45773687 ps
CPU time 2.13 seconds
Started Jan 24 09:54:08 PM PST 24
Finished Jan 24 09:54:11 PM PST 24
Peak memory 218112 kb
Host smart-1bb56879-1f30-475e-af7a-2c90ef920ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760768379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1760768379
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1933203120
Short name T816
Test name
Test status
Simulation time 1197733620 ps
CPU time 16.65 seconds
Started Jan 24 08:48:34 PM PST 24
Finished Jan 24 08:48:51 PM PST 24
Peak memory 218172 kb
Host smart-60412a68-0fc9-4455-877e-3df7e55fb892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933203120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1933203120
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2819949357
Short name T342
Test name
Test status
Simulation time 278000539 ps
CPU time 10.42 seconds
Started Jan 24 08:48:33 PM PST 24
Finished Jan 24 08:48:45 PM PST 24
Peak memory 218120 kb
Host smart-01042f5e-645e-48a3-ae37-bd19b55428c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819949357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2819949357
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2583561502
Short name T762
Test name
Test status
Simulation time 254242215 ps
CPU time 9.76 seconds
Started Jan 25 01:21:21 AM PST 24
Finished Jan 25 01:21:37 AM PST 24
Peak memory 218160 kb
Host smart-ed20daf2-0bb4-48ad-82a1-64a99c66b54f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583561502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2583561502
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1152675790
Short name T110
Test name
Test status
Simulation time 250165585 ps
CPU time 9.5 seconds
Started Jan 24 09:24:18 PM PST 24
Finished Jan 24 09:24:31 PM PST 24
Peak memory 218116 kb
Host smart-cacb1006-77de-4f93-96ff-d30edc7970be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152675790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1152675790
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2800439840
Short name T877
Test name
Test status
Simulation time 92593300 ps
CPU time 1.25 seconds
Started Jan 24 08:48:19 PM PST 24
Finished Jan 24 08:48:21 PM PST 24
Peak memory 213168 kb
Host smart-5a2a7169-60c4-4c9a-91b0-586a6d9fb430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800439840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2800439840
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3948804472
Short name T919
Test name
Test status
Simulation time 1250868667 ps
CPU time 23.78 seconds
Started Jan 24 08:48:19 PM PST 24
Finished Jan 24 08:48:43 PM PST 24
Peak memory 251036 kb
Host smart-3bd2c1d6-edd3-4d00-b9dd-8c314d184830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948804472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3948804472
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.295197582
Short name T688
Test name
Test status
Simulation time 805432749 ps
CPU time 7.42 seconds
Started Jan 24 10:33:09 PM PST 24
Finished Jan 24 10:33:17 PM PST 24
Peak memory 243808 kb
Host smart-dafa7a1e-663a-4330-9417-e57fd427bd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295197582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.295197582
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1316986299
Short name T505
Test name
Test status
Simulation time 2605482764 ps
CPU time 57.44 seconds
Started Jan 24 08:48:35 PM PST 24
Finished Jan 24 08:49:33 PM PST 24
Peak memory 251144 kb
Host smart-dc9fe8f5-1796-4e32-923e-79c34a08743c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316986299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1316986299
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1522660872
Short name T14
Test name
Test status
Simulation time 22196223 ps
CPU time 0.79 seconds
Started Jan 24 08:48:18 PM PST 24
Finished Jan 24 08:48:19 PM PST 24
Peak memory 207824 kb
Host smart-6dda7908-4cac-4128-9332-f205b75adb2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522660872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1522660872
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.500669970
Short name T967
Test name
Test status
Simulation time 215593499 ps
CPU time 0.94 seconds
Started Jan 24 08:48:42 PM PST 24
Finished Jan 24 08:48:44 PM PST 24
Peak memory 208088 kb
Host smart-dff3b181-d052-4ae7-97f6-1622884c7f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500669970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.500669970
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2270679731
Short name T938
Test name
Test status
Simulation time 293169856 ps
CPU time 9.88 seconds
Started Jan 24 08:48:40 PM PST 24
Finished Jan 24 08:48:51 PM PST 24
Peak memory 218060 kb
Host smart-970fa1cd-82ec-437c-bf6e-88c38da388d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270679731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2270679731
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3795521036
Short name T794
Test name
Test status
Simulation time 1252821959 ps
CPU time 5.91 seconds
Started Jan 24 08:48:41 PM PST 24
Finished Jan 24 08:48:47 PM PST 24
Peak memory 209516 kb
Host smart-97c5f624-f19d-4ca7-a27a-4526fe16d748
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795521036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.3795521036
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3794962264
Short name T550
Test name
Test status
Simulation time 215219766 ps
CPU time 3.48 seconds
Started Jan 24 09:41:30 PM PST 24
Finished Jan 24 09:41:35 PM PST 24
Peak memory 218148 kb
Host smart-970c15e6-1bf4-459a-8f3b-2b6bc6e00296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794962264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3794962264
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3251260267
Short name T704
Test name
Test status
Simulation time 618232255 ps
CPU time 15.67 seconds
Started Jan 24 08:48:41 PM PST 24
Finished Jan 24 08:48:58 PM PST 24
Peak memory 219136 kb
Host smart-a373bc68-a490-47c6-8ae6-60200dbcfc81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251260267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3251260267
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1119574209
Short name T814
Test name
Test status
Simulation time 1007793838 ps
CPU time 13.02 seconds
Started Jan 24 08:48:43 PM PST 24
Finished Jan 24 08:48:57 PM PST 24
Peak memory 218092 kb
Host smart-b668be96-35bc-4373-bb26-efff7e167668
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119574209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1119574209
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1818752413
Short name T49
Test name
Test status
Simulation time 1945044177 ps
CPU time 11.4 seconds
Started Jan 24 08:48:49 PM PST 24
Finished Jan 24 08:49:02 PM PST 24
Peak memory 218104 kb
Host smart-f6f61330-84b6-4d58-9017-0fe3e8eb135c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818752413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1818752413
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3152138270
Short name T176
Test name
Test status
Simulation time 914127801 ps
CPU time 5.69 seconds
Started Jan 24 08:48:49 PM PST 24
Finished Jan 24 08:48:55 PM PST 24
Peak memory 218100 kb
Host smart-f6510782-96b3-4ce4-bb12-d2a783f665cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152138270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3152138270
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3996644450
Short name T786
Test name
Test status
Simulation time 123685524 ps
CPU time 1.33 seconds
Started Jan 24 08:48:33 PM PST 24
Finished Jan 24 08:48:35 PM PST 24
Peak memory 213068 kb
Host smart-ad38791b-a66d-4853-ad3a-0510a5a25208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996644450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3996644450
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1456978781
Short name T105
Test name
Test status
Simulation time 682605208 ps
CPU time 32.17 seconds
Started Jan 24 09:21:07 PM PST 24
Finished Jan 24 09:21:40 PM PST 24
Peak memory 251052 kb
Host smart-9d79d309-bc64-41c8-ac19-70ce9d78e4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456978781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1456978781
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3450691207
Short name T626
Test name
Test status
Simulation time 113030606 ps
CPU time 7.05 seconds
Started Jan 24 08:48:34 PM PST 24
Finished Jan 24 08:48:42 PM PST 24
Peak memory 246252 kb
Host smart-ee194947-dea0-41a8-b0f5-00964b195630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450691207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3450691207
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.653459152
Short name T569
Test name
Test status
Simulation time 12930120 ps
CPU time 0.96 seconds
Started Jan 24 08:48:36 PM PST 24
Finished Jan 24 08:48:37 PM PST 24
Peak memory 208128 kb
Host smart-0acbfa5d-affa-4181-96fd-41385b18c4a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653459152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.653459152
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3719950883
Short name T458
Test name
Test status
Simulation time 13838895 ps
CPU time 0.96 seconds
Started Jan 24 08:49:05 PM PST 24
Finished Jan 24 08:49:08 PM PST 24
Peak memory 208080 kb
Host smart-13509e5d-d570-4958-be89-deb297a88f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719950883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3719950883
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1062770286
Short name T634
Test name
Test status
Simulation time 927479021 ps
CPU time 18.65 seconds
Started Jan 24 08:48:58 PM PST 24
Finished Jan 24 08:49:22 PM PST 24
Peak memory 218064 kb
Host smart-0064c4c1-9675-4ad2-8e9f-2687952c49ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062770286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1062770286
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.378250198
Short name T25
Test name
Test status
Simulation time 2928078679 ps
CPU time 8.26 seconds
Started Jan 24 08:48:53 PM PST 24
Finished Jan 24 08:49:02 PM PST 24
Peak memory 209572 kb
Host smart-89780bbd-0fd1-4b13-912c-176e69c28efc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378250198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_ac
cess.378250198
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.51903466
Short name T608
Test name
Test status
Simulation time 39234575 ps
CPU time 2.88 seconds
Started Jan 24 11:18:55 PM PST 24
Finished Jan 24 11:18:59 PM PST 24
Peak memory 218132 kb
Host smart-0ac725f8-5f2b-43ce-8cca-d497e38ed01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51903466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.51903466
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3551074790
Short name T495
Test name
Test status
Simulation time 464049043 ps
CPU time 15.31 seconds
Started Jan 24 09:17:26 PM PST 24
Finished Jan 24 09:17:42 PM PST 24
Peak memory 219220 kb
Host smart-ce4cf913-f30d-4499-b95c-cdf0b116cb79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551074790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3551074790
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4086863669
Short name T819
Test name
Test status
Simulation time 677950943 ps
CPU time 8.52 seconds
Started Jan 24 08:48:57 PM PST 24
Finished Jan 24 08:49:06 PM PST 24
Peak memory 218060 kb
Host smart-b0b0eb2c-7427-4866-b2c5-c010d467cbac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086863669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4086863669
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.20546502
Short name T601
Test name
Test status
Simulation time 1199410273 ps
CPU time 8.02 seconds
Started Jan 24 08:48:55 PM PST 24
Finished Jan 24 08:49:05 PM PST 24
Peak memory 218100 kb
Host smart-94862848-35f1-4c7e-998e-01d2f628f20d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20546502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.20546502
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3113070545
Short name T977
Test name
Test status
Simulation time 331493094 ps
CPU time 13.21 seconds
Started Jan 24 09:15:55 PM PST 24
Finished Jan 24 09:16:09 PM PST 24
Peak memory 218124 kb
Host smart-2baa0ca7-acab-4a67-8a1f-b8288a1455b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113070545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3113070545
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1876108464
Short name T742
Test name
Test status
Simulation time 83387408 ps
CPU time 3.25 seconds
Started Jan 24 08:48:43 PM PST 24
Finished Jan 24 08:48:46 PM PST 24
Peak memory 214480 kb
Host smart-7c249262-53a3-4920-aa71-99479d231a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876108464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1876108464
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2644931484
Short name T555
Test name
Test status
Simulation time 224589646 ps
CPU time 21.89 seconds
Started Jan 24 08:48:56 PM PST 24
Finished Jan 24 08:49:19 PM PST 24
Peak memory 243928 kb
Host smart-7e83809b-4a7c-491f-a650-fba16da50a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644931484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2644931484
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1190428795
Short name T792
Test name
Test status
Simulation time 73857677 ps
CPU time 7.62 seconds
Started Jan 24 09:07:22 PM PST 24
Finished Jan 24 09:07:31 PM PST 24
Peak memory 251140 kb
Host smart-98b4fe52-47bf-42c2-a466-8933bde80246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190428795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1190428795
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.325031441
Short name T464
Test name
Test status
Simulation time 17902128561 ps
CPU time 88 seconds
Started Jan 24 08:49:12 PM PST 24
Finished Jan 24 08:50:44 PM PST 24
Peak memory 275176 kb
Host smart-f8c62f5f-e181-4173-b356-ace8be7067e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325031441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.325031441
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2208266726
Short name T864
Test name
Test status
Simulation time 24013718 ps
CPU time 0.92 seconds
Started Jan 24 08:48:54 PM PST 24
Finished Jan 24 08:48:56 PM PST 24
Peak memory 208128 kb
Host smart-8a61b018-ce7f-47b3-ac4c-cb9d3ad82701
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208266726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2208266726
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3135829804
Short name T777
Test name
Test status
Simulation time 23439045 ps
CPU time 1.04 seconds
Started Jan 24 08:49:16 PM PST 24
Finished Jan 24 08:49:18 PM PST 24
Peak memory 209452 kb
Host smart-a6d57b5b-9173-47f8-805e-ef0dec68bea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135829804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3135829804
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2127909092
Short name T841
Test name
Test status
Simulation time 1405242380 ps
CPU time 9.29 seconds
Started Jan 24 09:21:57 PM PST 24
Finished Jan 24 09:22:08 PM PST 24
Peak memory 218200 kb
Host smart-e58b7448-4bf4-4ad0-b527-e2125987c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127909092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2127909092
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2259241365
Short name T856
Test name
Test status
Simulation time 4671618683 ps
CPU time 12.62 seconds
Started Jan 24 09:06:58 PM PST 24
Finished Jan 24 09:07:16 PM PST 24
Peak memory 209588 kb
Host smart-e5032614-eeff-481e-8c12-b59e342948cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259241365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.2259241365
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.44117437
Short name T855
Test name
Test status
Simulation time 65732537 ps
CPU time 2.72 seconds
Started Jan 24 08:49:19 PM PST 24
Finished Jan 24 08:49:23 PM PST 24
Peak memory 218116 kb
Host smart-3893ac0f-4b86-4841-82a6-ed6101f60131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44117437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.44117437
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.302951771
Short name T449
Test name
Test status
Simulation time 779760641 ps
CPU time 21.77 seconds
Started Jan 24 08:49:19 PM PST 24
Finished Jan 24 08:49:42 PM PST 24
Peak memory 219136 kb
Host smart-5880d0c0-e0e7-4145-9604-daf1ec771fb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302951771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.302951771
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3950970525
Short name T424
Test name
Test status
Simulation time 350456050 ps
CPU time 13.8 seconds
Started Jan 24 08:49:17 PM PST 24
Finished Jan 24 08:49:32 PM PST 24
Peak memory 218128 kb
Host smart-009f9195-5e45-42db-ae63-793d3fa17e7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950970525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3950970525
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.458475506
Short name T579
Test name
Test status
Simulation time 1364081672 ps
CPU time 9.18 seconds
Started Jan 24 08:49:18 PM PST 24
Finished Jan 24 08:49:28 PM PST 24
Peak memory 218064 kb
Host smart-2855016c-ca46-40a3-a88d-ac145742d276
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458475506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.458475506
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.566717944
Short name T671
Test name
Test status
Simulation time 1038558566 ps
CPU time 10.27 seconds
Started Jan 24 08:49:15 PM PST 24
Finished Jan 24 08:49:26 PM PST 24
Peak memory 218096 kb
Host smart-b883162d-e204-4673-8edf-1fe1a0d51901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566717944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.566717944
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.4124050292
Short name T32
Test name
Test status
Simulation time 265760611 ps
CPU time 3.43 seconds
Started Jan 24 08:49:11 PM PST 24
Finished Jan 24 08:49:16 PM PST 24
Peak memory 214240 kb
Host smart-41e44577-d157-460c-aa1b-9ae3c6dad45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124050292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.4124050292
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3489937528
Short name T606
Test name
Test status
Simulation time 682401994 ps
CPU time 35.32 seconds
Started Jan 24 08:49:04 PM PST 24
Finished Jan 24 08:49:42 PM PST 24
Peak memory 251052 kb
Host smart-fde5c2d2-3034-4d79-8e1a-1f2cabcdcc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489937528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3489937528
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.823502805
Short name T301
Test name
Test status
Simulation time 622452400 ps
CPU time 2.99 seconds
Started Jan 24 08:49:17 PM PST 24
Finished Jan 24 08:49:21 PM PST 24
Peak memory 221640 kb
Host smart-313a04b9-e483-4e7f-a90d-570f43c5e234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823502805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.823502805
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2739388954
Short name T551
Test name
Test status
Simulation time 32298057803 ps
CPU time 105.01 seconds
Started Jan 24 08:49:19 PM PST 24
Finished Jan 24 08:51:06 PM PST 24
Peak memory 248176 kb
Host smart-c43b91b3-cbe4-4c9a-bda0-25c160467696
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739388954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2739388954
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.569626663
Short name T921
Test name
Test status
Simulation time 15566765 ps
CPU time 0.84 seconds
Started Jan 24 08:49:04 PM PST 24
Finished Jan 24 08:49:07 PM PST 24
Peak memory 208368 kb
Host smart-77142914-b516-49b7-971b-651212cd91f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569626663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.569626663
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2251116114
Short name T698
Test name
Test status
Simulation time 25920507 ps
CPU time 0.98 seconds
Started Jan 24 08:49:36 PM PST 24
Finished Jan 24 08:49:38 PM PST 24
Peak memory 208116 kb
Host smart-b4a0f459-e8a8-4ff4-8e60-0455ef6bc721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251116114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2251116114
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1543064180
Short name T369
Test name
Test status
Simulation time 323331659 ps
CPU time 11.35 seconds
Started Jan 24 08:49:27 PM PST 24
Finished Jan 24 08:49:40 PM PST 24
Peak memory 218112 kb
Host smart-65b8ca3f-c3a9-4da1-966a-892c4fd2ac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543064180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1543064180
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.248192381
Short name T853
Test name
Test status
Simulation time 348784954 ps
CPU time 9.21 seconds
Started Jan 24 08:49:25 PM PST 24
Finished Jan 24 08:49:36 PM PST 24
Peak memory 209520 kb
Host smart-3660b92e-d61f-4bc3-9dde-730a9e62395b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248192381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_ac
cess.248192381
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4178418679
Short name T539
Test name
Test status
Simulation time 140149736 ps
CPU time 2.03 seconds
Started Jan 24 08:49:25 PM PST 24
Finished Jan 24 08:49:28 PM PST 24
Peak memory 218104 kb
Host smart-760a166a-1476-4b50-b365-f034050b96b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178418679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4178418679
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1643120832
Short name T42
Test name
Test status
Simulation time 397318282 ps
CPU time 17.28 seconds
Started Jan 24 08:49:37 PM PST 24
Finished Jan 24 08:49:55 PM PST 24
Peak memory 218124 kb
Host smart-9bb8bcd0-bf93-4802-9217-b6421c5e5f9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643120832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1643120832
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2935260781
Short name T522
Test name
Test status
Simulation time 2504935016 ps
CPU time 15.46 seconds
Started Jan 24 08:49:40 PM PST 24
Finished Jan 24 08:49:56 PM PST 24
Peak memory 218160 kb
Host smart-7a8118b2-8483-43b0-8a68-b658dd407eb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935260781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2935260781
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1940119798
Short name T400
Test name
Test status
Simulation time 353304234 ps
CPU time 12.98 seconds
Started Jan 24 08:49:37 PM PST 24
Finished Jan 24 08:49:51 PM PST 24
Peak memory 218112 kb
Host smart-f33ccc19-5cbe-4c3d-ae2a-887a88c13eca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940119798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1940119798
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.710426245
Short name T421
Test name
Test status
Simulation time 433624978 ps
CPU time 15.52 seconds
Started Jan 24 08:49:26 PM PST 24
Finished Jan 24 08:49:43 PM PST 24
Peak memory 218064 kb
Host smart-babc32b6-91df-469d-9cf3-856ea93b0c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710426245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.710426245
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.637520968
Short name T71
Test name
Test status
Simulation time 117246967 ps
CPU time 2.53 seconds
Started Jan 24 08:49:19 PM PST 24
Finished Jan 24 08:49:23 PM PST 24
Peak memory 213920 kb
Host smart-631744d2-b87a-4326-afb1-dd5788f409bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637520968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.637520968
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.734775136
Short name T310
Test name
Test status
Simulation time 354388544 ps
CPU time 40.55 seconds
Started Jan 24 08:49:28 PM PST 24
Finished Jan 24 08:50:10 PM PST 24
Peak memory 251048 kb
Host smart-388f5c89-569d-4a28-b082-6fea61ddb30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734775136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.734775136
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1497605502
Short name T377
Test name
Test status
Simulation time 94727821 ps
CPU time 9.82 seconds
Started Jan 24 08:49:26 PM PST 24
Finished Jan 24 08:49:38 PM PST 24
Peak memory 251100 kb
Host smart-a1a6ec43-008b-4303-86d4-50e2768b2607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497605502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1497605502
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4079997204
Short name T741
Test name
Test status
Simulation time 2885920126 ps
CPU time 86.38 seconds
Started Jan 24 08:49:36 PM PST 24
Finished Jan 24 08:51:04 PM PST 24
Peak memory 245736 kb
Host smart-585899d4-74c1-4fea-bc41-0b386a311e19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079997204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4079997204
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1860430463
Short name T572
Test name
Test status
Simulation time 13161121 ps
CPU time 0.97 seconds
Started Jan 24 08:49:26 PM PST 24
Finished Jan 24 08:49:29 PM PST 24
Peak memory 212316 kb
Host smart-21b37bd6-9d0d-4938-8e22-ca853bee8b44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860430463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1860430463
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.669107780
Short name T357
Test name
Test status
Simulation time 17625836 ps
CPU time 0.93 seconds
Started Jan 24 08:49:56 PM PST 24
Finished Jan 24 08:49:58 PM PST 24
Peak memory 209500 kb
Host smart-0514c404-e03a-404b-86b8-83b623ff81ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669107780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.669107780
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2525521823
Short name T438
Test name
Test status
Simulation time 2407580996 ps
CPU time 10.34 seconds
Started Jan 24 08:49:46 PM PST 24
Finished Jan 24 08:50:02 PM PST 24
Peak memory 226316 kb
Host smart-f0543d4c-9537-4f4b-85f2-5428cfe01cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525521823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2525521823
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1168533957
Short name T338
Test name
Test status
Simulation time 532120253 ps
CPU time 13.56 seconds
Started Jan 24 08:49:45 PM PST 24
Finished Jan 24 08:50:03 PM PST 24
Peak memory 209508 kb
Host smart-90e18cfd-01db-43b6-8c82-5cf4c9c7a686
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168533957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.1168533957
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.246101408
Short name T337
Test name
Test status
Simulation time 18169775 ps
CPU time 1.78 seconds
Started Jan 24 08:49:46 PM PST 24
Finished Jan 24 08:49:53 PM PST 24
Peak memory 218128 kb
Host smart-213ad866-8b3b-40d2-8349-238d58688ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246101408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.246101408
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2983013679
Short name T365
Test name
Test status
Simulation time 1564007009 ps
CPU time 12.93 seconds
Started Jan 24 08:49:50 PM PST 24
Finished Jan 24 08:50:05 PM PST 24
Peak memory 218112 kb
Host smart-05be3837-5f21-49db-84ab-0e073f81d2a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983013679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2983013679
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.117553202
Short name T107
Test name
Test status
Simulation time 1383135803 ps
CPU time 24.36 seconds
Started Jan 24 08:49:48 PM PST 24
Finished Jan 24 08:50:16 PM PST 24
Peak memory 218104 kb
Host smart-cc45245c-070e-479b-818e-c66c9b25740c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117553202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.117553202
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3786691998
Short name T545
Test name
Test status
Simulation time 216384159 ps
CPU time 9.09 seconds
Started Jan 24 08:49:49 PM PST 24
Finished Jan 24 08:50:01 PM PST 24
Peak memory 217828 kb
Host smart-05e52fb6-16d1-468f-8e70-7b68a9ddf7db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786691998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3786691998
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3158975378
Short name T607
Test name
Test status
Simulation time 1184683925 ps
CPU time 7.31 seconds
Started Jan 24 08:49:50 PM PST 24
Finished Jan 24 08:49:59 PM PST 24
Peak memory 217604 kb
Host smart-4af41b08-8b84-4a20-ac6a-4df26491ef74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158975378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3158975378
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4086406937
Short name T442
Test name
Test status
Simulation time 68380551 ps
CPU time 2.76 seconds
Started Jan 24 08:49:37 PM PST 24
Finished Jan 24 08:49:41 PM PST 24
Peak memory 213876 kb
Host smart-403e0457-1d01-46a4-885a-36c4eea0dbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086406937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4086406937
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3680872167
Short name T305
Test name
Test status
Simulation time 514132741 ps
CPU time 21.82 seconds
Started Jan 24 08:49:37 PM PST 24
Finished Jan 24 08:50:00 PM PST 24
Peak memory 251040 kb
Host smart-dfacaa2d-c22e-4092-aeb4-f6148441ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680872167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3680872167
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.79774942
Short name T657
Test name
Test status
Simulation time 522110491 ps
CPU time 10.07 seconds
Started Jan 24 09:14:07 PM PST 24
Finished Jan 24 09:14:18 PM PST 24
Peak memory 251084 kb
Host smart-98f47f2a-5689-428b-a6dc-ad12e132c476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79774942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.79774942
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.744066052
Short name T719
Test name
Test status
Simulation time 36089403271 ps
CPU time 95.01 seconds
Started Jan 24 08:49:56 PM PST 24
Finished Jan 24 08:51:33 PM PST 24
Peak memory 272080 kb
Host smart-0b9dd658-3c47-499e-9410-f4ea1d4d22b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744066052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.744066052
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3905483257
Short name T655
Test name
Test status
Simulation time 12526726 ps
CPU time 0.87 seconds
Started Jan 24 08:49:37 PM PST 24
Finished Jan 24 08:49:39 PM PST 24
Peak memory 207888 kb
Host smart-6a18ae27-6d64-413b-9739-de88c48ef17d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905483257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3905483257
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3337304909
Short name T736
Test name
Test status
Simulation time 77506446 ps
CPU time 1.25 seconds
Started Jan 24 11:24:35 PM PST 24
Finished Jan 24 11:24:40 PM PST 24
Peak memory 209500 kb
Host smart-54f9891e-d152-4de1-ae21-d00bc8f77994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337304909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3337304909
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.432218840
Short name T905
Test name
Test status
Simulation time 1837037222 ps
CPU time 15.97 seconds
Started Jan 24 08:49:54 PM PST 24
Finished Jan 24 08:50:12 PM PST 24
Peak memory 218132 kb
Host smart-edb5222d-2d39-4057-87ec-7288d5f8d857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432218840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.432218840
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.721995840
Short name T7
Test name
Test status
Simulation time 1046046838 ps
CPU time 24.16 seconds
Started Jan 24 08:50:05 PM PST 24
Finished Jan 24 08:50:30 PM PST 24
Peak memory 209496 kb
Host smart-3b1922ca-0336-49d2-89f8-8972d767c02d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721995840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_ac
cess.721995840
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1736175555
Short name T822
Test name
Test status
Simulation time 170559835 ps
CPU time 2.5 seconds
Started Jan 24 08:49:55 PM PST 24
Finished Jan 24 08:49:59 PM PST 24
Peak memory 218088 kb
Host smart-2449ccb3-27af-411a-9263-78e6ed38725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736175555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1736175555
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1398173854
Short name T675
Test name
Test status
Simulation time 718550423 ps
CPU time 17.45 seconds
Started Jan 24 08:50:07 PM PST 24
Finished Jan 24 08:50:25 PM PST 24
Peak memory 218608 kb
Host smart-a121639f-f1ec-4b0f-9828-7df74bd06c28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398173854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1398173854
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.624828642
Short name T333
Test name
Test status
Simulation time 779376286 ps
CPU time 26.79 seconds
Started Jan 24 08:50:04 PM PST 24
Finished Jan 24 08:50:32 PM PST 24
Peak memory 218120 kb
Host smart-c7c05cf8-a2ae-41c4-b107-d11ca4a98bcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624828642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.624828642
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.217813220
Short name T507
Test name
Test status
Simulation time 226272714 ps
CPU time 8.97 seconds
Started Jan 24 08:50:04 PM PST 24
Finished Jan 24 08:50:14 PM PST 24
Peak memory 218092 kb
Host smart-f7abfa28-d0df-4399-b03b-83cd33b074aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217813220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.217813220
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.532589660
Short name T179
Test name
Test status
Simulation time 281308508 ps
CPU time 12.01 seconds
Started Jan 24 08:50:10 PM PST 24
Finished Jan 24 08:50:23 PM PST 24
Peak memory 218236 kb
Host smart-5cd7ef9a-a49a-48f0-8f2a-aaae89b1a853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532589660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.532589660
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1415787318
Short name T767
Test name
Test status
Simulation time 107369836 ps
CPU time 3.38 seconds
Started Jan 24 08:49:57 PM PST 24
Finished Jan 24 08:50:01 PM PST 24
Peak memory 214176 kb
Host smart-1c4409c5-e258-4986-975f-83486bcddfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415787318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1415787318
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3314378685
Short name T528
Test name
Test status
Simulation time 757156510 ps
CPU time 28.58 seconds
Started Jan 24 09:04:01 PM PST 24
Finished Jan 24 09:04:41 PM PST 24
Peak memory 251064 kb
Host smart-b0b4aaac-9db9-40ea-a697-cc630c6c3f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314378685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3314378685
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3183495180
Short name T12
Test name
Test status
Simulation time 160588050 ps
CPU time 7.61 seconds
Started Jan 24 10:19:11 PM PST 24
Finished Jan 24 10:19:19 PM PST 24
Peak memory 250296 kb
Host smart-a226d3df-4263-48bf-bf0e-c6b1397352ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183495180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3183495180
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3849337947
Short name T946
Test name
Test status
Simulation time 26472766546 ps
CPU time 270.02 seconds
Started Jan 24 08:50:15 PM PST 24
Finished Jan 24 08:54:46 PM PST 24
Peak memory 275756 kb
Host smart-3ded4274-db13-4499-bd5e-5d27710185b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849337947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3849337947
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2653084814
Short name T737
Test name
Test status
Simulation time 12429787 ps
CPU time 0.92 seconds
Started Jan 24 08:49:57 PM PST 24
Finished Jan 24 08:49:59 PM PST 24
Peak memory 208076 kb
Host smart-0fed878f-99f7-4f5a-8beb-386ed3b0b416
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653084814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2653084814
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1788480853
Short name T485
Test name
Test status
Simulation time 45838807 ps
CPU time 0.9 seconds
Started Jan 24 08:52:51 PM PST 24
Finished Jan 24 08:52:53 PM PST 24
Peak memory 209488 kb
Host smart-4163b9c1-7b79-419d-8425-5bf5062ca256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788480853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1788480853
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3840154583
Short name T407
Test name
Test status
Simulation time 17400454 ps
CPU time 0.97 seconds
Started Jan 24 09:33:23 PM PST 24
Finished Jan 24 09:33:25 PM PST 24
Peak memory 208156 kb
Host smart-c4dc5028-ead5-409c-b34a-8cc4498534e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840154583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3840154583
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3724441869
Short name T752
Test name
Test status
Simulation time 968121266 ps
CPU time 26.86 seconds
Started Jan 24 08:35:39 PM PST 24
Finished Jan 24 08:36:06 PM PST 24
Peak memory 218104 kb
Host smart-b611f732-c4d8-4af1-b6f0-c0e598b435cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724441869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3724441869
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3459598975
Short name T22
Test name
Test status
Simulation time 520378105 ps
CPU time 3.95 seconds
Started Jan 24 10:05:58 PM PST 24
Finished Jan 24 10:06:03 PM PST 24
Peak memory 209480 kb
Host smart-9d737440-cb5d-4a63-b4f5-c3e3c94abc8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459598975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ac
cess.3459598975
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2063645808
Short name T554
Test name
Test status
Simulation time 2667609921 ps
CPU time 21.93 seconds
Started Jan 24 08:36:03 PM PST 24
Finished Jan 24 08:36:25 PM PST 24
Peak memory 219120 kb
Host smart-9c146491-c9e5-4af7-8562-93048e7bccf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063645808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2063645808
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.976707896
Short name T566
Test name
Test status
Simulation time 47559976 ps
CPU time 1.9 seconds
Started Jan 24 08:41:22 PM PST 24
Finished Jan 24 08:41:25 PM PST 24
Peak memory 209624 kb
Host smart-cc7b05aa-331a-4420-af6d-34db2f3e87ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976707896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_p
riority.976707896
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4279274008
Short name T910
Test name
Test status
Simulation time 983953978 ps
CPU time 4.32 seconds
Started Jan 24 08:48:06 PM PST 24
Finished Jan 24 08:48:11 PM PST 24
Peak memory 218060 kb
Host smart-2a40c5cb-cca6-47a4-9032-158880c28fc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279274008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4279274008
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3312153817
Short name T324
Test name
Test status
Simulation time 1029205418 ps
CPU time 18.02 seconds
Started Jan 24 10:22:34 PM PST 24
Finished Jan 24 10:22:54 PM PST 24
Peak memory 213052 kb
Host smart-8b2ce07a-2d19-4e34-b263-b00ce122d1a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312153817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3312153817
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2286381956
Short name T327
Test name
Test status
Simulation time 416342596 ps
CPU time 3.49 seconds
Started Jan 24 08:52:48 PM PST 24
Finished Jan 24 08:52:55 PM PST 24
Peak memory 212868 kb
Host smart-0019f055-d0db-4882-aa9c-ddc4e7a254a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286381956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2286381956
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1445636117
Short name T116
Test name
Test status
Simulation time 6694319559 ps
CPU time 70.29 seconds
Started Jan 24 09:17:18 PM PST 24
Finished Jan 24 09:18:29 PM PST 24
Peak memory 275640 kb
Host smart-808fc1d4-3b8f-4957-ac07-b19f1298a888
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445636117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1445636117
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2146911868
Short name T652
Test name
Test status
Simulation time 726596105 ps
CPU time 15.23 seconds
Started Jan 24 08:35:57 PM PST 24
Finished Jan 24 08:36:13 PM PST 24
Peak memory 250616 kb
Host smart-d0ccb8f9-6b50-4364-ab24-3a45926d7757
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146911868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2146911868
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3970894465
Short name T520
Test name
Test status
Simulation time 61652515 ps
CPU time 3.16 seconds
Started Jan 24 08:35:39 PM PST 24
Finished Jan 24 08:35:43 PM PST 24
Peak memory 218108 kb
Host smart-20447c2b-eb75-46d7-9e28-f7a2cda6de5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970894465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3970894465
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1544742642
Short name T684
Test name
Test status
Simulation time 288963762 ps
CPU time 10.16 seconds
Started Jan 24 10:42:45 PM PST 24
Finished Jan 24 10:42:56 PM PST 24
Peak memory 214036 kb
Host smart-c263e8a5-9f79-45aa-84ec-3ac69181de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544742642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1544742642
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.981146286
Short name T104
Test name
Test status
Simulation time 887765201 ps
CPU time 36.88 seconds
Started Jan 24 08:45:03 PM PST 24
Finished Jan 24 08:45:43 PM PST 24
Peak memory 284196 kb
Host smart-0c07a6e5-0b91-407c-ac54-84e5a3b92cbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981146286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.981146286
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3020625355
Short name T109
Test name
Test status
Simulation time 251265854 ps
CPU time 10.51 seconds
Started Jan 24 08:36:11 PM PST 24
Finished Jan 24 08:36:22 PM PST 24
Peak memory 218104 kb
Host smart-560b7c27-2526-49b9-9f87-213d0df6ebbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020625355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3020625355
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1290712303
Short name T362
Test name
Test status
Simulation time 3202738926 ps
CPU time 15.12 seconds
Started Jan 24 10:17:33 PM PST 24
Finished Jan 24 10:17:50 PM PST 24
Peak memory 218184 kb
Host smart-8a20b711-5918-4eba-b222-4147c5f85f9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290712303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1290712303
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.371210515
Short name T319
Test name
Test status
Simulation time 855288930 ps
CPU time 7.67 seconds
Started Jan 24 08:36:13 PM PST 24
Finished Jan 24 08:36:21 PM PST 24
Peak memory 218124 kb
Host smart-6358d4f5-4577-4a91-80bf-6179bd4faf52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371210515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.371210515
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1532283175
Short name T849
Test name
Test status
Simulation time 619346633 ps
CPU time 13.25 seconds
Started Jan 24 08:35:51 PM PST 24
Finished Jan 24 08:36:04 PM PST 24
Peak memory 218108 kb
Host smart-b50ce973-4655-4ae7-b7a2-34f03e9279c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532283175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1532283175
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3310094413
Short name T824
Test name
Test status
Simulation time 41525981 ps
CPU time 1.56 seconds
Started Jan 24 08:35:30 PM PST 24
Finished Jan 24 08:35:32 PM PST 24
Peak memory 213152 kb
Host smart-48ba1b3d-1521-4c04-97ed-b5bb512d73a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310094413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3310094413
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.956283811
Short name T876
Test name
Test status
Simulation time 651003793 ps
CPU time 21.23 seconds
Started Jan 24 08:35:38 PM PST 24
Finished Jan 24 08:36:00 PM PST 24
Peak memory 251136 kb
Host smart-b24455a7-dc4a-4af3-919a-9a23a6c01cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956283811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.956283811
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3876857046
Short name T965
Test name
Test status
Simulation time 78091266 ps
CPU time 7.72 seconds
Started Jan 24 08:35:38 PM PST 24
Finished Jan 24 08:35:46 PM PST 24
Peak memory 250476 kb
Host smart-5eddcd91-d421-481e-ae85-dd6f7ceca3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876857046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3876857046
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4180732081
Short name T974
Test name
Test status
Simulation time 49042398341 ps
CPU time 330.75 seconds
Started Jan 24 08:36:11 PM PST 24
Finished Jan 24 08:41:43 PM PST 24
Peak memory 269500 kb
Host smart-37d71ebf-2a03-45ae-a85f-6f04e2e2ef2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180732081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4180732081
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.373173439
Short name T511
Test name
Test status
Simulation time 15082690 ps
CPU time 0.8 seconds
Started Jan 24 08:35:38 PM PST 24
Finished Jan 24 08:35:39 PM PST 24
Peak memory 208040 kb
Host smart-6c8a77d2-2b5a-415f-8543-332d874a6f4c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373173439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.373173439
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2262233673
Short name T790
Test name
Test status
Simulation time 26143046 ps
CPU time 0.93 seconds
Started Jan 24 08:50:42 PM PST 24
Finished Jan 24 08:50:44 PM PST 24
Peak memory 209340 kb
Host smart-56b458a3-ab86-4efa-8908-004d8354bac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262233673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2262233673
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4129211961
Short name T425
Test name
Test status
Simulation time 266559068 ps
CPU time 12.3 seconds
Started Jan 24 08:50:19 PM PST 24
Finished Jan 24 08:50:32 PM PST 24
Peak memory 218080 kb
Host smart-8f9276d0-a780-4b7d-8848-4accff48750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129211961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4129211961
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.599079144
Short name T641
Test name
Test status
Simulation time 396379831 ps
CPU time 7.24 seconds
Started Jan 24 09:04:15 PM PST 24
Finished Jan 24 09:04:30 PM PST 24
Peak memory 209520 kb
Host smart-05c6245d-f4cd-437d-a8ad-73d7de75e9ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599079144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_ac
cess.599079144
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3572966258
Short name T490
Test name
Test status
Simulation time 103366448 ps
CPU time 2.64 seconds
Started Jan 24 09:07:33 PM PST 24
Finished Jan 24 09:07:38 PM PST 24
Peak memory 218112 kb
Host smart-d83d67dd-2ec1-4cac-bc6b-defe98897c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572966258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3572966258
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3047992808
Short name T496
Test name
Test status
Simulation time 1531871064 ps
CPU time 19.59 seconds
Started Jan 24 09:30:40 PM PST 24
Finished Jan 24 09:31:02 PM PST 24
Peak memory 219164 kb
Host smart-d7791ded-3a1a-46b0-b502-bfc3dcf64fa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047992808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3047992808
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2155151511
Short name T694
Test name
Test status
Simulation time 1336052663 ps
CPU time 14.1 seconds
Started Jan 24 09:02:21 PM PST 24
Finished Jan 24 09:02:36 PM PST 24
Peak memory 218096 kb
Host smart-b5555e51-37dc-4353-b4d8-f9200d3b14b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155151511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2155151511
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1324557511
Short name T802
Test name
Test status
Simulation time 3630576197 ps
CPU time 9.83 seconds
Started Jan 25 03:35:18 AM PST 24
Finished Jan 25 03:35:28 AM PST 24
Peak memory 218176 kb
Host smart-2cc53468-37ca-45c0-910f-ca6c6c8ed1e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324557511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1324557511
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.777996493
Short name T955
Test name
Test status
Simulation time 1273671105 ps
CPU time 11.19 seconds
Started Jan 24 08:50:20 PM PST 24
Finished Jan 24 08:50:32 PM PST 24
Peak memory 218108 kb
Host smart-b9d98d0b-4233-4c32-ac4f-f93dad454ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777996493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.777996493
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3820681967
Short name T343
Test name
Test status
Simulation time 121776147 ps
CPU time 1.41 seconds
Started Jan 24 08:50:17 PM PST 24
Finished Jan 24 08:50:19 PM PST 24
Peak memory 217796 kb
Host smart-505404a7-268c-4188-8a00-d8c8979887bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820681967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3820681967
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3849624851
Short name T414
Test name
Test status
Simulation time 1559513636 ps
CPU time 32.02 seconds
Started Jan 24 09:02:21 PM PST 24
Finished Jan 24 09:02:53 PM PST 24
Peak memory 251060 kb
Host smart-c7b31987-2f6b-4d1a-9d24-5143b910b9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849624851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3849624851
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2527088639
Short name T180
Test name
Test status
Simulation time 488321592 ps
CPU time 7.47 seconds
Started Jan 25 12:01:04 AM PST 24
Finished Jan 25 12:01:18 AM PST 24
Peak memory 251104 kb
Host smart-1753d7ef-5171-490d-83cf-84d32dfd2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527088639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2527088639
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3218452220
Short name T11
Test name
Test status
Simulation time 22697135524 ps
CPU time 86.38 seconds
Started Jan 24 08:50:38 PM PST 24
Finished Jan 24 08:52:06 PM PST 24
Peak memory 242956 kb
Host smart-1d94734a-2a8f-4c84-9ffb-59e22ca12421
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218452220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3218452220
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.376573097
Short name T565
Test name
Test status
Simulation time 58774238 ps
CPU time 0.86 seconds
Started Jan 24 08:50:17 PM PST 24
Finished Jan 24 08:50:19 PM PST 24
Peak memory 211144 kb
Host smart-4f2fe154-0044-4f08-a9b8-f55ccff20e22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376573097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.376573097
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.974912140
Short name T875
Test name
Test status
Simulation time 21270837 ps
CPU time 1.09 seconds
Started Jan 24 08:50:54 PM PST 24
Finished Jan 24 08:50:55 PM PST 24
Peak memory 208216 kb
Host smart-0df4b376-dc47-4f8e-b268-22dc1b446ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974912140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.974912140
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1430316520
Short name T934
Test name
Test status
Simulation time 1371584603 ps
CPU time 18.49 seconds
Started Jan 24 08:50:37 PM PST 24
Finished Jan 24 08:50:57 PM PST 24
Peak memory 218112 kb
Host smart-9ae7b2fc-6890-40fe-a0fe-7a4ffac358a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430316520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1430316520
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2104619288
Short name T858
Test name
Test status
Simulation time 2945968676 ps
CPU time 17.29 seconds
Started Jan 24 08:50:38 PM PST 24
Finished Jan 24 08:50:57 PM PST 24
Peak memory 209580 kb
Host smart-688746f9-0e95-49c1-b11c-8f11fb7a122c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104619288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.2104619288
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2804982147
Short name T820
Test name
Test status
Simulation time 20196014 ps
CPU time 1.76 seconds
Started Jan 24 08:50:43 PM PST 24
Finished Jan 24 08:50:45 PM PST 24
Peak memory 218104 kb
Host smart-a418b59e-b410-4663-b650-4a9d757eeb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804982147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2804982147
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.4060961883
Short name T785
Test name
Test status
Simulation time 659859729 ps
CPU time 11.78 seconds
Started Jan 24 08:50:38 PM PST 24
Finished Jan 24 08:50:52 PM PST 24
Peak memory 218428 kb
Host smart-db9af2bf-9e26-407d-9fef-e85dfc9fdb9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060961883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.4060961883
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3740369422
Short name T39
Test name
Test status
Simulation time 1055073657 ps
CPU time 15.56 seconds
Started Jan 24 08:51:00 PM PST 24
Finished Jan 24 08:51:16 PM PST 24
Peak memory 218096 kb
Host smart-ea52e75d-37b4-469a-8d5e-da72ec2eead3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740369422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3740369422
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2316020949
Short name T644
Test name
Test status
Simulation time 1779046478 ps
CPU time 9.38 seconds
Started Jan 24 08:50:56 PM PST 24
Finished Jan 24 08:51:06 PM PST 24
Peak memory 218112 kb
Host smart-8b5a245b-646a-4cf6-ad44-c43006c2e4f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316020949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2316020949
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.524353859
Short name T906
Test name
Test status
Simulation time 733062208 ps
CPU time 8.95 seconds
Started Jan 24 08:50:39 PM PST 24
Finished Jan 24 08:50:49 PM PST 24
Peak memory 218116 kb
Host smart-0cfb3d90-ea3d-4577-beb1-38797f38b39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524353859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.524353859
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2717333794
Short name T384
Test name
Test status
Simulation time 78125974 ps
CPU time 2.08 seconds
Started Jan 24 08:50:42 PM PST 24
Finished Jan 24 08:50:45 PM PST 24
Peak memory 213680 kb
Host smart-2f7c10f0-9f85-49e1-849d-c2fb077daa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717333794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2717333794
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.615121587
Short name T710
Test name
Test status
Simulation time 440682985 ps
CPU time 21.44 seconds
Started Jan 24 08:50:38 PM PST 24
Finished Jan 24 08:51:01 PM PST 24
Peak memory 250992 kb
Host smart-7376b965-91c4-4c03-9bcc-19bf598a02ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615121587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.615121587
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2007232935
Short name T689
Test name
Test status
Simulation time 211513148 ps
CPU time 6.8 seconds
Started Jan 24 08:50:42 PM PST 24
Finished Jan 24 08:50:49 PM PST 24
Peak memory 246428 kb
Host smart-ed7003ad-e1e5-446c-a0b4-602cc2e0b97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007232935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2007232935
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2675827061
Short name T755
Test name
Test status
Simulation time 3125474685 ps
CPU time 84.62 seconds
Started Jan 24 08:50:52 PM PST 24
Finished Jan 24 08:52:17 PM PST 24
Peak memory 270040 kb
Host smart-a0cbb1cc-370a-4650-8d7e-b5fd68f21f97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675827061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2675827061
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2523210992
Short name T38
Test name
Test status
Simulation time 35719730 ps
CPU time 0.77 seconds
Started Jan 24 08:50:42 PM PST 24
Finished Jan 24 08:50:44 PM PST 24
Peak memory 208176 kb
Host smart-b5fd0124-84c0-465b-bbfa-3be12699a6f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523210992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2523210992
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1682676382
Short name T332
Test name
Test status
Simulation time 18517303 ps
CPU time 1.14 seconds
Started Jan 24 08:50:51 PM PST 24
Finished Jan 24 08:50:53 PM PST 24
Peak memory 209428 kb
Host smart-85fa2804-c6c9-49ae-871b-f0dffb12b128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682676382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1682676382
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2867020481
Short name T298
Test name
Test status
Simulation time 1377364272 ps
CPU time 11.81 seconds
Started Jan 24 08:51:02 PM PST 24
Finished Jan 24 08:51:15 PM PST 24
Peak memory 218088 kb
Host smart-1c67b26d-8d74-4a9f-94e4-87e32a2c36d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867020481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2867020481
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2927373142
Short name T773
Test name
Test status
Simulation time 792019863 ps
CPU time 3.38 seconds
Started Jan 24 08:50:58 PM PST 24
Finished Jan 24 08:51:02 PM PST 24
Peak memory 209516 kb
Host smart-3cf6f40f-d424-42cf-9df9-515f78f4f501
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927373142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.2927373142
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.263367739
Short name T699
Test name
Test status
Simulation time 110671162 ps
CPU time 3.48 seconds
Started Jan 24 08:50:54 PM PST 24
Finished Jan 24 08:50:58 PM PST 24
Peak memory 218176 kb
Host smart-5d412584-8279-4be8-8c22-245737df3b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263367739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.263367739
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4260905873
Short name T642
Test name
Test status
Simulation time 1713563490 ps
CPU time 13.28 seconds
Started Jan 24 08:51:03 PM PST 24
Finished Jan 24 08:51:18 PM PST 24
Peak memory 219128 kb
Host smart-f8247f16-4c3e-4405-a3aa-4e1d28f4a186
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260905873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4260905873
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1194753505
Short name T440
Test name
Test status
Simulation time 867617389 ps
CPU time 16.04 seconds
Started Jan 24 08:50:58 PM PST 24
Finished Jan 24 08:51:15 PM PST 24
Peak memory 218116 kb
Host smart-b9420c62-1025-4709-bc38-0bdbe9ab3532
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194753505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1194753505
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1425559442
Short name T942
Test name
Test status
Simulation time 1981118872 ps
CPU time 7.53 seconds
Started Jan 24 08:51:00 PM PST 24
Finished Jan 24 08:51:08 PM PST 24
Peak memory 218024 kb
Host smart-b7638d45-823f-4458-8194-63a63961ac2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425559442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1425559442
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1609659654
Short name T788
Test name
Test status
Simulation time 1479499826 ps
CPU time 9.57 seconds
Started Jan 24 08:50:57 PM PST 24
Finished Jan 24 08:51:07 PM PST 24
Peak memory 218116 kb
Host smart-92da5954-1fb9-447f-9e29-c5b5f274cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609659654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1609659654
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1777759371
Short name T69
Test name
Test status
Simulation time 1420264972 ps
CPU time 10.76 seconds
Started Jan 24 08:50:54 PM PST 24
Finished Jan 24 08:51:06 PM PST 24
Peak memory 213768 kb
Host smart-d224a98f-ad46-42b8-8aee-5e457e7217a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777759371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1777759371
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4195984550
Short name T878
Test name
Test status
Simulation time 224694402 ps
CPU time 29.57 seconds
Started Jan 24 08:50:58 PM PST 24
Finished Jan 24 08:51:29 PM PST 24
Peak memory 251084 kb
Host smart-a9bc770f-0f39-4cba-abdb-d137e4974d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195984550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4195984550
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.4205533296
Short name T382
Test name
Test status
Simulation time 79557994 ps
CPU time 9.78 seconds
Started Jan 24 08:50:54 PM PST 24
Finished Jan 24 08:51:04 PM PST 24
Peak memory 251092 kb
Host smart-006258c0-6291-45dc-bb4c-f7d751e05af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205533296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.4205533296
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1657020992
Short name T433
Test name
Test status
Simulation time 15058926995 ps
CPU time 152.14 seconds
Started Jan 24 08:50:50 PM PST 24
Finished Jan 24 08:53:23 PM PST 24
Peak memory 283888 kb
Host smart-9245da4f-48cb-4255-a7fe-59af18d6075c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657020992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1657020992
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3664329951
Short name T308
Test name
Test status
Simulation time 12122897 ps
CPU time 0.91 seconds
Started Jan 24 08:51:00 PM PST 24
Finished Jan 24 08:51:01 PM PST 24
Peak memory 207456 kb
Host smart-3e2dab23-54fd-4dcc-b88f-474236332f16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664329951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3664329951
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.390862932
Short name T835
Test name
Test status
Simulation time 44107432 ps
CPU time 0.87 seconds
Started Jan 24 08:51:18 PM PST 24
Finished Jan 24 08:51:20 PM PST 24
Peak memory 209332 kb
Host smart-cefd3656-e782-49ed-9e6f-d04f8c2befa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390862932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.390862932
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.620644335
Short name T925
Test name
Test status
Simulation time 1242208626 ps
CPU time 14.99 seconds
Started Jan 24 08:51:06 PM PST 24
Finished Jan 24 08:51:22 PM PST 24
Peak memory 218116 kb
Host smart-647ff8a3-1740-46fe-a6ab-7f5fa3f6c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620644335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.620644335
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2270167947
Short name T668
Test name
Test status
Simulation time 709984272 ps
CPU time 2.85 seconds
Started Jan 24 08:51:13 PM PST 24
Finished Jan 24 08:51:18 PM PST 24
Peak memory 209484 kb
Host smart-4efd967a-7b80-4c4b-aedd-e93c62af65d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270167947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.2270167947
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.999383282
Short name T416
Test name
Test status
Simulation time 241303198 ps
CPU time 3.49 seconds
Started Jan 24 08:51:06 PM PST 24
Finished Jan 24 08:51:10 PM PST 24
Peak memory 218128 kb
Host smart-e948cac6-9551-43f7-a406-50d12d774db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999383282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.999383282
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2846752304
Short name T811
Test name
Test status
Simulation time 1409219932 ps
CPU time 17.72 seconds
Started Jan 24 08:51:13 PM PST 24
Finished Jan 24 08:51:32 PM PST 24
Peak memory 218468 kb
Host smart-9b247816-50e3-47fd-8ab1-ffaadec35061
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846752304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2846752304
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4102144628
Short name T602
Test name
Test status
Simulation time 1238718475 ps
CPU time 29.83 seconds
Started Jan 24 08:51:07 PM PST 24
Finished Jan 24 08:51:38 PM PST 24
Peak memory 218092 kb
Host smart-15c35038-6f9e-4aad-92fd-5fe2d3b64ac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102144628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.4102144628
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3418700701
Short name T348
Test name
Test status
Simulation time 438327661 ps
CPU time 9.22 seconds
Started Jan 24 08:51:13 PM PST 24
Finished Jan 24 08:51:23 PM PST 24
Peak memory 218100 kb
Host smart-0326f3dd-a2c0-47c4-a0ba-d37fa3382566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418700701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3418700701
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1648728237
Short name T728
Test name
Test status
Simulation time 504512681 ps
CPU time 6.57 seconds
Started Jan 24 08:51:13 PM PST 24
Finished Jan 24 08:51:21 PM PST 24
Peak memory 218096 kb
Host smart-cb581861-7235-4d2b-a487-b44155be1d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648728237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1648728237
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.4245668500
Short name T940
Test name
Test status
Simulation time 19167694 ps
CPU time 1.51 seconds
Started Jan 24 08:50:58 PM PST 24
Finished Jan 24 08:51:01 PM PST 24
Peak memory 213268 kb
Host smart-bd6a879d-4526-4cf1-aeaf-9c40eade7ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245668500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.4245668500
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3415561944
Short name T510
Test name
Test status
Simulation time 192615448 ps
CPU time 26.52 seconds
Started Jan 24 08:51:10 PM PST 24
Finished Jan 24 08:51:37 PM PST 24
Peak memory 251060 kb
Host smart-ecde8025-cd84-4bef-b5b0-4e62e0a80cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415561944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3415561944
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2810183699
Short name T654
Test name
Test status
Simulation time 110505483 ps
CPU time 8.24 seconds
Started Jan 24 08:51:06 PM PST 24
Finished Jan 24 08:51:15 PM PST 24
Peak memory 251140 kb
Host smart-a0dbd53b-888a-4234-890e-98e7126acf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810183699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2810183699
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1042594498
Short name T813
Test name
Test status
Simulation time 2305072932 ps
CPU time 17.4 seconds
Started Jan 24 08:51:13 PM PST 24
Finished Jan 24 08:51:32 PM PST 24
Peak memory 249844 kb
Host smart-171b6567-c755-4a94-bb37-6c8c38eb25f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042594498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1042594498
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.258889828
Short name T702
Test name
Test status
Simulation time 31542406 ps
CPU time 0.75 seconds
Started Jan 24 08:51:08 PM PST 24
Finished Jan 24 08:51:09 PM PST 24
Peak memory 207720 kb
Host smart-a00755b6-90bc-49ee-aff4-60cffeb600fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258889828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.258889828
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.261027632
Short name T29
Test name
Test status
Simulation time 17709672 ps
CPU time 1.18 seconds
Started Jan 24 08:51:44 PM PST 24
Finished Jan 24 08:51:48 PM PST 24
Peak memory 208212 kb
Host smart-baecb39e-6557-4fb1-aa96-589b4a4b2cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261027632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.261027632
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.735034922
Short name T935
Test name
Test status
Simulation time 401567036 ps
CPU time 11.08 seconds
Started Jan 24 08:51:21 PM PST 24
Finished Jan 24 08:51:33 PM PST 24
Peak memory 218116 kb
Host smart-caffc27d-d34f-4102-a904-a3daac94026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735034922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.735034922
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.264700318
Short name T23
Test name
Test status
Simulation time 1547174719 ps
CPU time 8.57 seconds
Started Jan 24 08:51:37 PM PST 24
Finished Jan 24 08:51:46 PM PST 24
Peak memory 209520 kb
Host smart-d3d61339-31e6-43bf-9515-ed79428ef124
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264700318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_ac
cess.264700318
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2139482713
Short name T687
Test name
Test status
Simulation time 245277144 ps
CPU time 3.34 seconds
Started Jan 24 08:51:24 PM PST 24
Finished Jan 24 08:51:28 PM PST 24
Peak memory 218092 kb
Host smart-9fd5071f-ee29-47de-bca9-7b69ee069e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139482713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2139482713
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.4128144008
Short name T598
Test name
Test status
Simulation time 194167735 ps
CPU time 10.61 seconds
Started Jan 24 08:51:37 PM PST 24
Finished Jan 24 08:51:48 PM PST 24
Peak memory 219136 kb
Host smart-1314d1e9-1d0a-447b-be17-8c06933c5a64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128144008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4128144008
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2450463211
Short name T386
Test name
Test status
Simulation time 1453922795 ps
CPU time 12.51 seconds
Started Jan 24 08:51:32 PM PST 24
Finished Jan 24 08:51:46 PM PST 24
Peak memory 218100 kb
Host smart-8bb4a794-bab9-4cca-9a97-7e70f62e40f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450463211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2450463211
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3789619301
Short name T739
Test name
Test status
Simulation time 4813227009 ps
CPU time 20.1 seconds
Started Jan 24 08:51:33 PM PST 24
Finished Jan 24 08:51:54 PM PST 24
Peak memory 218176 kb
Host smart-9b0d38c4-cb03-4e10-a1f5-b63109c5b4e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789619301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3789619301
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2645052648
Short name T894
Test name
Test status
Simulation time 247841795 ps
CPU time 6.64 seconds
Started Jan 24 08:51:29 PM PST 24
Finished Jan 24 08:51:37 PM PST 24
Peak memory 218124 kb
Host smart-0f7f97fc-b96e-45e3-8d2a-8e74d9192ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645052648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2645052648
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.785882779
Short name T463
Test name
Test status
Simulation time 151800762 ps
CPU time 4.23 seconds
Started Jan 24 08:51:18 PM PST 24
Finished Jan 24 08:51:23 PM PST 24
Peak memory 214248 kb
Host smart-fe0ea431-3a20-457a-8794-85f3096336dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785882779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.785882779
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3530288351
Short name T959
Test name
Test status
Simulation time 1345803382 ps
CPU time 31.49 seconds
Started Jan 24 08:51:18 PM PST 24
Finished Jan 24 08:51:51 PM PST 24
Peak memory 251012 kb
Host smart-936defa3-75a4-4978-9ee7-905f5fa12caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530288351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3530288351
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.635127542
Short name T627
Test name
Test status
Simulation time 71334542 ps
CPU time 3.97 seconds
Started Jan 24 08:51:19 PM PST 24
Finished Jan 24 08:51:25 PM PST 24
Peak memory 218084 kb
Host smart-bbf386b9-80e7-47ee-9542-f8c6571516ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635127542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.635127542
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4157415015
Short name T613
Test name
Test status
Simulation time 705327290 ps
CPU time 20.13 seconds
Started Jan 24 08:51:32 PM PST 24
Finished Jan 24 08:51:53 PM PST 24
Peak memory 218120 kb
Host smart-517fc36e-bcbb-45f0-af10-ac358ceab8e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157415015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4157415015
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2998074420
Short name T899
Test name
Test status
Simulation time 32553193 ps
CPU time 0.85 seconds
Started Jan 24 08:51:20 PM PST 24
Finished Jan 24 08:51:22 PM PST 24
Peak memory 208156 kb
Host smart-8d292c2a-2ee2-49e6-82e7-82aec6fc4b55
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998074420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2998074420
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1560374933
Short name T359
Test name
Test status
Simulation time 18758668 ps
CPU time 0.92 seconds
Started Jan 24 08:51:59 PM PST 24
Finished Jan 24 08:52:05 PM PST 24
Peak memory 209496 kb
Host smart-a7384518-6373-4884-93dc-5253846379b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560374933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1560374933
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1546665121
Short name T561
Test name
Test status
Simulation time 416906283 ps
CPU time 17.83 seconds
Started Jan 24 08:51:43 PM PST 24
Finished Jan 24 08:52:01 PM PST 24
Peak memory 218128 kb
Host smart-03c99e62-672c-4af0-b848-c05dc4c2cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546665121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1546665121
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1762671688
Short name T361
Test name
Test status
Simulation time 1955236176 ps
CPU time 8.68 seconds
Started Jan 24 08:51:46 PM PST 24
Finished Jan 24 08:51:56 PM PST 24
Peak memory 209560 kb
Host smart-d3b4fb6d-2253-41d8-ac29-7cd1560120b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762671688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.1762671688
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.733778555
Short name T646
Test name
Test status
Simulation time 14439680 ps
CPU time 1.65 seconds
Started Jan 24 08:51:45 PM PST 24
Finished Jan 24 08:51:49 PM PST 24
Peak memory 218132 kb
Host smart-1a263dcb-708c-4934-b694-341d20ed9d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733778555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.733778555
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.182965393
Short name T830
Test name
Test status
Simulation time 1728412418 ps
CPU time 14.02 seconds
Started Jan 24 09:03:58 PM PST 24
Finished Jan 24 09:04:26 PM PST 24
Peak memory 218180 kb
Host smart-eab7bc9b-f20d-47eb-9402-c44ed9801a6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182965393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.182965393
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2677232578
Short name T725
Test name
Test status
Simulation time 803602282 ps
CPU time 8.04 seconds
Started Jan 24 08:51:45 PM PST 24
Finished Jan 24 08:51:55 PM PST 24
Peak memory 218104 kb
Host smart-76df9cff-3f19-4986-9f1b-f7d1d417d04f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677232578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2677232578
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4029739155
Short name T518
Test name
Test status
Simulation time 415931896 ps
CPU time 12.31 seconds
Started Jan 25 12:18:41 AM PST 24
Finished Jan 25 12:18:56 AM PST 24
Peak memory 218132 kb
Host smart-fd2acf13-297d-4929-ab4f-f2e65df0bbef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029739155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4029739155
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.966867175
Short name T966
Test name
Test status
Simulation time 698547649 ps
CPU time 12.59 seconds
Started Jan 24 09:05:16 PM PST 24
Finished Jan 24 09:05:29 PM PST 24
Peak memory 218132 kb
Host smart-dc9fc3ba-0d7d-4fa5-b3a9-5ed8bde8c4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966867175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.966867175
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.745677471
Short name T783
Test name
Test status
Simulation time 49417380 ps
CPU time 1.37 seconds
Started Jan 24 08:51:46 PM PST 24
Finished Jan 24 08:51:57 PM PST 24
Peak memory 213072 kb
Host smart-c18e4eae-fe19-425c-89cf-74ad08ea46c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745677471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.745677471
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2912462723
Short name T778
Test name
Test status
Simulation time 3947537883 ps
CPU time 21.78 seconds
Started Jan 24 09:03:25 PM PST 24
Finished Jan 24 09:03:47 PM PST 24
Peak memory 251104 kb
Host smart-d233e41a-4bed-423a-88a4-a05b52bc88ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912462723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2912462723
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.748880118
Short name T455
Test name
Test status
Simulation time 85596171 ps
CPU time 6.84 seconds
Started Jan 24 08:51:45 PM PST 24
Finished Jan 24 08:51:54 PM PST 24
Peak memory 247820 kb
Host smart-e9392b95-354c-4d99-b14c-9558d7868027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748880118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.748880118
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.265962852
Short name T21
Test name
Test status
Simulation time 3714346179 ps
CPU time 140.63 seconds
Started Jan 24 08:52:03 PM PST 24
Finished Jan 24 08:54:26 PM PST 24
Peak memory 275764 kb
Host smart-a0cab0bc-3534-4dea-9abc-54ed8580f2ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265962852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.265962852
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3611385619
Short name T594
Test name
Test status
Simulation time 11375573 ps
CPU time 0.92 seconds
Started Jan 24 09:12:15 PM PST 24
Finished Jan 24 09:12:17 PM PST 24
Peak memory 208160 kb
Host smart-a98fff4b-1fce-4660-8291-c05052a012ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611385619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3611385619
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1258040885
Short name T75
Test name
Test status
Simulation time 42152438 ps
CPU time 0.85 seconds
Started Jan 24 08:52:16 PM PST 24
Finished Jan 24 08:52:18 PM PST 24
Peak memory 207872 kb
Host smart-476efa78-e725-4009-83b1-c3f5a0c99a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258040885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1258040885
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2519923567
Short name T509
Test name
Test status
Simulation time 1469133818 ps
CPU time 16.83 seconds
Started Jan 24 08:51:57 PM PST 24
Finished Jan 24 08:52:20 PM PST 24
Peak memory 218112 kb
Host smart-d2f5379c-53a8-4b2c-b41d-ad10ca10a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519923567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2519923567
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.881674895
Short name T567
Test name
Test status
Simulation time 80903568 ps
CPU time 2.9 seconds
Started Jan 24 08:52:02 PM PST 24
Finished Jan 24 08:52:07 PM PST 24
Peak memory 209480 kb
Host smart-92e90573-4622-4956-8898-c8c223bb160c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881674895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_ac
cess.881674895
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1752377624
Short name T926
Test name
Test status
Simulation time 99781300 ps
CPU time 2.58 seconds
Started Jan 24 08:51:59 PM PST 24
Finished Jan 24 08:52:06 PM PST 24
Peak memory 218144 kb
Host smart-0c7e5e27-d5d7-4eba-8bd0-bac3ff08bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752377624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1752377624
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3187786275
Short name T360
Test name
Test status
Simulation time 647568576 ps
CPU time 11.98 seconds
Started Jan 24 08:52:04 PM PST 24
Finished Jan 24 08:52:18 PM PST 24
Peak memory 218096 kb
Host smart-03d936dc-2a11-42f1-8438-d498d74b31ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187786275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3187786275
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1081306437
Short name T491
Test name
Test status
Simulation time 1798510201 ps
CPU time 12.79 seconds
Started Jan 24 09:12:31 PM PST 24
Finished Jan 24 09:12:45 PM PST 24
Peak memory 218104 kb
Host smart-8c71f667-d0f9-429f-b909-2f8ccbebad9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081306437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1081306437
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2242098549
Short name T896
Test name
Test status
Simulation time 1518327519 ps
CPU time 7.31 seconds
Started Jan 24 08:51:59 PM PST 24
Finished Jan 24 08:52:11 PM PST 24
Peak memory 218152 kb
Host smart-a36ca01c-9d06-4b7c-ab1e-4b619a0256c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242098549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2242098549
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3050584082
Short name T724
Test name
Test status
Simulation time 1547092985 ps
CPU time 10.19 seconds
Started Jan 24 08:52:04 PM PST 24
Finished Jan 24 08:52:16 PM PST 24
Peak memory 218168 kb
Host smart-4cd31bb4-15eb-421d-b7fa-cc1beae727e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050584082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3050584082
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2420213336
Short name T302
Test name
Test status
Simulation time 152908679 ps
CPU time 4.23 seconds
Started Jan 24 08:52:01 PM PST 24
Finished Jan 24 08:52:09 PM PST 24
Peak memory 213664 kb
Host smart-b7144809-025a-4c34-9dd5-2dc22db814ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420213336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2420213336
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3843952124
Short name T431
Test name
Test status
Simulation time 1565424276 ps
CPU time 31.77 seconds
Started Jan 24 08:52:02 PM PST 24
Finished Jan 24 08:52:36 PM PST 24
Peak memory 251040 kb
Host smart-b29d3971-71a6-4eb3-8595-e17de64b21f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843952124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3843952124
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2817890399
Short name T701
Test name
Test status
Simulation time 276450962 ps
CPU time 9.49 seconds
Started Jan 24 08:51:57 PM PST 24
Finished Jan 24 08:52:13 PM PST 24
Peak memory 251168 kb
Host smart-c89c4d0f-7959-404d-9d9d-f8d2ec05bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817890399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2817890399
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1263619127
Short name T589
Test name
Test status
Simulation time 5994597651 ps
CPU time 74.96 seconds
Started Jan 24 08:51:59 PM PST 24
Finished Jan 24 08:53:19 PM PST 24
Peak memory 248608 kb
Host smart-bbe45dee-ecd8-4148-83d3-9e0cf55729d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263619127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1263619127
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1656146780
Short name T474
Test name
Test status
Simulation time 21357959 ps
CPU time 0.93 seconds
Started Jan 24 09:13:01 PM PST 24
Finished Jan 24 09:13:05 PM PST 24
Peak memory 211292 kb
Host smart-e095f1ea-2492-4846-a17f-a064ec902c9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656146780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1656146780
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.868348273
Short name T453
Test name
Test status
Simulation time 63103848 ps
CPU time 0.9 seconds
Started Jan 24 10:59:09 PM PST 24
Finished Jan 24 10:59:10 PM PST 24
Peak memory 209504 kb
Host smart-5e00656a-99ed-491a-b4d5-802d595fff9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868348273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.868348273
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.4180986838
Short name T947
Test name
Test status
Simulation time 372624915 ps
CPU time 16.59 seconds
Started Jan 24 08:52:20 PM PST 24
Finished Jan 24 08:52:37 PM PST 24
Peak memory 218096 kb
Host smart-dbe54e0f-950f-40d1-a003-0c004ddc9728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180986838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.4180986838
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1290261273
Short name T547
Test name
Test status
Simulation time 308546757 ps
CPU time 2.95 seconds
Started Jan 24 08:52:15 PM PST 24
Finished Jan 24 08:52:19 PM PST 24
Peak memory 218112 kb
Host smart-352caf00-ced4-498a-9750-6ec455b8275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290261273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1290261273
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.616620986
Short name T50
Test name
Test status
Simulation time 1804737920 ps
CPU time 14.64 seconds
Started Jan 24 08:52:16 PM PST 24
Finished Jan 24 08:52:32 PM PST 24
Peak memory 218112 kb
Host smart-38c1583e-5766-4829-8bc3-fc752f1455d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616620986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.616620986
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2112727450
Short name T326
Test name
Test status
Simulation time 214148618 ps
CPU time 7.66 seconds
Started Jan 24 10:02:57 PM PST 24
Finished Jan 24 10:03:05 PM PST 24
Peak memory 218144 kb
Host smart-19435599-d1c3-4ce3-97e4-95ca1c8263b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112727450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2112727450
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3508761414
Short name T311
Test name
Test status
Simulation time 646692775 ps
CPU time 9.54 seconds
Started Jan 24 09:02:33 PM PST 24
Finished Jan 24 09:02:43 PM PST 24
Peak memory 218116 kb
Host smart-3cd790ee-7bc6-4f7c-b5eb-09745bca5d45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508761414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3508761414
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3637174441
Short name T883
Test name
Test status
Simulation time 526857355 ps
CPU time 11.6 seconds
Started Jan 24 08:52:17 PM PST 24
Finished Jan 24 08:52:30 PM PST 24
Peak memory 218120 kb
Host smart-0691c952-9417-4331-a10c-2c8e747580e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637174441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3637174441
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1437371051
Short name T617
Test name
Test status
Simulation time 364096240 ps
CPU time 3.87 seconds
Started Jan 24 08:52:16 PM PST 24
Finished Jan 24 08:52:21 PM PST 24
Peak memory 214004 kb
Host smart-88db9656-2cda-4dd4-b823-f8f0156ed731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437371051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1437371051
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.101634138
Short name T521
Test name
Test status
Simulation time 287865195 ps
CPU time 28.89 seconds
Started Jan 24 08:52:17 PM PST 24
Finished Jan 24 08:52:47 PM PST 24
Peak memory 251052 kb
Host smart-2151e0ac-3cf3-4647-acdb-c24080cc3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101634138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.101634138
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.4150718156
Short name T836
Test name
Test status
Simulation time 387701733 ps
CPU time 6.15 seconds
Started Jan 24 11:24:31 PM PST 24
Finished Jan 24 11:24:39 PM PST 24
Peak memory 246292 kb
Host smart-8a748895-603f-4a31-8b5f-1d99719037fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150718156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4150718156
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3541619454
Short name T948
Test name
Test status
Simulation time 27426676487 ps
CPU time 132.28 seconds
Started Jan 24 08:52:17 PM PST 24
Finished Jan 24 08:54:30 PM PST 24
Peak memory 261308 kb
Host smart-6305c7cb-ddfe-4823-8fd2-f64422303fe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541619454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3541619454
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1413325998
Short name T720
Test name
Test status
Simulation time 19628134 ps
CPU time 0.78 seconds
Started Jan 24 08:52:21 PM PST 24
Finished Jan 24 08:52:22 PM PST 24
Peak memory 207720 kb
Host smart-5e5b8ec8-b94b-4e8b-9799-7052a92fdf67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413325998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1413325998
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2104057195
Short name T530
Test name
Test status
Simulation time 72733031 ps
CPU time 1.02 seconds
Started Jan 24 08:52:58 PM PST 24
Finished Jan 24 08:53:00 PM PST 24
Peak memory 208136 kb
Host smart-c70ab9a2-4031-4639-8b56-930e396ae862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104057195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2104057195
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2085152601
Short name T838
Test name
Test status
Simulation time 3223459511 ps
CPU time 7.57 seconds
Started Jan 24 09:05:17 PM PST 24
Finished Jan 24 09:05:25 PM PST 24
Peak memory 218168 kb
Host smart-35144813-7f13-4819-918c-2d9eb22adba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085152601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2085152601
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2790059230
Short name T6
Test name
Test status
Simulation time 953859701 ps
CPU time 11.49 seconds
Started Jan 24 10:46:37 PM PST 24
Finished Jan 24 10:46:54 PM PST 24
Peak memory 209536 kb
Host smart-6a4f2ed3-767e-47f3-8833-8bbeb0043ddc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790059230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.2790059230
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2918388726
Short name T803
Test name
Test status
Simulation time 284034886 ps
CPU time 3.19 seconds
Started Jan 24 09:48:58 PM PST 24
Finished Jan 24 09:49:02 PM PST 24
Peak memory 218112 kb
Host smart-6cc46df7-e261-4d3a-9150-034697b30b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918388726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2918388726
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.4065699845
Short name T299
Test name
Test status
Simulation time 1208724354 ps
CPU time 14.6 seconds
Started Jan 25 01:24:21 AM PST 24
Finished Jan 25 01:24:38 AM PST 24
Peak memory 218124 kb
Host smart-2730df85-5c4b-4d04-8e26-43830cfe3db7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065699845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.4065699845
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.934851557
Short name T735
Test name
Test status
Simulation time 4524569541 ps
CPU time 27.62 seconds
Started Jan 24 08:52:43 PM PST 24
Finished Jan 24 08:53:14 PM PST 24
Peak memory 218284 kb
Host smart-602dd60f-7286-45cb-9c43-e32d041ced1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934851557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.934851557
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2900466460
Short name T451
Test name
Test status
Simulation time 1232989065 ps
CPU time 9.28 seconds
Started Jan 24 08:52:43 PM PST 24
Finished Jan 24 08:52:55 PM PST 24
Peak memory 218132 kb
Host smart-91328bc4-41f0-4b4a-81e8-e5a3a718b815
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900466460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2900466460
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2144704253
Short name T900
Test name
Test status
Simulation time 446609725 ps
CPU time 2.99 seconds
Started Jan 24 08:52:25 PM PST 24
Finished Jan 24 08:52:29 PM PST 24
Peak memory 213952 kb
Host smart-3ede7d3c-06fc-47bf-a320-e437b42c582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144704253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2144704253
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.821738809
Short name T335
Test name
Test status
Simulation time 1755049757 ps
CPU time 29.85 seconds
Started Jan 24 09:07:49 PM PST 24
Finished Jan 24 09:08:21 PM PST 24
Peak memory 251076 kb
Host smart-de6ac219-deba-4c8b-aa69-5f46635aa475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821738809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.821738809
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.706669481
Short name T969
Test name
Test status
Simulation time 135278161 ps
CPU time 9.11 seconds
Started Jan 24 09:13:01 PM PST 24
Finished Jan 24 09:13:13 PM PST 24
Peak memory 251124 kb
Host smart-1604d87f-92ef-4d59-bcdb-bf66a24fd905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706669481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.706669481
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1655310154
Short name T399
Test name
Test status
Simulation time 4090480113 ps
CPU time 158.1 seconds
Started Jan 24 08:52:48 PM PST 24
Finished Jan 24 08:55:30 PM PST 24
Peak memory 283964 kb
Host smart-0f9ca540-18f3-4634-8f7c-d9c392d269b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655310154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1655310154
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.50054374
Short name T962
Test name
Test status
Simulation time 84226374 ps
CPU time 0.88 seconds
Started Jan 24 08:52:24 PM PST 24
Finished Jan 24 08:52:26 PM PST 24
Peak memory 211192 kb
Host smart-fea42a5e-3fb8-4a3a-a121-595b7d577fda
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50054374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctr
l_volatile_unlock_smoke.50054374
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.717059201
Short name T691
Test name
Test status
Simulation time 85573581 ps
CPU time 1.2 seconds
Started Jan 24 08:53:04 PM PST 24
Finished Jan 24 08:53:06 PM PST 24
Peak memory 209480 kb
Host smart-c626689a-5b64-4d65-96f0-2b19ba0dcc8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717059201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.717059201
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3783561366
Short name T355
Test name
Test status
Simulation time 3645863549 ps
CPU time 11.48 seconds
Started Jan 24 08:52:57 PM PST 24
Finished Jan 24 08:53:10 PM PST 24
Peak memory 218180 kb
Host smart-f838df8b-8624-4ff2-a2af-ecfecfaf3f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783561366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3783561366
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3546099858
Short name T843
Test name
Test status
Simulation time 2863496764 ps
CPU time 7.42 seconds
Started Jan 24 08:52:58 PM PST 24
Finished Jan 24 08:53:07 PM PST 24
Peak memory 209584 kb
Host smart-121c930d-d187-48f8-93d5-f37747590f54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546099858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_a
ccess.3546099858
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2368244646
Short name T723
Test name
Test status
Simulation time 31009425 ps
CPU time 1.57 seconds
Started Jan 24 08:52:57 PM PST 24
Finished Jan 24 08:53:00 PM PST 24
Peak memory 218100 kb
Host smart-d0e8a161-2303-448b-8629-bed58465af71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368244646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2368244646
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2962084436
Short name T533
Test name
Test status
Simulation time 2721897001 ps
CPU time 16.21 seconds
Started Jan 24 08:53:00 PM PST 24
Finished Jan 24 08:53:18 PM PST 24
Peak memory 218172 kb
Host smart-ffadfca3-7ce0-45d2-822c-9185e9ff686b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962084436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2962084436
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3253988202
Short name T534
Test name
Test status
Simulation time 376541982 ps
CPU time 12.34 seconds
Started Jan 24 08:53:00 PM PST 24
Finished Jan 24 08:53:14 PM PST 24
Peak memory 218120 kb
Host smart-67b832f4-d914-4eeb-a8c1-2ee857294ebc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253988202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3253988202
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2085712913
Short name T340
Test name
Test status
Simulation time 1088925308 ps
CPU time 9.96 seconds
Started Jan 24 08:52:57 PM PST 24
Finished Jan 24 08:53:07 PM PST 24
Peak memory 218120 kb
Host smart-c7c7d172-8caa-43eb-bc64-72dbbf84ed32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085712913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2085712913
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1523443970
Short name T897
Test name
Test status
Simulation time 457773418 ps
CPU time 9.62 seconds
Started Jan 24 08:52:56 PM PST 24
Finished Jan 24 08:53:07 PM PST 24
Peak memory 218120 kb
Host smart-f43867b6-c04a-4321-b9ca-98e9736ab4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523443970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1523443970
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.396032756
Short name T411
Test name
Test status
Simulation time 62939439 ps
CPU time 2.71 seconds
Started Jan 24 08:52:55 PM PST 24
Finished Jan 24 08:52:59 PM PST 24
Peak memory 213976 kb
Host smart-a02677ec-c63d-4a26-9a84-d84b86536fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396032756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.396032756
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3367752325
Short name T503
Test name
Test status
Simulation time 377664713 ps
CPU time 18.46 seconds
Started Jan 24 08:52:57 PM PST 24
Finished Jan 24 08:53:17 PM PST 24
Peak memory 251004 kb
Host smart-aed3e56b-2aca-4aeb-ace5-58395335de05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367752325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3367752325
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1963065860
Short name T293
Test name
Test status
Simulation time 273012247 ps
CPU time 9.39 seconds
Started Jan 24 08:52:54 PM PST 24
Finished Jan 24 08:53:05 PM PST 24
Peak memory 251104 kb
Host smart-004d275a-c4e2-45dc-852c-78c884327fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963065860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1963065860
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.569247268
Short name T670
Test name
Test status
Simulation time 5534954216 ps
CPU time 99.66 seconds
Started Jan 24 09:07:43 PM PST 24
Finished Jan 24 09:09:24 PM PST 24
Peak memory 283956 kb
Host smart-2669f897-6984-4d8d-a68a-ddcbb76e8f95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569247268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.569247268
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2330288111
Short name T389
Test name
Test status
Simulation time 20650150 ps
CPU time 0.85 seconds
Started Jan 24 08:52:54 PM PST 24
Finished Jan 24 08:52:56 PM PST 24
Peak memory 208100 kb
Host smart-c49b81bc-2851-4792-91a8-2fc585bbc2a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330288111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2330288111
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2712291975
Short name T612
Test name
Test status
Simulation time 42630759 ps
CPU time 0.98 seconds
Started Jan 24 08:37:09 PM PST 24
Finished Jan 24 08:37:12 PM PST 24
Peak memory 208148 kb
Host smart-e56184c0-ba3b-4816-8e38-1ce00ce4c2dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712291975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2712291975
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.189138550
Short name T174
Test name
Test status
Simulation time 20804340 ps
CPU time 0.79 seconds
Started Jan 24 08:36:38 PM PST 24
Finished Jan 24 08:36:39 PM PST 24
Peak memory 207984 kb
Host smart-3e74370a-7928-40c0-b150-ecfa5941c7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189138550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.189138550
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.718668225
Short name T660
Test name
Test status
Simulation time 571230970 ps
CPU time 11.73 seconds
Started Jan 24 08:36:32 PM PST 24
Finished Jan 24 08:36:45 PM PST 24
Peak memory 218064 kb
Host smart-23feb8ce-66b8-47d8-8bb4-b571eb4e639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718668225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.718668225
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2488314591
Short name T102
Test name
Test status
Simulation time 225564322 ps
CPU time 1.35 seconds
Started Jan 24 08:36:59 PM PST 24
Finished Jan 24 08:37:02 PM PST 24
Peak memory 209488 kb
Host smart-c319fd23-9bd8-491e-9ee5-3b9505b694a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488314591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ac
cess.2488314591
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.20007483
Short name T460
Test name
Test status
Simulation time 1103076820 ps
CPU time 18.37 seconds
Started Jan 24 08:36:55 PM PST 24
Finished Jan 24 08:37:14 PM PST 24
Peak memory 218044 kb
Host smart-45c5a320-0ddf-4bc1-8433-3386a82c859d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20007483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_erro
rs.20007483
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2327613452
Short name T316
Test name
Test status
Simulation time 335287042 ps
CPU time 8.58 seconds
Started Jan 24 09:01:28 PM PST 24
Finished Jan 24 09:01:38 PM PST 24
Peak memory 217780 kb
Host smart-a1b5a381-1ef6-4246-999b-b94fc4da8a7d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327613452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.2327613452
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.11466139
Short name T700
Test name
Test status
Simulation time 106873055 ps
CPU time 4.12 seconds
Started Jan 24 08:36:52 PM PST 24
Finished Jan 24 08:36:59 PM PST 24
Peak memory 218052 kb
Host smart-16901ae5-eca3-4142-90d5-d2f1583dbe1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11466139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_p
rog_failure.11466139
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1071056749
Short name T54
Test name
Test status
Simulation time 3727856466 ps
CPU time 14.93 seconds
Started Jan 24 08:50:24 PM PST 24
Finished Jan 24 08:50:40 PM PST 24
Peak memory 213648 kb
Host smart-ccc37839-dad5-4e9c-b5bf-eafa7c6911a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071056749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1071056749
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4131450444
Short name T904
Test name
Test status
Simulation time 322838908 ps
CPU time 4.81 seconds
Started Jan 24 10:20:48 PM PST 24
Finished Jan 24 10:20:54 PM PST 24
Peak memory 212852 kb
Host smart-d166423c-7f8f-4ea7-aa3c-11da6c12c1f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131450444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
4131450444
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1783173297
Short name T538
Test name
Test status
Simulation time 2404596972 ps
CPU time 52.4 seconds
Started Jan 24 08:36:49 PM PST 24
Finished Jan 24 08:37:44 PM PST 24
Peak memory 280528 kb
Host smart-1ac8e7e4-7ebd-47eb-b1db-e6d3444e7bf4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783173297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1783173297
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2755601500
Short name T517
Test name
Test status
Simulation time 1962400275 ps
CPU time 19.26 seconds
Started Jan 24 09:09:39 PM PST 24
Finished Jan 24 09:09:59 PM PST 24
Peak memory 251060 kb
Host smart-1e5ad723-3779-4f6d-96d3-c3d43f215564
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755601500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2755601500
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3492175416
Short name T373
Test name
Test status
Simulation time 61862000 ps
CPU time 1.75 seconds
Started Jan 24 08:36:21 PM PST 24
Finished Jan 24 08:36:23 PM PST 24
Peak memory 218072 kb
Host smart-db0e8ea8-7c3e-4876-9e1a-9f497cb06ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492175416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3492175416
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1571331980
Short name T683
Test name
Test status
Simulation time 4785150674 ps
CPU time 19.44 seconds
Started Jan 24 08:36:28 PM PST 24
Finished Jan 24 08:36:48 PM PST 24
Peak memory 214628 kb
Host smart-ab603731-507e-4286-8829-efdda74227fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571331980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1571331980
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2993949807
Short name T351
Test name
Test status
Simulation time 1440822509 ps
CPU time 11.04 seconds
Started Jan 24 08:41:19 PM PST 24
Finished Jan 24 08:41:30 PM PST 24
Peak memory 218076 kb
Host smart-c30c4987-6660-4ca5-acde-45880955f4e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993949807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2993949807
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1424902359
Short name T929
Test name
Test status
Simulation time 876830426 ps
CPU time 8.52 seconds
Started Jan 24 08:56:57 PM PST 24
Finished Jan 24 08:57:07 PM PST 24
Peak memory 218116 kb
Host smart-93a1a77c-8311-4dcb-8802-d3d4d93e7839
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424902359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1424902359
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.4141541890
Short name T964
Test name
Test status
Simulation time 377988935 ps
CPU time 10.75 seconds
Started Jan 24 09:20:14 PM PST 24
Finished Jan 24 09:20:26 PM PST 24
Peak memory 218188 kb
Host smart-84f8f0fd-2e6f-4a35-8dd7-f4e7edcf587e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141541890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.4
141541890
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.508873352
Short name T488
Test name
Test status
Simulation time 302472195 ps
CPU time 8.09 seconds
Started Jan 24 08:36:32 PM PST 24
Finished Jan 24 08:36:40 PM PST 24
Peak memory 218108 kb
Host smart-7c357cee-9468-43ec-9c7d-a7efd50ff728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508873352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.508873352
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2402028960
Short name T61
Test name
Test status
Simulation time 153373590 ps
CPU time 2.19 seconds
Started Jan 24 08:36:21 PM PST 24
Finished Jan 24 08:36:24 PM PST 24
Peak memory 213676 kb
Host smart-b9e80e94-c5a6-42cf-afa0-73e202dece80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402028960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2402028960
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.219855858
Short name T857
Test name
Test status
Simulation time 867366187 ps
CPU time 29.25 seconds
Started Jan 24 08:36:22 PM PST 24
Finished Jan 24 08:36:52 PM PST 24
Peak memory 251032 kb
Host smart-67e542f4-d96e-4786-a640-74d955fc107a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219855858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.219855858
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3984863216
Short name T430
Test name
Test status
Simulation time 46623764 ps
CPU time 7.51 seconds
Started Jan 24 08:36:25 PM PST 24
Finished Jan 24 08:36:33 PM PST 24
Peak memory 251092 kb
Host smart-468e7f41-04db-4e10-bd2e-424b654d9335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984863216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3984863216
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1549548680
Short name T949
Test name
Test status
Simulation time 1019528248 ps
CPU time 34.15 seconds
Started Jan 24 08:37:05 PM PST 24
Finished Jan 24 08:37:44 PM PST 24
Peak memory 226296 kb
Host smart-9bc443ea-e0dd-4050-973e-96b30dd5ad70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549548680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1549548680
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3053119540
Short name T10
Test name
Test status
Simulation time 17037798 ps
CPU time 0.71 seconds
Started Jan 24 08:54:07 PM PST 24
Finished Jan 24 08:54:09 PM PST 24
Peak memory 206376 kb
Host smart-5dc93fc1-d150-45a9-b068-377ddd770d87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053119540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3053119540
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.40082762
Short name T972
Test name
Test status
Simulation time 163014625 ps
CPU time 0.87 seconds
Started Jan 24 08:38:05 PM PST 24
Finished Jan 24 08:38:06 PM PST 24
Peak memory 207932 kb
Host smart-419f072f-5c38-44da-8a4b-0e38f930ef58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40082762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.40082762
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1397199701
Short name T334
Test name
Test status
Simulation time 13892654 ps
CPU time 0.87 seconds
Started Jan 24 08:37:28 PM PST 24
Finished Jan 24 08:37:30 PM PST 24
Peak memory 207952 kb
Host smart-8662433b-a5d7-4c10-854d-b5854fa20879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397199701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1397199701
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2799407104
Short name T516
Test name
Test status
Simulation time 303197154 ps
CPU time 10.47 seconds
Started Jan 24 08:37:13 PM PST 24
Finished Jan 24 08:37:24 PM PST 24
Peak memory 218108 kb
Host smart-bb8a807c-bf3b-40f4-a993-06704528637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799407104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2799407104
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.434812924
Short name T650
Test name
Test status
Simulation time 1609922998 ps
CPU time 5.64 seconds
Started Jan 24 08:37:41 PM PST 24
Finished Jan 24 08:37:48 PM PST 24
Peak memory 209512 kb
Host smart-483f982a-1943-4dff-b4dd-b080daf4cdbc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434812924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_acc
ess.434812924
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3426047877
Short name T309
Test name
Test status
Simulation time 6146246166 ps
CPU time 47.85 seconds
Started Jan 24 09:00:21 PM PST 24
Finished Jan 24 09:01:10 PM PST 24
Peak memory 219200 kb
Host smart-42651847-1500-4824-9971-1c45a11e675f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426047877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3426047877
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2013380839
Short name T364
Test name
Test status
Simulation time 154009677 ps
CPU time 2.72 seconds
Started Jan 24 08:37:44 PM PST 24
Finished Jan 24 08:37:48 PM PST 24
Peak memory 209580 kb
Host smart-bba15f6c-d77b-4c8b-82e1-9e86826098d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013380839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.2013380839
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2752944611
Short name T390
Test name
Test status
Simulation time 487640175 ps
CPU time 7.1 seconds
Started Jan 24 08:37:43 PM PST 24
Finished Jan 24 08:37:51 PM PST 24
Peak memory 218068 kb
Host smart-b44610f3-dc44-4644-aa7c-58cf1dae8a16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752944611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2752944611
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1995866791
Short name T647
Test name
Test status
Simulation time 2805130880 ps
CPU time 18.33 seconds
Started Jan 24 08:37:46 PM PST 24
Finished Jan 24 08:38:05 PM PST 24
Peak memory 212948 kb
Host smart-c153d247-ea12-4737-aa3d-8afdebf34e06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995866791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1995866791
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3443206928
Short name T610
Test name
Test status
Simulation time 937361969 ps
CPU time 6.29 seconds
Started Jan 24 08:37:30 PM PST 24
Finished Jan 24 08:37:37 PM PST 24
Peak memory 212964 kb
Host smart-fbee3779-1473-416d-93f4-e49e5a5441da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443206928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3443206928
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2075291213
Short name T615
Test name
Test status
Simulation time 2723029360 ps
CPU time 87.02 seconds
Started Jan 24 09:04:00 PM PST 24
Finished Jan 24 09:05:39 PM PST 24
Peak memory 275836 kb
Host smart-4f797a08-5c23-448b-92ce-96fcc9c60518
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075291213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2075291213
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3814444939
Short name T971
Test name
Test status
Simulation time 1474615398 ps
CPU time 13.37 seconds
Started Jan 24 08:37:44 PM PST 24
Finished Jan 24 08:37:58 PM PST 24
Peak memory 251024 kb
Host smart-603a046e-8eab-48d0-baca-6116db982bab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814444939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3814444939
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3990889138
Short name T621
Test name
Test status
Simulation time 764766456 ps
CPU time 3.2 seconds
Started Jan 24 08:37:09 PM PST 24
Finished Jan 24 08:37:15 PM PST 24
Peak memory 218104 kb
Host smart-d3a1fd41-54da-48eb-b02f-82d7b45c016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990889138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3990889138
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1445146236
Short name T55
Test name
Test status
Simulation time 6260862226 ps
CPU time 8.18 seconds
Started Jan 24 08:54:54 PM PST 24
Finished Jan 24 08:55:06 PM PST 24
Peak memory 217984 kb
Host smart-952f0ec9-4e6a-41c5-bb4d-f884a11c0e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445146236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1445146236
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1084612146
Short name T903
Test name
Test status
Simulation time 432937731 ps
CPU time 13.43 seconds
Started Jan 24 08:37:46 PM PST 24
Finished Jan 24 08:38:00 PM PST 24
Peak memory 218440 kb
Host smart-2e98c8b0-4e61-4970-9104-dd67393bb49e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084612146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1084612146
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2738819344
Short name T928
Test name
Test status
Simulation time 2882777994 ps
CPU time 9.27 seconds
Started Jan 24 08:37:49 PM PST 24
Finished Jan 24 08:37:59 PM PST 24
Peak memory 218128 kb
Host smart-36bdc585-cce4-40f4-9c8e-a22907b4344e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738819344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2738819344
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2588879077
Short name T800
Test name
Test status
Simulation time 1866501012 ps
CPU time 11.98 seconds
Started Jan 24 10:31:58 PM PST 24
Finished Jan 24 10:32:11 PM PST 24
Peak memory 218120 kb
Host smart-a6c9a415-b947-47cc-9053-2807cef7912a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588879077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
588879077
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.145827678
Short name T643
Test name
Test status
Simulation time 301406881 ps
CPU time 7.74 seconds
Started Jan 24 09:20:22 PM PST 24
Finished Jan 24 09:20:30 PM PST 24
Peak memory 218216 kb
Host smart-88861fe1-5660-4ef4-8eae-cd464b6f478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145827678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.145827678
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2246958113
Short name T317
Test name
Test status
Simulation time 28104773 ps
CPU time 1.94 seconds
Started Jan 24 09:47:43 PM PST 24
Finished Jan 24 09:47:46 PM PST 24
Peak memory 213388 kb
Host smart-3e444ea4-3268-445c-8ca0-2ff4a8c3947f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246958113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2246958113
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1700182220
Short name T782
Test name
Test status
Simulation time 1166664109 ps
CPU time 29.38 seconds
Started Jan 24 08:37:11 PM PST 24
Finished Jan 24 08:37:43 PM PST 24
Peak memory 250952 kb
Host smart-6af2fb63-3313-43de-9494-a82c7b10d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700182220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1700182220
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.164491100
Short name T410
Test name
Test status
Simulation time 842836417 ps
CPU time 8.55 seconds
Started Jan 24 08:37:10 PM PST 24
Finished Jan 24 08:37:22 PM PST 24
Peak memory 251116 kb
Host smart-da0136e7-4d44-4d2d-b5af-ec955b27099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164491100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.164491100
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4164601797
Short name T559
Test name
Test status
Simulation time 1875766269 ps
CPU time 35.52 seconds
Started Jan 24 08:37:47 PM PST 24
Finished Jan 24 08:38:23 PM PST 24
Peak memory 248940 kb
Host smart-80a205a2-c836-4649-bcd8-c1f2c64dc5f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164601797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4164601797
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.616564114
Short name T381
Test name
Test status
Simulation time 23455781 ps
CPU time 0.91 seconds
Started Jan 24 08:47:49 PM PST 24
Finished Jan 24 08:47:51 PM PST 24
Peak memory 207940 kb
Host smart-25385237-64ce-4b66-927d-295b3d4586e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616564114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.616564114
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.861951045
Short name T909
Test name
Test status
Simulation time 46147256 ps
CPU time 1.02 seconds
Started Jan 24 08:38:36 PM PST 24
Finished Jan 24 08:38:38 PM PST 24
Peak memory 208168 kb
Host smart-858b0b53-db2a-4443-a257-7c16aa5a8b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861951045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.861951045
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2417178374
Short name T363
Test name
Test status
Simulation time 232092351 ps
CPU time 10.84 seconds
Started Jan 24 08:38:14 PM PST 24
Finished Jan 24 08:38:26 PM PST 24
Peak memory 218176 kb
Host smart-f0191ce4-f711-4e3e-8202-a7fe38649cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417178374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2417178374
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2145168363
Short name T806
Test name
Test status
Simulation time 2621991413 ps
CPU time 11.52 seconds
Started Jan 24 08:38:28 PM PST 24
Finished Jan 24 08:38:40 PM PST 24
Peak memory 209568 kb
Host smart-e1135a22-b851-4a12-8d7d-545868b35dcb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145168363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.2145168363
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3951504583
Short name T912
Test name
Test status
Simulation time 11085211895 ps
CPU time 23.43 seconds
Started Jan 24 08:38:28 PM PST 24
Finished Jan 24 08:38:52 PM PST 24
Peak memory 218092 kb
Host smart-3219df39-c258-40fc-98bf-14aab2559c94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951504583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3951504583
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.50371196
Short name T874
Test name
Test status
Simulation time 171309295 ps
CPU time 2.72 seconds
Started Jan 24 08:38:32 PM PST 24
Finished Jan 24 08:38:36 PM PST 24
Peak memory 209592 kb
Host smart-3c98b6bd-e16f-4c0b-9ca6-0afecd7ed771
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50371196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_pr
iority.50371196
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2099210544
Short name T20
Test name
Test status
Simulation time 2568506673 ps
CPU time 31.5 seconds
Started Jan 24 08:38:28 PM PST 24
Finished Jan 24 08:39:00 PM PST 24
Peak memory 218104 kb
Host smart-f492ab97-75a2-400a-a101-2ec581d38ce4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099210544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2099210544
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2965326641
Short name T471
Test name
Test status
Simulation time 978159501 ps
CPU time 18.82 seconds
Started Jan 24 09:48:55 PM PST 24
Finished Jan 24 09:49:17 PM PST 24
Peak memory 212868 kb
Host smart-044b46ef-5dff-47a5-b5e2-e7304147830b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965326641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2965326641
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.108240949
Short name T658
Test name
Test status
Simulation time 102139633 ps
CPU time 3.68 seconds
Started Jan 24 08:38:18 PM PST 24
Finished Jan 24 08:38:23 PM PST 24
Peak memory 212640 kb
Host smart-b6166022-4ada-4282-8fc2-09afb4bb84dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108240949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.108240949
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1415376818
Short name T705
Test name
Test status
Simulation time 5022563736 ps
CPU time 55.48 seconds
Started Jan 24 08:38:22 PM PST 24
Finished Jan 24 08:39:18 PM PST 24
Peak memory 267440 kb
Host smart-89a42f9c-b074-4da6-a3c3-aaf619ccee6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415376818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1415376818
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1631718520
Short name T540
Test name
Test status
Simulation time 330318855 ps
CPU time 14.54 seconds
Started Jan 24 08:38:24 PM PST 24
Finished Jan 24 08:38:39 PM PST 24
Peak memory 250624 kb
Host smart-f9304f36-29f2-4781-b87f-1670cba456a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631718520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1631718520
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2038811538
Short name T541
Test name
Test status
Simulation time 153183892 ps
CPU time 3.22 seconds
Started Jan 24 08:38:20 PM PST 24
Finished Jan 24 08:38:25 PM PST 24
Peak memory 218136 kb
Host smart-2ed1d1bf-efc2-4538-bc59-142dfa401655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038811538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2038811538
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.220032576
Short name T880
Test name
Test status
Simulation time 2154674455 ps
CPU time 5.21 seconds
Started Jan 24 08:38:17 PM PST 24
Finished Jan 24 08:38:23 PM PST 24
Peak memory 213840 kb
Host smart-f4be04c2-0c2b-4c03-8568-8bc2abe2e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220032576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.220032576
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2680711861
Short name T747
Test name
Test status
Simulation time 439090229 ps
CPU time 12.92 seconds
Started Jan 25 12:25:40 AM PST 24
Finished Jan 25 12:26:00 AM PST 24
Peak memory 219160 kb
Host smart-98159786-4f8d-460a-bca3-f6b18bfc93f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680711861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2680711861
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.919603864
Short name T394
Test name
Test status
Simulation time 259322808 ps
CPU time 11.5 seconds
Started Jan 24 08:38:37 PM PST 24
Finished Jan 24 08:38:49 PM PST 24
Peak memory 218112 kb
Host smart-2dd618d5-5877-44c0-934c-c5f801ee9679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919603864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.919603864
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3580570049
Short name T847
Test name
Test status
Simulation time 407140731 ps
CPU time 8.26 seconds
Started Jan 24 08:38:30 PM PST 24
Finished Jan 24 08:38:39 PM PST 24
Peak memory 218104 kb
Host smart-d0dadd0b-e10b-41e8-8ca2-f3e4c9132d73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580570049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
580570049
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2717928447
Short name T500
Test name
Test status
Simulation time 283454902 ps
CPU time 9.23 seconds
Started Jan 24 08:38:18 PM PST 24
Finished Jan 24 08:38:28 PM PST 24
Peak memory 218148 kb
Host smart-e2345845-1287-47a7-8f54-5bc331dbb4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717928447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2717928447
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.361355531
Short name T70
Test name
Test status
Simulation time 88848566 ps
CPU time 3.69 seconds
Started Jan 24 08:38:08 PM PST 24
Finished Jan 24 08:38:12 PM PST 24
Peak memory 214232 kb
Host smart-6c670b4b-5607-4bbb-90f6-817dc84507dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361355531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.361355531
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.844160954
Short name T325
Test name
Test status
Simulation time 662327346 ps
CPU time 31.25 seconds
Started Jan 24 08:38:04 PM PST 24
Finished Jan 24 08:38:36 PM PST 24
Peak memory 251048 kb
Host smart-0f715d15-f5ea-4be3-aa61-a3c369bbfbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844160954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.844160954
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2811966414
Short name T881
Test name
Test status
Simulation time 60091013 ps
CPU time 3.2 seconds
Started Jan 24 08:38:20 PM PST 24
Finished Jan 24 08:38:24 PM PST 24
Peak memory 221708 kb
Host smart-5185564a-2b79-48f8-b526-b6a036979e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811966414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2811966414
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2384630478
Short name T834
Test name
Test status
Simulation time 143977957286 ps
CPU time 520.29 seconds
Started Jan 24 10:28:27 PM PST 24
Finished Jan 24 10:37:08 PM PST 24
Peak memory 333100 kb
Host smart-8e45aa15-e4ee-4982-95a8-b3d129c43b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384630478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2384630478
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.183277732
Short name T616
Test name
Test status
Simulation time 43927509 ps
CPU time 1.04 seconds
Started Jan 24 08:38:07 PM PST 24
Finished Jan 24 08:38:09 PM PST 24
Peak memory 211300 kb
Host smart-09491626-8a6c-47a0-adf3-37e525e6a63a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183277732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.183277732
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2373348366
Short name T385
Test name
Test status
Simulation time 15560581 ps
CPU time 0.89 seconds
Started Jan 24 08:39:20 PM PST 24
Finished Jan 24 08:39:23 PM PST 24
Peak memory 207868 kb
Host smart-8eda2897-c5b7-471c-a078-529f94665e09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373348366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2373348366
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1478529704
Short name T592
Test name
Test status
Simulation time 2355002989 ps
CPU time 21.6 seconds
Started Jan 24 08:38:57 PM PST 24
Finished Jan 24 08:39:19 PM PST 24
Peak memory 225588 kb
Host smart-e1609ea5-af31-4974-a34f-2d05815f5f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478529704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1478529704
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1600008379
Short name T419
Test name
Test status
Simulation time 278901405 ps
CPU time 7.1 seconds
Started Jan 24 08:39:12 PM PST 24
Finished Jan 24 08:39:19 PM PST 24
Peak memory 209548 kb
Host smart-262c38a5-f9db-4f1f-9a25-e954fbf76142
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600008379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.1600008379
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3739219381
Short name T436
Test name
Test status
Simulation time 1201660629 ps
CPU time 37.49 seconds
Started Jan 24 08:39:10 PM PST 24
Finished Jan 24 08:39:49 PM PST 24
Peak memory 218060 kb
Host smart-fe57d97c-f73e-41ad-9acb-3e41a7d9b667
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739219381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3739219381
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2702884112
Short name T9
Test name
Test status
Simulation time 378044594 ps
CPU time 10.42 seconds
Started Jan 24 08:39:10 PM PST 24
Finished Jan 24 08:39:21 PM PST 24
Peak memory 217824 kb
Host smart-0f0904f9-ab3b-44b4-9291-4cdf5f3dfcbb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702884112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.2702884112
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.174663971
Short name T441
Test name
Test status
Simulation time 2451145987 ps
CPU time 9.48 seconds
Started Jan 24 08:39:11 PM PST 24
Finished Jan 24 08:39:21 PM PST 24
Peak memory 218128 kb
Host smart-123f14f7-5efa-4478-98aa-66d671532dc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174663971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.174663971
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2125276153
Short name T776
Test name
Test status
Simulation time 6367743699 ps
CPU time 31.81 seconds
Started Jan 24 08:39:09 PM PST 24
Finished Jan 24 08:39:42 PM PST 24
Peak memory 213676 kb
Host smart-dbc20090-87fc-4bdb-bff4-00ab7b85f742
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125276153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2125276153
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3908335572
Short name T367
Test name
Test status
Simulation time 310105714 ps
CPU time 5.25 seconds
Started Jan 24 08:39:04 PM PST 24
Finished Jan 24 08:39:10 PM PST 24
Peak memory 213272 kb
Host smart-2b0aeed4-d5f2-4c27-874e-93e1582ebe2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908335572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3908335572
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.658291840
Short name T303
Test name
Test status
Simulation time 3361612910 ps
CPU time 45.07 seconds
Started Jan 24 09:26:01 PM PST 24
Finished Jan 24 09:26:47 PM PST 24
Peak memory 275708 kb
Host smart-7177a780-f4a1-4dac-812c-ec46757290e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658291840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.658291840
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2019034857
Short name T871
Test name
Test status
Simulation time 7082466044 ps
CPU time 13.88 seconds
Started Jan 24 08:39:12 PM PST 24
Finished Jan 24 08:39:27 PM PST 24
Peak memory 223344 kb
Host smart-3b532408-fed7-4618-a4d9-25f2175e459f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019034857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2019034857
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2522987524
Short name T480
Test name
Test status
Simulation time 232237494 ps
CPU time 2.81 seconds
Started Jan 24 08:38:57 PM PST 24
Finished Jan 24 08:39:00 PM PST 24
Peak memory 218108 kb
Host smart-01aacec3-0db2-4045-9121-1e93d571b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522987524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2522987524
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1210023152
Short name T60
Test name
Test status
Simulation time 505348282 ps
CPU time 7.75 seconds
Started Jan 24 08:39:02 PM PST 24
Finished Jan 24 08:39:10 PM PST 24
Peak memory 213948 kb
Host smart-7d765091-8387-4a9d-a35d-3cdbde3d5587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210023152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1210023152
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.347355092
Short name T957
Test name
Test status
Simulation time 166623486 ps
CPU time 9.39 seconds
Started Jan 24 08:39:11 PM PST 24
Finished Jan 24 08:39:21 PM PST 24
Peak memory 218112 kb
Host smart-07b2cbfb-d6c6-445d-be58-20b4baf1a126
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347355092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.347355092
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2486650288
Short name T797
Test name
Test status
Simulation time 873836313 ps
CPU time 10.34 seconds
Started Jan 24 09:04:51 PM PST 24
Finished Jan 24 09:05:07 PM PST 24
Peak memory 218104 kb
Host smart-f6402aa0-6212-46da-88df-799c1f88e34a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486650288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2486650288
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3118328147
Short name T590
Test name
Test status
Simulation time 1348183362 ps
CPU time 9.16 seconds
Started Jan 24 08:39:18 PM PST 24
Finished Jan 24 08:39:32 PM PST 24
Peak memory 218128 kb
Host smart-c67ca4e2-7f94-415a-a049-bc15fd1ea8df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118328147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
118328147
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.921801916
Short name T114
Test name
Test status
Simulation time 2578876764 ps
CPU time 10.34 seconds
Started Jan 24 08:38:57 PM PST 24
Finished Jan 24 08:39:08 PM PST 24
Peak memory 218176 kb
Host smart-01315039-2609-44b4-a167-95a7979858eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921801916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.921801916
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.805607837
Short name T789
Test name
Test status
Simulation time 517496773 ps
CPU time 7.21 seconds
Started Jan 24 09:02:00 PM PST 24
Finished Jan 24 09:02:08 PM PST 24
Peak memory 213492 kb
Host smart-8767347b-8f2f-4af7-bead-bf239b2cf167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805607837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.805607837
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2120007427
Short name T307
Test name
Test status
Simulation time 272584468 ps
CPU time 23.53 seconds
Started Jan 24 08:38:54 PM PST 24
Finished Jan 24 08:39:18 PM PST 24
Peak memory 251020 kb
Host smart-6930f9ef-789d-41b9-a81f-e632e0147255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120007427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2120007427
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3367211411
Short name T766
Test name
Test status
Simulation time 144978411 ps
CPU time 6.95 seconds
Started Jan 24 08:38:55 PM PST 24
Finished Jan 24 08:39:03 PM PST 24
Peak memory 246168 kb
Host smart-b468973d-1e91-4522-907b-f1a0fe42ff4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367211411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3367211411
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2800608186
Short name T583
Test name
Test status
Simulation time 39279719090 ps
CPU time 142.84 seconds
Started Jan 24 08:39:18 PM PST 24
Finished Jan 24 08:41:45 PM PST 24
Peak memory 267568 kb
Host smart-aae47518-62ee-4836-b73f-613788ca25fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800608186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2800608186
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.11425710
Short name T33
Test name
Test status
Simulation time 20285210 ps
CPU time 0.89 seconds
Started Jan 24 08:38:52 PM PST 24
Finished Jan 24 08:38:54 PM PST 24
Peak memory 211156 kb
Host smart-1ac91a97-4b22-4279-8c7e-aaa0ca1f2035
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11425710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_volatile_unlock_smoke.11425710
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.770948293
Short name T772
Test name
Test status
Simulation time 12442426 ps
CPU time 1.02 seconds
Started Jan 24 08:56:17 PM PST 24
Finished Jan 24 08:56:19 PM PST 24
Peak memory 209484 kb
Host smart-c3264371-6cd1-45a0-b38d-6b55e55ad7e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770948293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.770948293
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.964565535
Short name T171
Test name
Test status
Simulation time 13194854 ps
CPU time 0.98 seconds
Started Jan 24 08:39:27 PM PST 24
Finished Jan 24 08:39:29 PM PST 24
Peak memory 209536 kb
Host smart-d324f8e0-9551-460b-8833-4ba4aedb47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964565535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.964565535
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2708107266
Short name T866
Test name
Test status
Simulation time 2736800302 ps
CPU time 16.39 seconds
Started Jan 24 08:39:25 PM PST 24
Finished Jan 24 08:39:43 PM PST 24
Peak memory 218188 kb
Host smart-7ed8d810-706d-441b-bdc0-1837980a3366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708107266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2708107266
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3567521195
Short name T963
Test name
Test status
Simulation time 533265691 ps
CPU time 3.6 seconds
Started Jan 24 08:39:38 PM PST 24
Finished Jan 24 08:39:45 PM PST 24
Peak memory 209544 kb
Host smart-cf866f6c-98a1-4af2-b97b-f0f3d9ada8b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567521195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.3567521195
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.10475946
Short name T553
Test name
Test status
Simulation time 2726643207 ps
CPU time 43.74 seconds
Started Jan 24 08:39:42 PM PST 24
Finished Jan 24 08:40:29 PM PST 24
Peak memory 218096 kb
Host smart-d93374de-74ff-4fd0-8b38-0d3a42c21b27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10475946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_erro
rs.10475946
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1790320463
Short name T443
Test name
Test status
Simulation time 121464533 ps
CPU time 1.95 seconds
Started Jan 24 08:59:06 PM PST 24
Finished Jan 24 08:59:09 PM PST 24
Peak memory 209676 kb
Host smart-036e6e6b-f62a-4c5b-ad7d-b7e566663c1c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790320463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
priority.1790320463
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2116292777
Short name T489
Test name
Test status
Simulation time 7144789663 ps
CPU time 9.62 seconds
Started Jan 24 08:39:35 PM PST 24
Finished Jan 24 08:39:46 PM PST 24
Peak memory 218068 kb
Host smart-831cc3c7-0d7b-455d-b52d-16936f94402c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116292777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2116292777
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1860579016
Short name T596
Test name
Test status
Simulation time 2573265759 ps
CPU time 16.34 seconds
Started Jan 24 08:39:45 PM PST 24
Finished Jan 24 08:40:03 PM PST 24
Peak memory 213284 kb
Host smart-227a94f7-7738-4c9f-a0d7-4ff96a4927df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860579016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1860579016
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1992413668
Short name T915
Test name
Test status
Simulation time 271430259 ps
CPU time 4.89 seconds
Started Jan 24 08:48:59 PM PST 24
Finished Jan 24 08:49:08 PM PST 24
Peak memory 213256 kb
Host smart-3a038654-ef23-4614-ac3b-896136c37f9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992413668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1992413668
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.4000895768
Short name T475
Test name
Test status
Simulation time 2675366549 ps
CPU time 36.03 seconds
Started Jan 24 08:55:23 PM PST 24
Finished Jan 24 08:56:01 PM PST 24
Peak memory 252360 kb
Host smart-9061af69-d068-40fe-b279-568be95ddc1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000895768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.4000895768
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.286958358
Short name T848
Test name
Test status
Simulation time 2261306649 ps
CPU time 10.42 seconds
Started Jan 24 08:39:35 PM PST 24
Finished Jan 24 08:39:47 PM PST 24
Peak memory 222548 kb
Host smart-aa90dde0-f78b-4e04-b64c-aadafd8013fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286958358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.286958358
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3875304064
Short name T586
Test name
Test status
Simulation time 241400863 ps
CPU time 2.55 seconds
Started Jan 24 08:39:27 PM PST 24
Finished Jan 24 08:39:30 PM PST 24
Peak memory 218108 kb
Host smart-9e9f0d68-c031-4126-89f4-cdc27118aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875304064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3875304064
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3320667169
Short name T53
Test name
Test status
Simulation time 1640376961 ps
CPU time 9.4 seconds
Started Jan 24 08:39:26 PM PST 24
Finished Jan 24 08:39:36 PM PST 24
Peak memory 214024 kb
Host smart-7f2fe1b1-0958-4ba9-9402-d55ffa711024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320667169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3320667169
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.174457741
Short name T479
Test name
Test status
Simulation time 3197555588 ps
CPU time 16.89 seconds
Started Jan 24 08:39:50 PM PST 24
Finished Jan 24 08:40:09 PM PST 24
Peak memory 219260 kb
Host smart-3ef5e38b-0e36-4603-a507-6988f12cb7f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174457741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.174457741
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2230787852
Short name T408
Test name
Test status
Simulation time 841004591 ps
CPU time 10.22 seconds
Started Jan 24 08:39:48 PM PST 24
Finished Jan 24 08:40:02 PM PST 24
Peak memory 218108 kb
Host smart-305cd7e5-849a-4f5b-b1c9-7f80df7c01d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230787852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2230787852
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1057984829
Short name T556
Test name
Test status
Simulation time 342846631 ps
CPU time 11.67 seconds
Started Jan 24 08:39:48 PM PST 24
Finished Jan 24 08:40:04 PM PST 24
Peak memory 218092 kb
Host smart-6442ba26-e062-4c2e-96d6-7993cac2cb85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057984829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
057984829
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3638965571
Short name T454
Test name
Test status
Simulation time 368531340 ps
CPU time 10.58 seconds
Started Jan 24 08:39:28 PM PST 24
Finished Jan 24 08:39:40 PM PST 24
Peak memory 218108 kb
Host smart-0cdcb5f5-542b-4a93-bdc2-30df9dffe048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638965571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3638965571
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2722762193
Short name T563
Test name
Test status
Simulation time 30185508 ps
CPU time 1.96 seconds
Started Jan 24 08:39:25 PM PST 24
Finished Jan 24 08:39:28 PM PST 24
Peak memory 213396 kb
Host smart-17fa8022-452b-4295-814c-4f1a4bfc51b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722762193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2722762193
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2877078958
Short name T733
Test name
Test status
Simulation time 292531393 ps
CPU time 30.74 seconds
Started Jan 24 08:39:25 PM PST 24
Finished Jan 24 08:39:57 PM PST 24
Peak memory 250464 kb
Host smart-c94d3811-6f30-4499-86c5-0257841aa4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877078958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2877078958
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.529682706
Short name T391
Test name
Test status
Simulation time 67265940 ps
CPU time 8.57 seconds
Started Jan 24 08:39:24 PM PST 24
Finished Jan 24 08:39:35 PM PST 24
Peak memory 250996 kb
Host smart-c52eab21-1ac4-4d33-b3e7-50760368e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529682706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.529682706
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1177877584
Short name T746
Test name
Test status
Simulation time 8189770629 ps
CPU time 188.28 seconds
Started Jan 24 08:39:57 PM PST 24
Finished Jan 24 08:43:06 PM PST 24
Peak memory 267552 kb
Host smart-8a9043b3-bdbc-4942-94b5-971d6c67dc18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177877584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1177877584
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4125993085
Short name T459
Test name
Test status
Simulation time 10615789 ps
CPU time 0.92 seconds
Started Jan 24 08:39:28 PM PST 24
Finished Jan 24 08:39:29 PM PST 24
Peak memory 208144 kb
Host smart-82131b4a-5092-4bea-9ede-9814bb1d2ed2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125993085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.4125993085
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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