Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55240068

1

T60

1752

T86

92402

T87

49424

auto[1]

1098383

1

T3

4257

T4

8336

T5

1287

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55263320

1

T60

1752

T86

92402

T87

49424

auto[1]

1075131

1

T3

4059

T4

6358

T5

1386

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	4834348	1			T60	82		T86	71		T87	69
auto[IdleSt]	15098025	1			T60	1670		T86	92331		T87	49355
auto[ClkMuxSt]	27951	1			T4	64		T5	41		T11	46
auto[CntIncrSt]	27785	1			T4	64		T5	41		T11	45
auto[CntProgSt]	1385919	1			T4	1706		T5	10294		T11	4732
auto[TransCheckSt]	22076	1			T4	28		T5	31		T11	23
auto[TokenHashSt]	15569093	1			T4	209		T5	1533		T11	11505
auto[FlashRmaSt]	21417	1			T4	17		T5	106		T11	18
auto[TokenCheck0St]	9570	1			T4	17		T5	26		T11	18
auto[TokenCheck1St]	6864	1			T4	17		T5	16		T11	18
auto[TransProgSt]	317056	1			T4	39		T5	3567		T11	42
auto[PostTransSt]	8557930	1			T5	5314		T6	6975		T12	697
auto[ScrapSt]	86154	1			T88	1156		T109	1230		T110	751
auto[EscalateSt]	4424724	1			T3	12147		T4	11278		T5	3464
auto[InvalidSt]	5948364	1			T3	13324		T5	1283		T6	7081

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1175	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	5948364	1			T3	13324		T5	1283		T6	7081
EscalateSt	4424724	1			T3	12147		T4	11278		T5	3464
ScrapSt	86154	1			T88	1156		T109	1230		T110	751
PostTransSt	8557930	1			T5	5314		T6	6975		T12	697
TransProgSt	317056	1			T4	39		T5	3567		T11	42
TokenCheck1St	6864	1			T4	17		T5	16		T11	18
TokenCheck0St	9570	1			T4	17		T5	26		T11	18
FlashRmaSt	21417	1			T4	17		T5	106		T11	18
TokenHashSt	15569093	1			T4	209		T5	1533		T11	11505
TransCheckSt	22076	1			T4	28		T5	31		T11	23
CntProgSt	1385919	1			T4	1706		T5	10294		T11	4732
CntIncrSt	27785	1			T4	64		T5	41		T11	45
ClkMuxSt	27951	1			T4	64		T5	41		T11	46
IdleSt	15098025	1			T60	1670		T86	92331		T87	49355
ResetSt	4834348	1			T60	82		T86	71		T87	69
arcs[ResetSt=>IdleSt]	39489	1			T60	1		T86	1		T87	1
arcs[IdleSt=>ScrapSt]	221	1			T88	1		T109	2		T110	2
arcs[IdleSt=>ClkMuxSt]	27850	1			T4	64		T5	41		T11	46
arcs[ClkMuxSt=>CntIncrSt]	27785	1			T4	64		T5	41		T11	45
arcs[CntIncrSt=>PostTransSt]	1214	1			T15	11		T7	7		T19	11
arcs[CntIncrSt=>CntProgSt]	26501	1			T4	64		T5	41		T11	41
arcs[CntProgSt=>PostTransSt]	3353	1			T5	10		T12	9		T15	10
arcs[CntProgSt=>TransCheckSt]	22076	1			T4	28		T5	31		T11	23
arcs[TransCheckSt=>PostTransSt]	3234	1			T15	12		T7	7		T19	8
arcs[TransCheckSt=>TokenHashSt]	18699	1			T4	28		T5	31		T11	23
arcs[TokenHashSt=>PostTransSt]	8365	1			T5	5		T15	22		T7	20
arcs[TokenHashSt=>FlashRmaSt]	9651	1			T4	17		T5	26		T11	18
arcs[FlashRmaSt=>TokenCheck0St]	9570	1			T4	17		T5	26		T11	18
arcs[TokenCheck0St=>PostTransSt]	2682	1			T5	10		T15	8		T7	5
arcs[TokenCheck0St=>TokenCheck1St]	6864	1			T4	17		T5	16		T11	18
arcs[TokenCheck1St=>PostTransSt]	596	1			T5	1		T7	1		T19	3
arcs[TransProgSt=>PostTransSt]	5408	1			T5	15		T6	4		T13	1
arcs[IdleSt=>EscalateSt]	174	1			T11	2		T14	10		T81	4
arcs[ClkMuxSt=>EscalateSt]	65	1			T11	1		T13	1		T14	2
arcs[CntIncrSt=>EscalateSt]	70	1			T11	4		T13	1		T14	1
arcs[CntProgSt=>EscalateSt]	1072	1			T4	36		T11	18		T13	39
arcs[TransCheckSt=>EscalateSt]	143	1			T13	3		T82	6		T193	6
arcs[TokenHashSt=>EscalateSt]	676	1			T4	11		T11	5		T13	6
arcs[FlashRmaSt=>EscalateSt]	81	1			T13	5		T14	2		T81	2
arcs[TokenCheck0St=>EscalateSt]	24	1			T13	1		T14	1		T81	2
arcs[TokenCheck1St=>EscalateSt]	136	1			T4	3		T11	1		T13	2
arcs[TransProgSt=>EscalateSt]	724	1			T4	14		T11	17		T13	19
arcs[PostTransSt=>EscalateSt]	3614	1			T5	10		T12	9		T13	1
arcs[InvalidSt=>EscalateSt]	9277	1			T3	84		T5	17		T6	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	4834173	1			T60	82		T86	71		T87	69
auto[0]	auto[IdleSt]	15097916	1			T60	1670		T86	92331		T87	49355
auto[0]	auto[ClkMuxSt]	27908	1			T4	64		T5	41		T11	45
auto[0]	auto[CntIncrSt]	27740	1			T4	64		T5	41		T11	43
auto[0]	auto[CntProgSt]	1385199	1			T4	1681		T5	10294		T11	4718
auto[0]	auto[TransCheckSt]	21968	1			T4	28		T5	31		T11	23
auto[0]	auto[TokenHashSt]	15568637	1			T4	200		T5	1533		T11	11501
auto[0]	auto[FlashRmaSt]	21361	1			T4	17		T5	106		T11	18
auto[0]	auto[TokenCheck0St]	9552	1			T4	17		T5	26		T11	18
auto[0]	auto[TokenCheck1St]	6762	1			T4	14		T5	16		T11	17
auto[0]	auto[TransProgSt]	316572	1			T4	30		T5	3567		T11	30
auto[0]	auto[PostTransSt]	8556079	1			T5	5311		T6	6975		T12	693
auto[0]	auto[ScrapSt]	86097	1			T88	1156		T109	1230		T110	751
auto[0]	auto[EscalateSt]	3335235	1			T3	7933		T4	2991		T5	2190
auto[0]	auto[InvalidSt]	5943694	1			T3	13281		T5	1273		T6	7080
auto[1]	auto[ResetSt]	175	1			T4	3		T11	1		T13	6
auto[1]	auto[IdleSt]	109	1			T11	2		T14	6		T81	2
auto[1]	auto[ClkMuxSt]	43	1			T11	1		T13	1		T14	1
auto[1]	auto[CntIncrSt]	45	1			T11	2		T193	1		T194	2
auto[1]	auto[CntProgSt]	720	1			T4	25		T11	14		T13	29
auto[1]	auto[TransCheckSt]	108	1			T13	3		T82	5		T193	5
auto[1]	auto[TokenHashSt]	456	1			T4	9		T11	4		T13	4
auto[1]	auto[FlashRmaSt]	56	1			T13	4		T82	1		T195	1
auto[1]	auto[TokenCheck0St]	18	1			T13	1		T14	1		T82	1
auto[1]	auto[TokenCheck1St]	102	1			T4	3		T11	1		T13	2
auto[1]	auto[TransProgSt]	484	1			T4	9		T11	12		T13	15
auto[1]	auto[PostTransSt]	1851	1			T5	3		T12	4		T13	1
auto[1]	auto[ScrapSt]	57	1			T11	1		T14	2		T81	1
auto[1]	auto[EscalateSt]	1089489	1			T3	4214		T4	8287		T5	1274
auto[1]	auto[InvalidSt]	4670	1			T3	43		T5	10		T6	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	4834184	1			T60	82		T86	71		T87	69
auto[0]	auto[IdleSt]	15097910	1			T60	1670		T86	92331		T87	49355
auto[0]	auto[ClkMuxSt]	27903	1			T4	64		T5	41		T11	46
auto[0]	auto[CntIncrSt]	27733	1			T4	64		T5	41		T11	42
auto[0]	auto[CntProgSt]	1385230	1			T4	1684		T5	10294		T11	4724
auto[0]	auto[TransCheckSt]	21989	1			T4	28		T5	31		T11	23
auto[0]	auto[TokenHashSt]	15568668	1			T4	202		T5	1533		T11	11502
auto[0]	auto[FlashRmaSt]	21361	1			T4	17		T5	106		T11	18
auto[0]	auto[TokenCheck0St]	9556	1			T4	17		T5	26		T11	18
auto[0]	auto[TokenCheck1St]	6773	1			T4	15		T5	16		T11	17
auto[0]	auto[TransProgSt]	316568	1			T4	33		T5	3567		T11	30
auto[0]	auto[PostTransSt]	8556092	1			T5	5307		T6	6975		T12	692
auto[0]	auto[ScrapSt]	86103	1			T88	1156		T109	1230		T110	751
auto[0]	auto[EscalateSt]	3358318	1			T3	8129		T4	4958		T5	2092
auto[0]	auto[InvalidSt]	5943757	1			T3	13283		T5	1276		T6	7076
auto[1]	auto[ResetSt]	164	1			T4	1		T11	1		T13	6
auto[1]	auto[IdleSt]	115	1			T11	2		T14	8		T81	2
auto[1]	auto[ClkMuxSt]	48	1			T13	1		T14	2		T82	1
auto[1]	auto[CntIncrSt]	52	1			T11	3		T13	1		T14	1
auto[1]	auto[CntProgSt]	689	1			T4	22		T11	8		T13	20
auto[1]	auto[TransCheckSt]	87	1			T13	2		T82	3		T193	4
auto[1]	auto[TokenHashSt]	425	1			T4	7		T11	3		T13	5
auto[1]	auto[FlashRmaSt]	56	1			T13	2		T14	2		T81	2
auto[1]	auto[TokenCheck0St]	14	1			T13	1		T14	1		T81	2
auto[1]	auto[TokenCheck1St]	91	1			T4	2		T11	1		T14	1
auto[1]	auto[TransProgSt]	488	1			T4	6		T11	12		T13	15
auto[1]	auto[PostTransSt]	1838	1			T5	7		T12	5		T13	1
auto[1]	auto[ScrapSt]	51	1			T11	1		T13	1		T14	1
auto[1]	auto[EscalateSt]	1066406	1			T3	4018		T4	6320		T5	1372
auto[1]	auto[InvalidSt]	4607	1			T3	41		T5	7		T6	5