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 LINE       1288
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T60,T86,T87
1	0	1	Covered	T60,T87,T88
1	1	0	Covered	T140
1	1	1	Covered	T3,T4,T5

 LINE       1289
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T60,T86,T87
1	0	1	Covered	T60,T87,T88
1	1	0	Covered	T92
1	1	1	Covered	T3,T4,T5

 LINE       1290
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T60,T86,T87
1	0	1	Covered	T60,T87,T88
1	1	0	Covered	T145
1	1	1	Covered	T3,T4,T5

 LINE       1291
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T60,T86,T87
1	0	1	Covered	T60,T87,T88
1	1	0	Covered	T106,T148
1	1	1	Covered	T3,T4,T5