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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 97.29 95.78 91.98 97.67 96.13 98.73 94.82


Total test records in report: 982
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T771 /workspace/coverage/default/16.lc_ctrl_security_escalation.326545308 Feb 04 01:14:17 PM PST 24 Feb 04 01:14:29 PM PST 24 2203677254 ps
T772 /workspace/coverage/default/26.lc_ctrl_stress_all.800098832 Feb 04 01:15:03 PM PST 24 Feb 04 01:16:39 PM PST 24 6421947424 ps
T773 /workspace/coverage/default/8.lc_ctrl_state_failure.2278625473 Feb 04 01:13:35 PM PST 24 Feb 04 01:13:56 PM PST 24 192317517 ps
T774 /workspace/coverage/default/27.lc_ctrl_errors.3812661323 Feb 04 01:15:07 PM PST 24 Feb 04 01:15:24 PM PST 24 2224449447 ps
T126 /workspace/coverage/default/2.lc_ctrl_sec_cm.1197108811 Feb 04 01:12:43 PM PST 24 Feb 04 01:13:09 PM PST 24 218912806 ps
T775 /workspace/coverage/default/26.lc_ctrl_smoke.374755372 Feb 04 01:14:49 PM PST 24 Feb 04 01:14:54 PM PST 24 78956555 ps
T776 /workspace/coverage/default/39.lc_ctrl_state_post_trans.1614027901 Feb 04 01:15:35 PM PST 24 Feb 04 01:15:46 PM PST 24 107857891 ps
T777 /workspace/coverage/default/46.lc_ctrl_errors.2670296794 Feb 04 01:15:58 PM PST 24 Feb 04 01:16:18 PM PST 24 1337142750 ps
T778 /workspace/coverage/default/2.lc_ctrl_prog_failure.1304863011 Feb 04 01:12:38 PM PST 24 Feb 04 01:12:43 PM PST 24 414379721 ps
T779 /workspace/coverage/default/21.lc_ctrl_state_post_trans.2554762573 Feb 04 01:14:38 PM PST 24 Feb 04 01:14:44 PM PST 24 104131940 ps
T780 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2648597075 Feb 04 01:14:12 PM PST 24 Feb 04 01:14:24 PM PST 24 760912832 ps
T781 /workspace/coverage/default/41.lc_ctrl_state_failure.4068693057 Feb 04 01:15:49 PM PST 24 Feb 04 01:16:19 PM PST 24 389855962 ps
T782 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3019095140 Feb 04 01:14:19 PM PST 24 Feb 04 01:14:30 PM PST 24 1038005440 ps
T783 /workspace/coverage/default/46.lc_ctrl_sec_mubi.3720454649 Feb 04 01:15:52 PM PST 24 Feb 04 01:16:14 PM PST 24 594087196 ps
T79 /workspace/coverage/default/11.lc_ctrl_smoke.2603193365 Feb 04 01:14:10 PM PST 24 Feb 04 01:14:13 PM PST 24 643281455 ps
T784 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.939689417 Feb 04 01:13:26 PM PST 24 Feb 04 01:13:40 PM PST 24 373370596 ps
T785 /workspace/coverage/default/36.lc_ctrl_sec_mubi.1812701394 Feb 04 01:15:35 PM PST 24 Feb 04 01:15:49 PM PST 24 272464084 ps
T786 /workspace/coverage/default/11.lc_ctrl_sec_mubi.3161242716 Feb 04 01:14:02 PM PST 24 Feb 04 01:14:12 PM PST 24 264748103 ps
T787 /workspace/coverage/default/16.lc_ctrl_alert_test.2669583768 Feb 04 01:14:18 PM PST 24 Feb 04 01:14:20 PM PST 24 17595325 ps
T788 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.295029383 Feb 04 01:15:38 PM PST 24 Feb 04 01:15:52 PM PST 24 336818277 ps
T80 /workspace/coverage/default/39.lc_ctrl_smoke.3768087372 Feb 04 01:15:33 PM PST 24 Feb 04 01:15:39 PM PST 24 219615876 ps
T789 /workspace/coverage/default/19.lc_ctrl_jtag_errors.201545389 Feb 04 01:14:26 PM PST 24 Feb 04 01:15:02 PM PST 24 1102946689 ps
T790 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1036292603 Feb 04 01:14:07 PM PST 24 Feb 04 01:14:21 PM PST 24 1991316383 ps
T791 /workspace/coverage/default/4.lc_ctrl_stress_all.1327686343 Feb 04 01:13:14 PM PST 24 Feb 04 01:14:21 PM PST 24 3576675617 ps
T792 /workspace/coverage/default/49.lc_ctrl_alert_test.3024373688 Feb 04 01:16:06 PM PST 24 Feb 04 01:16:08 PM PST 24 16964598 ps
T793 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3815160452 Feb 04 01:13:58 PM PST 24 Feb 04 01:14:00 PM PST 24 107272653 ps
T794 /workspace/coverage/default/40.lc_ctrl_sec_mubi.2139496923 Feb 04 01:15:39 PM PST 24 Feb 04 01:15:55 PM PST 24 617167953 ps
T795 /workspace/coverage/default/15.lc_ctrl_security_escalation.1988047621 Feb 04 01:14:24 PM PST 24 Feb 04 01:14:40 PM PST 24 390828849 ps
T796 /workspace/coverage/default/22.lc_ctrl_state_failure.2722075022 Feb 04 01:14:42 PM PST 24 Feb 04 01:15:11 PM PST 24 1266670023 ps
T797 /workspace/coverage/default/40.lc_ctrl_errors.1807479245 Feb 04 01:15:41 PM PST 24 Feb 04 01:15:50 PM PST 24 275238274 ps
T798 /workspace/coverage/default/48.lc_ctrl_prog_failure.816173544 Feb 04 01:15:51 PM PST 24 Feb 04 01:16:01 PM PST 24 239468296 ps
T71 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1222077125 Feb 04 01:13:40 PM PST 24 Feb 04 01:13:58 PM PST 24 802562561 ps
T799 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2939559066 Feb 04 01:16:03 PM PST 24 Feb 04 01:16:13 PM PST 24 912982210 ps
T800 /workspace/coverage/default/35.lc_ctrl_stress_all.2307317039 Feb 04 01:15:33 PM PST 24 Feb 04 01:21:41 PM PST 24 7584763239 ps
T801 /workspace/coverage/default/23.lc_ctrl_state_post_trans.2570539068 Feb 04 01:14:46 PM PST 24 Feb 04 01:14:52 PM PST 24 260849244 ps
T802 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2637358160 Feb 04 01:13:09 PM PST 24 Feb 04 01:13:24 PM PST 24 605913642 ps
T803 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.541954682 Feb 04 01:12:44 PM PST 24 Feb 04 01:12:50 PM PST 24 251105930 ps
T804 /workspace/coverage/default/32.lc_ctrl_state_post_trans.1380793254 Feb 04 01:15:18 PM PST 24 Feb 04 01:15:22 PM PST 24 144465675 ps
T805 /workspace/coverage/default/1.lc_ctrl_jtag_errors.2950576293 Feb 04 01:12:32 PM PST 24 Feb 04 01:14:02 PM PST 24 12316555962 ps
T806 /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.870581066 Feb 04 01:12:33 PM PST 24 Feb 04 01:12:56 PM PST 24 1260040746 ps
T807 /workspace/coverage/default/5.lc_ctrl_prog_failure.882890877 Feb 04 01:13:22 PM PST 24 Feb 04 01:13:25 PM PST 24 33524722 ps
T808 /workspace/coverage/default/6.lc_ctrl_state_post_trans.902657480 Feb 04 01:13:24 PM PST 24 Feb 04 01:13:40 PM PST 24 280190947 ps
T809 /workspace/coverage/default/4.lc_ctrl_jtag_access.3874328997 Feb 04 01:13:16 PM PST 24 Feb 04 01:13:23 PM PST 24 1219171139 ps
T810 /workspace/coverage/default/26.lc_ctrl_state_failure.3162444038 Feb 04 01:15:00 PM PST 24 Feb 04 01:15:23 PM PST 24 878737816 ps
T811 /workspace/coverage/default/3.lc_ctrl_sec_mubi.4185862373 Feb 04 01:12:58 PM PST 24 Feb 04 01:13:14 PM PST 24 1695858763 ps
T72 /workspace/coverage/default/2.lc_ctrl_alert_test.4119396504 Feb 04 01:12:51 PM PST 24 Feb 04 01:12:53 PM PST 24 35101546 ps
T812 /workspace/coverage/default/47.lc_ctrl_state_failure.38335336 Feb 04 01:15:50 PM PST 24 Feb 04 01:16:23 PM PST 24 585116593 ps
T813 /workspace/coverage/default/0.lc_ctrl_stress_all.3577742246 Feb 04 01:12:21 PM PST 24 Feb 04 01:13:46 PM PST 24 88627822691 ps
T814 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1977350664 Feb 04 01:14:12 PM PST 24 Feb 04 01:14:31 PM PST 24 2647914361 ps
T815 /workspace/coverage/default/4.lc_ctrl_state_failure.307277681 Feb 04 01:13:14 PM PST 24 Feb 04 01:13:45 PM PST 24 1371885533 ps
T816 /workspace/coverage/default/36.lc_ctrl_stress_all.32653560 Feb 04 01:15:28 PM PST 24 Feb 04 01:26:07 PM PST 24 27437300535 ps
T817 /workspace/coverage/default/10.lc_ctrl_smoke.3242115361 Feb 04 01:13:42 PM PST 24 Feb 04 01:13:49 PM PST 24 65553225 ps
T818 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3968107600 Feb 04 01:12:21 PM PST 24 Feb 04 01:12:24 PM PST 24 70470577 ps
T73 /workspace/coverage/default/11.lc_ctrl_alert_test.340661459 Feb 04 01:14:08 PM PST 24 Feb 04 01:14:11 PM PST 24 95342787 ps
T819 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1546961610 Feb 04 01:13:16 PM PST 24 Feb 04 01:13:24 PM PST 24 1178184125 ps
T820 /workspace/coverage/default/23.lc_ctrl_prog_failure.1936026412 Feb 04 01:14:40 PM PST 24 Feb 04 01:14:44 PM PST 24 49628201 ps
T821 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3880188012 Feb 04 01:15:05 PM PST 24 Feb 04 01:15:18 PM PST 24 1015567051 ps
T822 /workspace/coverage/default/23.lc_ctrl_stress_all.1638087363 Feb 04 01:14:51 PM PST 24 Feb 04 01:16:17 PM PST 24 5634945313 ps
T823 /workspace/coverage/default/43.lc_ctrl_stress_all.1311452033 Feb 04 01:15:49 PM PST 24 Feb 04 01:16:52 PM PST 24 6244341725 ps
T824 /workspace/coverage/default/33.lc_ctrl_stress_all.130154313 Feb 04 01:15:15 PM PST 24 Feb 04 01:15:52 PM PST 24 1953330029 ps
T825 /workspace/coverage/default/46.lc_ctrl_state_post_trans.2797463329 Feb 04 01:15:58 PM PST 24 Feb 04 01:16:09 PM PST 24 139473994 ps
T826 /workspace/coverage/default/22.lc_ctrl_prog_failure.784778038 Feb 04 01:14:42 PM PST 24 Feb 04 01:14:45 PM PST 24 35432343 ps
T827 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3211585462 Feb 04 01:14:11 PM PST 24 Feb 04 01:14:22 PM PST 24 1572951481 ps
T828 /workspace/coverage/default/8.lc_ctrl_stress_all.255633832 Feb 04 01:13:40 PM PST 24 Feb 04 01:15:13 PM PST 24 10969405702 ps
T829 /workspace/coverage/default/19.lc_ctrl_jtag_access.3200409671 Feb 04 01:14:29 PM PST 24 Feb 04 01:14:40 PM PST 24 916168140 ps
T830 /workspace/coverage/default/25.lc_ctrl_alert_test.1105233203 Feb 04 01:14:48 PM PST 24 Feb 04 01:14:51 PM PST 24 74172534 ps
T831 /workspace/coverage/default/24.lc_ctrl_smoke.3536694331 Feb 04 01:14:53 PM PST 24 Feb 04 01:15:02 PM PST 24 164870594 ps
T832 /workspace/coverage/default/38.lc_ctrl_errors.2638622872 Feb 04 01:15:36 PM PST 24 Feb 04 01:15:49 PM PST 24 1259523270 ps
T833 /workspace/coverage/default/19.lc_ctrl_errors.1193320692 Feb 04 01:14:29 PM PST 24 Feb 04 01:14:53 PM PST 24 2408737879 ps
T834 /workspace/coverage/default/14.lc_ctrl_jtag_errors.3498428490 Feb 04 01:14:14 PM PST 24 Feb 04 01:15:21 PM PST 24 5459614314 ps
T835 /workspace/coverage/default/6.lc_ctrl_state_failure.3779954454 Feb 04 01:13:24 PM PST 24 Feb 04 01:13:51 PM PST 24 1034838280 ps
T50 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4044904889 Feb 04 01:14:18 PM PST 24 Feb 04 01:14:20 PM PST 24 20969193 ps
T836 /workspace/coverage/default/4.lc_ctrl_errors.26055768 Feb 04 01:13:14 PM PST 24 Feb 04 01:13:30 PM PST 24 1960510684 ps
T837 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3258858345 Feb 04 01:14:44 PM PST 24 Feb 04 01:14:57 PM PST 24 706411412 ps
T838 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2767644854 Feb 04 01:14:55 PM PST 24 Feb 04 01:15:10 PM PST 24 287589546 ps
T839 /workspace/coverage/default/29.lc_ctrl_alert_test.2349569565 Feb 04 01:15:14 PM PST 24 Feb 04 01:15:17 PM PST 24 15038353 ps
T840 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2385184971 Feb 04 01:12:46 PM PST 24 Feb 04 01:13:01 PM PST 24 1490624054 ps
T841 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1095497439 Feb 04 01:14:26 PM PST 24 Feb 04 01:14:45 PM PST 24 1077314399 ps
T842 /workspace/coverage/default/34.lc_ctrl_security_escalation.4123996298 Feb 04 01:15:20 PM PST 24 Feb 04 01:15:33 PM PST 24 234475901 ps
T843 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2604866471 Feb 04 01:13:25 PM PST 24 Feb 04 01:13:44 PM PST 24 1670195353 ps
T844 /workspace/coverage/default/3.lc_ctrl_jtag_access.4257509032 Feb 04 01:12:50 PM PST 24 Feb 04 01:13:15 PM PST 24 8974285051 ps
T845 /workspace/coverage/default/41.lc_ctrl_security_escalation.3229659787 Feb 04 01:15:40 PM PST 24 Feb 04 01:15:53 PM PST 24 284929489 ps
T846 /workspace/coverage/default/24.lc_ctrl_errors.3936419669 Feb 04 01:15:04 PM PST 24 Feb 04 01:15:16 PM PST 24 270887050 ps
T847 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3285930406 Feb 04 01:15:21 PM PST 24 Feb 04 01:15:34 PM PST 24 526653693 ps
T848 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.723585338 Feb 04 01:15:28 PM PST 24 Feb 04 01:15:49 PM PST 24 769612901 ps
T849 /workspace/coverage/default/39.lc_ctrl_alert_test.3622239825 Feb 04 01:15:40 PM PST 24 Feb 04 01:15:42 PM PST 24 17851521 ps
T850 /workspace/coverage/default/13.lc_ctrl_prog_failure.2301761258 Feb 04 01:14:12 PM PST 24 Feb 04 01:14:16 PM PST 24 35788509 ps
T851 /workspace/coverage/default/21.lc_ctrl_errors.3650007103 Feb 04 01:14:40 PM PST 24 Feb 04 01:15:00 PM PST 24 811805482 ps
T852 /workspace/coverage/default/17.lc_ctrl_prog_failure.1784344679 Feb 04 01:14:22 PM PST 24 Feb 04 01:14:25 PM PST 24 22353482 ps
T853 /workspace/coverage/default/46.lc_ctrl_alert_test.3151811708 Feb 04 01:15:58 PM PST 24 Feb 04 01:16:03 PM PST 24 20950751 ps
T854 /workspace/coverage/default/3.lc_ctrl_jtag_priority.4168409741 Feb 04 01:12:43 PM PST 24 Feb 04 01:12:58 PM PST 24 611516506 ps
T855 /workspace/coverage/default/45.lc_ctrl_sec_mubi.1728222347 Feb 04 01:15:56 PM PST 24 Feb 04 01:16:13 PM PST 24 914650325 ps
T856 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.166293344 Feb 04 01:13:43 PM PST 24 Feb 04 01:13:55 PM PST 24 505305567 ps
T857 /workspace/coverage/default/13.lc_ctrl_sec_mubi.933805788 Feb 04 01:14:12 PM PST 24 Feb 04 01:14:25 PM PST 24 2036207271 ps
T858 /workspace/coverage/default/31.lc_ctrl_state_failure.3539473950 Feb 04 01:15:08 PM PST 24 Feb 04 01:15:43 PM PST 24 1436768637 ps
T859 /workspace/coverage/default/19.lc_ctrl_state_post_trans.1023464380 Feb 04 01:14:17 PM PST 24 Feb 04 01:14:27 PM PST 24 226839522 ps
T860 /workspace/coverage/default/26.lc_ctrl_state_post_trans.4266865490 Feb 04 01:14:53 PM PST 24 Feb 04 01:15:02 PM PST 24 74963222 ps
T861 /workspace/coverage/default/5.lc_ctrl_jtag_errors.2748220673 Feb 04 01:13:22 PM PST 24 Feb 04 01:13:43 PM PST 24 2325651005 ps
T862 /workspace/coverage/default/29.lc_ctrl_smoke.4276325459 Feb 04 01:15:14 PM PST 24 Feb 04 01:15:18 PM PST 24 35567006 ps
T863 /workspace/coverage/default/48.lc_ctrl_jtag_access.572841828 Feb 04 01:16:03 PM PST 24 Feb 04 01:16:13 PM PST 24 525292343 ps
T864 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.4121736650 Feb 04 01:15:26 PM PST 24 Feb 04 01:15:34 PM PST 24 272493761 ps
T865 /workspace/coverage/default/27.lc_ctrl_jtag_access.2945846093 Feb 04 01:15:07 PM PST 24 Feb 04 01:15:13 PM PST 24 176548018 ps
T866 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3869373602 Feb 04 01:12:31 PM PST 24 Feb 04 01:13:06 PM PST 24 6302260615 ps
T867 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1260379117 Feb 04 01:14:47 PM PST 24 Feb 04 01:15:01 PM PST 24 633164021 ps
T868 /workspace/coverage/default/0.lc_ctrl_prog_failure.2241117465 Feb 04 01:12:17 PM PST 24 Feb 04 01:12:20 PM PST 24 475332871 ps
T869 /workspace/coverage/default/28.lc_ctrl_alert_test.1530480267 Feb 04 01:15:14 PM PST 24 Feb 04 01:15:17 PM PST 24 38346569 ps
T870 /workspace/coverage/default/48.lc_ctrl_state_failure.2334291382 Feb 04 01:15:49 PM PST 24 Feb 04 01:16:19 PM PST 24 235267607 ps
T871 /workspace/coverage/default/47.lc_ctrl_sec_mubi.3612273528 Feb 04 01:15:51 PM PST 24 Feb 04 01:16:15 PM PST 24 1492304825 ps
T872 /workspace/coverage/default/20.lc_ctrl_security_escalation.3944944787 Feb 04 01:14:26 PM PST 24 Feb 04 01:14:36 PM PST 24 479593221 ps
T873 /workspace/coverage/default/4.lc_ctrl_smoke.1878080645 Feb 04 01:13:15 PM PST 24 Feb 04 01:13:18 PM PST 24 163642669 ps
T874 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.60436204 Feb 04 01:14:29 PM PST 24 Feb 04 01:15:12 PM PST 24 2144651245 ps
T875 /workspace/coverage/default/36.lc_ctrl_alert_test.3139936355 Feb 04 01:15:35 PM PST 24 Feb 04 01:15:38 PM PST 24 17974842 ps
T876 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1525174555 Feb 04 01:13:23 PM PST 24 Feb 04 01:13:25 PM PST 24 32798981 ps
T877 /workspace/coverage/default/43.lc_ctrl_jtag_access.3165102416 Feb 04 01:15:34 PM PST 24 Feb 04 01:15:41 PM PST 24 657561225 ps
T878 /workspace/coverage/default/1.lc_ctrl_alert_test.1701405529 Feb 04 01:12:29 PM PST 24 Feb 04 01:12:31 PM PST 24 12224225 ps
T879 /workspace/coverage/default/23.lc_ctrl_smoke.283218901 Feb 04 01:14:37 PM PST 24 Feb 04 01:14:43 PM PST 24 109980865 ps
T880 /workspace/coverage/default/26.lc_ctrl_errors.178642648 Feb 04 01:14:53 PM PST 24 Feb 04 01:15:12 PM PST 24 296359024 ps
T881 /workspace/coverage/default/9.lc_ctrl_jtag_errors.861112075 Feb 04 01:13:40 PM PST 24 Feb 04 01:14:38 PM PST 24 9345400236 ps
T882 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3063334965 Feb 04 01:14:10 PM PST 24 Feb 04 01:14:13 PM PST 24 56744112 ps
T883 /workspace/coverage/default/44.lc_ctrl_smoke.191420737 Feb 04 01:15:46 PM PST 24 Feb 04 01:15:54 PM PST 24 981263810 ps
T74 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.660618683 Feb 04 01:14:02 PM PST 24 Feb 04 01:14:06 PM PST 24 85376710 ps
T884 /workspace/coverage/default/2.lc_ctrl_jtag_access.1741693875 Feb 04 01:12:48 PM PST 24 Feb 04 01:13:00 PM PST 24 407122114 ps
T885 /workspace/coverage/default/14.lc_ctrl_state_post_trans.1458409357 Feb 04 01:14:10 PM PST 24 Feb 04 01:14:19 PM PST 24 70513824 ps
T886 /workspace/coverage/default/37.lc_ctrl_jtag_access.2589950555 Feb 04 01:15:24 PM PST 24 Feb 04 01:15:33 PM PST 24 700595252 ps
T887 /workspace/coverage/default/1.lc_ctrl_smoke.387877482 Feb 04 01:12:25 PM PST 24 Feb 04 01:12:27 PM PST 24 33629299 ps
T888 /workspace/coverage/default/5.lc_ctrl_sec_mubi.1527664669 Feb 04 01:13:31 PM PST 24 Feb 04 01:13:46 PM PST 24 297711720 ps
T889 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3646665545 Feb 04 01:14:10 PM PST 24 Feb 04 01:14:13 PM PST 24 11470341 ps
T137 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3666737295 Feb 04 01:13:38 PM PST 24 Feb 04 01:14:22 PM PST 24 2956808517 ps
T890 /workspace/coverage/default/17.lc_ctrl_state_post_trans.2681464672 Feb 04 01:14:16 PM PST 24 Feb 04 01:14:22 PM PST 24 76741912 ps
T891 /workspace/coverage/default/22.lc_ctrl_stress_all.3609202929 Feb 04 01:14:38 PM PST 24 Feb 04 01:15:23 PM PST 24 1490354829 ps
T892 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.4029531107 Feb 04 01:13:24 PM PST 24 Feb 04 01:14:13 PM PST 24 1312921275 ps
T893 /workspace/coverage/default/31.lc_ctrl_jtag_access.3279129495 Feb 04 01:15:12 PM PST 24 Feb 04 01:15:15 PM PST 24 746133221 ps
T894 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3693339699 Feb 04 01:14:12 PM PST 24 Feb 04 01:14:21 PM PST 24 228910727 ps
T895 /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1693678552 Feb 04 01:13:40 PM PST 24 Feb 04 01:13:54 PM PST 24 637983837 ps
T896 /workspace/coverage/default/26.lc_ctrl_jtag_access.2388216820 Feb 04 01:14:49 PM PST 24 Feb 04 01:14:53 PM PST 24 163528981 ps
T897 /workspace/coverage/default/12.lc_ctrl_stress_all.1153831477 Feb 04 01:14:12 PM PST 24 Feb 04 01:14:51 PM PST 24 8496557900 ps
T898 /workspace/coverage/default/25.lc_ctrl_jtag_access.1898246419 Feb 04 01:14:45 PM PST 24 Feb 04 01:14:55 PM PST 24 2187137769 ps
T899 /workspace/coverage/default/19.lc_ctrl_state_failure.2224120545 Feb 04 01:14:29 PM PST 24 Feb 04 01:14:55 PM PST 24 183254518 ps
T900 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3563359512 Feb 04 01:14:18 PM PST 24 Feb 04 01:14:39 PM PST 24 1986786144 ps
T901 /workspace/coverage/default/38.lc_ctrl_smoke.266337037 Feb 04 01:15:48 PM PST 24 Feb 04 01:15:53 PM PST 24 97548577 ps
T902 /workspace/coverage/default/42.lc_ctrl_sec_mubi.3937064976 Feb 04 01:15:49 PM PST 24 Feb 04 01:16:08 PM PST 24 2730445566 ps
T903 /workspace/coverage/default/45.lc_ctrl_state_failure.1589855021 Feb 04 01:15:49 PM PST 24 Feb 04 01:16:21 PM PST 24 974000763 ps
T904 /workspace/coverage/default/1.lc_ctrl_sec_mubi.4071735945 Feb 04 01:12:30 PM PST 24 Feb 04 01:12:48 PM PST 24 1274501649 ps
T905 /workspace/coverage/default/1.lc_ctrl_state_post_trans.214946463 Feb 04 01:12:26 PM PST 24 Feb 04 01:12:37 PM PST 24 247796844 ps
T906 /workspace/coverage/default/48.lc_ctrl_sec_mubi.628474955 Feb 04 01:16:03 PM PST 24 Feb 04 01:16:14 PM PST 24 257158618 ps
T907 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2272601478 Feb 04 01:13:40 PM PST 24 Feb 04 01:13:55 PM PST 24 324549805 ps
T908 /workspace/coverage/default/32.lc_ctrl_smoke.3358939045 Feb 04 01:15:18 PM PST 24 Feb 04 01:15:20 PM PST 24 104034035 ps
T909 /workspace/coverage/default/41.lc_ctrl_state_post_trans.2498075550 Feb 04 01:15:49 PM PST 24 Feb 04 01:15:56 PM PST 24 59103922 ps
T910 /workspace/coverage/default/14.lc_ctrl_errors.3629013595 Feb 04 01:14:19 PM PST 24 Feb 04 01:14:31 PM PST 24 1166403131 ps
T911 /workspace/coverage/default/43.lc_ctrl_smoke.2323875341 Feb 04 01:15:37 PM PST 24 Feb 04 01:15:40 PM PST 24 32261953 ps
T912 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3471701220 Feb 04 01:14:13 PM PST 24 Feb 04 01:14:17 PM PST 24 131108688 ps
T913 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.518281443 Feb 04 01:13:22 PM PST 24 Feb 04 01:13:40 PM PST 24 1298728091 ps
T914 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3163782192 Feb 04 01:14:13 PM PST 24 Feb 04 01:14:21 PM PST 24 863250951 ps
T915 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.579309726 Feb 04 01:12:34 PM PST 24 Feb 04 01:12:43 PM PST 24 148734834 ps
T916 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3984290970 Feb 04 01:12:37 PM PST 24 Feb 04 01:14:07 PM PST 24 6008683613 ps
T917 /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.72832470 Feb 04 01:13:45 PM PST 24 Feb 04 01:13:48 PM PST 24 18613339 ps
T918 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2772363134 Feb 04 01:15:47 PM PST 24 Feb 04 01:16:03 PM PST 24 279262536 ps
T919 /workspace/coverage/default/11.lc_ctrl_state_failure.174487034 Feb 04 01:14:08 PM PST 24 Feb 04 01:14:37 PM PST 24 546329992 ps
T920 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2095466620 Feb 04 01:15:36 PM PST 24 Feb 04 01:15:51 PM PST 24 2275337603 ps
T921 /workspace/coverage/default/0.lc_ctrl_alert_test.440473651 Feb 04 01:12:26 PM PST 24 Feb 04 01:12:28 PM PST 24 53174944 ps
T922 /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.356015706 Feb 04 01:14:05 PM PST 24 Feb 04 01:15:02 PM PST 24 2475105537 ps
T923 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2284933140 Feb 04 01:14:06 PM PST 24 Feb 04 01:14:18 PM PST 24 1291260450 ps
T924 /workspace/coverage/default/15.lc_ctrl_state_post_trans.2191812576 Feb 04 01:14:23 PM PST 24 Feb 04 01:14:33 PM PST 24 66699646 ps
T925 /workspace/coverage/default/46.lc_ctrl_stress_all.3141761062 Feb 04 01:15:52 PM PST 24 Feb 04 01:17:20 PM PST 24 7535473231 ps
T926 /workspace/coverage/default/21.lc_ctrl_jtag_access.3488685371 Feb 04 01:14:45 PM PST 24 Feb 04 01:14:51 PM PST 24 169720148 ps
T927 /workspace/coverage/default/11.lc_ctrl_errors.3573528667 Feb 04 01:14:22 PM PST 24 Feb 04 01:14:32 PM PST 24 2549424699 ps
T928 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3511461775 Feb 04 01:14:51 PM PST 24 Feb 04 01:14:59 PM PST 24 32649380 ps
T929 /workspace/coverage/default/10.lc_ctrl_errors.2045422414 Feb 04 01:13:54 PM PST 24 Feb 04 01:14:02 PM PST 24 383874045 ps
T930 /workspace/coverage/default/16.lc_ctrl_jtag_access.1879016513 Feb 04 01:14:12 PM PST 24 Feb 04 01:14:16 PM PST 24 295476038 ps
T931 /workspace/coverage/default/32.lc_ctrl_sec_mubi.1664437675 Feb 04 01:15:18 PM PST 24 Feb 04 01:15:34 PM PST 24 983593830 ps
T932 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.640021199 Feb 04 01:14:11 PM PST 24 Feb 04 01:14:43 PM PST 24 5124857848 ps
T933 /workspace/coverage/default/6.lc_ctrl_sec_mubi.4131759091 Feb 04 01:13:21 PM PST 24 Feb 04 01:13:37 PM PST 24 702431449 ps
T934 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.749526924 Feb 04 01:14:16 PM PST 24 Feb 04 01:14:44 PM PST 24 2489805307 ps
T935 /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3396876187 Feb 04 01:13:40 PM PST 24 Feb 04 01:13:52 PM PST 24 1162128108 ps
T936 /workspace/coverage/default/20.lc_ctrl_jtag_access.3365374208 Feb 04 01:14:25 PM PST 24 Feb 04 01:14:29 PM PST 24 644288393 ps
T937 /workspace/coverage/default/1.lc_ctrl_stress_all.1258754254 Feb 04 01:12:38 PM PST 24 Feb 04 01:13:33 PM PST 24 3365527319 ps
T938 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.739842407 Feb 04 01:14:41 PM PST 24 Feb 04 01:14:43 PM PST 24 33511394 ps
T939 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1263603467 Feb 04 01:15:15 PM PST 24 Feb 04 01:15:29 PM PST 24 510191185 ps
T940 /workspace/coverage/default/42.lc_ctrl_errors.3459260570 Feb 04 01:15:30 PM PST 24 Feb 04 01:15:47 PM PST 24 509323756 ps
T941 /workspace/coverage/default/44.lc_ctrl_sec_mubi.1647666463 Feb 04 01:15:45 PM PST 24 Feb 04 01:16:07 PM PST 24 2605055981 ps
T942 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2811609055 Feb 04 01:14:27 PM PST 24 Feb 04 01:14:39 PM PST 24 330586472 ps
T943 /workspace/coverage/default/14.lc_ctrl_alert_test.2832633182 Feb 04 01:14:21 PM PST 24 Feb 04 01:14:23 PM PST 24 18708446 ps
T115 /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2358522523 Feb 04 01:12:51 PM PST 24 Feb 04 01:15:45 PM PST 24 7926826337 ps
T116 /workspace/coverage/default/23.lc_ctrl_sec_mubi.2061637096 Feb 04 01:14:40 PM PST 24 Feb 04 01:14:52 PM PST 24 1138621886 ps
T117 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3027240051 Feb 04 01:13:24 PM PST 24 Feb 04 01:13:38 PM PST 24 311831702 ps
T118 /workspace/coverage/default/35.lc_ctrl_state_post_trans.2832546897 Feb 04 01:15:20 PM PST 24 Feb 04 01:15:30 PM PST 24 98441253 ps
T119 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.418979032 Feb 04 01:13:20 PM PST 24 Feb 04 01:13:31 PM PST 24 3030772281 ps
T120 /workspace/coverage/default/17.lc_ctrl_smoke.472238480 Feb 04 01:14:16 PM PST 24 Feb 04 01:14:24 PM PST 24 366649498 ps
T121 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2734874445 Feb 04 01:15:43 PM PST 24 Feb 04 01:15:45 PM PST 24 34827391 ps
T122 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1186527509 Feb 04 01:15:07 PM PST 24 Feb 04 01:15:22 PM PST 24 342805366 ps
T123 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3192368870 Feb 04 01:14:40 PM PST 24 Feb 04 01:14:52 PM PST 24 4342324667 ps
T124 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2377153083 Feb 04 01:15:11 PM PST 24 Feb 04 01:15:26 PM PST 24 7708461946 ps
T944 /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.351821887 Feb 04 01:13:20 PM PST 24 Feb 04 01:14:32 PM PST 24 1673231179 ps
T945 /workspace/coverage/default/40.lc_ctrl_smoke.3709133791 Feb 04 01:15:40 PM PST 24 Feb 04 01:15:43 PM PST 24 122371574 ps
T946 /workspace/coverage/default/14.lc_ctrl_prog_failure.1505974424 Feb 04 01:14:23 PM PST 24 Feb 04 01:14:27 PM PST 24 233348896 ps
T947 /workspace/coverage/default/3.lc_ctrl_errors.87628470 Feb 04 01:12:52 PM PST 24 Feb 04 01:13:12 PM PST 24 435901129 ps
T948 /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1576078584 Feb 04 01:15:07 PM PST 24 Feb 04 01:15:10 PM PST 24 18080198 ps
T949 /workspace/coverage/default/29.lc_ctrl_jtag_access.3196556077 Feb 04 01:15:15 PM PST 24 Feb 04 01:15:21 PM PST 24 536556158 ps
T950 /workspace/coverage/default/15.lc_ctrl_sec_mubi.2801184524 Feb 04 01:14:12 PM PST 24 Feb 04 01:14:25 PM PST 24 204561999 ps
T192 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.4052049182 Feb 04 01:13:29 PM PST 24 Feb 04 01:13:32 PM PST 24 18687049 ps
T951 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1158958082 Feb 04 01:14:34 PM PST 24 Feb 04 01:14:41 PM PST 24 12897179 ps
T952 /workspace/coverage/default/24.lc_ctrl_sec_mubi.1872282549 Feb 04 01:14:53 PM PST 24 Feb 04 01:15:13 PM PST 24 1626681456 ps
T953 /workspace/coverage/default/30.lc_ctrl_state_post_trans.3189383949 Feb 04 01:15:06 PM PST 24 Feb 04 01:15:11 PM PST 24 604458685 ps
T954 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1452261291 Feb 04 01:15:31 PM PST 24 Feb 04 01:15:36 PM PST 24 33906329 ps
T955 /workspace/coverage/default/34.lc_ctrl_sec_mubi.4262127035 Feb 04 01:15:23 PM PST 24 Feb 04 01:15:38 PM PST 24 1055188434 ps
T956 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3963508272 Feb 04 01:13:20 PM PST 24 Feb 04 01:13:35 PM PST 24 809974540 ps
T957 /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.926219546 Feb 04 01:14:15 PM PST 24 Feb 04 01:15:03 PM PST 24 2148231321 ps
T958 /workspace/coverage/default/28.lc_ctrl_errors.861064875 Feb 04 01:15:00 PM PST 24 Feb 04 01:15:16 PM PST 24 347825132 ps
T959 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1622160368 Feb 04 01:13:40 PM PST 24 Feb 04 01:14:06 PM PST 24 795689692 ps
T960 /workspace/coverage/default/7.lc_ctrl_sec_mubi.2026267337 Feb 04 01:13:42 PM PST 24 Feb 04 01:14:05 PM PST 24 1939206966 ps
T961 /workspace/coverage/default/24.lc_ctrl_prog_failure.3313240298 Feb 04 01:14:49 PM PST 24 Feb 04 01:14:54 PM PST 24 203570523 ps
T962 /workspace/coverage/default/6.lc_ctrl_security_escalation.3611087334 Feb 04 01:13:19 PM PST 24 Feb 04 01:13:31 PM PST 24 486122976 ps
T963 /workspace/coverage/default/0.lc_ctrl_sec_mubi.1738766921 Feb 04 01:12:20 PM PST 24 Feb 04 01:12:32 PM PST 24 656904977 ps
T964 /workspace/coverage/default/8.lc_ctrl_prog_failure.3974957515 Feb 04 01:13:37 PM PST 24 Feb 04 01:13:41 PM PST 24 256903624 ps
T965 /workspace/coverage/default/46.lc_ctrl_prog_failure.4224605627 Feb 04 01:15:50 PM PST 24 Feb 04 01:15:57 PM PST 24 272606086 ps
T966 /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2628737747 Feb 04 01:14:58 PM PST 24 Feb 04 01:15:02 PM PST 24 12648174 ps
T967 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.998722053 Feb 04 01:12:52 PM PST 24 Feb 04 01:13:01 PM PST 24 285341929 ps
T968 /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2600991682 Feb 04 01:14:26 PM PST 24 Feb 04 01:14:36 PM PST 24 239787799 ps
T969 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2625603389 Feb 04 01:14:42 PM PST 24 Feb 04 01:14:44 PM PST 24 19228867 ps
T970 /workspace/coverage/default/9.lc_ctrl_security_escalation.953305771 Feb 04 01:13:38 PM PST 24 Feb 04 01:13:47 PM PST 24 214938265 ps
T971 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1289504844 Feb 04 01:13:37 PM PST 24 Feb 04 01:13:43 PM PST 24 117596572 ps
T972 /workspace/coverage/default/33.lc_ctrl_state_post_trans.4281825504 Feb 04 01:15:14 PM PST 24 Feb 04 01:15:24 PM PST 24 130540935 ps
T973 /workspace/coverage/default/15.lc_ctrl_prog_failure.3605543384 Feb 04 01:14:22 PM PST 24 Feb 04 01:14:27 PM PST 24 296039515 ps
T974 /workspace/coverage/default/13.lc_ctrl_errors.1907615048 Feb 04 01:14:09 PM PST 24 Feb 04 01:14:19 PM PST 24 368034880 ps
T975 /workspace/coverage/default/6.lc_ctrl_stress_all.3858934048 Feb 04 01:13:23 PM PST 24 Feb 04 01:14:57 PM PST 24 4112207860 ps
T976 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.849062080 Feb 04 01:14:09 PM PST 24 Feb 04 01:14:26 PM PST 24 1365202995 ps
T977 /workspace/coverage/default/39.lc_ctrl_stress_all.2352930973 Feb 04 01:15:34 PM PST 24 Feb 04 01:17:20 PM PST 24 3741663711 ps
T978 /workspace/coverage/default/31.lc_ctrl_sec_mubi.1185500025 Feb 04 01:15:17 PM PST 24 Feb 04 01:15:29 PM PST 24 460177503 ps
T979 /workspace/coverage/default/29.lc_ctrl_state_failure.607046424 Feb 04 01:15:10 PM PST 24 Feb 04 01:15:32 PM PST 24 817185880 ps
T980 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4015903182 Feb 04 12:35:59 PM PST 24 Feb 04 12:36:12 PM PST 24 2558875070 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2161385848 Feb 04 12:36:01 PM PST 24 Feb 04 12:36:12 PM PST 24 409567822 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2083048345 Feb 04 12:36:24 PM PST 24 Feb 04 12:36:36 PM PST 24 348301183 ps

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.571335406
Short name T60
Test name
Test status
Simulation time 35068869 ps
CPU time 1.31 seconds
Started Feb 04 12:35:54 PM PST 24
Finished Feb 04 12:36:01 PM PST 24
Peak memory 209004 kb
Host smart-a5f4d9e4-2d85-491c-a95a-424c72ed65c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571335406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.571335406
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.136570290
Short name T5
Test name
Test status
Simulation time 1428614167 ps
CPU time 10.64 seconds
Started Feb 04 01:14:47 PM PST 24
Finished Feb 04 01:15:01 PM PST 24
Peak memory 217844 kb
Host smart-fede0975-4d24-4603-9b0a-bd6798301488
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136570290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.136570290
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1446170587
Short name T94
Test name
Test status
Simulation time 39408373 ps
CPU time 1.28 seconds
Started Feb 04 12:36:00 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 218384 kb
Host smart-e2d859b9-1784-46a9-8728-a97f31c20095
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144617
0587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1446170587
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3557187769
Short name T21
Test name
Test status
Simulation time 97904739717 ps
CPU time 353.02 seconds
Started Feb 04 01:15:37 PM PST 24
Finished Feb 04 01:21:31 PM PST 24
Peak memory 282640 kb
Host smart-82bd5068-d7de-4957-9ebb-6628618ca31e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557187769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3557187769
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2355485652
Short name T92
Test name
Test status
Simulation time 88301069 ps
CPU time 1.86 seconds
Started Feb 04 12:36:46 PM PST 24
Finished Feb 04 12:36:51 PM PST 24
Peak memory 217340 kb
Host smart-6a970b61-6a78-4cc9-b45f-ca274d16597e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355485652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2355485652
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2782500287
Short name T100
Test name
Test status
Simulation time 314829661 ps
CPU time 1.64 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 210304 kb
Host smart-2fe845e1-f597-4f22-acd8-43731beb6c15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782500287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2782500287
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2380675756
Short name T14
Test name
Test status
Simulation time 1351357899 ps
CPU time 11.53 seconds
Started Feb 04 01:14:30 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 217768 kb
Host smart-d6af3175-63ed-43f7-8f03-8d9f006c4442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380675756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2380675756
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2314729303
Short name T39
Test name
Test status
Simulation time 38143553014 ps
CPU time 162.57 seconds
Started Feb 04 01:15:51 PM PST 24
Finished Feb 04 01:18:41 PM PST 24
Peak memory 267972 kb
Host smart-d7bc62c7-217b-4164-8bb3-50f469d1f085
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314729303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2314729303
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.521511641
Short name T139
Test name
Test status
Simulation time 183127912 ps
CPU time 4.05 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:21 PM PST 24
Peak memory 217232 kb
Host smart-005740bb-aef2-4a60-a837-e5a487fb6e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521511641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.521511641
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.573536910
Short name T51
Test name
Test status
Simulation time 6162637891 ps
CPU time 216.11 seconds
Started Feb 04 01:15:55 PM PST 24
Finished Feb 04 01:19:38 PM PST 24
Peak memory 273140 kb
Host smart-265815d5-8362-44ac-a730-51ae38e669b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573536910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.573536910
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2382421758
Short name T31
Test name
Test status
Simulation time 32669984 ps
CPU time 0.77 seconds
Started Feb 04 01:15:05 PM PST 24
Finished Feb 04 01:15:09 PM PST 24
Peak memory 208088 kb
Host smart-6c28f941-b04b-4f8c-873b-447c3f16b3d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382421758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2382421758
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3455225083
Short name T46
Test name
Test status
Simulation time 1028708209 ps
CPU time 8.3 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:25 PM PST 24
Peak memory 217848 kb
Host smart-a277c54b-eb97-4121-8416-71e6726d0134
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455225083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3455225083
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.258038334
Short name T109
Test name
Test status
Simulation time 89769331 ps
CPU time 1.27 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:54 PM PST 24
Peak memory 219064 kb
Host smart-164d7201-ab35-45a4-88b1-7748c7f561c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258038334 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.258038334
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4261370770
Short name T3
Test name
Test status
Simulation time 393059424 ps
CPU time 27.66 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:15:27 PM PST 24
Peak memory 250852 kb
Host smart-2221269d-58e8-472b-81af-f30c3e955c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261370770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4261370770
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3305887176
Short name T66
Test name
Test status
Simulation time 401134010 ps
CPU time 32.73 seconds
Started Feb 04 01:13:11 PM PST 24
Finished Feb 04 01:13:45 PM PST 24
Peak memory 284204 kb
Host smart-7478cd50-5be5-4ef3-9b02-e1387ae16142
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305887176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3305887176
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.340260360
Short name T106
Test name
Test status
Simulation time 456986492 ps
CPU time 2.85 seconds
Started Feb 04 12:35:55 PM PST 24
Finished Feb 04 12:36:03 PM PST 24
Peak memory 221616 kb
Host smart-146256b3-28ef-4a4a-9d80-4fa3a36ce46c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340260360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.340260360
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3825396038
Short name T194
Test name
Test status
Simulation time 304725537 ps
CPU time 12.45 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:29 PM PST 24
Peak memory 217860 kb
Host smart-8d81fb59-b6d9-4e3a-9cf3-3173c25e1a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825396038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3825396038
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.271404414
Short name T315
Test name
Test status
Simulation time 65571253 ps
CPU time 1.09 seconds
Started Feb 04 01:14:09 PM PST 24
Finished Feb 04 01:14:11 PM PST 24
Peak memory 208232 kb
Host smart-6c171208-971e-46ca-9e2f-438e8ad962b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271404414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.271404414
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2073581653
Short name T1
Test name
Test status
Simulation time 690921282 ps
CPU time 6.83 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:16 PM PST 24
Peak memory 208892 kb
Host smart-ebd411b7-2ea0-4833-bd2b-c70f5c92fe1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073581653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.2073581653
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1128685275
Short name T58
Test name
Test status
Simulation time 9285726589 ps
CPU time 275.68 seconds
Started Feb 04 01:13:43 PM PST 24
Finished Feb 04 01:18:22 PM PST 24
Peak memory 259112 kb
Host smart-0b2731db-a58d-4394-882d-5d619cec0608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128685275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1128685275
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1198620
Short name T101
Test name
Test status
Simulation time 60365109 ps
CPU time 2.62 seconds
Started Feb 04 12:36:43 PM PST 24
Finished Feb 04 12:36:48 PM PST 24
Peak memory 217404 kb
Host smart-51d0058b-160c-46ca-9237-7ced84b7d2bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_er
r.1198620
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3068431589
Short name T143
Test name
Test status
Simulation time 399569918 ps
CPU time 2.94 seconds
Started Feb 04 12:36:35 PM PST 24
Finished Feb 04 12:36:42 PM PST 24
Peak memory 221280 kb
Host smart-aff05cee-1124-47dc-941d-bade354f3e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068431589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3068431589
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2616076399
Short name T368
Test name
Test status
Simulation time 11832939498 ps
CPU time 123.27 seconds
Started Feb 04 01:13:38 PM PST 24
Finished Feb 04 01:15:43 PM PST 24
Peak memory 283704 kb
Host smart-a7404a51-73f8-48d5-84e4-d01db7dfd7d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616076399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2616076399
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2494109157
Short name T112
Test name
Test status
Simulation time 34594093 ps
CPU time 1.27 seconds
Started Feb 04 12:35:53 PM PST 24
Finished Feb 04 12:36:01 PM PST 24
Peak memory 210792 kb
Host smart-30c0a2be-6e65-4445-a50e-2f01c44c3c70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494109157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2494109157
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3985511164
Short name T33
Test name
Test status
Simulation time 95343437 ps
CPU time 1 seconds
Started Feb 04 01:13:43 PM PST 24
Finished Feb 04 01:13:48 PM PST 24
Peak memory 211248 kb
Host smart-280ec757-0169-4913-a6ee-8a210562a70a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985511164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3985511164
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3666737295
Short name T137
Test name
Test status
Simulation time 2956808517 ps
CPU time 42.49 seconds
Started Feb 04 01:13:38 PM PST 24
Finished Feb 04 01:14:22 PM PST 24
Peak memory 275664 kb
Host smart-1c3d3adb-111a-4547-8e5c-8bb9a4ec7e0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666737295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3666737295
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.4282037660
Short name T357
Test name
Test status
Simulation time 130368748 ps
CPU time 0.71 seconds
Started Feb 04 01:12:27 PM PST 24
Finished Feb 04 01:12:29 PM PST 24
Peak memory 207952 kb
Host smart-8e9de290-ce83-4c82-8d40-9f669c00397c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282037660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.4282037660
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4058799873
Short name T180
Test name
Test status
Simulation time 150132385 ps
CPU time 0.82 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:49 PM PST 24
Peak memory 208308 kb
Host smart-c2d2b2c3-e309-44ef-b573-2db5c6f3f2a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058799873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.4058799873
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2358522523
Short name T115
Test name
Test status
Simulation time 7926826337 ps
CPU time 173.49 seconds
Started Feb 04 01:12:51 PM PST 24
Finished Feb 04 01:15:45 PM PST 24
Peak memory 277732 kb
Host smart-931de68a-78f5-4290-8eb3-ed73657dae3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2358522523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2358522523
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2029961091
Short name T140
Test name
Test status
Simulation time 48856205 ps
CPU time 1.81 seconds
Started Feb 04 12:35:56 PM PST 24
Finished Feb 04 12:36:05 PM PST 24
Peak memory 221152 kb
Host smart-56d9aced-6fe4-41af-b029-643e2d377780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029961091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2029961091
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2348428097
Short name T147
Test name
Test status
Simulation time 310789856 ps
CPU time 2.48 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 217228 kb
Host smart-ae4839b7-6e0c-467b-9e78-8a9d727f2b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348428097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2348428097
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4100502320
Short name T142
Test name
Test status
Simulation time 95304277 ps
CPU time 3.35 seconds
Started Feb 04 12:36:42 PM PST 24
Finished Feb 04 12:36:48 PM PST 24
Peak memory 217304 kb
Host smart-6aa7bf15-cd2d-4d39-85e9-32698cf5ec85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100502320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4100502320
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.65768273
Short name T150
Test name
Test status
Simulation time 415061684 ps
CPU time 2.89 seconds
Started Feb 04 12:36:46 PM PST 24
Finished Feb 04 12:36:52 PM PST 24
Peak memory 221160 kb
Host smart-67389c42-4339-4980-959b-91505dfbb216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65768273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_e
rr.65768273
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.165567737
Short name T151
Test name
Test status
Simulation time 61142918 ps
CPU time 2.47 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:15 PM PST 24
Peak memory 217248 kb
Host smart-9f562d14-aa93-4a79-aaa7-11fceb96e7ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165567737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.165567737
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1861618261
Short name T188
Test name
Test status
Simulation time 22430227 ps
CPU time 0.77 seconds
Started Feb 04 01:12:16 PM PST 24
Finished Feb 04 01:12:18 PM PST 24
Peak memory 209272 kb
Host smart-eeb6292d-6f3c-44d9-a598-b2fa0190ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861618261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1861618261
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1670070531
Short name T191
Test name
Test status
Simulation time 13245486 ps
CPU time 0.91 seconds
Started Feb 04 01:12:37 PM PST 24
Finished Feb 04 01:12:41 PM PST 24
Peak memory 209280 kb
Host smart-66bae79e-a913-44c0-a474-fcd033fb0f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670070531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1670070531
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3807117047
Short name T190
Test name
Test status
Simulation time 33208159 ps
CPU time 0.86 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:24 PM PST 24
Peak memory 209448 kb
Host smart-6c47d74c-048a-4d41-bd5e-cbf91fb57d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807117047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3807117047
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1247571787
Short name T18
Test name
Test status
Simulation time 6302301231 ps
CPU time 22.96 seconds
Started Feb 04 01:12:35 PM PST 24
Finished Feb 04 01:13:03 PM PST 24
Peak memory 250792 kb
Host smart-6f510880-54a4-4abf-8310-e922b007b3a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247571787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1247571787
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4021519214
Short name T110
Test name
Test status
Simulation time 64803058 ps
CPU time 2.67 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:51 PM PST 24
Peak memory 217324 kb
Host smart-3fe81797-7451-4d17-9972-d67086bb688a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021519214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.4021519214
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1957020746
Short name T102
Test name
Test status
Simulation time 72781430 ps
CPU time 1.87 seconds
Started Feb 04 12:36:38 PM PST 24
Finished Feb 04 12:36:41 PM PST 24
Peak memory 221400 kb
Host smart-446ea679-ef7c-44ee-88af-a958820b6cac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957020746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1957020746
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1738631283
Short name T145
Test name
Test status
Simulation time 147808799 ps
CPU time 2.12 seconds
Started Feb 04 12:36:00 PM PST 24
Finished Feb 04 12:36:10 PM PST 24
Peak memory 221044 kb
Host smart-bae60b88-2b85-46fe-9858-33ff325c7faf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738631283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1738631283
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4260297629
Short name T144
Test name
Test status
Simulation time 69216957 ps
CPU time 2.51 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 217124 kb
Host smart-e6dbf50e-04d9-4406-b5dc-184b8f520d77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260297629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4260297629
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.696628755
Short name T105
Test name
Test status
Simulation time 109516220 ps
CPU time 3.53 seconds
Started Feb 04 12:36:24 PM PST 24
Finished Feb 04 12:36:30 PM PST 24
Peak memory 217320 kb
Host smart-bfec84d9-77fc-4d82-af61-600630a911cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696628755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.696628755
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3086169929
Short name T113
Test name
Test status
Simulation time 341379546 ps
CPU time 4.2 seconds
Started Feb 04 12:36:13 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 208948 kb
Host smart-c2eb6f2d-f56c-4f1a-b1cf-65d5ed248507
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086169929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3086169929
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.2514048545
Short name T135
Test name
Test status
Simulation time 375631161798 ps
CPU time 911.43 seconds
Started Feb 04 01:15:53 PM PST 24
Finished Feb 04 01:31:12 PM PST 24
Peak memory 372680 kb
Host smart-32a83146-084f-4574-a7a0-be6b772acfe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2514048545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.2514048545
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.190107529
Short name T154
Test name
Test status
Simulation time 178951520 ps
CPU time 1.13 seconds
Started Feb 04 12:35:58 PM PST 24
Finished Feb 04 12:36:06 PM PST 24
Peak memory 208924 kb
Host smart-74083228-d9af-4f59-be56-3e872ddcf34b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190107529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.190107529
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.606250446
Short name T268
Test name
Test status
Simulation time 35564117 ps
CPU time 1.25 seconds
Started Feb 04 12:35:49 PM PST 24
Finished Feb 04 12:35:59 PM PST 24
Peak memory 208744 kb
Host smart-94ff65bd-7dcf-4fbd-9a2c-ebe53646e41b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606250446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.606250446
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.701683992
Short name T231
Test name
Test status
Simulation time 596904025 ps
CPU time 1.19 seconds
Started Feb 04 12:35:49 PM PST 24
Finished Feb 04 12:35:58 PM PST 24
Peak memory 209152 kb
Host smart-b12e73d8-6516-422e-91cc-223d6f51129e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701683992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.701683992
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2628131974
Short name T173
Test name
Test status
Simulation time 59832161 ps
CPU time 1.05 seconds
Started Feb 04 12:35:46 PM PST 24
Finished Feb 04 12:35:56 PM PST 24
Peak memory 210980 kb
Host smart-21183f16-f5b7-481e-bfa3-f14c5ec268bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628131974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2628131974
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4053996659
Short name T206
Test name
Test status
Simulation time 15129723 ps
CPU time 0.99 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 209200 kb
Host smart-00297183-959a-4ad9-b86d-37bcf652cfd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053996659 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4053996659
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2884948282
Short name T164
Test name
Test status
Simulation time 30951222 ps
CPU time 0.87 seconds
Started Feb 04 12:35:54 PM PST 24
Finished Feb 04 12:36:01 PM PST 24
Peak memory 208708 kb
Host smart-e61ee74b-faeb-4454-b951-3c8ed3ead89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884948282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2884948282
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2501886954
Short name T253
Test name
Test status
Simulation time 713018092 ps
CPU time 15.46 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:28 PM PST 24
Peak memory 207904 kb
Host smart-20fce1a7-dec7-41fa-a07a-334133bca621
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501886954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2501886954
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2959495270
Short name T291
Test name
Test status
Simulation time 1077216087 ps
CPU time 11.87 seconds
Started Feb 04 12:35:46 PM PST 24
Finished Feb 04 12:36:06 PM PST 24
Peak memory 208952 kb
Host smart-2c8cd603-5bb0-474e-b6f1-94e00083e946
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959495270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2959495270
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3816346710
Short name T250
Test name
Test status
Simulation time 105857845 ps
CPU time 2.98 seconds
Started Feb 04 12:35:58 PM PST 24
Finished Feb 04 12:36:08 PM PST 24
Peak memory 210376 kb
Host smart-027327c0-dd72-4339-9d66-8e618a14bd1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816346710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3816346710
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3582810921
Short name T307
Test name
Test status
Simulation time 218448558 ps
CPU time 2.42 seconds
Started Feb 04 12:35:58 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 222068 kb
Host smart-b255d6e2-04d0-4a8e-99ee-c93f82db48fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358281
0921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3582810921
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2255831702
Short name T152
Test name
Test status
Simulation time 72988767 ps
CPU time 1.07 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 208788 kb
Host smart-c7173da8-9138-4c8b-9e40-013d30df1924
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255831702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2255831702
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4181299087
Short name T187
Test name
Test status
Simulation time 172345732 ps
CPU time 1.37 seconds
Started Feb 04 12:35:59 PM PST 24
Finished Feb 04 12:36:08 PM PST 24
Peak memory 208928 kb
Host smart-929df4ee-9fe9-420c-8cd8-3c3c95f94ea2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181299087 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.4181299087
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4064830253
Short name T215
Test name
Test status
Simulation time 48981921 ps
CPU time 1.32 seconds
Started Feb 04 12:35:49 PM PST 24
Finished Feb 04 12:35:59 PM PST 24
Peak memory 208852 kb
Host smart-39a81817-09fd-4865-ad45-d0c90710308e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064830253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.4064830253
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1944592761
Short name T184
Test name
Test status
Simulation time 69044743 ps
CPU time 1.47 seconds
Started Feb 04 12:35:54 PM PST 24
Finished Feb 04 12:36:01 PM PST 24
Peak memory 218392 kb
Host smart-640a6e5c-5c68-4693-b9f1-1a4f40a51128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944592761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1944592761
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1464271826
Short name T269
Test name
Test status
Simulation time 218324260 ps
CPU time 1.22 seconds
Started Feb 04 12:35:58 PM PST 24
Finished Feb 04 12:36:07 PM PST 24
Peak memory 208436 kb
Host smart-9c905920-9b0a-4bbb-8ea1-ea8a9f065a42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464271826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1464271826
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2446456892
Short name T261
Test name
Test status
Simulation time 48603719 ps
CPU time 1.78 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 207624 kb
Host smart-54bacc01-b766-4163-b788-e27ed5e560d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446456892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2446456892
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3660109111
Short name T241
Test name
Test status
Simulation time 20304991 ps
CPU time 0.86 seconds
Started Feb 04 12:36:03 PM PST 24
Finished Feb 04 12:36:12 PM PST 24
Peak memory 208972 kb
Host smart-bb7881ff-8ca2-4f20-bb54-36f6315f5507
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660109111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3660109111
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3496934497
Short name T221
Test name
Test status
Simulation time 269447263 ps
CPU time 1.69 seconds
Started Feb 04 12:35:57 PM PST 24
Finished Feb 04 12:36:06 PM PST 24
Peak memory 217872 kb
Host smart-f38cb04d-0d65-4f94-b01d-af4c00edef39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496934497 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3496934497
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.940397085
Short name T280
Test name
Test status
Simulation time 15717970 ps
CPU time 0.83 seconds
Started Feb 04 12:35:56 PM PST 24
Finished Feb 04 12:36:04 PM PST 24
Peak memory 208000 kb
Host smart-5ac9da5d-0207-4581-8dd6-28fa3056ffb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940397085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.940397085
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1182783301
Short name T239
Test name
Test status
Simulation time 82058100 ps
CPU time 1.12 seconds
Started Feb 04 12:35:54 PM PST 24
Finished Feb 04 12:36:01 PM PST 24
Peak memory 208776 kb
Host smart-a4b1497c-9286-42e6-bd62-79d0af031450
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182783301 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1182783301
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1904378161
Short name T202
Test name
Test status
Simulation time 3415531065 ps
CPU time 6.21 seconds
Started Feb 04 12:35:56 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 207952 kb
Host smart-0af571a8-b336-4a9f-b3f5-7969e5cdd3f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904378161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1904378161
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.357515374
Short name T86
Test name
Test status
Simulation time 952591310 ps
CPU time 21.43 seconds
Started Feb 04 12:35:57 PM PST 24
Finished Feb 04 12:36:26 PM PST 24
Peak memory 208044 kb
Host smart-ef354453-8bda-40ff-bb37-9c64e2c155dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357515374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.357515374
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4286566565
Short name T217
Test name
Test status
Simulation time 58011535 ps
CPU time 1.25 seconds
Started Feb 04 12:35:54 PM PST 24
Finished Feb 04 12:36:02 PM PST 24
Peak memory 209872 kb
Host smart-9bdb5fcf-3860-49bc-8735-41cafd579118
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286566565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.4286566565
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2495106063
Short name T300
Test name
Test status
Simulation time 120643108 ps
CPU time 2.21 seconds
Started Feb 04 12:36:00 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 217232 kb
Host smart-5176eec3-4396-489a-ad35-725ed6c2f5bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249510
6063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2495106063
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1865003553
Short name T282
Test name
Test status
Simulation time 83497265 ps
CPU time 1.4 seconds
Started Feb 04 12:35:55 PM PST 24
Finished Feb 04 12:36:03 PM PST 24
Peak memory 208888 kb
Host smart-470fe7fc-06a4-4ff0-9187-7f8c864381a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865003553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1865003553
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3090097362
Short name T277
Test name
Test status
Simulation time 60875192 ps
CPU time 0.94 seconds
Started Feb 04 12:35:55 PM PST 24
Finished Feb 04 12:36:02 PM PST 24
Peak memory 209040 kb
Host smart-b509c30d-a17f-491d-8bed-e6be1a76e602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090097362 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3090097362
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2657210216
Short name T88
Test name
Test status
Simulation time 25323751 ps
CPU time 1.11 seconds
Started Feb 04 12:35:57 PM PST 24
Finished Feb 04 12:36:06 PM PST 24
Peak memory 209036 kb
Host smart-d1709cd4-4056-4556-b552-c6ae4bbdaf5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657210216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2657210216
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2058054721
Short name T211
Test name
Test status
Simulation time 108175786 ps
CPU time 3.94 seconds
Started Feb 04 12:35:55 PM PST 24
Finished Feb 04 12:36:05 PM PST 24
Peak memory 217224 kb
Host smart-74b5bf44-4639-4157-9e54-c8fe4774addf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058054721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2058054721
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1730665113
Short name T259
Test name
Test status
Simulation time 31770130 ps
CPU time 1.46 seconds
Started Feb 04 12:36:43 PM PST 24
Finished Feb 04 12:36:47 PM PST 24
Peak memory 217460 kb
Host smart-4d7f3431-1902-4977-a1f0-1b2dc34db339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730665113 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1730665113
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2117764132
Short name T167
Test name
Test status
Simulation time 37959965 ps
CPU time 1.43 seconds
Started Feb 04 12:36:40 PM PST 24
Finished Feb 04 12:36:46 PM PST 24
Peak memory 210996 kb
Host smart-ec588533-04a6-463d-a728-3254010bcdbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117764132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2117764132
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2556729987
Short name T246
Test name
Test status
Simulation time 294843315 ps
CPU time 1.83 seconds
Started Feb 04 12:36:47 PM PST 24
Finished Feb 04 12:36:51 PM PST 24
Peak memory 217328 kb
Host smart-df80a59c-95c7-4594-b0fb-454aec45a20e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556729987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2556729987
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3167629915
Short name T148
Test name
Test status
Simulation time 177231131 ps
CPU time 2.77 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:51 PM PST 24
Peak memory 221540 kb
Host smart-52d133e9-f371-4027-bbfe-598f74f26e57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167629915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3167629915
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2160833223
Short name T236
Test name
Test status
Simulation time 59507559 ps
CPU time 1.34 seconds
Started Feb 04 12:36:38 PM PST 24
Finished Feb 04 12:36:40 PM PST 24
Peak memory 217316 kb
Host smart-18cb9595-644a-454a-ad6d-29b718225afa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160833223 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2160833223
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1320269618
Short name T176
Test name
Test status
Simulation time 34374080 ps
CPU time 1.11 seconds
Started Feb 04 12:36:44 PM PST 24
Finished Feb 04 12:36:48 PM PST 24
Peak memory 209028 kb
Host smart-718363ca-14e0-44ba-92e8-a7a9cf2629b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320269618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1320269618
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1611353562
Short name T278
Test name
Test status
Simulation time 25929691 ps
CPU time 1.35 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:50 PM PST 24
Peak memory 208452 kb
Host smart-9f4e74cd-8916-4280-b42b-d578b59b4656
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611353562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1611353562
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1420816699
Short name T287
Test name
Test status
Simulation time 127839486 ps
CPU time 2.61 seconds
Started Feb 04 12:36:44 PM PST 24
Finished Feb 04 12:36:49 PM PST 24
Peak memory 217288 kb
Host smart-2bb27307-7d50-4eed-a4db-0b66fe690257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420816699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1420816699
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2470060857
Short name T226
Test name
Test status
Simulation time 198047671 ps
CPU time 2.77 seconds
Started Feb 04 12:36:37 PM PST 24
Finished Feb 04 12:36:42 PM PST 24
Peak memory 221288 kb
Host smart-5524f1df-6642-4163-9d43-53dc707089ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470060857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2470060857
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.964666998
Short name T264
Test name
Test status
Simulation time 56073313 ps
CPU time 1.17 seconds
Started Feb 04 12:36:35 PM PST 24
Finished Feb 04 12:36:40 PM PST 24
Peak memory 217500 kb
Host smart-39bb2890-eb0a-4225-90ba-37a0f8b6e7e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964666998 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.964666998
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2702293229
Short name T177
Test name
Test status
Simulation time 17061962 ps
CPU time 0.82 seconds
Started Feb 04 12:36:42 PM PST 24
Finished Feb 04 12:36:46 PM PST 24
Peak memory 209028 kb
Host smart-7e09b4f6-5997-4532-9775-5ac386956c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702293229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2702293229
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.19969644
Short name T266
Test name
Test status
Simulation time 51319252 ps
CPU time 1.05 seconds
Started Feb 04 12:36:43 PM PST 24
Finished Feb 04 12:36:47 PM PST 24
Peak memory 209124 kb
Host smart-2487dfcc-ac9b-4770-a3b0-6fc9484f161b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19969644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
same_csr_outstanding.19969644
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3643292350
Short name T225
Test name
Test status
Simulation time 89722426 ps
CPU time 1.66 seconds
Started Feb 04 12:36:37 PM PST 24
Finished Feb 04 12:36:41 PM PST 24
Peak memory 218392 kb
Host smart-2b7fb5a0-9c59-4d0e-8980-4783e421d89f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643292350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3643292350
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1357737096
Short name T308
Test name
Test status
Simulation time 17640320 ps
CPU time 1.22 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:49 PM PST 24
Peak memory 217384 kb
Host smart-bf0b016f-481a-40b4-a3f8-c851fb6f3f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357737096 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1357737096
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3209311780
Short name T262
Test name
Test status
Simulation time 59756050 ps
CPU time 1.13 seconds
Started Feb 04 12:36:36 PM PST 24
Finished Feb 04 12:36:40 PM PST 24
Peak memory 208500 kb
Host smart-57d91b1c-125d-4da2-944c-763ecd8809db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209311780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3209311780
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.891984996
Short name T171
Test name
Test status
Simulation time 24989259 ps
CPU time 1.6 seconds
Started Feb 04 12:36:36 PM PST 24
Finished Feb 04 12:36:41 PM PST 24
Peak memory 209380 kb
Host smart-6b9c1caf-cd15-4d6e-a15b-b93b82fb8fcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891984996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.891984996
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.888525390
Short name T161
Test name
Test status
Simulation time 100584560 ps
CPU time 4.07 seconds
Started Feb 04 12:36:40 PM PST 24
Finished Feb 04 12:36:48 PM PST 24
Peak memory 217220 kb
Host smart-4ed64d3d-5ee4-49ec-9169-17f9a69ba670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888525390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.888525390
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2980084898
Short name T305
Test name
Test status
Simulation time 24808947 ps
CPU time 1.32 seconds
Started Feb 04 12:36:39 PM PST 24
Finished Feb 04 12:36:44 PM PST 24
Peak memory 218608 kb
Host smart-e95e9528-6e6c-4302-8b28-c20d15661329
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980084898 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2980084898
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3441873525
Short name T203
Test name
Test status
Simulation time 43362328 ps
CPU time 0.9 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:49 PM PST 24
Peak memory 208452 kb
Host smart-b3a7bca3-4605-4dc6-a035-103d1cad527c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441873525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3441873525
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.417493952
Short name T227
Test name
Test status
Simulation time 30887528 ps
CPU time 1.43 seconds
Started Feb 04 12:36:46 PM PST 24
Finished Feb 04 12:36:51 PM PST 24
Peak memory 209128 kb
Host smart-f967e35e-612a-41fe-a2c0-5a620c62cd50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417493952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.417493952
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4213868695
Short name T108
Test name
Test status
Simulation time 590340170 ps
CPU time 3.99 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:53 PM PST 24
Peak memory 217308 kb
Host smart-2e16ce01-c5d9-4f91-8412-989246158e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213868695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4213868695
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1723883485
Short name T104
Test name
Test status
Simulation time 27917736 ps
CPU time 1.03 seconds
Started Feb 04 12:36:47 PM PST 24
Finished Feb 04 12:36:52 PM PST 24
Peak memory 217380 kb
Host smart-d2ea4a8b-b915-4b51-aa9c-164cf78676e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723883485 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1723883485
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2604484955
Short name T169
Test name
Test status
Simulation time 69427752 ps
CPU time 0.92 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:53 PM PST 24
Peak memory 209124 kb
Host smart-5dba5844-4250-4f6c-9e14-dc73589660f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604484955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2604484955
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3641876629
Short name T159
Test name
Test status
Simulation time 61003884 ps
CPU time 2.04 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:54 PM PST 24
Peak memory 211080 kb
Host smart-1ba13c22-0a23-4292-ab9d-400c6f45e500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641876629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3641876629
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4294060646
Short name T292
Test name
Test status
Simulation time 120584383 ps
CPU time 3.39 seconds
Started Feb 04 12:36:43 PM PST 24
Finished Feb 04 12:36:49 PM PST 24
Peak memory 217320 kb
Host smart-103e5fc7-8476-41b7-9aab-be5852d5f5c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294060646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4294060646
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3824586313
Short name T141
Test name
Test status
Simulation time 113793946 ps
CPU time 3.07 seconds
Started Feb 04 12:36:47 PM PST 24
Finished Feb 04 12:36:53 PM PST 24
Peak memory 221040 kb
Host smart-0f6c73c6-81a8-4b8d-b6b6-dd255c94ae81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824586313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3824586313
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1188040275
Short name T260
Test name
Test status
Simulation time 21565147 ps
CPU time 1.06 seconds
Started Feb 04 12:36:47 PM PST 24
Finished Feb 04 12:36:51 PM PST 24
Peak memory 218704 kb
Host smart-df52f302-f566-4164-aa3d-a76d7c896085
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188040275 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1188040275
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4072379041
Short name T296
Test name
Test status
Simulation time 12411393 ps
CPU time 0.81 seconds
Started Feb 04 12:36:39 PM PST 24
Finished Feb 04 12:36:42 PM PST 24
Peak memory 208068 kb
Host smart-5dc2ce75-572e-4f93-bea7-c8099482dba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072379041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.4072379041
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2166660649
Short name T283
Test name
Test status
Simulation time 17307158 ps
CPU time 1.25 seconds
Started Feb 04 12:36:42 PM PST 24
Finished Feb 04 12:36:46 PM PST 24
Peak memory 209176 kb
Host smart-cdb3df8d-0810-41ec-ba95-96601b73aa49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166660649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2166660649
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.672790265
Short name T270
Test name
Test status
Simulation time 81542319 ps
CPU time 2.54 seconds
Started Feb 04 12:36:40 PM PST 24
Finished Feb 04 12:36:47 PM PST 24
Peak memory 217372 kb
Host smart-779eaa35-9e83-4bd2-9b4d-9a69d239b619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672790265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.672790265
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1177509129
Short name T158
Test name
Test status
Simulation time 178616357 ps
CPU time 1.52 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:50 PM PST 24
Peak memory 216792 kb
Host smart-3b0a8d57-863b-4f58-982f-5473fe8dca8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177509129 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1177509129
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3262551465
Short name T306
Test name
Test status
Simulation time 14572367 ps
CPU time 0.85 seconds
Started Feb 04 12:36:46 PM PST 24
Finished Feb 04 12:36:50 PM PST 24
Peak memory 208352 kb
Host smart-c56609c2-a8db-4580-9f84-730c61ff886f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262551465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3262551465
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2823542138
Short name T224
Test name
Test status
Simulation time 41736182 ps
CPU time 1.37 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:54 PM PST 24
Peak memory 210832 kb
Host smart-da201aff-84fe-451d-a121-7592e512d57a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823542138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2823542138
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2330890518
Short name T162
Test name
Test status
Simulation time 260982740 ps
CPU time 2.7 seconds
Started Feb 04 12:36:43 PM PST 24
Finished Feb 04 12:36:48 PM PST 24
Peak memory 217300 kb
Host smart-0f4bc1d1-92ed-4750-816a-6d9e0b45b083
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330890518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2330890518
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4001091621
Short name T178
Test name
Test status
Simulation time 66639860 ps
CPU time 1.05 seconds
Started Feb 04 12:36:47 PM PST 24
Finished Feb 04 12:36:52 PM PST 24
Peak memory 208992 kb
Host smart-aa29167f-4972-4388-9d03-089acf5cbf12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001091621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.4001091621
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4135718728
Short name T302
Test name
Test status
Simulation time 35091671 ps
CPU time 1.21 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:53 PM PST 24
Peak memory 209112 kb
Host smart-3ea014ea-699e-4513-9913-df9f2c9283f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135718728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.4135718728
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2693398575
Short name T263
Test name
Test status
Simulation time 161513128 ps
CPU time 2.75 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:50 PM PST 24
Peak memory 217316 kb
Host smart-3bf4fa63-4980-4ae7-b032-511a9e6073d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693398575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2693398575
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.622626955
Short name T146
Test name
Test status
Simulation time 1048853951 ps
CPU time 1.9 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:50 PM PST 24
Peak memory 221288 kb
Host smart-64711101-7b68-4d0f-91f0-6bd796dcca06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622626955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.622626955
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.174019435
Short name T216
Test name
Test status
Simulation time 39700762 ps
CPU time 1.4 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:54 PM PST 24
Peak memory 218504 kb
Host smart-5cb48b3a-ac22-4460-8758-3af848d9f6b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174019435 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.174019435
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2167642256
Short name T168
Test name
Test status
Simulation time 25371152 ps
CPU time 0.97 seconds
Started Feb 04 12:36:47 PM PST 24
Finished Feb 04 12:36:52 PM PST 24
Peak memory 209160 kb
Host smart-ada00dde-c0e6-4fd2-bc1f-96e5d753d419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167642256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2167642256
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2736109159
Short name T233
Test name
Test status
Simulation time 265256952 ps
CPU time 1.4 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:54 PM PST 24
Peak memory 210856 kb
Host smart-f34fecfc-41de-4273-814e-8b0361aa96c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736109159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2736109159
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2824937323
Short name T205
Test name
Test status
Simulation time 54365012 ps
CPU time 3 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:55 PM PST 24
Peak memory 217388 kb
Host smart-faf0aaaa-d6be-4054-a0bf-007bfc49949b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824937323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2824937323
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1052186020
Short name T293
Test name
Test status
Simulation time 242036230 ps
CPU time 1.77 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 208988 kb
Host smart-43a1a2cb-868f-4e23-9710-66dabf9835e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052186020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1052186020
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2522472570
Short name T170
Test name
Test status
Simulation time 11935236 ps
CPU time 0.99 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 209260 kb
Host smart-7b6a91e4-2540-4bcd-b020-8724e9af0e0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522472570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2522472570
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3113140316
Short name T99
Test name
Test status
Simulation time 38622490 ps
CPU time 1.12 seconds
Started Feb 04 12:35:51 PM PST 24
Finished Feb 04 12:36:00 PM PST 24
Peak memory 217380 kb
Host smart-2e4b1cd8-9f98-48b5-9bc0-74bbcd7f5691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113140316 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3113140316
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1641658185
Short name T244
Test name
Test status
Simulation time 179389877 ps
CPU time 0.84 seconds
Started Feb 04 12:35:54 PM PST 24
Finished Feb 04 12:36:01 PM PST 24
Peak memory 208860 kb
Host smart-50a48bc0-b065-4703-81cf-078472a1c7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641658185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1641658185
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.935777578
Short name T91
Test name
Test status
Simulation time 110400783 ps
CPU time 2 seconds
Started Feb 04 12:35:59 PM PST 24
Finished Feb 04 12:36:08 PM PST 24
Peak memory 208824 kb
Host smart-c186c3b6-5572-41d0-9b43-c983fab81787
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935777578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.935777578
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4015903182
Short name T980
Test name
Test status
Simulation time 2558875070 ps
CPU time 5.55 seconds
Started Feb 04 12:35:59 PM PST 24
Finished Feb 04 12:36:12 PM PST 24
Peak memory 209068 kb
Host smart-d860e262-73f6-4e62-bf09-5c8fb324b159
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015903182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4015903182
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.956046238
Short name T156
Test name
Test status
Simulation time 16999877157 ps
CPU time 21.43 seconds
Started Feb 04 12:35:46 PM PST 24
Finished Feb 04 12:36:17 PM PST 24
Peak memory 209032 kb
Host smart-acc7ca59-fb08-41dc-8aa5-5df9e0c9116a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956046238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.956046238
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3010976751
Short name T90
Test name
Test status
Simulation time 534055418 ps
CPU time 1.74 seconds
Started Feb 04 12:35:57 PM PST 24
Finished Feb 04 12:36:06 PM PST 24
Peak memory 210140 kb
Host smart-6ac7fb6a-b0cd-42e6-8b78-bccd3adcc49b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010976751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3010976751
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3698996398
Short name T297
Test name
Test status
Simulation time 325337786 ps
CPU time 1.85 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 218228 kb
Host smart-3210463d-7a98-45a1-ab04-b36df8c8115f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369899
6398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3698996398
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.792608540
Short name T256
Test name
Test status
Simulation time 219436371 ps
CPU time 1.38 seconds
Started Feb 04 12:35:57 PM PST 24
Finished Feb 04 12:36:06 PM PST 24
Peak memory 208900 kb
Host smart-186b5ca7-3c4d-4b2a-9297-dfb77b214d61
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792608540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.792608540
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2474996892
Short name T301
Test name
Test status
Simulation time 49090271 ps
CPU time 1 seconds
Started Feb 04 12:35:59 PM PST 24
Finished Feb 04 12:36:07 PM PST 24
Peak memory 209144 kb
Host smart-21b15638-e083-40bc-bee8-ef90519d1c27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474996892 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2474996892
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2536049452
Short name T93
Test name
Test status
Simulation time 159486166 ps
CPU time 3.78 seconds
Started Feb 04 12:35:58 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 217312 kb
Host smart-0ccbc452-2b30-4c13-bfb6-a144a805f1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536049452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2536049452
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3264769097
Short name T179
Test name
Test status
Simulation time 15797075 ps
CPU time 0.96 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 209068 kb
Host smart-ab801bca-ee88-4d28-a245-dcd8d1eb8dcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264769097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3264769097
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.542939167
Short name T248
Test name
Test status
Simulation time 159689493 ps
CPU time 1.23 seconds
Started Feb 04 12:38:03 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 208852 kb
Host smart-806b08c1-1a47-42be-a3d0-a319f89bfe51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542939167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.542939167
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1789630877
Short name T172
Test name
Test status
Simulation time 23212442 ps
CPU time 1 seconds
Started Feb 04 12:37:40 PM PST 24
Finished Feb 04 12:37:47 PM PST 24
Peak memory 207856 kb
Host smart-d09a4187-ea99-460b-8a42-f1819ddabe53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789630877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1789630877
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2826310633
Short name T214
Test name
Test status
Simulation time 135760860 ps
CPU time 1.94 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 222748 kb
Host smart-3b565a39-bfb3-47c2-b654-59c808664a86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826310633 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2826310633
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1306036555
Short name T230
Test name
Test status
Simulation time 38980773 ps
CPU time 0.96 seconds
Started Feb 04 12:36:02 PM PST 24
Finished Feb 04 12:36:10 PM PST 24
Peak memory 209264 kb
Host smart-3708b31f-c053-426f-86af-e0d4f877b8aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306036555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1306036555
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2296192957
Short name T245
Test name
Test status
Simulation time 274555509 ps
CPU time 1.6 seconds
Started Feb 04 12:36:13 PM PST 24
Finished Feb 04 12:36:17 PM PST 24
Peak memory 208940 kb
Host smart-6fe28755-1a68-4d73-ad05-f1d441296289
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296192957 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2296192957
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2444496585
Short name T251
Test name
Test status
Simulation time 644397954 ps
CPU time 12.74 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:29 PM PST 24
Peak memory 208964 kb
Host smart-b405b99d-e332-4f99-936e-e7131ef3dbd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444496585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2444496585
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3576714943
Short name T281
Test name
Test status
Simulation time 1209797028 ps
CPU time 21.1 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:37 PM PST 24
Peak memory 208964 kb
Host smart-9ff98e68-aca7-48f1-a012-c71e5e79a9d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576714943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3576714943
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4253041372
Short name T210
Test name
Test status
Simulation time 1438653628 ps
CPU time 2.23 seconds
Started Feb 04 12:35:51 PM PST 24
Finished Feb 04 12:36:01 PM PST 24
Peak memory 210336 kb
Host smart-cec82c28-2b18-4f22-a4ab-c71967b265f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253041372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.4253041372
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1317519555
Short name T286
Test name
Test status
Simulation time 81055326 ps
CPU time 1.51 seconds
Started Feb 04 12:36:01 PM PST 24
Finished Feb 04 12:36:10 PM PST 24
Peak memory 218680 kb
Host smart-170784ca-6944-4263-af08-77c3e5f306f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131751
9555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1317519555
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3718194231
Short name T267
Test name
Test status
Simulation time 283899186 ps
CPU time 1.69 seconds
Started Feb 04 12:35:55 PM PST 24
Finished Feb 04 12:36:04 PM PST 24
Peak memory 208912 kb
Host smart-1ca778e2-9ada-4a48-9320-4316075db98b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718194231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3718194231
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1488009551
Short name T303
Test name
Test status
Simulation time 26334534 ps
CPU time 1.13 seconds
Started Feb 04 12:36:00 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 209100 kb
Host smart-6890e208-2986-4fd7-82e9-da84d8e48fa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488009551 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1488009551
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4024874739
Short name T290
Test name
Test status
Simulation time 34142937 ps
CPU time 1.38 seconds
Started Feb 04 12:36:00 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 209108 kb
Host smart-29c588df-2144-4bf5-800f-815ecc7c5134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024874739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.4024874739
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.591163495
Short name T89
Test name
Test status
Simulation time 165615769 ps
CPU time 2.77 seconds
Started Feb 04 12:36:13 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 218372 kb
Host smart-8aab8ede-c1f2-442e-b2b5-533239ec8537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591163495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.591163495
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3960762705
Short name T175
Test name
Test status
Simulation time 25183267 ps
CPU time 1.11 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 208876 kb
Host smart-51af4c74-e1d8-433b-97d9-7e36d34ef5d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960762705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3960762705
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3426457823
Short name T288
Test name
Test status
Simulation time 144373515 ps
CPU time 1.59 seconds
Started Feb 04 12:36:13 PM PST 24
Finished Feb 04 12:36:17 PM PST 24
Peak memory 208788 kb
Host smart-aa68a2af-92d6-4b3b-a4c6-e94ce4aabb32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426457823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3426457823
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1898077077
Short name T234
Test name
Test status
Simulation time 35347587 ps
CPU time 0.82 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:17 PM PST 24
Peak memory 208296 kb
Host smart-006d465b-9157-4a0b-8bbc-3c13b0b7f16e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898077077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1898077077
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.401475085
Short name T219
Test name
Test status
Simulation time 261580106 ps
CPU time 1.15 seconds
Started Feb 04 12:38:03 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 218316 kb
Host smart-91dcafa4-135e-4639-a11b-d20e673cbd8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401475085 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.401475085
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.278599395
Short name T111
Test name
Test status
Simulation time 74717658 ps
CPU time 0.85 seconds
Started Feb 04 12:35:58 PM PST 24
Finished Feb 04 12:36:06 PM PST 24
Peak memory 209120 kb
Host smart-e7d1b2d2-52e9-4c8d-8ace-a3d990230a3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278599395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.278599395
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3480439307
Short name T232
Test name
Test status
Simulation time 31782509 ps
CPU time 0.93 seconds
Started Feb 04 12:36:13 PM PST 24
Finished Feb 04 12:36:16 PM PST 24
Peak memory 207332 kb
Host smart-9ef314c2-a65f-4466-9a59-5f69f5d032cb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480439307 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3480439307
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1713982770
Short name T87
Test name
Test status
Simulation time 499251259 ps
CPU time 13.06 seconds
Started Feb 04 12:36:02 PM PST 24
Finished Feb 04 12:36:22 PM PST 24
Peak memory 207944 kb
Host smart-f5b855f5-38a0-431b-b2ea-7caf0245ae25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713982770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1713982770
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3548539237
Short name T243
Test name
Test status
Simulation time 478544608 ps
CPU time 10.86 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:28 PM PST 24
Peak memory 208880 kb
Host smart-3f8a38af-349b-4cc1-9700-989c39f87603
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548539237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3548539237
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.504872747
Short name T235
Test name
Test status
Simulation time 248235291 ps
CPU time 2.64 seconds
Started Feb 04 12:36:16 PM PST 24
Finished Feb 04 12:36:20 PM PST 24
Peak memory 210212 kb
Host smart-a6c5eefc-1099-45be-8fd5-55613e7020f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504872747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.504872747
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2563865366
Short name T255
Test name
Test status
Simulation time 205689000 ps
CPU time 2.15 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 217024 kb
Host smart-258b171a-71e5-4421-9a70-cdb22a895e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256386
5366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2563865366
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3641953105
Short name T155
Test name
Test status
Simulation time 75644660 ps
CPU time 1.32 seconds
Started Feb 04 12:36:06 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 208716 kb
Host smart-32f742a3-d13d-4df1-8029-3ba28f31739e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641953105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3641953105
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1944302935
Short name T242
Test name
Test status
Simulation time 32220565 ps
CPU time 1.38 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 210808 kb
Host smart-54cf1ecc-549a-4225-b8b5-83b1f5eef1d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944302935 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1944302935
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.855034729
Short name T185
Test name
Test status
Simulation time 14508452 ps
CPU time 0.95 seconds
Started Feb 04 12:38:03 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 208840 kb
Host smart-132393fd-c797-4e2a-9d54-705f5470d317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855034729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.855034729
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1987957862
Short name T207
Test name
Test status
Simulation time 73979186 ps
CPU time 1.44 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:17 PM PST 24
Peak memory 217204 kb
Host smart-8d134cc4-e20e-4c65-beb6-11e243e2167b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987957862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1987957862
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1111265761
Short name T160
Test name
Test status
Simulation time 43309592 ps
CPU time 1.31 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:38:05 PM PST 24
Peak memory 217240 kb
Host smart-9fa48927-f807-4416-b5b1-09d252034c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111265761 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1111265761
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1826952981
Short name T304
Test name
Test status
Simulation time 37611177 ps
CPU time 0.97 seconds
Started Feb 04 12:37:40 PM PST 24
Finished Feb 04 12:37:47 PM PST 24
Peak memory 207536 kb
Host smart-6bf43765-06f1-4d54-93a3-f5687c912047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826952981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1826952981
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3987590990
Short name T295
Test name
Test status
Simulation time 481866800 ps
CPU time 1.71 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 208244 kb
Host smart-b0e30f98-7991-42ca-9c5f-f8052de0d6a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987590990 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3987590990
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.595103709
Short name T252
Test name
Test status
Simulation time 1801004338 ps
CPU time 5.29 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:21 PM PST 24
Peak memory 207844 kb
Host smart-1cc38fa3-f647-4d95-b68b-0242848c7b24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595103709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.595103709
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1003505325
Short name T285
Test name
Test status
Simulation time 56231609 ps
CPU time 1.46 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:38:05 PM PST 24
Peak memory 218200 kb
Host smart-1e75fc32-61e1-48be-8683-d0b312c0508b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100350
5325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1003505325
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2470441836
Short name T265
Test name
Test status
Simulation time 221978371 ps
CPU time 1.46 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 208892 kb
Host smart-6fd8e6cd-9560-4bf0-ba4e-bc3457036577
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470441836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2470441836
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3097639719
Short name T258
Test name
Test status
Simulation time 100478045 ps
CPU time 1.24 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 208380 kb
Host smart-7001c964-6c43-4164-966a-59067dac7f11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097639719 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3097639719
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.159204648
Short name T107
Test name
Test status
Simulation time 35923918 ps
CPU time 1.44 seconds
Started Feb 04 12:36:09 PM PST 24
Finished Feb 04 12:36:15 PM PST 24
Peak memory 208616 kb
Host smart-0acf39b6-217d-4664-b83b-cb546e12846d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159204648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.159204648
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3769479063
Short name T222
Test name
Test status
Simulation time 220805716 ps
CPU time 2.46 seconds
Started Feb 04 12:36:13 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 217296 kb
Host smart-444dcd9d-0dc0-43dc-8c88-97e4e3864470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769479063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3769479063
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3595381330
Short name T103
Test name
Test status
Simulation time 21240431 ps
CPU time 1.22 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:38:05 PM PST 24
Peak memory 217164 kb
Host smart-de4c07c4-dd14-47c4-8ce1-8beed666b3e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595381330 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3595381330
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4149143388
Short name T165
Test name
Test status
Simulation time 56565360 ps
CPU time 0.93 seconds
Started Feb 04 12:36:16 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 208972 kb
Host smart-2487606d-1006-4be7-a94d-9525eea7e43a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149143388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4149143388
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3624648409
Short name T279
Test name
Test status
Simulation time 60205933 ps
CPU time 1.83 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 208880 kb
Host smart-ecc9c0e0-d822-49ce-8263-d0d22cb13081
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624648409 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3624648409
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4251439215
Short name T257
Test name
Test status
Simulation time 219871556 ps
CPU time 5.76 seconds
Started Feb 04 12:36:14 PM PST 24
Finished Feb 04 12:36:22 PM PST 24
Peak memory 208956 kb
Host smart-400a0441-7816-42fe-92ff-0cf5a249a1bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251439215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4251439215
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4254299081
Short name T247
Test name
Test status
Simulation time 6845837377 ps
CPU time 36.86 seconds
Started Feb 04 12:36:12 PM PST 24
Finished Feb 04 12:36:52 PM PST 24
Peak memory 209028 kb
Host smart-2ce89a47-1c95-46c0-9803-3302ad0db21b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254299081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4254299081
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3021658354
Short name T271
Test name
Test status
Simulation time 190898386 ps
CPU time 2.33 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 210144 kb
Host smart-4a928fae-2ef2-47ae-af4f-af8a3694b5cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021658354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3021658354
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3504584413
Short name T237
Test name
Test status
Simulation time 35063846 ps
CPU time 1.42 seconds
Started Feb 04 12:36:00 PM PST 24
Finished Feb 04 12:36:08 PM PST 24
Peak memory 208920 kb
Host smart-732a1852-1d91-4808-a02f-78d2bfce7b87
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504584413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3504584413
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.389218516
Short name T254
Test name
Test status
Simulation time 22547716 ps
CPU time 1.34 seconds
Started Feb 04 12:38:03 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 208872 kb
Host smart-c2b69ff2-544a-4e69-bd95-a978fd45631e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389218516 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.389218516
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1413688786
Short name T289
Test name
Test status
Simulation time 52474300 ps
CPU time 1.78 seconds
Started Feb 04 12:36:16 PM PST 24
Finished Feb 04 12:36:20 PM PST 24
Peak memory 210992 kb
Host smart-323c835e-437a-4914-baad-79b89ab8ebfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413688786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1413688786
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1643388242
Short name T138
Test name
Test status
Simulation time 413600342 ps
CPU time 3.23 seconds
Started Feb 04 12:36:16 PM PST 24
Finished Feb 04 12:36:21 PM PST 24
Peak memory 217696 kb
Host smart-f459dfab-ac74-4338-bcdf-bc338247ff02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643388242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1643388242
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3029820160
Short name T149
Test name
Test status
Simulation time 169258999 ps
CPU time 1.91 seconds
Started Feb 04 12:36:02 PM PST 24
Finished Feb 04 12:36:11 PM PST 24
Peak memory 221008 kb
Host smart-0603573b-c51a-4ecb-9c9c-1c7b51cf0ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029820160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3029820160
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3745095007
Short name T183
Test name
Test status
Simulation time 71360255 ps
CPU time 1.38 seconds
Started Feb 04 12:36:25 PM PST 24
Finished Feb 04 12:36:30 PM PST 24
Peak memory 217976 kb
Host smart-b598f6be-12cc-4f7b-ab40-9d094bf35e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745095007 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3745095007
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1782421160
Short name T174
Test name
Test status
Simulation time 14139637 ps
CPU time 0.94 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 208440 kb
Host smart-11ceb9ce-03ef-45ab-94a8-1d787c32ef44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782421160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1782421160
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4087902656
Short name T274
Test name
Test status
Simulation time 31411563 ps
CPU time 1.3 seconds
Started Feb 04 12:38:02 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 208772 kb
Host smart-f0718850-31d1-424c-81d3-1bc356fed65c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087902656 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4087902656
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3025831817
Short name T238
Test name
Test status
Simulation time 569488068 ps
CPU time 11.83 seconds
Started Feb 04 12:36:01 PM PST 24
Finished Feb 04 12:36:20 PM PST 24
Peak memory 208832 kb
Host smart-a2bdcebb-a8dd-4e13-a3a4-cf4027109916
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025831817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3025831817
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2161385848
Short name T981
Test name
Test status
Simulation time 409567822 ps
CPU time 4.29 seconds
Started Feb 04 12:36:01 PM PST 24
Finished Feb 04 12:36:12 PM PST 24
Peak memory 208824 kb
Host smart-afe0a9ac-76b9-4290-bb02-c7f5272efef4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161385848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2161385848
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.22247178
Short name T157
Test name
Test status
Simulation time 170938315 ps
CPU time 4.49 seconds
Started Feb 04 12:36:04 PM PST 24
Finished Feb 04 12:36:16 PM PST 24
Peak memory 210448 kb
Host smart-4624b6cc-e1a7-44d4-970c-67e0349c65d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22247178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.22247178
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1581463137
Short name T249
Test name
Test status
Simulation time 107265484 ps
CPU time 2.15 seconds
Started Feb 04 12:36:01 PM PST 24
Finished Feb 04 12:36:10 PM PST 24
Peak memory 218548 kb
Host smart-12686436-735f-4499-9cf4-31a74aba723e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158146
3137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1581463137
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3417126660
Short name T276
Test name
Test status
Simulation time 73076028 ps
CPU time 1.44 seconds
Started Feb 04 12:36:15 PM PST 24
Finished Feb 04 12:36:18 PM PST 24
Peak memory 208880 kb
Host smart-2d79aae5-8243-46cc-845f-8090aa1cfd18
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417126660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3417126660
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.492831806
Short name T240
Test name
Test status
Simulation time 30175643 ps
CPU time 1.04 seconds
Started Feb 04 12:36:02 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 208336 kb
Host smart-348416a3-a21e-4973-96e6-24ea7e26b383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492831806 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.492831806
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4017682934
Short name T163
Test name
Test status
Simulation time 27625795 ps
CPU time 1.12 seconds
Started Feb 04 12:36:24 PM PST 24
Finished Feb 04 12:36:28 PM PST 24
Peak memory 208456 kb
Host smart-410d03d8-bc8d-4013-84be-31dd57745e27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017682934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4017682934
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1627691526
Short name T181
Test name
Test status
Simulation time 76775689 ps
CPU time 3.03 seconds
Started Feb 04 12:38:06 PM PST 24
Finished Feb 04 12:38:11 PM PST 24
Peak memory 217248 kb
Host smart-7d77b2ff-6aab-4248-b995-c240d9c912cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627691526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1627691526
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1240931692
Short name T220
Test name
Test status
Simulation time 45443498 ps
CPU time 1.18 seconds
Started Feb 04 12:36:20 PM PST 24
Finished Feb 04 12:36:23 PM PST 24
Peak memory 217516 kb
Host smart-d7cd626f-5c92-407d-9473-e152180b6ffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240931692 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1240931692
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3897404123
Short name T166
Test name
Test status
Simulation time 23794670 ps
CPU time 0.91 seconds
Started Feb 04 12:36:24 PM PST 24
Finished Feb 04 12:36:29 PM PST 24
Peak memory 209160 kb
Host smart-58a5474a-bab9-421b-b749-dfe7a1c119bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897404123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3897404123
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3918264268
Short name T209
Test name
Test status
Simulation time 69553268 ps
CPU time 1.04 seconds
Started Feb 04 12:36:28 PM PST 24
Finished Feb 04 12:36:33 PM PST 24
Peak memory 208956 kb
Host smart-1523101c-5f55-4918-a8d9-0ef6ac62a46a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918264268 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3918264268
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3839474271
Short name T208
Test name
Test status
Simulation time 1145199552 ps
CPU time 12.5 seconds
Started Feb 04 12:36:21 PM PST 24
Finished Feb 04 12:36:36 PM PST 24
Peak memory 209000 kb
Host smart-c93847cb-762e-4b50-b39f-65acabaa524b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839474271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3839474271
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.28451331
Short name T182
Test name
Test status
Simulation time 3596621827 ps
CPU time 5.91 seconds
Started Feb 04 12:36:37 PM PST 24
Finished Feb 04 12:36:45 PM PST 24
Peak memory 208868 kb
Host smart-da824a7e-376c-443b-a339-de43e8c27b7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28451331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.28451331
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1653335578
Short name T223
Test name
Test status
Simulation time 348589008 ps
CPU time 2.84 seconds
Started Feb 04 12:36:22 PM PST 24
Finished Feb 04 12:36:28 PM PST 24
Peak memory 210508 kb
Host smart-0ba77b2e-5c7a-4d76-a303-6c9db1251f64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653335578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1653335578
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.665393607
Short name T275
Test name
Test status
Simulation time 192286859 ps
CPU time 1.9 seconds
Started Feb 04 12:36:24 PM PST 24
Finished Feb 04 12:36:30 PM PST 24
Peak memory 217732 kb
Host smart-bd58e774-0ac5-4706-a7fd-78325ca62f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665393
607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.665393607
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.194031501
Short name T228
Test name
Test status
Simulation time 104918096 ps
CPU time 2.01 seconds
Started Feb 04 12:36:27 PM PST 24
Finished Feb 04 12:36:33 PM PST 24
Peak memory 208924 kb
Host smart-8e02e88c-43d7-4c98-9fcd-7c86c8f348fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194031501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.194031501
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3119502791
Short name T213
Test name
Test status
Simulation time 182178015 ps
CPU time 1.93 seconds
Started Feb 04 12:36:40 PM PST 24
Finished Feb 04 12:36:46 PM PST 24
Peak memory 208964 kb
Host smart-97bebe9f-322b-48fe-ba59-fcf8e02e5e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119502791 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3119502791
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2539598947
Short name T299
Test name
Test status
Simulation time 15705154 ps
CPU time 1 seconds
Started Feb 04 12:36:19 PM PST 24
Finished Feb 04 12:36:22 PM PST 24
Peak memory 208856 kb
Host smart-7c59aa40-7bbc-4a8a-8475-eb16968de265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539598947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2539598947
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.869246195
Short name T218
Test name
Test status
Simulation time 95683928 ps
CPU time 1.75 seconds
Started Feb 04 12:36:24 PM PST 24
Finished Feb 04 12:36:28 PM PST 24
Peak memory 217648 kb
Host smart-235927e1-8a3b-4fce-b816-bad879e118a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869246195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.869246195
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2434036126
Short name T272
Test name
Test status
Simulation time 128945507 ps
CPU time 1.27 seconds
Started Feb 04 12:36:45 PM PST 24
Finished Feb 04 12:36:50 PM PST 24
Peak memory 218680 kb
Host smart-539d462b-98be-4e3f-bcdb-c4c63fa44f15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434036126 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2434036126
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1075334403
Short name T204
Test name
Test status
Simulation time 15697687 ps
CPU time 0.89 seconds
Started Feb 04 12:36:48 PM PST 24
Finished Feb 04 12:36:53 PM PST 24
Peak memory 209120 kb
Host smart-d9753683-5c6b-48d6-8821-320bc80504ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075334403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1075334403
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2661820423
Short name T153
Test name
Test status
Simulation time 69125622 ps
CPU time 1.49 seconds
Started Feb 04 12:36:28 PM PST 24
Finished Feb 04 12:36:33 PM PST 24
Peak memory 208940 kb
Host smart-84b37399-daa6-45cf-8587-d468621bb0b8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661820423 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2661820423
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1981848081
Short name T229
Test name
Test status
Simulation time 2659127948 ps
CPU time 8.06 seconds
Started Feb 04 12:36:23 PM PST 24
Finished Feb 04 12:36:34 PM PST 24
Peak memory 209044 kb
Host smart-12fa3f8b-1b39-49ac-830f-84aeb84131d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981848081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1981848081
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2083048345
Short name T982
Test name
Test status
Simulation time 348301183 ps
CPU time 9.26 seconds
Started Feb 04 12:36:24 PM PST 24
Finished Feb 04 12:36:36 PM PST 24
Peak memory 208996 kb
Host smart-e22d0e0c-2e18-490e-8270-3a976d2bd0b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083048345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2083048345
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.399030377
Short name T284
Test name
Test status
Simulation time 250178500 ps
CPU time 1.9 seconds
Started Feb 04 12:36:25 PM PST 24
Finished Feb 04 12:36:30 PM PST 24
Peak memory 210364 kb
Host smart-63ffd119-bebc-480a-8bff-4aa3d7ec5f77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399030377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.399030377
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4156500999
Short name T212
Test name
Test status
Simulation time 468775840 ps
CPU time 3.26 seconds
Started Feb 04 12:36:20 PM PST 24
Finished Feb 04 12:36:25 PM PST 24
Peak memory 218076 kb
Host smart-072d149d-6a2b-4f63-ac9e-fdbec85be966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415650
0999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4156500999
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2434691638
Short name T298
Test name
Test status
Simulation time 250097293 ps
CPU time 1.46 seconds
Started Feb 04 12:36:27 PM PST 24
Finished Feb 04 12:36:32 PM PST 24
Peak memory 208884 kb
Host smart-1341bf04-d9c3-41dd-be30-b765b8ab5c66
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434691638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2434691638
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3399595993
Short name T186
Test name
Test status
Simulation time 71914820 ps
CPU time 1.33 seconds
Started Feb 04 12:36:20 PM PST 24
Finished Feb 04 12:36:22 PM PST 24
Peak memory 208308 kb
Host smart-3e9ef806-ad26-4248-ba75-ef8492001aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399595993 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3399595993
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1101465638
Short name T294
Test name
Test status
Simulation time 142662496 ps
CPU time 1.31 seconds
Started Feb 04 12:36:46 PM PST 24
Finished Feb 04 12:36:50 PM PST 24
Peak memory 210852 kb
Host smart-1e4edd2f-3cdd-4022-b5d4-c026f845724a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101465638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1101465638
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1288629418
Short name T273
Test name
Test status
Simulation time 71180153 ps
CPU time 1.38 seconds
Started Feb 04 12:36:40 PM PST 24
Finished Feb 04 12:36:46 PM PST 24
Peak memory 209084 kb
Host smart-5e7056d8-90a5-46e8-9ec6-a575cdaed41f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288629418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1288629418
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.440473651
Short name T921
Test name
Test status
Simulation time 53174944 ps
CPU time 0.85 seconds
Started Feb 04 01:12:26 PM PST 24
Finished Feb 04 01:12:28 PM PST 24
Peak memory 209392 kb
Host smart-689ea503-d44a-4ec4-8e59-411cbf0e66fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440473651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.440473651
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3446246586
Short name T510
Test name
Test status
Simulation time 708970021 ps
CPU time 12.73 seconds
Started Feb 04 01:12:27 PM PST 24
Finished Feb 04 01:12:42 PM PST 24
Peak memory 217812 kb
Host smart-27a43ec5-00cc-4316-8b3b-1dccdd8e9a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446246586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3446246586
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3568159109
Short name T27
Test name
Test status
Simulation time 439803225 ps
CPU time 5.04 seconds
Started Feb 04 01:12:29 PM PST 24
Finished Feb 04 01:12:35 PM PST 24
Peak memory 209464 kb
Host smart-13557e7c-22fb-427c-937a-5a7f641f6e3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568159109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.3568159109
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.931010941
Short name T697
Test name
Test status
Simulation time 1267853936 ps
CPU time 38.64 seconds
Started Feb 04 01:12:35 PM PST 24
Finished Feb 04 01:13:18 PM PST 24
Peak memory 217688 kb
Host smart-78fbe580-c1fd-46b4-a281-c6d5c4bcbca8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931010941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.931010941
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3771466104
Short name T703
Test name
Test status
Simulation time 195490139 ps
CPU time 2.84 seconds
Started Feb 04 01:12:19 PM PST 24
Finished Feb 04 01:12:27 PM PST 24
Peak memory 209528 kb
Host smart-36d44d4f-d18c-49f1-8dae-9a1e2f9891c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771466104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.3771466104
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1305375379
Short name T768
Test name
Test status
Simulation time 201441404 ps
CPU time 4.08 seconds
Started Feb 04 01:12:28 PM PST 24
Finished Feb 04 01:12:33 PM PST 24
Peak memory 217796 kb
Host smart-b9772453-0ec2-4b1b-9b97-b6bb126dd8b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305375379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1305375379
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3869373602
Short name T866
Test name
Test status
Simulation time 6302260615 ps
CPU time 33.58 seconds
Started Feb 04 01:12:31 PM PST 24
Finished Feb 04 01:13:06 PM PST 24
Peak memory 213824 kb
Host smart-0d845af3-7686-4100-bca7-aa5d9dd126af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869373602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3869373602
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3990480487
Short name T369
Test name
Test status
Simulation time 1482970719 ps
CPU time 3.44 seconds
Started Feb 04 01:12:31 PM PST 24
Finished Feb 04 01:12:36 PM PST 24
Peak memory 212652 kb
Host smart-e7b530a4-f4ae-47d5-956d-27fd98ccd90b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990480487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3990480487
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2699428001
Short name T632
Test name
Test status
Simulation time 8277040313 ps
CPU time 127.88 seconds
Started Feb 04 01:12:17 PM PST 24
Finished Feb 04 01:14:26 PM PST 24
Peak memory 283460 kb
Host smart-8e15a35b-091e-43e9-a357-2de2b07b7f1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699428001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2699428001
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2241117465
Short name T868
Test name
Test status
Simulation time 475332871 ps
CPU time 2.15 seconds
Started Feb 04 01:12:17 PM PST 24
Finished Feb 04 01:12:20 PM PST 24
Peak memory 217828 kb
Host smart-8985e979-e762-4084-999d-ed3f0c140f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241117465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2241117465
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1250932464
Short name T608
Test name
Test status
Simulation time 620323457 ps
CPU time 10.02 seconds
Started Feb 04 01:12:25 PM PST 24
Finished Feb 04 01:12:36 PM PST 24
Peak memory 213708 kb
Host smart-11b9fdb7-7726-4999-b607-75ff697a7c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250932464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1250932464
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2762660504
Short name T125
Test name
Test status
Simulation time 660102464 ps
CPU time 21.87 seconds
Started Feb 04 01:12:19 PM PST 24
Finished Feb 04 01:12:46 PM PST 24
Peak memory 281608 kb
Host smart-9c286fda-a472-425f-8c9c-e66a72144514
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762660504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2762660504
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1738766921
Short name T963
Test name
Test status
Simulation time 656904977 ps
CPU time 8.66 seconds
Started Feb 04 01:12:20 PM PST 24
Finished Feb 04 01:12:32 PM PST 24
Peak memory 217756 kb
Host smart-d4788025-cfdd-450e-8053-6febc5e9b463
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738766921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1738766921
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2101878884
Short name T477
Test name
Test status
Simulation time 823680624 ps
CPU time 12.02 seconds
Started Feb 04 01:12:21 PM PST 24
Finished Feb 04 01:12:36 PM PST 24
Peak memory 217816 kb
Host smart-b503741f-29e0-4075-b058-c880b6e425c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101878884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2101878884
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.524628996
Short name T63
Test name
Test status
Simulation time 349653846 ps
CPU time 11.82 seconds
Started Feb 04 01:12:23 PM PST 24
Finished Feb 04 01:12:36 PM PST 24
Peak memory 217768 kb
Host smart-71092e13-d19b-47f3-b266-83f7822cdad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524628996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.524628996
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2228030671
Short name T11
Test name
Test status
Simulation time 786163314 ps
CPU time 8.28 seconds
Started Feb 04 01:12:21 PM PST 24
Finished Feb 04 01:12:32 PM PST 24
Peak memory 217832 kb
Host smart-4b3dc48c-4897-4ee7-8ddd-1aa8dcdbc8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228030671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2228030671
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1939542933
Short name T355
Test name
Test status
Simulation time 67783258 ps
CPU time 1.25 seconds
Started Feb 04 01:12:23 PM PST 24
Finished Feb 04 01:12:26 PM PST 24
Peak memory 212772 kb
Host smart-89717ef0-699a-4626-a62d-4f52e07725ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939542933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1939542933
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.196325766
Short name T612
Test name
Test status
Simulation time 230730410 ps
CPU time 19.94 seconds
Started Feb 04 01:12:19 PM PST 24
Finished Feb 04 01:12:44 PM PST 24
Peak memory 250884 kb
Host smart-3c123514-7bb0-4972-9ad7-eb2021188543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196325766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.196325766
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2354627952
Short name T386
Test name
Test status
Simulation time 68254258 ps
CPU time 6.83 seconds
Started Feb 04 01:12:24 PM PST 24
Finished Feb 04 01:12:32 PM PST 24
Peak memory 246212 kb
Host smart-a084b862-74cf-4e37-8a2c-2458c951b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354627952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2354627952
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3577742246
Short name T813
Test name
Test status
Simulation time 88627822691 ps
CPU time 82.42 seconds
Started Feb 04 01:12:21 PM PST 24
Finished Feb 04 01:13:46 PM PST 24
Peak memory 250944 kb
Host smart-aed56542-2a44-4da0-af13-ad8d7635e803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577742246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3577742246
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1701405529
Short name T878
Test name
Test status
Simulation time 12224225 ps
CPU time 0.94 seconds
Started Feb 04 01:12:29 PM PST 24
Finished Feb 04 01:12:31 PM PST 24
Peak memory 209412 kb
Host smart-741ec473-4768-445a-808f-8736cd9ed124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701405529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1701405529
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.864005970
Short name T406
Test name
Test status
Simulation time 33351567 ps
CPU time 0.88 seconds
Started Feb 04 01:12:37 PM PST 24
Finished Feb 04 01:12:41 PM PST 24
Peak memory 209320 kb
Host smart-0bdb0e7d-37b6-4ed9-acc1-ae9bde36f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864005970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.864005970
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1205502541
Short name T769
Test name
Test status
Simulation time 373737070 ps
CPU time 9.88 seconds
Started Feb 04 01:12:24 PM PST 24
Finished Feb 04 01:12:35 PM PST 24
Peak memory 217716 kb
Host smart-10aaec88-8e09-4147-a9f4-40e28115f8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205502541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1205502541
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3493710967
Short name T714
Test name
Test status
Simulation time 71375394 ps
CPU time 1.06 seconds
Started Feb 04 01:12:35 PM PST 24
Finished Feb 04 01:12:41 PM PST 24
Peak memory 209420 kb
Host smart-625d57de-b5aa-438f-851c-492ea2846863
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493710967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.3493710967
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2950576293
Short name T805
Test name
Test status
Simulation time 12316555962 ps
CPU time 83.45 seconds
Started Feb 04 01:12:32 PM PST 24
Finished Feb 04 01:14:02 PM PST 24
Peak memory 218316 kb
Host smart-604d0d1c-503f-4081-bb9d-a58653b36806
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950576293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2950576293
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2152649711
Short name T641
Test name
Test status
Simulation time 172662526 ps
CPU time 5 seconds
Started Feb 04 01:12:37 PM PST 24
Finished Feb 04 01:12:45 PM PST 24
Peak memory 209452 kb
Host smart-515b4423-b595-436d-845e-87919f82cc8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152649711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.2152649711
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.870581066
Short name T806
Test name
Test status
Simulation time 1260040746 ps
CPU time 17.23 seconds
Started Feb 04 01:12:33 PM PST 24
Finished Feb 04 01:12:56 PM PST 24
Peak memory 217800 kb
Host smart-88d9f7a7-8638-4b1a-a32a-85ce9311a757
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870581066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.870581066
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2948310838
Short name T648
Test name
Test status
Simulation time 2653702895 ps
CPU time 15.48 seconds
Started Feb 04 01:12:38 PM PST 24
Finished Feb 04 01:12:56 PM PST 24
Peak memory 213196 kb
Host smart-85869d49-e9b7-49fd-8563-d6570fa61a91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948310838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2948310838
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.579309726
Short name T915
Test name
Test status
Simulation time 148734834 ps
CPU time 3.54 seconds
Started Feb 04 01:12:34 PM PST 24
Finished Feb 04 01:12:43 PM PST 24
Peak memory 212776 kb
Host smart-a5dadb37-5eeb-4e41-9917-7bcd2e5f3560
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579309726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.579309726
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1537714435
Short name T433
Test name
Test status
Simulation time 972732310 ps
CPU time 31.66 seconds
Started Feb 04 01:12:39 PM PST 24
Finished Feb 04 01:13:12 PM PST 24
Peak memory 250812 kb
Host smart-d12f6200-f847-400f-bc40-79dfa66432c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537714435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1537714435
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3220821942
Short name T197
Test name
Test status
Simulation time 2400428375 ps
CPU time 13.27 seconds
Started Feb 04 01:12:35 PM PST 24
Finished Feb 04 01:12:53 PM PST 24
Peak memory 246272 kb
Host smart-9256bd0a-0e20-4c39-8951-f080dfd22bb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220821942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3220821942
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3523353000
Short name T327
Test name
Test status
Simulation time 173352650 ps
CPU time 1.51 seconds
Started Feb 04 01:12:25 PM PST 24
Finished Feb 04 01:12:27 PM PST 24
Peak memory 217736 kb
Host smart-1fb391dd-c1ac-45c2-afb5-39c6eea24616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523353000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3523353000
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2910081236
Short name T536
Test name
Test status
Simulation time 308499639 ps
CPU time 8.65 seconds
Started Feb 04 01:12:25 PM PST 24
Finished Feb 04 01:12:35 PM PST 24
Peak memory 213984 kb
Host smart-4156dbe1-477f-4196-89ce-6053ea0db7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910081236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2910081236
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1986145522
Short name T96
Test name
Test status
Simulation time 215485915 ps
CPU time 39.76 seconds
Started Feb 04 01:12:37 PM PST 24
Finished Feb 04 01:13:20 PM PST 24
Peak memory 281720 kb
Host smart-30c076be-b980-4077-8961-2c5ce1508d52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986145522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1986145522
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4071735945
Short name T904
Test name
Test status
Simulation time 1274501649 ps
CPU time 15.87 seconds
Started Feb 04 01:12:30 PM PST 24
Finished Feb 04 01:12:48 PM PST 24
Peak memory 218832 kb
Host smart-8281e0f2-2f16-4f55-baaa-be6726799172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071735945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4071735945
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1164621751
Short name T319
Test name
Test status
Simulation time 310713578 ps
CPU time 9.26 seconds
Started Feb 04 01:12:39 PM PST 24
Finished Feb 04 01:12:50 PM PST 24
Peak memory 217880 kb
Host smart-e61f2436-d761-446a-a91e-7e4099e9ec8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164621751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1164621751
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2273052799
Short name T728
Test name
Test status
Simulation time 1437243012 ps
CPU time 9.63 seconds
Started Feb 04 01:12:37 PM PST 24
Finished Feb 04 01:12:50 PM PST 24
Peak memory 217796 kb
Host smart-34f1eaac-4c00-4f61-a74d-2d28810a6eaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273052799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
273052799
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1462395049
Short name T755
Test name
Test status
Simulation time 249139217 ps
CPU time 6.62 seconds
Started Feb 04 01:12:31 PM PST 24
Finished Feb 04 01:12:39 PM PST 24
Peak memory 217856 kb
Host smart-cbb15fec-04ad-4432-99a7-ee8cc9cfb5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462395049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1462395049
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.387877482
Short name T887
Test name
Test status
Simulation time 33629299 ps
CPU time 1.97 seconds
Started Feb 04 01:12:25 PM PST 24
Finished Feb 04 01:12:27 PM PST 24
Peak memory 213228 kb
Host smart-13d98f98-1063-4bfc-b2ac-90958529090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387877482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.387877482
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.433585675
Short name T372
Test name
Test status
Simulation time 839637386 ps
CPU time 25.52 seconds
Started Feb 04 01:12:21 PM PST 24
Finished Feb 04 01:12:49 PM PST 24
Peak memory 250880 kb
Host smart-f519138d-509e-41b7-9e0f-5b805efe9dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433585675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.433585675
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.214946463
Short name T905
Test name
Test status
Simulation time 247796844 ps
CPU time 9.99 seconds
Started Feb 04 01:12:26 PM PST 24
Finished Feb 04 01:12:37 PM PST 24
Peak memory 250904 kb
Host smart-d3c290f1-6b9a-4ec5-809d-fdd073d6468d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214946463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.214946463
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1258754254
Short name T937
Test name
Test status
Simulation time 3365527319 ps
CPU time 52.72 seconds
Started Feb 04 01:12:38 PM PST 24
Finished Feb 04 01:13:33 PM PST 24
Peak memory 250900 kb
Host smart-28d028fe-8892-4458-9f84-983dc75fdd77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258754254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1258754254
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3968107600
Short name T818
Test name
Test status
Simulation time 70470577 ps
CPU time 0.74 seconds
Started Feb 04 01:12:21 PM PST 24
Finished Feb 04 01:12:24 PM PST 24
Peak memory 207972 kb
Host smart-4cd2acbc-6737-48e1-9a30-5e445ede9687
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968107600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3968107600
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1841841682
Short name T702
Test name
Test status
Simulation time 53384318 ps
CPU time 0.92 seconds
Started Feb 04 01:14:13 PM PST 24
Finished Feb 04 01:14:15 PM PST 24
Peak memory 209388 kb
Host smart-b1d75e75-6d61-46db-a43a-2ec14eab269f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841841682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1841841682
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2045422414
Short name T929
Test name
Test status
Simulation time 383874045 ps
CPU time 7.85 seconds
Started Feb 04 01:13:54 PM PST 24
Finished Feb 04 01:14:02 PM PST 24
Peak memory 217932 kb
Host smart-3539d545-2b91-4dad-acc8-7f02aef24b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045422414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2045422414
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1424805957
Short name T673
Test name
Test status
Simulation time 120540531 ps
CPU time 1.02 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 209420 kb
Host smart-8dfb6b25-f796-4115-893a-7eafa6b12eb3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424805957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.1424805957
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.4044363846
Short name T615
Test name
Test status
Simulation time 4637750753 ps
CPU time 35.21 seconds
Started Feb 04 01:13:55 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 217856 kb
Host smart-d7042d53-64ab-4ff0-bdc8-5e0c1e0e4416
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044363846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.4044363846
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1821291336
Short name T326
Test name
Test status
Simulation time 358306595 ps
CPU time 5.29 seconds
Started Feb 04 01:14:10 PM PST 24
Finished Feb 04 01:14:17 PM PST 24
Peak memory 217800 kb
Host smart-28a18546-74d6-4c9d-a949-d4b4d638baa2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821291336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1821291336
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.689140866
Short name T552
Test name
Test status
Simulation time 384023826 ps
CPU time 5.68 seconds
Started Feb 04 01:13:54 PM PST 24
Finished Feb 04 01:14:01 PM PST 24
Peak memory 212928 kb
Host smart-2c9e7d93-a86f-4371-8836-c2a7b045c74f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689140866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
689140866
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.356015706
Short name T922
Test name
Test status
Simulation time 2475105537 ps
CPU time 52.42 seconds
Started Feb 04 01:14:05 PM PST 24
Finished Feb 04 01:15:02 PM PST 24
Peak memory 267324 kb
Host smart-af21029c-7dc0-4597-8d37-eb640ba696ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356015706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.356015706
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3115709802
Short name T129
Test name
Test status
Simulation time 735850505 ps
CPU time 12.47 seconds
Started Feb 04 01:14:00 PM PST 24
Finished Feb 04 01:14:15 PM PST 24
Peak memory 250808 kb
Host smart-2ecfa39e-bbb1-4b49-a97d-95f050f8e706
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115709802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3115709802
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2142725344
Short name T450
Test name
Test status
Simulation time 199381897 ps
CPU time 2.83 seconds
Started Feb 04 01:13:41 PM PST 24
Finished Feb 04 01:13:49 PM PST 24
Peak memory 217828 kb
Host smart-353fe392-be05-4e69-be4d-0adb8a9ed93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142725344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2142725344
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1746220049
Short name T411
Test name
Test status
Simulation time 2310307935 ps
CPU time 12.56 seconds
Started Feb 04 01:14:04 PM PST 24
Finished Feb 04 01:14:22 PM PST 24
Peak memory 218160 kb
Host smart-b0e131e2-abff-4e63-9686-9b83fb95bac7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746220049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1746220049
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2284933140
Short name T923
Test name
Test status
Simulation time 1291260450 ps
CPU time 8.44 seconds
Started Feb 04 01:14:06 PM PST 24
Finished Feb 04 01:14:18 PM PST 24
Peak memory 217768 kb
Host smart-a1444f72-6a7d-482e-8ba9-f8e2003cdbad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284933140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2284933140
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3408921093
Short name T361
Test name
Test status
Simulation time 1847292727 ps
CPU time 9.26 seconds
Started Feb 04 01:14:08 PM PST 24
Finished Feb 04 01:14:19 PM PST 24
Peak memory 217760 kb
Host smart-2501124b-d5aa-4f58-937e-a9d4e494667c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408921093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3408921093
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2729813477
Short name T13
Test name
Test status
Simulation time 414601427 ps
CPU time 10.2 seconds
Started Feb 04 01:13:42 PM PST 24
Finished Feb 04 01:13:57 PM PST 24
Peak memory 217804 kb
Host smart-e3dc54fc-5ad8-4434-9c74-c1c690c96f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729813477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2729813477
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3242115361
Short name T817
Test name
Test status
Simulation time 65553225 ps
CPU time 2.53 seconds
Started Feb 04 01:13:42 PM PST 24
Finished Feb 04 01:13:49 PM PST 24
Peak memory 213420 kb
Host smart-df901a15-9782-496a-a176-27a1e7d409c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242115361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3242115361
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.370535585
Short name T464
Test name
Test status
Simulation time 485713449 ps
CPU time 25.46 seconds
Started Feb 04 01:13:43 PM PST 24
Finished Feb 04 01:14:12 PM PST 24
Peak memory 250880 kb
Host smart-1590b2f3-42c6-446f-9910-93b3b4c0bfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370535585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.370535585
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3627255159
Short name T765
Test name
Test status
Simulation time 125277532 ps
CPU time 8.87 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:55 PM PST 24
Peak memory 250924 kb
Host smart-c2bdf7fd-7645-40dd-ad07-6d5bee22303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627255159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3627255159
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2684834741
Short name T687
Test name
Test status
Simulation time 21606471553 ps
CPU time 103.78 seconds
Started Feb 04 01:14:02 PM PST 24
Finished Feb 04 01:15:47 PM PST 24
Peak memory 275188 kb
Host smart-fe16b01b-7d4d-448b-be03-06246d348a81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684834741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2684834741
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.340661459
Short name T73
Test name
Test status
Simulation time 95342787 ps
CPU time 1.04 seconds
Started Feb 04 01:14:08 PM PST 24
Finished Feb 04 01:14:11 PM PST 24
Peak memory 209452 kb
Host smart-41dac915-ca03-4b92-863d-a4b120204a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340661459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.340661459
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3573528667
Short name T927
Test name
Test status
Simulation time 2549424699 ps
CPU time 8.63 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:32 PM PST 24
Peak memory 217820 kb
Host smart-99260227-46b5-4188-8429-2d1955ccd59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573528667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3573528667
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.4276288085
Short name T559
Test name
Test status
Simulation time 691800361 ps
CPU time 6.38 seconds
Started Feb 04 01:13:59 PM PST 24
Finished Feb 04 01:14:09 PM PST 24
Peak memory 209420 kb
Host smart-7e48c8ce-a2d1-47d5-a456-2c9ecdb3cd24
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276288085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.4276288085
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2666701546
Short name T397
Test name
Test status
Simulation time 3675865958 ps
CPU time 55.46 seconds
Started Feb 04 01:14:01 PM PST 24
Finished Feb 04 01:14:58 PM PST 24
Peak memory 218896 kb
Host smart-9bab9c8b-4eea-410f-9c66-24dc03ce3432
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666701546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2666701546
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3587143017
Short name T413
Test name
Test status
Simulation time 250902330 ps
CPU time 1.9 seconds
Started Feb 04 01:14:09 PM PST 24
Finished Feb 04 01:14:12 PM PST 24
Peak memory 217800 kb
Host smart-e8b686e1-cfcd-48e1-b3b6-2ce124aa25e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587143017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3587143017
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3909520158
Short name T562
Test name
Test status
Simulation time 279895382 ps
CPU time 2.55 seconds
Started Feb 04 01:14:09 PM PST 24
Finished Feb 04 01:14:13 PM PST 24
Peak memory 212588 kb
Host smart-81832d47-f74d-46ce-9677-0fe41b55809a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909520158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3909520158
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1817723686
Short name T613
Test name
Test status
Simulation time 2328416678 ps
CPU time 86.7 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:15:39 PM PST 24
Peak memory 283492 kb
Host smart-7b025325-3b94-4b03-9c3f-0cc279bf792d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817723686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1817723686
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1423118618
Short name T310
Test name
Test status
Simulation time 2340626076 ps
CPU time 10.46 seconds
Started Feb 04 01:14:02 PM PST 24
Finished Feb 04 01:14:14 PM PST 24
Peak memory 222568 kb
Host smart-2a843790-b652-46df-918c-26287f25bac8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423118618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1423118618
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1751999878
Short name T707
Test name
Test status
Simulation time 89626797 ps
CPU time 1.54 seconds
Started Feb 04 01:14:01 PM PST 24
Finished Feb 04 01:14:04 PM PST 24
Peak memory 217872 kb
Host smart-e4eaeecf-84cc-40b5-997d-5eaf21ea117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751999878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1751999878
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3161242716
Short name T786
Test name
Test status
Simulation time 264748103 ps
CPU time 8.41 seconds
Started Feb 04 01:14:02 PM PST 24
Finished Feb 04 01:14:12 PM PST 24
Peak memory 217708 kb
Host smart-48eb24f6-ee1c-47ac-8068-820ea79ab128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161242716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3161242716
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3693339699
Short name T894
Test name
Test status
Simulation time 228910727 ps
CPU time 7.18 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:21 PM PST 24
Peak memory 217872 kb
Host smart-f9448f44-cd1c-4304-89cb-c94eedd3854a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693339699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3693339699
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2886982291
Short name T531
Test name
Test status
Simulation time 1644412111 ps
CPU time 9.74 seconds
Started Feb 04 01:14:13 PM PST 24
Finished Feb 04 01:14:25 PM PST 24
Peak memory 217816 kb
Host smart-5717b255-2b85-47e9-8df9-9ae65a9b0bdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886982291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2886982291
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3236631437
Short name T694
Test name
Test status
Simulation time 1007303739 ps
CPU time 6.12 seconds
Started Feb 04 01:13:59 PM PST 24
Finished Feb 04 01:14:08 PM PST 24
Peak memory 217852 kb
Host smart-e8ddb8f5-abde-4c5d-b85c-fcab8166d1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236631437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3236631437
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2603193365
Short name T79
Test name
Test status
Simulation time 643281455 ps
CPU time 2.18 seconds
Started Feb 04 01:14:10 PM PST 24
Finished Feb 04 01:14:13 PM PST 24
Peak memory 213412 kb
Host smart-3543a2f2-106f-4e30-86bb-c26d6ee16137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603193365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2603193365
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.174487034
Short name T919
Test name
Test status
Simulation time 546329992 ps
CPU time 26.77 seconds
Started Feb 04 01:14:08 PM PST 24
Finished Feb 04 01:14:37 PM PST 24
Peak memory 250728 kb
Host smart-054caf25-efeb-4915-bef6-226c130f3753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174487034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.174487034
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.617514064
Short name T547
Test name
Test status
Simulation time 62599224 ps
CPU time 3.06 seconds
Started Feb 04 01:14:03 PM PST 24
Finished Feb 04 01:14:12 PM PST 24
Peak memory 221684 kb
Host smart-3d555f62-925d-4762-9130-c60019926747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617514064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.617514064
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3727871361
Short name T568
Test name
Test status
Simulation time 29688923056 ps
CPU time 104.35 seconds
Started Feb 04 01:14:01 PM PST 24
Finished Feb 04 01:15:47 PM PST 24
Peak memory 259140 kb
Host smart-fffbb894-96ad-4f76-b97c-51e0b2461107
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727871361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3727871361
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3815160452
Short name T793
Test name
Test status
Simulation time 107272653 ps
CPU time 0.69 seconds
Started Feb 04 01:13:58 PM PST 24
Finished Feb 04 01:14:00 PM PST 24
Peak memory 206292 kb
Host smart-2facbee5-9323-44c1-949a-de0fcb9fcd76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815160452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3815160452
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2561581927
Short name T720
Test name
Test status
Simulation time 344200165 ps
CPU time 14.23 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:38 PM PST 24
Peak memory 217760 kb
Host smart-465163a9-cb2c-4445-b05c-41c6230d826c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561581927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2561581927
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.189762781
Short name T629
Test name
Test status
Simulation time 356794406 ps
CPU time 7.46 seconds
Started Feb 04 01:14:13 PM PST 24
Finished Feb 04 01:14:22 PM PST 24
Peak memory 209432 kb
Host smart-a4af6d35-40f2-4db0-a7db-cff15abaaaa4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189762781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_ac
cess.189762781
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.815587051
Short name T663
Test name
Test status
Simulation time 31171333537 ps
CPU time 29.88 seconds
Started Feb 04 01:13:58 PM PST 24
Finished Feb 04 01:14:29 PM PST 24
Peak memory 218228 kb
Host smart-5b1e0fb3-210c-4ee1-ba69-3c299d9ca3a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815587051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.815587051
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3063334965
Short name T882
Test name
Test status
Simulation time 56744112 ps
CPU time 2.56 seconds
Started Feb 04 01:14:10 PM PST 24
Finished Feb 04 01:14:13 PM PST 24
Peak memory 217796 kb
Host smart-39ef66c1-7d3b-4c3f-adee-7dacc0f20407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063334965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3063334965
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.660618683
Short name T74
Test name
Test status
Simulation time 85376710 ps
CPU time 2.95 seconds
Started Feb 04 01:14:02 PM PST 24
Finished Feb 04 01:14:06 PM PST 24
Peak memory 212628 kb
Host smart-6683be21-b24b-4221-9241-4ee088658517
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660618683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
660618683
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.640021199
Short name T932
Test name
Test status
Simulation time 5124857848 ps
CPU time 30.22 seconds
Started Feb 04 01:14:11 PM PST 24
Finished Feb 04 01:14:43 PM PST 24
Peak memory 250688 kb
Host smart-d9265721-7a04-494a-a9df-5930e33ea109
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640021199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.640021199
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1593844826
Short name T672
Test name
Test status
Simulation time 554179933 ps
CPU time 20.68 seconds
Started Feb 04 01:14:05 PM PST 24
Finished Feb 04 01:14:30 PM PST 24
Peak memory 250928 kb
Host smart-e34287fa-8d73-494c-b787-3662f0cc83dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593844826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1593844826
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.750276746
Short name T394
Test name
Test status
Simulation time 84614775 ps
CPU time 2.36 seconds
Started Feb 04 01:13:59 PM PST 24
Finished Feb 04 01:14:04 PM PST 24
Peak memory 217812 kb
Host smart-eec9a584-edaa-4e4a-8b1a-722b82d0284f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750276746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.750276746
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2526492802
Short name T54
Test name
Test status
Simulation time 1355554142 ps
CPU time 11.22 seconds
Started Feb 04 01:14:01 PM PST 24
Finished Feb 04 01:14:14 PM PST 24
Peak memory 218412 kb
Host smart-c35b0799-2668-4a27-8425-f5db41aef12f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526492802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2526492802
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3211585462
Short name T827
Test name
Test status
Simulation time 1572951481 ps
CPU time 9.99 seconds
Started Feb 04 01:14:11 PM PST 24
Finished Feb 04 01:14:22 PM PST 24
Peak memory 217732 kb
Host smart-b69a7e8e-fd19-460f-8be6-539b89c0c885
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211585462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3211585462
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1036292603
Short name T790
Test name
Test status
Simulation time 1991316383 ps
CPU time 11.53 seconds
Started Feb 04 01:14:07 PM PST 24
Finished Feb 04 01:14:21 PM PST 24
Peak memory 217860 kb
Host smart-b7abe599-ad7a-4782-87d5-979678254d86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036292603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1036292603
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3852846971
Short name T650
Test name
Test status
Simulation time 1026709630 ps
CPU time 6.29 seconds
Started Feb 04 01:14:05 PM PST 24
Finished Feb 04 01:14:16 PM PST 24
Peak memory 217928 kb
Host smart-d811050d-d170-495d-b8a2-4797cab36405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852846971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3852846971
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.216131616
Short name T733
Test name
Test status
Simulation time 38713198 ps
CPU time 2.24 seconds
Started Feb 04 01:14:09 PM PST 24
Finished Feb 04 01:14:13 PM PST 24
Peak memory 213552 kb
Host smart-4f09f932-198e-45f8-8729-22fe4bcdc364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216131616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.216131616
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2770900532
Short name T484
Test name
Test status
Simulation time 1272380367 ps
CPU time 30.68 seconds
Started Feb 04 01:14:25 PM PST 24
Finished Feb 04 01:14:57 PM PST 24
Peak memory 250740 kb
Host smart-4cf4c6ed-5b48-4d7d-99e8-00cef8974b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770900532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2770900532
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1538288213
Short name T201
Test name
Test status
Simulation time 165827006 ps
CPU time 8.51 seconds
Started Feb 04 01:14:06 PM PST 24
Finished Feb 04 01:14:18 PM PST 24
Peak memory 246948 kb
Host smart-79bdd0b9-a595-4014-836a-4d4a9f36f650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538288213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1538288213
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1153831477
Short name T897
Test name
Test status
Simulation time 8496557900 ps
CPU time 37.44 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:51 PM PST 24
Peak memory 250700 kb
Host smart-0494875d-757e-4564-a4a7-d662111406cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153831477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1153831477
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4044904889
Short name T50
Test name
Test status
Simulation time 20969193 ps
CPU time 1.01 seconds
Started Feb 04 01:14:18 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 211236 kb
Host smart-7eb5783c-54ce-4142-b034-891f52d686b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044904889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4044904889
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.701029064
Short name T744
Test name
Test status
Simulation time 17377808 ps
CPU time 0.88 seconds
Started Feb 04 01:14:13 PM PST 24
Finished Feb 04 01:14:15 PM PST 24
Peak memory 209172 kb
Host smart-34967d86-471b-4bd2-892b-feb122681302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701029064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.701029064
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1907615048
Short name T974
Test name
Test status
Simulation time 368034880 ps
CPU time 9.01 seconds
Started Feb 04 01:14:09 PM PST 24
Finished Feb 04 01:14:19 PM PST 24
Peak memory 217832 kb
Host smart-38c9bd8f-cbe4-400e-997a-39fde1551c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907615048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1907615048
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2491922904
Short name T689
Test name
Test status
Simulation time 1483209376 ps
CPU time 26.75 seconds
Started Feb 04 01:14:13 PM PST 24
Finished Feb 04 01:14:41 PM PST 24
Peak memory 217456 kb
Host smart-24b488bb-eacf-4c83-abaf-73b15f143dc2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491922904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_a
ccess.2491922904
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3461580299
Short name T19
Test name
Test status
Simulation time 4426505535 ps
CPU time 45.35 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:15:03 PM PST 24
Peak memory 218780 kb
Host smart-066beba2-de96-4683-8b43-b6f69a296c51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461580299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3461580299
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3317624887
Short name T366
Test name
Test status
Simulation time 464564111 ps
CPU time 4.78 seconds
Started Feb 04 01:14:25 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 217764 kb
Host smart-253c7712-1d41-48de-b935-13eeef1dace4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317624887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3317624887
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.496175414
Short name T22
Test name
Test status
Simulation time 347482514 ps
CPU time 2.17 seconds
Started Feb 04 01:14:25 PM PST 24
Finished Feb 04 01:14:28 PM PST 24
Peak memory 212532 kb
Host smart-447a3a03-308b-4235-8da8-80267604acf4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496175414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
496175414
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2124688783
Short name T764
Test name
Test status
Simulation time 1347256616 ps
CPU time 37.37 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:55 PM PST 24
Peak memory 250700 kb
Host smart-b7dfcc94-79b2-441d-a06d-e8faeb406440
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124688783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2124688783
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3563359512
Short name T900
Test name
Test status
Simulation time 1986786144 ps
CPU time 19.43 seconds
Started Feb 04 01:14:18 PM PST 24
Finished Feb 04 01:14:39 PM PST 24
Peak memory 250840 kb
Host smart-b87aec34-ac8b-48c5-95ee-eac1a47867ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563359512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3563359512
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2301761258
Short name T850
Test name
Test status
Simulation time 35788509 ps
CPU time 2.45 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:16 PM PST 24
Peak memory 217676 kb
Host smart-67be3725-3490-47e4-937d-aedccbc2c03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301761258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2301761258
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.933805788
Short name T857
Test name
Test status
Simulation time 2036207271 ps
CPU time 11.81 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:25 PM PST 24
Peak memory 218128 kb
Host smart-c7c6ae58-b47a-4dda-a73c-bb2694ca47a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933805788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.933805788
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3042645418
Short name T392
Test name
Test status
Simulation time 651946428 ps
CPU time 22.29 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:14:41 PM PST 24
Peak memory 217844 kb
Host smart-8ed0fb57-10df-4f1c-bd42-4e86306ebd56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042645418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3042645418
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.162828541
Short name T127
Test name
Test status
Simulation time 1137113428 ps
CPU time 10.77 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:14:29 PM PST 24
Peak memory 217840 kb
Host smart-7a85db90-14e2-42e2-adbf-5493fbb45567
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162828541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.162828541
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.4052416507
Short name T4
Test name
Test status
Simulation time 442818732 ps
CPU time 9.38 seconds
Started Feb 04 01:13:58 PM PST 24
Finished Feb 04 01:14:09 PM PST 24
Peak memory 217808 kb
Host smart-1a24a64d-45e9-49c4-8450-3bc2bdc219f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052416507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.4052416507
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2922708303
Short name T624
Test name
Test status
Simulation time 42777700 ps
CPU time 1.77 seconds
Started Feb 04 01:14:06 PM PST 24
Finished Feb 04 01:14:11 PM PST 24
Peak memory 213544 kb
Host smart-9df73573-a52e-4ac0-99ca-38a83bd56965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922708303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2922708303
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2878724392
Short name T756
Test name
Test status
Simulation time 1175289517 ps
CPU time 28.64 seconds
Started Feb 04 01:14:01 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 250840 kb
Host smart-1aa8edc2-bbad-4877-987d-1a9a99920fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878724392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2878724392
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.4192109822
Short name T762
Test name
Test status
Simulation time 56808592 ps
CPU time 2.78 seconds
Started Feb 04 01:13:59 PM PST 24
Finished Feb 04 01:14:05 PM PST 24
Peak memory 221908 kb
Host smart-b2b2ca41-d21d-4933-82f3-8db68656160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192109822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.4192109822
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1786149487
Short name T128
Test name
Test status
Simulation time 15646709166 ps
CPU time 112.62 seconds
Started Feb 04 01:14:21 PM PST 24
Finished Feb 04 01:16:15 PM PST 24
Peak memory 221368 kb
Host smart-4beb8a58-f0c2-407f-b9b9-76ed0aa7255e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786149487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1786149487
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3646665545
Short name T889
Test name
Test status
Simulation time 11470341 ps
CPU time 0.78 seconds
Started Feb 04 01:14:10 PM PST 24
Finished Feb 04 01:14:13 PM PST 24
Peak memory 208216 kb
Host smart-f6b140d8-2912-4fee-99c6-dfb7b930e5d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646665545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3646665545
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2832633182
Short name T943
Test name
Test status
Simulation time 18708446 ps
CPU time 0.77 seconds
Started Feb 04 01:14:21 PM PST 24
Finished Feb 04 01:14:23 PM PST 24
Peak memory 209192 kb
Host smart-8fc3c249-6561-44ee-8e72-76156da4e003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832633182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2832633182
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3629013595
Short name T910
Test name
Test status
Simulation time 1166403131 ps
CPU time 10.45 seconds
Started Feb 04 01:14:19 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 217816 kb
Host smart-fc602bce-720b-4d85-90a3-2626896d728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629013595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3629013595
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.877608479
Short name T10
Test name
Test status
Simulation time 871080810 ps
CPU time 2.95 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 209376 kb
Host smart-cf4db008-9227-4894-8fa9-2a8072956863
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877608479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_ac
cess.877608479
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3498428490
Short name T834
Test name
Test status
Simulation time 5459614314 ps
CPU time 65.64 seconds
Started Feb 04 01:14:14 PM PST 24
Finished Feb 04 01:15:21 PM PST 24
Peak memory 218900 kb
Host smart-2ed8459f-c58f-44cc-877e-37cc97fa3d2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498428490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3498428490
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2053104807
Short name T398
Test name
Test status
Simulation time 613978894 ps
CPU time 5.25 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:23 PM PST 24
Peak memory 217712 kb
Host smart-215c88e4-21ee-4dbe-be66-841d0cfbb0f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053104807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2053104807
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.659518985
Short name T352
Test name
Test status
Simulation time 90998655 ps
CPU time 3.04 seconds
Started Feb 04 01:14:11 PM PST 24
Finished Feb 04 01:14:15 PM PST 24
Peak memory 212660 kb
Host smart-611dfb1a-88f7-4cf5-83a5-827038d3e7a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659518985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
659518985
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.457599108
Short name T746
Test name
Test status
Simulation time 1666357525 ps
CPU time 49.04 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:15:07 PM PST 24
Peak memory 283456 kb
Host smart-c3eb6495-7a51-4b79-92d9-2a4d83a23b83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457599108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.457599108
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1515316155
Short name T584
Test name
Test status
Simulation time 532291723 ps
CPU time 12.33 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:26 PM PST 24
Peak memory 245552 kb
Host smart-77034134-bf2e-404b-979d-413ebb6f41f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515316155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1515316155
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1505974424
Short name T946
Test name
Test status
Simulation time 233348896 ps
CPU time 2.52 seconds
Started Feb 04 01:14:23 PM PST 24
Finished Feb 04 01:14:27 PM PST 24
Peak memory 217820 kb
Host smart-060f7411-866a-4a62-8156-e4506b570648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505974424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1505974424
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.179491606
Short name T639
Test name
Test status
Simulation time 3353102157 ps
CPU time 14.3 seconds
Started Feb 04 01:14:24 PM PST 24
Finished Feb 04 01:14:40 PM PST 24
Peak memory 218884 kb
Host smart-77a459b0-9788-423d-8508-80196fe5a9ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179491606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.179491606
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2648597075
Short name T780
Test name
Test status
Simulation time 760912832 ps
CPU time 10.1 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:24 PM PST 24
Peak memory 217876 kb
Host smart-542c0b1f-3734-4697-bf38-e55931276f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648597075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2648597075
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.199673118
Short name T729
Test name
Test status
Simulation time 1890862713 ps
CPU time 10.1 seconds
Started Feb 04 01:14:19 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 217820 kb
Host smart-10449b2f-5fdf-443d-a922-7ced6c080cb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199673118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.199673118
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2660943653
Short name T403
Test name
Test status
Simulation time 496900854 ps
CPU time 10.58 seconds
Started Feb 04 01:14:07 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 217752 kb
Host smart-7aed74d1-3170-4785-a60f-f327089d902e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660943653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2660943653
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2574361444
Short name T64
Test name
Test status
Simulation time 30177858 ps
CPU time 1.9 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:15 PM PST 24
Peak memory 213256 kb
Host smart-71b4e826-fe4a-46e6-a895-661174d22b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574361444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2574361444
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3195880447
Short name T717
Test name
Test status
Simulation time 321284452 ps
CPU time 14.11 seconds
Started Feb 04 01:14:05 PM PST 24
Finished Feb 04 01:14:24 PM PST 24
Peak memory 250868 kb
Host smart-271a59d6-4095-4938-bac3-c4a9583ac76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195880447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3195880447
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1458409357
Short name T885
Test name
Test status
Simulation time 70513824 ps
CPU time 7.98 seconds
Started Feb 04 01:14:10 PM PST 24
Finished Feb 04 01:14:19 PM PST 24
Peak memory 246676 kb
Host smart-f854e229-780a-4a68-80b0-eb35d4f4286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458409357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1458409357
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2633266584
Short name T427
Test name
Test status
Simulation time 2830241699 ps
CPU time 61.99 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:15:15 PM PST 24
Peak memory 250972 kb
Host smart-e0e19229-4bd0-413d-85f2-790422330c61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633266584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2633266584
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2361092838
Short name T23
Test name
Test status
Simulation time 74527964 ps
CPU time 0.71 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:14:19 PM PST 24
Peak memory 206640 kb
Host smart-254591f6-6644-479f-b9b7-221104a42a6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361092838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2361092838
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3652694419
Short name T585
Test name
Test status
Simulation time 18375754 ps
CPU time 0.92 seconds
Started Feb 04 01:14:10 PM PST 24
Finished Feb 04 01:14:12 PM PST 24
Peak memory 209396 kb
Host smart-471f16c8-95a5-4634-95b4-43ec370765b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652694419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3652694419
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.407819491
Short name T627
Test name
Test status
Simulation time 436563316 ps
CPU time 16.54 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:40 PM PST 24
Peak memory 217796 kb
Host smart-f3ae30bc-9c7b-45ec-9118-5c05f0d202c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407819491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.407819491
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2589679116
Short name T9
Test name
Test status
Simulation time 167047395 ps
CPU time 2.26 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:19 PM PST 24
Peak memory 209360 kb
Host smart-2d3b9fa9-ad5b-47ae-a75c-11de640a3b38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589679116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.2589679116
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.897230227
Short name T133
Test name
Test status
Simulation time 877665726 ps
CPU time 25.36 seconds
Started Feb 04 01:14:09 PM PST 24
Finished Feb 04 01:14:36 PM PST 24
Peak memory 217788 kb
Host smart-02dc1240-c7e3-4ab9-adef-4ff1584586e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897230227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.897230227
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.481459213
Short name T486
Test name
Test status
Simulation time 413272303 ps
CPU time 12.03 seconds
Started Feb 04 01:14:24 PM PST 24
Finished Feb 04 01:14:38 PM PST 24
Peak memory 217748 kb
Host smart-6cb9f41c-6f0a-48e7-9470-57c1f787390d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481459213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.481459213
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3163782192
Short name T914
Test name
Test status
Simulation time 863250951 ps
CPU time 6.32 seconds
Started Feb 04 01:14:13 PM PST 24
Finished Feb 04 01:14:21 PM PST 24
Peak memory 213124 kb
Host smart-b7a8d08a-35d7-4213-ad18-fd4c50ee1531
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163782192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3163782192
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2010650995
Short name T610
Test name
Test status
Simulation time 7046166542 ps
CPU time 68.18 seconds
Started Feb 04 01:14:23 PM PST 24
Finished Feb 04 01:15:33 PM PST 24
Peak memory 278268 kb
Host smart-e4fdc1e9-cb43-4408-af73-fbe0943aab56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010650995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2010650995
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1604310888
Short name T20
Test name
Test status
Simulation time 849880991 ps
CPU time 17.29 seconds
Started Feb 04 01:14:10 PM PST 24
Finished Feb 04 01:14:28 PM PST 24
Peak memory 250828 kb
Host smart-7cdfcc4e-dd56-43cb-8fab-81d8b3fd11c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604310888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1604310888
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3605543384
Short name T973
Test name
Test status
Simulation time 296039515 ps
CPU time 3.64 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:27 PM PST 24
Peak memory 217816 kb
Host smart-bff92561-8dcd-499e-8571-2fb1d7db17d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605543384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3605543384
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2801184524
Short name T950
Test name
Test status
Simulation time 204561999 ps
CPU time 11.36 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:25 PM PST 24
Peak memory 218844 kb
Host smart-9d4a52e1-802d-499e-831e-b26bf2cabdbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801184524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2801184524
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.749526924
Short name T934
Test name
Test status
Simulation time 2489805307 ps
CPU time 27.39 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 217840 kb
Host smart-eec81391-e1c4-47e4-b687-f7e2ba20a46f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749526924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.749526924
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.45270078
Short name T59
Test name
Test status
Simulation time 818795053 ps
CPU time 7.2 seconds
Started Feb 04 01:14:19 PM PST 24
Finished Feb 04 01:14:28 PM PST 24
Peak memory 217864 kb
Host smart-eb781e25-6dd2-4362-a04b-ebfe1ab3fddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45270078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.45270078
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1988047621
Short name T795
Test name
Test status
Simulation time 390828849 ps
CPU time 14.3 seconds
Started Feb 04 01:14:24 PM PST 24
Finished Feb 04 01:14:40 PM PST 24
Peak memory 217800 kb
Host smart-f9ce4fc0-0fdb-424a-8902-bed451f47910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988047621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1988047621
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1068743741
Short name T512
Test name
Test status
Simulation time 147486001 ps
CPU time 3.87 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:27 PM PST 24
Peak memory 213948 kb
Host smart-ecd35afe-b388-4f69-8f3d-b9a3a27107ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068743741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1068743741
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2478203762
Short name T638
Test name
Test status
Simulation time 230188880 ps
CPU time 19.25 seconds
Started Feb 04 01:14:23 PM PST 24
Finished Feb 04 01:14:45 PM PST 24
Peak memory 250932 kb
Host smart-bf62dbbb-fef7-4a1b-9da5-909c6cf92641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478203762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2478203762
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2191812576
Short name T924
Test name
Test status
Simulation time 66699646 ps
CPU time 8.14 seconds
Started Feb 04 01:14:23 PM PST 24
Finished Feb 04 01:14:33 PM PST 24
Peak memory 250660 kb
Host smart-f9e06004-ddd2-4de5-87db-d6ef0fb495ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191812576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2191812576
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1337012151
Short name T418
Test name
Test status
Simulation time 2903284189 ps
CPU time 97.13 seconds
Started Feb 04 01:14:15 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 250872 kb
Host smart-1bfbbe5c-f38f-4ace-afb3-817c2a8679ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337012151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1337012151
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1170161265
Short name T557
Test name
Test status
Simulation time 36965078 ps
CPU time 0.73 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:13 PM PST 24
Peak memory 207964 kb
Host smart-45d893de-2fd5-4019-ae43-ba8aaa496416
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170161265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1170161265
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2669583768
Short name T787
Test name
Test status
Simulation time 17595325 ps
CPU time 0.86 seconds
Started Feb 04 01:14:18 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 209408 kb
Host smart-ac97f63e-abc7-4fbb-9311-5ab7b116db3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669583768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2669583768
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1807775189
Short name T478
Test name
Test status
Simulation time 331957025 ps
CPU time 11.6 seconds
Started Feb 04 01:14:27 PM PST 24
Finished Feb 04 01:14:41 PM PST 24
Peak memory 217856 kb
Host smart-b394e84d-1fec-4243-b7cc-62600dff2544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807775189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1807775189
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1879016513
Short name T930
Test name
Test status
Simulation time 295476038 ps
CPU time 2.66 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:16 PM PST 24
Peak memory 209488 kb
Host smart-18823d45-704a-4b9b-9fd2-3eff4a0bc9f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879016513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.1879016513
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1921286725
Short name T503
Test name
Test status
Simulation time 4546406958 ps
CPU time 19.9 seconds
Started Feb 04 01:14:09 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 218008 kb
Host smart-0db67392-2e7b-4a40-8b99-90e91d80c25d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921286725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1921286725
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.849062080
Short name T976
Test name
Test status
Simulation time 1365202995 ps
CPU time 15.29 seconds
Started Feb 04 01:14:09 PM PST 24
Finished Feb 04 01:14:26 PM PST 24
Peak memory 217804 kb
Host smart-7d19ed00-9b01-4f71-bb5c-42c760d8c809
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849062080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.849062080
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3471701220
Short name T912
Test name
Test status
Simulation time 131108688 ps
CPU time 1.79 seconds
Started Feb 04 01:14:13 PM PST 24
Finished Feb 04 01:14:17 PM PST 24
Peak memory 212584 kb
Host smart-740b22b4-6dc8-4cdd-818b-f0a532b0b3f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471701220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3471701220
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.926219546
Short name T957
Test name
Test status
Simulation time 2148231321 ps
CPU time 47.13 seconds
Started Feb 04 01:14:15 PM PST 24
Finished Feb 04 01:15:03 PM PST 24
Peak memory 252960 kb
Host smart-515947d2-e3e2-4ca0-8964-522f4cbae196
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926219546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.926219546
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.888458601
Short name T667
Test name
Test status
Simulation time 1500860415 ps
CPU time 10.31 seconds
Started Feb 04 01:14:19 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 249796 kb
Host smart-90a1b705-8b6f-4b51-bbc5-c560e08fdc01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888458601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.888458601
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1076297301
Short name T657
Test name
Test status
Simulation time 208258542 ps
CPU time 2.41 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 217772 kb
Host smart-dc00076a-b56f-4491-a8a2-f43524c84016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076297301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1076297301
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1248948907
Short name T652
Test name
Test status
Simulation time 1023657198 ps
CPU time 19.38 seconds
Started Feb 04 01:14:23 PM PST 24
Finished Feb 04 01:14:43 PM PST 24
Peak memory 218808 kb
Host smart-fc4f014c-5354-43bf-8698-a0500a64e054
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248948907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1248948907
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1977350664
Short name T814
Test name
Test status
Simulation time 2647914361 ps
CPU time 17.31 seconds
Started Feb 04 01:14:12 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 217748 kb
Host smart-8744af77-ac92-4209-a0b0-b9145dd43237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977350664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1977350664
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.81557674
Short name T436
Test name
Test status
Simulation time 475220451 ps
CPU time 9.21 seconds
Started Feb 04 01:14:19 PM PST 24
Finished Feb 04 01:14:30 PM PST 24
Peak memory 217864 kb
Host smart-d1923201-bde9-48b8-812a-772bab8428cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81557674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.81557674
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.326545308
Short name T771
Test name
Test status
Simulation time 2203677254 ps
CPU time 10.25 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:14:29 PM PST 24
Peak memory 217832 kb
Host smart-3e26c786-7104-4923-8672-927060110cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326545308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.326545308
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3244852787
Short name T43
Test name
Test status
Simulation time 155079308 ps
CPU time 2.18 seconds
Started Feb 04 01:14:20 PM PST 24
Finished Feb 04 01:14:23 PM PST 24
Peak memory 213496 kb
Host smart-48abef14-1c88-4fce-be80-1e3976c442df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244852787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3244852787
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.400605598
Short name T574
Test name
Test status
Simulation time 3456795652 ps
CPU time 27.22 seconds
Started Feb 04 01:14:06 PM PST 24
Finished Feb 04 01:14:37 PM PST 24
Peak memory 250876 kb
Host smart-5c206ac6-09b4-4314-bc6f-700008e0e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400605598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.400605598
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.569833703
Short name T535
Test name
Test status
Simulation time 254700606 ps
CPU time 9.1 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:33 PM PST 24
Peak memory 250816 kb
Host smart-7acd3af0-e564-4716-8bfd-ab6eb6b03787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569833703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.569833703
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1697535313
Short name T430
Test name
Test status
Simulation time 20173230610 ps
CPU time 306.4 seconds
Started Feb 04 01:14:13 PM PST 24
Finished Feb 04 01:19:21 PM PST 24
Peak memory 258852 kb
Host smart-c2c500f9-6874-409b-b991-54aa920bd29c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697535313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1697535313
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.167720258
Short name T382
Test name
Test status
Simulation time 21217586 ps
CPU time 0.74 seconds
Started Feb 04 01:14:23 PM PST 24
Finished Feb 04 01:14:25 PM PST 24
Peak memory 207868 kb
Host smart-f997ee0e-35ce-4d77-ab02-6da941cb335e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167720258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.167720258
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2681932001
Short name T381
Test name
Test status
Simulation time 41324784 ps
CPU time 0.82 seconds
Started Feb 04 01:14:18 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 209212 kb
Host smart-a3bceea6-c22a-4b2b-aace-432571bffc7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681932001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2681932001
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3232017945
Short name T356
Test name
Test status
Simulation time 282210445 ps
CPU time 14.08 seconds
Started Feb 04 01:14:20 PM PST 24
Finished Feb 04 01:14:35 PM PST 24
Peak memory 217860 kb
Host smart-b79463df-25c2-49f5-9953-14c617ac4193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232017945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3232017945
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.881773711
Short name T29
Test name
Test status
Simulation time 1711819954 ps
CPU time 4.49 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:28 PM PST 24
Peak memory 209192 kb
Host smart-eead3eb7-0232-4b75-84d0-368b8d0dea7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881773711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_ac
cess.881773711
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3491546929
Short name T53
Test name
Test status
Simulation time 8443004899 ps
CPU time 30.96 seconds
Started Feb 04 01:14:34 PM PST 24
Finished Feb 04 01:15:12 PM PST 24
Peak memory 218032 kb
Host smart-080b2b3c-10c8-44d3-b42c-94df430b5fec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491546929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3491546929
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2916926569
Short name T199
Test name
Test status
Simulation time 239430164 ps
CPU time 7.08 seconds
Started Feb 04 01:14:34 PM PST 24
Finished Feb 04 01:14:48 PM PST 24
Peak memory 217448 kb
Host smart-a985ebc3-c57a-470b-80df-87c83b4c8530
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916926569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2916926569
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1317774372
Short name T451
Test name
Test status
Simulation time 243535584 ps
CPU time 6.32 seconds
Started Feb 04 01:14:34 PM PST 24
Finished Feb 04 01:14:47 PM PST 24
Peak memory 212576 kb
Host smart-5017ffa1-0441-4b6b-9c82-89fe4920a3f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317774372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1317774372
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1083831180
Short name T437
Test name
Test status
Simulation time 15393689157 ps
CPU time 44.4 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:15:02 PM PST 24
Peak memory 269464 kb
Host smart-403edeb7-70d5-404f-8d6b-6e8770e9b71d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083831180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1083831180
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1095497439
Short name T841
Test name
Test status
Simulation time 1077314399 ps
CPU time 17.63 seconds
Started Feb 04 01:14:26 PM PST 24
Finished Feb 04 01:14:45 PM PST 24
Peak memory 250844 kb
Host smart-807b41df-16b6-41cf-af34-1a0669128a4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095497439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1095497439
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1784344679
Short name T852
Test name
Test status
Simulation time 22353482 ps
CPU time 1.76 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:25 PM PST 24
Peak memory 217880 kb
Host smart-8f4ae503-adbe-4966-a4b0-3c4aa317dfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784344679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1784344679
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3757260710
Short name T329
Test name
Test status
Simulation time 1232812294 ps
CPU time 18.39 seconds
Started Feb 04 01:14:18 PM PST 24
Finished Feb 04 01:14:38 PM PST 24
Peak memory 218852 kb
Host smart-56136cda-0d97-4038-8421-dd969b080529
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757260710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3757260710
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1920770463
Short name T489
Test name
Test status
Simulation time 674436686 ps
CPU time 9.03 seconds
Started Feb 04 01:14:19 PM PST 24
Finished Feb 04 01:14:30 PM PST 24
Peak memory 217820 kb
Host smart-6ca6b476-4361-45f9-b9d6-4449c231cd46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920770463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1920770463
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3019095140
Short name T782
Test name
Test status
Simulation time 1038005440 ps
CPU time 8.66 seconds
Started Feb 04 01:14:19 PM PST 24
Finished Feb 04 01:14:30 PM PST 24
Peak memory 217888 kb
Host smart-92c5113f-b445-4e4d-87cb-53cd36ba122a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019095140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3019095140
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1499910046
Short name T646
Test name
Test status
Simulation time 2108689613 ps
CPU time 6.67 seconds
Started Feb 04 01:14:34 PM PST 24
Finished Feb 04 01:14:47 PM PST 24
Peak memory 217792 kb
Host smart-8602b0af-2e93-42ec-aa53-28a368164b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499910046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1499910046
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.472238480
Short name T120
Test name
Test status
Simulation time 366649498 ps
CPU time 6.67 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:24 PM PST 24
Peak memory 213808 kb
Host smart-496ae1a8-029d-44e2-a712-ab5ef9bbaf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472238480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.472238480
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3295295696
Short name T331
Test name
Test status
Simulation time 416243527 ps
CPU time 20.13 seconds
Started Feb 04 01:14:18 PM PST 24
Finished Feb 04 01:14:40 PM PST 24
Peak memory 250824 kb
Host smart-8371758b-1945-419e-8977-970227a8d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295295696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3295295696
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2681464672
Short name T890
Test name
Test status
Simulation time 76741912 ps
CPU time 3.95 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:22 PM PST 24
Peak memory 221940 kb
Host smart-865c40c6-2c24-4e2c-884c-5252ef1879ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681464672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2681464672
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1078770245
Short name T767
Test name
Test status
Simulation time 6575567568 ps
CPU time 81.38 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:15:40 PM PST 24
Peak memory 267376 kb
Host smart-78822f18-397c-4539-a7da-3f8c237e1992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078770245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1078770245
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.168158257
Short name T35
Test name
Test status
Simulation time 10581534 ps
CPU time 0.74 seconds
Started Feb 04 01:14:18 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 207868 kb
Host smart-07ea297c-9e1c-4f0f-bfb9-904f7d74d1ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168158257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.168158257
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1840484927
Short name T373
Test name
Test status
Simulation time 70215324 ps
CPU time 0.84 seconds
Started Feb 04 01:14:35 PM PST 24
Finished Feb 04 01:14:41 PM PST 24
Peak memory 209212 kb
Host smart-1556f937-3bc7-47e2-a8e8-eaff7984b224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840484927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1840484927
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.420948588
Short name T754
Test name
Test status
Simulation time 1378843109 ps
CPU time 11.41 seconds
Started Feb 04 01:14:21 PM PST 24
Finished Feb 04 01:14:33 PM PST 24
Peak memory 217816 kb
Host smart-31735707-b4cb-4b1e-a0fb-df12fe2bc3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420948588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.420948588
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3639067997
Short name T623
Test name
Test status
Simulation time 340813441 ps
CPU time 8.8 seconds
Started Feb 04 01:14:19 PM PST 24
Finished Feb 04 01:14:30 PM PST 24
Peak memory 209416 kb
Host smart-4b09bfe7-a107-440c-bf35-7a9b634fa54c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639067997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.3639067997
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.4025542446
Short name T41
Test name
Test status
Simulation time 2143112008 ps
CPU time 28.74 seconds
Started Feb 04 01:14:29 PM PST 24
Finished Feb 04 01:15:00 PM PST 24
Peak memory 217240 kb
Host smart-912b6da4-6765-4cf5-9d1a-5d4ef9189e60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025542446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.4025542446
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.496340069
Short name T412
Test name
Test status
Simulation time 95385761 ps
CPU time 3.86 seconds
Started Feb 04 01:14:21 PM PST 24
Finished Feb 04 01:14:26 PM PST 24
Peak memory 217776 kb
Host smart-d3118ee7-1bd8-4b12-91af-41cf4b5b041d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496340069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.496340069
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.511380353
Short name T83
Test name
Test status
Simulation time 410822653 ps
CPU time 5.07 seconds
Started Feb 04 01:14:21 PM PST 24
Finished Feb 04 01:14:28 PM PST 24
Peak memory 212968 kb
Host smart-61a4347a-ece7-4e22-a4f1-e866908d3535
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511380353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
511380353
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.60436204
Short name T874
Test name
Test status
Simulation time 2144651245 ps
CPU time 40.75 seconds
Started Feb 04 01:14:29 PM PST 24
Finished Feb 04 01:15:12 PM PST 24
Peak memory 250156 kb
Host smart-9ca2c3b5-0a24-415a-b62b-3570ff190edb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60436204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_state_failure.60436204
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1649087772
Short name T379
Test name
Test status
Simulation time 1602189034 ps
CPU time 22.56 seconds
Started Feb 04 01:14:34 PM PST 24
Finished Feb 04 01:15:03 PM PST 24
Peak memory 250740 kb
Host smart-c1311935-a975-485c-ba73-e8ce385d1ab3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649087772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1649087772
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2668341538
Short name T12
Test name
Test status
Simulation time 70623980 ps
CPU time 2.68 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:14:21 PM PST 24
Peak memory 217744 kb
Host smart-c3c7d520-b168-41f4-ba5d-f551e7cdb100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668341538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2668341538
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.4082696078
Short name T684
Test name
Test status
Simulation time 257613431 ps
CPU time 10.25 seconds
Started Feb 04 01:14:16 PM PST 24
Finished Feb 04 01:14:28 PM PST 24
Peak memory 217860 kb
Host smart-db475baf-ce97-45a6-ba0a-7f84ccfe71d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082696078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.4082696078
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2571064664
Short name T637
Test name
Test status
Simulation time 1594752127 ps
CPU time 15.34 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:14:34 PM PST 24
Peak memory 217868 kb
Host smart-3992db00-a8b9-4cd3-8e51-618b1ee166b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571064664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2571064664
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2615911704
Short name T336
Test name
Test status
Simulation time 232784540 ps
CPU time 8.36 seconds
Started Feb 04 01:14:30 PM PST 24
Finished Feb 04 01:14:41 PM PST 24
Peak memory 217772 kb
Host smart-6dd805b2-5792-4701-981e-4eb9eb0815b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615911704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2615911704
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.589654750
Short name T711
Test name
Test status
Simulation time 19508523 ps
CPU time 1.13 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:24 PM PST 24
Peak memory 212576 kb
Host smart-93d26e59-72e6-4de0-b664-226cbb7b53bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589654750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.589654750
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2963330129
Short name T320
Test name
Test status
Simulation time 897780007 ps
CPU time 23.98 seconds
Started Feb 04 01:14:18 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 250300 kb
Host smart-55dde61b-a7af-44bd-891d-5e1f0f60bd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963330129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2963330129
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3952060223
Short name T597
Test name
Test status
Simulation time 184013921 ps
CPU time 6.33 seconds
Started Feb 04 01:14:29 PM PST 24
Finished Feb 04 01:14:39 PM PST 24
Peak memory 250668 kb
Host smart-062a7650-6da9-4995-a66e-0ddb63454855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952060223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3952060223
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.992902589
Short name T365
Test name
Test status
Simulation time 16386691637 ps
CPU time 141.11 seconds
Started Feb 04 01:14:29 PM PST 24
Finished Feb 04 01:16:54 PM PST 24
Peak memory 275516 kb
Host smart-934216b3-6d66-476c-82c7-217a5133f6cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992902589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.992902589
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4174740274
Short name T48
Test name
Test status
Simulation time 14592738 ps
CPU time 0.95 seconds
Started Feb 04 01:14:21 PM PST 24
Finished Feb 04 01:14:23 PM PST 24
Peak memory 211208 kb
Host smart-c68b9927-8ee7-4c91-bbec-c0f1fc4bd692
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174740274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4174740274
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.4294574343
Short name T97
Test name
Test status
Simulation time 37913002 ps
CPU time 0.88 seconds
Started Feb 04 01:14:27 PM PST 24
Finished Feb 04 01:14:30 PM PST 24
Peak memory 208112 kb
Host smart-a4b9e4cb-857a-420c-904c-1130f8084013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294574343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.4294574343
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1193320692
Short name T833
Test name
Test status
Simulation time 2408737879 ps
CPU time 20.39 seconds
Started Feb 04 01:14:29 PM PST 24
Finished Feb 04 01:14:53 PM PST 24
Peak memory 217828 kb
Host smart-e1fbd1c8-5397-40f9-9a93-5b8c97b37035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193320692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1193320692
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3200409671
Short name T829
Test name
Test status
Simulation time 916168140 ps
CPU time 7.92 seconds
Started Feb 04 01:14:29 PM PST 24
Finished Feb 04 01:14:40 PM PST 24
Peak memory 209476 kb
Host smart-994ebd8c-d271-4e80-a2f4-4dec248baa60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200409671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.3200409671
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.201545389
Short name T789
Test name
Test status
Simulation time 1102946689 ps
CPU time 34.39 seconds
Started Feb 04 01:14:26 PM PST 24
Finished Feb 04 01:15:02 PM PST 24
Peak memory 217780 kb
Host smart-b4ce1124-7a7f-41f5-8abd-da8364931ff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201545389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.201545389
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1647563411
Short name T17
Test name
Test status
Simulation time 1400262736 ps
CPU time 6.63 seconds
Started Feb 04 01:14:35 PM PST 24
Finished Feb 04 01:14:47 PM PST 24
Peak memory 217736 kb
Host smart-3f9543c8-5ce6-4675-9024-6f93146e1236
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647563411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1647563411
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1470350465
Short name T578
Test name
Test status
Simulation time 1275464284 ps
CPU time 4.05 seconds
Started Feb 04 01:14:26 PM PST 24
Finished Feb 04 01:14:31 PM PST 24
Peak memory 213044 kb
Host smart-fe5a486a-e727-472c-8b16-9618f87a9e4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470350465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1470350465
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3080547460
Short name T16
Test name
Test status
Simulation time 2486494677 ps
CPU time 81.51 seconds
Started Feb 04 01:14:32 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 277688 kb
Host smart-45bb4537-5b5d-4787-aaf1-8d11b35a4b6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080547460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3080547460
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3774491910
Short name T533
Test name
Test status
Simulation time 594111789 ps
CPU time 10.1 seconds
Started Feb 04 01:14:26 PM PST 24
Finished Feb 04 01:14:38 PM PST 24
Peak memory 224412 kb
Host smart-ce503cb9-1dce-4922-bd23-2c6b09427794
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774491910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3774491910
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3791086103
Short name T405
Test name
Test status
Simulation time 30648604 ps
CPU time 1.86 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:25 PM PST 24
Peak memory 217768 kb
Host smart-ce0001ad-9973-451d-bbb9-fb84716301f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791086103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3791086103
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.671293318
Short name T447
Test name
Test status
Simulation time 3634821686 ps
CPU time 10.7 seconds
Started Feb 04 01:14:28 PM PST 24
Finished Feb 04 01:14:41 PM PST 24
Peak memory 218004 kb
Host smart-66ef0153-5cfd-4374-acc9-1354cbe9ca4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671293318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.671293318
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2811609055
Short name T942
Test name
Test status
Simulation time 330586472 ps
CPU time 10.28 seconds
Started Feb 04 01:14:27 PM PST 24
Finished Feb 04 01:14:39 PM PST 24
Peak memory 217828 kb
Host smart-ce939f75-0ded-4b4c-9331-f7715c2ddbbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811609055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2811609055
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2600991682
Short name T968
Test name
Test status
Simulation time 239787799 ps
CPU time 9.13 seconds
Started Feb 04 01:14:26 PM PST 24
Finished Feb 04 01:14:36 PM PST 24
Peak memory 217832 kb
Host smart-89ff8db4-5557-445b-ac01-d80f6602c371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600991682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2600991682
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.244967886
Short name T572
Test name
Test status
Simulation time 471252128 ps
CPU time 9.03 seconds
Started Feb 04 01:14:22 PM PST 24
Finished Feb 04 01:14:32 PM PST 24
Peak memory 217752 kb
Host smart-3a9b9b33-cdfe-4196-8b21-460dfe110b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244967886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.244967886
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3135417804
Short name T664
Test name
Test status
Simulation time 92045063 ps
CPU time 2.17 seconds
Started Feb 04 01:14:30 PM PST 24
Finished Feb 04 01:14:35 PM PST 24
Peak memory 213680 kb
Host smart-90aee13c-9a5a-4a67-ac27-bc73e1f7ec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135417804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3135417804
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2224120545
Short name T899
Test name
Test status
Simulation time 183254518 ps
CPU time 23.37 seconds
Started Feb 04 01:14:29 PM PST 24
Finished Feb 04 01:14:55 PM PST 24
Peak memory 250776 kb
Host smart-eab5f42b-4a44-4476-a039-8c0e1a68f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224120545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2224120545
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1023464380
Short name T859
Test name
Test status
Simulation time 226839522 ps
CPU time 9.06 seconds
Started Feb 04 01:14:17 PM PST 24
Finished Feb 04 01:14:27 PM PST 24
Peak memory 250772 kb
Host smart-3f91e392-6b3f-43ea-a169-5a3593abba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023464380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1023464380
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1912764640
Short name T540
Test name
Test status
Simulation time 4964785678 ps
CPU time 75.2 seconds
Started Feb 04 01:14:24 PM PST 24
Finished Feb 04 01:15:41 PM PST 24
Peak memory 226052 kb
Host smart-29e24209-82a7-41c2-a4c2-e56eda350975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912764640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1912764640
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.92964721
Short name T36
Test name
Test status
Simulation time 18111293 ps
CPU time 0.82 seconds
Started Feb 04 01:14:34 PM PST 24
Finished Feb 04 01:14:41 PM PST 24
Peak memory 207872 kb
Host smart-f96b68b0-8d3c-4b37-a7b0-8381039cfd50
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92964721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_volatile_unlock_smoke.92964721
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4119396504
Short name T72
Test name
Test status
Simulation time 35101546 ps
CPU time 1.15 seconds
Started Feb 04 01:12:51 PM PST 24
Finished Feb 04 01:12:53 PM PST 24
Peak memory 209424 kb
Host smart-6560a715-3350-4e63-b34d-0232f9249d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119396504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4119396504
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2791977214
Short name T456
Test name
Test status
Simulation time 1364185261 ps
CPU time 11.22 seconds
Started Feb 04 01:12:38 PM PST 24
Finished Feb 04 01:12:51 PM PST 24
Peak memory 217840 kb
Host smart-52e7450a-0e8a-4abc-b3a8-d626a5d530d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791977214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2791977214
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1741693875
Short name T884
Test name
Test status
Simulation time 407122114 ps
CPU time 11.4 seconds
Started Feb 04 01:12:48 PM PST 24
Finished Feb 04 01:13:00 PM PST 24
Peak memory 209524 kb
Host smart-2cc5adf7-7e87-4041-a17b-4ab0cbcb3bfe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741693875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ac
cess.1741693875
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2223759905
Short name T311
Test name
Test status
Simulation time 2534623679 ps
CPU time 35.82 seconds
Started Feb 04 01:12:56 PM PST 24
Finished Feb 04 01:13:35 PM PST 24
Peak memory 217780 kb
Host smart-eae79288-3c73-4a53-a54e-bcaeec515381
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223759905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2223759905
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3157992700
Short name T493
Test name
Test status
Simulation time 539341422 ps
CPU time 2.58 seconds
Started Feb 04 01:12:43 PM PST 24
Finished Feb 04 01:12:46 PM PST 24
Peak memory 217676 kb
Host smart-484f658b-b125-4584-ba7a-c3046f0ffe93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157992700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.3157992700
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2311431586
Short name T647
Test name
Test status
Simulation time 142497018 ps
CPU time 5.3 seconds
Started Feb 04 01:12:43 PM PST 24
Finished Feb 04 01:12:49 PM PST 24
Peak memory 217808 kb
Host smart-c862f76e-51ab-4b2e-a1ef-a70b64cc15eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311431586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2311431586
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.255153500
Short name T404
Test name
Test status
Simulation time 1103016199 ps
CPU time 30.97 seconds
Started Feb 04 01:12:44 PM PST 24
Finished Feb 04 01:13:16 PM PST 24
Peak memory 212860 kb
Host smart-95b1e96b-8a88-4646-aeca-9e5ff96f5337
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255153500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.255153500
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.824018415
Short name T114
Test name
Test status
Simulation time 260921213 ps
CPU time 6.9 seconds
Started Feb 04 01:12:39 PM PST 24
Finished Feb 04 01:12:47 PM PST 24
Peak memory 213100 kb
Host smart-34ddf370-7849-4b45-91cb-742f82c42934
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824018415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.824018415
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3984290970
Short name T916
Test name
Test status
Simulation time 6008683613 ps
CPU time 87.01 seconds
Started Feb 04 01:12:37 PM PST 24
Finished Feb 04 01:14:07 PM PST 24
Peak memory 267252 kb
Host smart-25aea17d-58c4-4672-9c75-8da414fdbe73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984290970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3984290970
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3270704927
Short name T6
Test name
Test status
Simulation time 652861348 ps
CPU time 15.61 seconds
Started Feb 04 01:12:51 PM PST 24
Finished Feb 04 01:13:07 PM PST 24
Peak memory 250856 kb
Host smart-cafcae4d-abea-4afc-8bd6-50f34954e440
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270704927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3270704927
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1304863011
Short name T778
Test name
Test status
Simulation time 414379721 ps
CPU time 2.63 seconds
Started Feb 04 01:12:38 PM PST 24
Finished Feb 04 01:12:43 PM PST 24
Peak memory 217812 kb
Host smart-ea32fca6-c63f-4fdb-a5e3-7889e99ea3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304863011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1304863011
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3849753492
Short name T61
Test name
Test status
Simulation time 239307606 ps
CPU time 12.58 seconds
Started Feb 04 01:12:39 PM PST 24
Finished Feb 04 01:12:53 PM PST 24
Peak memory 213900 kb
Host smart-b3b52a96-dc91-47e6-8407-2024ed783277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849753492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3849753492
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1197108811
Short name T126
Test name
Test status
Simulation time 218912806 ps
CPU time 24.99 seconds
Started Feb 04 01:12:43 PM PST 24
Finished Feb 04 01:13:09 PM PST 24
Peak memory 272796 kb
Host smart-11f8639a-d6d3-4156-9329-e4a29e2b363f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197108811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1197108811
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.4016853778
Short name T737
Test name
Test status
Simulation time 1022567874 ps
CPU time 11.2 seconds
Started Feb 04 01:12:49 PM PST 24
Finished Feb 04 01:13:01 PM PST 24
Peak memory 218832 kb
Host smart-d79fe80d-2b95-4bc4-9e40-4f31a2e588d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016853778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.4016853778
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4239521433
Short name T376
Test name
Test status
Simulation time 196111837 ps
CPU time 7.55 seconds
Started Feb 04 01:12:45 PM PST 24
Finished Feb 04 01:12:54 PM PST 24
Peak memory 217832 kb
Host smart-746a3f58-9ea4-4118-8a61-ba09bf97e601
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239521433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4239521433
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.998722053
Short name T967
Test name
Test status
Simulation time 285341929 ps
CPU time 8.09 seconds
Started Feb 04 01:12:52 PM PST 24
Finished Feb 04 01:13:01 PM PST 24
Peak memory 217692 kb
Host smart-7f7c4e26-cca1-429d-8c25-a739db54a235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998722053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.998722053
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1218535774
Short name T461
Test name
Test status
Simulation time 494673799 ps
CPU time 9.71 seconds
Started Feb 04 01:12:38 PM PST 24
Finished Feb 04 01:12:50 PM PST 24
Peak memory 217832 kb
Host smart-43ae9142-9b04-42e7-870b-9e7de4bc1545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218535774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1218535774
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3613805692
Short name T582
Test name
Test status
Simulation time 163705081 ps
CPU time 2.47 seconds
Started Feb 04 01:12:30 PM PST 24
Finished Feb 04 01:12:34 PM PST 24
Peak memory 213608 kb
Host smart-8893f483-5475-45f5-ae26-533ae4897356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613805692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3613805692
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2850291757
Short name T609
Test name
Test status
Simulation time 658033353 ps
CPU time 34.87 seconds
Started Feb 04 01:12:32 PM PST 24
Finished Feb 04 01:13:08 PM PST 24
Peak memory 250932 kb
Host smart-cc708314-9b1a-454d-ac1d-4c55d3e344f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850291757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2850291757
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.180243920
Short name T730
Test name
Test status
Simulation time 295940106 ps
CPU time 5.73 seconds
Started Feb 04 01:12:32 PM PST 24
Finished Feb 04 01:12:44 PM PST 24
Peak memory 245656 kb
Host smart-e5c43e3f-e933-4210-afe4-5a36f4f9fbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180243920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.180243920
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1973439562
Short name T693
Test name
Test status
Simulation time 68108605805 ps
CPU time 216.83 seconds
Started Feb 04 01:12:50 PM PST 24
Finished Feb 04 01:16:28 PM PST 24
Peak memory 267320 kb
Host smart-84e395b4-efc8-4371-8787-39d363d06d3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973439562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1973439562
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1698255095
Short name T34
Test name
Test status
Simulation time 12498121 ps
CPU time 0.87 seconds
Started Feb 04 01:12:31 PM PST 24
Finished Feb 04 01:12:33 PM PST 24
Peak memory 207908 kb
Host smart-37689b00-c051-4e75-a7d5-fa2de5e4d82e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698255095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1698255095
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1929367947
Short name T752
Test name
Test status
Simulation time 16459770 ps
CPU time 0.82 seconds
Started Feb 04 01:14:42 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 209224 kb
Host smart-3af8fa60-1e6d-4ff9-8b8f-8852d74b89b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929367947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1929367947
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1419555411
Short name T598
Test name
Test status
Simulation time 1364441177 ps
CPU time 15.31 seconds
Started Feb 04 01:14:27 PM PST 24
Finished Feb 04 01:14:45 PM PST 24
Peak memory 217948 kb
Host smart-cc4d0b01-e94c-42a2-be2e-033726614068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419555411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1419555411
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3365374208
Short name T936
Test name
Test status
Simulation time 644288393 ps
CPU time 2.35 seconds
Started Feb 04 01:14:25 PM PST 24
Finished Feb 04 01:14:29 PM PST 24
Peak memory 209460 kb
Host smart-8f26fcff-4953-418f-9755-1b433b22a882
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365374208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.3365374208
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1747893691
Short name T758
Test name
Test status
Simulation time 216047111 ps
CPU time 3.3 seconds
Started Feb 04 01:14:25 PM PST 24
Finished Feb 04 01:14:29 PM PST 24
Peak memory 217820 kb
Host smart-2e937d31-4b1e-4bcc-94e9-7c457298cefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747893691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1747893691
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3191617924
Short name T342
Test name
Test status
Simulation time 1109730056 ps
CPU time 16.39 seconds
Started Feb 04 01:14:28 PM PST 24
Finished Feb 04 01:14:46 PM PST 24
Peak memory 218884 kb
Host smart-c9d30117-8a94-4172-bd4c-94304f534d9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191617924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3191617924
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.906601873
Short name T333
Test name
Test status
Simulation time 438790028 ps
CPU time 7.52 seconds
Started Feb 04 01:14:25 PM PST 24
Finished Feb 04 01:14:34 PM PST 24
Peak memory 217840 kb
Host smart-e00da7ca-118b-48a6-8461-0cab714b318f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906601873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.906601873
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3914147943
Short name T564
Test name
Test status
Simulation time 665039385 ps
CPU time 11.39 seconds
Started Feb 04 01:14:31 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 217756 kb
Host smart-e7b87642-d458-44c2-9ceb-4b884aaea3a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914147943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3914147943
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3944944787
Short name T872
Test name
Test status
Simulation time 479593221 ps
CPU time 9.11 seconds
Started Feb 04 01:14:26 PM PST 24
Finished Feb 04 01:14:36 PM PST 24
Peak memory 217828 kb
Host smart-58c9cdf0-87b5-4d68-8286-5c7cdcf3f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944944787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3944944787
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1336949854
Short name T67
Test name
Test status
Simulation time 760954584 ps
CPU time 2.41 seconds
Started Feb 04 01:14:31 PM PST 24
Finished Feb 04 01:14:35 PM PST 24
Peak memory 217596 kb
Host smart-51eb0208-1ac5-4973-9655-3839235075f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336949854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1336949854
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3158523758
Short name T370
Test name
Test status
Simulation time 322808413 ps
CPU time 28.91 seconds
Started Feb 04 01:14:23 PM PST 24
Finished Feb 04 01:14:54 PM PST 24
Peak memory 250856 kb
Host smart-46225291-a353-456c-ad13-063f5607076b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158523758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3158523758
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.185913321
Short name T375
Test name
Test status
Simulation time 199596267 ps
CPU time 6.01 seconds
Started Feb 04 01:14:28 PM PST 24
Finished Feb 04 01:14:36 PM PST 24
Peak memory 246260 kb
Host smart-f06a5086-4e26-41c5-adfd-3cde4a01f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185913321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.185913321
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3925290816
Short name T571
Test name
Test status
Simulation time 12088358010 ps
CPU time 39.29 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:15:21 PM PST 24
Peak memory 267380 kb
Host smart-ca7439b9-e014-4af7-beeb-e484788684cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925290816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3925290816
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1158958082
Short name T951
Test name
Test status
Simulation time 12897179 ps
CPU time 0.78 seconds
Started Feb 04 01:14:34 PM PST 24
Finished Feb 04 01:14:41 PM PST 24
Peak memory 207868 kb
Host smart-1b8cf152-4e59-4780-bd27-25ed984809bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158958082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1158958082
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.840951105
Short name T345
Test name
Test status
Simulation time 63584708 ps
CPU time 0.89 seconds
Started Feb 04 01:14:42 PM PST 24
Finished Feb 04 01:14:45 PM PST 24
Peak memory 209416 kb
Host smart-a8359870-4022-4556-8967-9497d5b83e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840951105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.840951105
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3650007103
Short name T851
Test name
Test status
Simulation time 811805482 ps
CPU time 18.13 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:15:00 PM PST 24
Peak memory 217832 kb
Host smart-050ff2d6-2a65-417d-804e-3645fa383dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650007103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3650007103
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3488685371
Short name T926
Test name
Test status
Simulation time 169720148 ps
CPU time 1.32 seconds
Started Feb 04 01:14:45 PM PST 24
Finished Feb 04 01:14:51 PM PST 24
Peak memory 209420 kb
Host smart-36999b54-3ea5-4123-aa4e-ea1351a2a144
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488685371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.3488685371
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3086092182
Short name T390
Test name
Test status
Simulation time 797593444 ps
CPU time 2.33 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 217832 kb
Host smart-8d74bb86-449c-4aff-a525-39d9edf27285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086092182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3086092182
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.90698533
Short name T722
Test name
Test status
Simulation time 320246501 ps
CPU time 10.95 seconds
Started Feb 04 01:14:41 PM PST 24
Finished Feb 04 01:14:53 PM PST 24
Peak memory 218832 kb
Host smart-cd5cfa5d-0d59-4b3e-8d20-0d2884d6cceb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90698533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.90698533
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3192368870
Short name T123
Test name
Test status
Simulation time 4342324667 ps
CPU time 10.23 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:14:52 PM PST 24
Peak memory 217872 kb
Host smart-372507fc-7a38-4086-9b3c-1366074985ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192368870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3192368870
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1737017958
Short name T469
Test name
Test status
Simulation time 829180374 ps
CPU time 9.94 seconds
Started Feb 04 01:14:42 PM PST 24
Finished Feb 04 01:14:54 PM PST 24
Peak memory 217836 kb
Host smart-d58b0993-0219-48e1-a326-0cdbc157e188
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737017958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1737017958
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1757582005
Short name T760
Test name
Test status
Simulation time 1715620446 ps
CPU time 9.24 seconds
Started Feb 04 01:14:49 PM PST 24
Finished Feb 04 01:15:00 PM PST 24
Peak memory 217820 kb
Host smart-cd1d6c8e-1ae6-470c-a612-48f852299f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757582005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1757582005
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3588267372
Short name T358
Test name
Test status
Simulation time 135522850 ps
CPU time 2.78 seconds
Started Feb 04 01:14:36 PM PST 24
Finished Feb 04 01:14:43 PM PST 24
Peak memory 213412 kb
Host smart-6e15dee8-e730-4d5d-9981-e34f60b05908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588267372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3588267372
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1935977884
Short name T534
Test name
Test status
Simulation time 2411639253 ps
CPU time 32.27 seconds
Started Feb 04 01:14:50 PM PST 24
Finished Feb 04 01:15:30 PM PST 24
Peak memory 250860 kb
Host smart-1175d404-cb4e-4d42-a4d4-d119c51f58ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935977884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1935977884
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2554762573
Short name T779
Test name
Test status
Simulation time 104131940 ps
CPU time 3.47 seconds
Started Feb 04 01:14:38 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 222248 kb
Host smart-8b7eff0f-3534-4d4b-aac8-f7b80093633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554762573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2554762573
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3079466676
Short name T704
Test name
Test status
Simulation time 6477344095 ps
CPU time 102.58 seconds
Started Feb 04 01:14:46 PM PST 24
Finished Feb 04 01:16:32 PM PST 24
Peak memory 267224 kb
Host smart-34757507-1173-4a04-9d7c-a7b3af3509ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079466676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3079466676
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2535309553
Short name T494
Test name
Test status
Simulation time 49479667 ps
CPU time 1.03 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:14:43 PM PST 24
Peak memory 211352 kb
Host smart-5bcc08d8-f05d-4043-87cb-dea747fddede
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535309553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2535309553
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4177656433
Short name T69
Test name
Test status
Simulation time 78209701 ps
CPU time 0.86 seconds
Started Feb 04 01:14:37 PM PST 24
Finished Feb 04 01:14:42 PM PST 24
Peak memory 209444 kb
Host smart-a03863e1-97ae-4a8a-a58f-610774ceeefd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177656433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4177656433
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3125403979
Short name T75
Test name
Test status
Simulation time 1261496742 ps
CPU time 10.11 seconds
Started Feb 04 01:14:41 PM PST 24
Finished Feb 04 01:14:52 PM PST 24
Peak memory 217868 kb
Host smart-08d32c4e-669e-4ce5-aac3-da3d3aed75c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125403979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3125403979
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1564496936
Short name T701
Test name
Test status
Simulation time 2891065180 ps
CPU time 17.14 seconds
Started Feb 04 01:14:47 PM PST 24
Finished Feb 04 01:15:07 PM PST 24
Peak memory 209428 kb
Host smart-ab37e10e-dcff-4258-9346-3d090ecaebae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564496936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.1564496936
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.784778038
Short name T826
Test name
Test status
Simulation time 35432343 ps
CPU time 2.06 seconds
Started Feb 04 01:14:42 PM PST 24
Finished Feb 04 01:14:45 PM PST 24
Peak memory 217860 kb
Host smart-365e69b7-52f1-4b63-8712-a9c4b2a36e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784778038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.784778038
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4293004125
Short name T55
Test name
Test status
Simulation time 924623703 ps
CPU time 13.8 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:14:56 PM PST 24
Peak memory 218896 kb
Host smart-0cbc6ca8-d338-4e52-a517-dc5de5667a0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293004125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4293004125
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.16572334
Short name T661
Test name
Test status
Simulation time 10168738054 ps
CPU time 11.84 seconds
Started Feb 04 01:14:37 PM PST 24
Finished Feb 04 01:14:52 PM PST 24
Peak memory 217876 kb
Host smart-2b1b54ef-50a8-4099-b70a-3e4c100e6fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16572334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_dig
est.16572334
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.769843475
Short name T40
Test name
Test status
Simulation time 262021500 ps
CPU time 9.39 seconds
Started Feb 04 01:14:38 PM PST 24
Finished Feb 04 01:14:50 PM PST 24
Peak memory 217872 kb
Host smart-d3e608f2-76da-4fc0-8df7-cc3d1dcb7739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769843475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.769843475
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3162962659
Short name T750
Test name
Test status
Simulation time 384508727 ps
CPU time 15.41 seconds
Started Feb 04 01:14:46 PM PST 24
Finished Feb 04 01:15:05 PM PST 24
Peak memory 217724 kb
Host smart-f877f32d-6b90-43ae-8f0a-349b1e124992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162962659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3162962659
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1167244421
Short name T492
Test name
Test status
Simulation time 58547683 ps
CPU time 2.12 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 213608 kb
Host smart-b4472b22-798b-442f-91fd-9a42be153151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167244421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1167244421
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2722075022
Short name T796
Test name
Test status
Simulation time 1266670023 ps
CPU time 28.13 seconds
Started Feb 04 01:14:42 PM PST 24
Finished Feb 04 01:15:11 PM PST 24
Peak memory 250884 kb
Host smart-56113c53-e9fc-4a8f-92df-2e86446c366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722075022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2722075022
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.27257369
Short name T434
Test name
Test status
Simulation time 392936853 ps
CPU time 8.95 seconds
Started Feb 04 01:14:39 PM PST 24
Finished Feb 04 01:14:50 PM PST 24
Peak memory 250884 kb
Host smart-e9b2c3ec-4bb1-43db-83cf-6eba1846c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27257369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.27257369
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3609202929
Short name T891
Test name
Test status
Simulation time 1490354829 ps
CPU time 41.79 seconds
Started Feb 04 01:14:38 PM PST 24
Finished Feb 04 01:15:23 PM PST 24
Peak memory 248924 kb
Host smart-77c8470f-42d0-4044-bca7-9e9710afe717
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609202929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3609202929
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.739842407
Short name T938
Test name
Test status
Simulation time 33511394 ps
CPU time 0.77 seconds
Started Feb 04 01:14:41 PM PST 24
Finished Feb 04 01:14:43 PM PST 24
Peak memory 207944 kb
Host smart-bfa18bb4-c7ad-4a5a-97db-e3813abfa5cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739842407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.739842407
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1740123121
Short name T529
Test name
Test status
Simulation time 72268617 ps
CPU time 1.19 seconds
Started Feb 04 01:14:57 PM PST 24
Finished Feb 04 01:15:01 PM PST 24
Peak memory 209296 kb
Host smart-807d84ad-438d-48cb-a933-3664d372397d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740123121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1740123121
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2617633563
Short name T630
Test name
Test status
Simulation time 502017646 ps
CPU time 13.19 seconds
Started Feb 04 01:14:50 PM PST 24
Finished Feb 04 01:15:11 PM PST 24
Peak memory 217860 kb
Host smart-27c27938-d5ce-41e9-a163-5bf5d2deaf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617633563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2617633563
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3109191131
Short name T751
Test name
Test status
Simulation time 985338998 ps
CPU time 5.32 seconds
Started Feb 04 01:14:44 PM PST 24
Finished Feb 04 01:14:53 PM PST 24
Peak memory 209444 kb
Host smart-3d215387-456f-43b3-afee-581b9588e6a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109191131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.3109191131
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1936026412
Short name T820
Test name
Test status
Simulation time 49628201 ps
CPU time 2.11 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 217860 kb
Host smart-7909380b-b0ef-4d40-bb1d-b67ca2f05592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936026412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1936026412
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2061637096
Short name T116
Test name
Test status
Simulation time 1138621886 ps
CPU time 9.63 seconds
Started Feb 04 01:14:40 PM PST 24
Finished Feb 04 01:14:52 PM PST 24
Peak memory 217836 kb
Host smart-8c3f2c11-5a17-491a-9c94-6b6ae740c10b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061637096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2061637096
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3785183728
Short name T748
Test name
Test status
Simulation time 550177442 ps
CPU time 14.76 seconds
Started Feb 04 01:14:47 PM PST 24
Finished Feb 04 01:15:05 PM PST 24
Peak memory 217820 kb
Host smart-8c3ab206-064b-4326-9408-4782c03129ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785183728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3785183728
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.58791991
Short name T739
Test name
Test status
Simulation time 367719818 ps
CPU time 9.35 seconds
Started Feb 04 01:14:45 PM PST 24
Finished Feb 04 01:14:59 PM PST 24
Peak memory 217816 kb
Host smart-8cef2069-0655-4cc4-b94d-cf047a171988
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58791991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.58791991
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1454243203
Short name T459
Test name
Test status
Simulation time 982532487 ps
CPU time 9.65 seconds
Started Feb 04 01:14:57 PM PST 24
Finished Feb 04 01:15:09 PM PST 24
Peak memory 217852 kb
Host smart-845eee24-554a-4b3e-afe1-cfa0cab58b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454243203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1454243203
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.283218901
Short name T879
Test name
Test status
Simulation time 109980865 ps
CPU time 2.15 seconds
Started Feb 04 01:14:37 PM PST 24
Finished Feb 04 01:14:43 PM PST 24
Peak memory 213972 kb
Host smart-fbf50dc9-9de9-4d07-850b-296fab34c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283218901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.283218901
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3832259551
Short name T592
Test name
Test status
Simulation time 1414740614 ps
CPU time 26.34 seconds
Started Feb 04 01:14:46 PM PST 24
Finished Feb 04 01:15:16 PM PST 24
Peak memory 250860 kb
Host smart-3430a553-58c9-467e-bee6-05204ae0e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832259551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3832259551
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2570539068
Short name T801
Test name
Test status
Simulation time 260849244 ps
CPU time 2.77 seconds
Started Feb 04 01:14:46 PM PST 24
Finished Feb 04 01:14:52 PM PST 24
Peak memory 217800 kb
Host smart-b2980b36-46c9-41dd-a5e0-514a6ac9b909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570539068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2570539068
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1638087363
Short name T822
Test name
Test status
Simulation time 5634945313 ps
CPU time 79.59 seconds
Started Feb 04 01:14:51 PM PST 24
Finished Feb 04 01:16:17 PM PST 24
Peak memory 234536 kb
Host smart-c387593b-9d2f-429b-a027-e2731fbd9598
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638087363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1638087363
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2625603389
Short name T969
Test name
Test status
Simulation time 19228867 ps
CPU time 0.85 seconds
Started Feb 04 01:14:42 PM PST 24
Finished Feb 04 01:14:44 PM PST 24
Peak memory 208124 kb
Host smart-99f4b87a-b7eb-4d69-aa8b-7caf5b98174d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625603389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2625603389
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.136463946
Short name T346
Test name
Test status
Simulation time 22352311 ps
CPU time 0.92 seconds
Started Feb 04 01:14:58 PM PST 24
Finished Feb 04 01:15:02 PM PST 24
Peak memory 209504 kb
Host smart-1772d586-80a8-4503-bd52-0cf5fb836749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136463946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.136463946
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3936419669
Short name T846
Test name
Test status
Simulation time 270887050 ps
CPU time 8.16 seconds
Started Feb 04 01:15:04 PM PST 24
Finished Feb 04 01:15:16 PM PST 24
Peak memory 217788 kb
Host smart-211b6fea-9f81-47ab-94e4-350696cbe335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936419669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3936419669
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.603096280
Short name T28
Test name
Test status
Simulation time 367141222 ps
CPU time 9.3 seconds
Started Feb 04 01:15:02 PM PST 24
Finished Feb 04 01:15:13 PM PST 24
Peak memory 209476 kb
Host smart-cbddc800-5228-4750-8483-8c2fe32311f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603096280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_ac
cess.603096280
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3313240298
Short name T961
Test name
Test status
Simulation time 203570523 ps
CPU time 2.78 seconds
Started Feb 04 01:14:49 PM PST 24
Finished Feb 04 01:14:54 PM PST 24
Peak memory 217784 kb
Host smart-56f81b55-1a8a-474f-be38-4cec90fec1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313240298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3313240298
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1872282549
Short name T952
Test name
Test status
Simulation time 1626681456 ps
CPU time 14.31 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:15:13 PM PST 24
Peak memory 218860 kb
Host smart-0dc1464f-657f-4012-80c0-c21329a35a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872282549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1872282549
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2767644854
Short name T838
Test name
Test status
Simulation time 287589546 ps
CPU time 10.29 seconds
Started Feb 04 01:14:55 PM PST 24
Finished Feb 04 01:15:10 PM PST 24
Peak memory 217832 kb
Host smart-71fb9c8c-e8dc-43b8-b2b0-d5a17e5fa24a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767644854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2767644854
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3258858345
Short name T837
Test name
Test status
Simulation time 706411412 ps
CPU time 9.02 seconds
Started Feb 04 01:14:44 PM PST 24
Finished Feb 04 01:14:57 PM PST 24
Peak memory 217808 kb
Host smart-bf11dcc4-c871-4f21-ae41-6ba239959957
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258858345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3258858345
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3083614728
Short name T442
Test name
Test status
Simulation time 330033245 ps
CPU time 11.22 seconds
Started Feb 04 01:14:59 PM PST 24
Finished Feb 04 01:15:12 PM PST 24
Peak memory 217824 kb
Host smart-63cedd17-2b3a-4f97-b1c3-d97ed1e83721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083614728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3083614728
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3536694331
Short name T831
Test name
Test status
Simulation time 164870594 ps
CPU time 3.21 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:15:02 PM PST 24
Peak memory 213068 kb
Host smart-d6d89218-508b-415a-a53e-df8c0c91adfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536694331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3536694331
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1313021028
Short name T399
Test name
Test status
Simulation time 309443711 ps
CPU time 9.61 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:15:09 PM PST 24
Peak memory 250860 kb
Host smart-9bd1e1ab-50a7-4b95-ae3d-2052025d8281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313021028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1313021028
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.900021049
Short name T385
Test name
Test status
Simulation time 3168190532 ps
CPU time 101.8 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:16:41 PM PST 24
Peak memory 250800 kb
Host smart-b582b669-451c-4434-b68e-4aa684cd664d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900021049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.900021049
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2628737747
Short name T966
Test name
Test status
Simulation time 12648174 ps
CPU time 0.88 seconds
Started Feb 04 01:14:58 PM PST 24
Finished Feb 04 01:15:02 PM PST 24
Peak memory 208156 kb
Host smart-e0696942-e66b-4328-a714-2f5e202326a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628737747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2628737747
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1105233203
Short name T830
Test name
Test status
Simulation time 74172534 ps
CPU time 0.9 seconds
Started Feb 04 01:14:48 PM PST 24
Finished Feb 04 01:14:51 PM PST 24
Peak memory 209436 kb
Host smart-c8bc6e2c-ee70-41c4-8824-5228e59ffe6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105233203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1105233203
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1390781204
Short name T620
Test name
Test status
Simulation time 986389902 ps
CPU time 7.68 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:15:07 PM PST 24
Peak memory 217848 kb
Host smart-5b0866f7-d78c-4a7e-bf27-55412f140c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390781204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1390781204
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1898246419
Short name T898
Test name
Test status
Simulation time 2187137769 ps
CPU time 6.02 seconds
Started Feb 04 01:14:45 PM PST 24
Finished Feb 04 01:14:55 PM PST 24
Peak memory 209488 kb
Host smart-abb8d016-e70d-4bd5-97a8-5256299f6c1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898246419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_a
ccess.1898246419
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2262269323
Short name T558
Test name
Test status
Simulation time 50816518 ps
CPU time 1.76 seconds
Started Feb 04 01:14:52 PM PST 24
Finished Feb 04 01:15:01 PM PST 24
Peak memory 217832 kb
Host smart-1208b2e3-a98c-419d-8484-b66557116e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262269323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2262269323
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3544533245
Short name T675
Test name
Test status
Simulation time 1810545718 ps
CPU time 11.48 seconds
Started Feb 04 01:14:51 PM PST 24
Finished Feb 04 01:15:10 PM PST 24
Peak memory 218892 kb
Host smart-fd03a530-9434-41d8-9e62-2aedb257f312
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544533245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3544533245
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1260379117
Short name T867
Test name
Test status
Simulation time 633164021 ps
CPU time 10.22 seconds
Started Feb 04 01:14:47 PM PST 24
Finished Feb 04 01:15:01 PM PST 24
Peak memory 217792 kb
Host smart-722ab986-3918-40ea-bf26-04f903075212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260379117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1260379117
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1077012066
Short name T497
Test name
Test status
Simulation time 650823192 ps
CPU time 7.11 seconds
Started Feb 04 01:14:49 PM PST 24
Finished Feb 04 01:14:58 PM PST 24
Peak memory 217872 kb
Host smart-eeb5992e-0823-4bb3-b0a0-63b7302bef9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077012066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1077012066
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2252405868
Short name T460
Test name
Test status
Simulation time 305029736 ps
CPU time 11.49 seconds
Started Feb 04 01:14:50 PM PST 24
Finished Feb 04 01:15:09 PM PST 24
Peak memory 217896 kb
Host smart-53a9e9fe-473c-4e4e-ac6d-e290a179a0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252405868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2252405868
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.492397569
Short name T76
Test name
Test status
Simulation time 30647279 ps
CPU time 2.09 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:15:01 PM PST 24
Peak memory 222244 kb
Host smart-c4a8412d-c9ab-448b-9894-011d564b81a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492397569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.492397569
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1622002109
Short name T470
Test name
Test status
Simulation time 436614877 ps
CPU time 18.75 seconds
Started Feb 04 01:15:03 PM PST 24
Finished Feb 04 01:15:25 PM PST 24
Peak memory 250840 kb
Host smart-c172778f-6b5c-47d2-b34d-a3f641b1de14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622002109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1622002109
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.4288065190
Short name T589
Test name
Test status
Simulation time 100773419 ps
CPU time 2.74 seconds
Started Feb 04 01:14:50 PM PST 24
Finished Feb 04 01:15:00 PM PST 24
Peak memory 221968 kb
Host smart-700692d7-1793-49ce-95c1-6d085cb5de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288065190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.4288065190
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.4102757447
Short name T715
Test name
Test status
Simulation time 16209348144 ps
CPU time 30.48 seconds
Started Feb 04 01:14:57 PM PST 24
Finished Feb 04 01:15:30 PM PST 24
Peak memory 226144 kb
Host smart-b9a91483-ec29-4d6e-b5b7-68ff046e9e89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102757447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.4102757447
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3511461775
Short name T928
Test name
Test status
Simulation time 32649380 ps
CPU time 0.86 seconds
Started Feb 04 01:14:51 PM PST 24
Finished Feb 04 01:14:59 PM PST 24
Peak memory 208412 kb
Host smart-5252eb68-25aa-4bc3-9ac3-8aa5c9a9a4ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511461775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3511461775
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1964486137
Short name T362
Test name
Test status
Simulation time 20493102 ps
CPU time 0.93 seconds
Started Feb 04 01:15:05 PM PST 24
Finished Feb 04 01:15:09 PM PST 24
Peak memory 208044 kb
Host smart-8ec2c907-bd08-446e-8924-6f66fdb4b47f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964486137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1964486137
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.178642648
Short name T880
Test name
Test status
Simulation time 296359024 ps
CPU time 13.12 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:15:12 PM PST 24
Peak memory 217772 kb
Host smart-141a2fec-1cab-4401-ab7e-b0a7c5e23c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178642648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.178642648
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2388216820
Short name T896
Test name
Test status
Simulation time 163528981 ps
CPU time 2.04 seconds
Started Feb 04 01:14:49 PM PST 24
Finished Feb 04 01:14:53 PM PST 24
Peak memory 209448 kb
Host smart-36747522-6ec5-44ec-8180-e0bb55f14848
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388216820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.2388216820
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3598514865
Short name T506
Test name
Test status
Simulation time 94871041 ps
CPU time 2.81 seconds
Started Feb 04 01:14:50 PM PST 24
Finished Feb 04 01:15:00 PM PST 24
Peak memory 217840 kb
Host smart-a3513646-f423-41e4-91d2-1c08bcbba043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598514865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3598514865
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1146804069
Short name T335
Test name
Test status
Simulation time 3877002574 ps
CPU time 19.82 seconds
Started Feb 04 01:15:00 PM PST 24
Finished Feb 04 01:15:23 PM PST 24
Peak memory 217884 kb
Host smart-d9b6c72f-4ebd-4c7f-a378-748f4eefe895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146804069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1146804069
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3398410695
Short name T633
Test name
Test status
Simulation time 367885316 ps
CPU time 9.65 seconds
Started Feb 04 01:14:52 PM PST 24
Finished Feb 04 01:15:09 PM PST 24
Peak memory 217824 kb
Host smart-3f64a4dc-443d-4252-80da-be10ac8927df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398410695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3398410695
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1515677469
Short name T611
Test name
Test status
Simulation time 378785074 ps
CPU time 13.25 seconds
Started Feb 04 01:14:49 PM PST 24
Finished Feb 04 01:15:04 PM PST 24
Peak memory 217856 kb
Host smart-739c8e8c-bb2e-463b-b737-9dfb92da7b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515677469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1515677469
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.374755372
Short name T775
Test name
Test status
Simulation time 78956555 ps
CPU time 3.14 seconds
Started Feb 04 01:14:49 PM PST 24
Finished Feb 04 01:14:54 PM PST 24
Peak memory 213752 kb
Host smart-4ca92975-a49b-4a65-b54c-7618e2d01161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374755372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.374755372
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3162444038
Short name T810
Test name
Test status
Simulation time 878737816 ps
CPU time 20.45 seconds
Started Feb 04 01:15:00 PM PST 24
Finished Feb 04 01:15:23 PM PST 24
Peak memory 250820 kb
Host smart-517d19b5-ca06-4b87-beae-5aed42ba0b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162444038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3162444038
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4266865490
Short name T860
Test name
Test status
Simulation time 74963222 ps
CPU time 3.03 seconds
Started Feb 04 01:14:53 PM PST 24
Finished Feb 04 01:15:02 PM PST 24
Peak memory 221520 kb
Host smart-72c37a77-2cab-4482-adb5-0e0f70c853f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266865490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4266865490
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.800098832
Short name T772
Test name
Test status
Simulation time 6421947424 ps
CPU time 92.1 seconds
Started Feb 04 01:15:03 PM PST 24
Finished Feb 04 01:16:39 PM PST 24
Peak memory 242800 kb
Host smart-11e7438b-79e7-449e-9a6b-065b45b109c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800098832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.800098832
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1661748193
Short name T49
Test name
Test status
Simulation time 22948014 ps
CPU time 0.96 seconds
Started Feb 04 01:14:51 PM PST 24
Finished Feb 04 01:14:59 PM PST 24
Peak memory 212464 kb
Host smart-646752f3-76b6-4ed2-b8e4-eaf5c1189a6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661748193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1661748193
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3512036006
Short name T761
Test name
Test status
Simulation time 21605383 ps
CPU time 1.18 seconds
Started Feb 04 01:14:57 PM PST 24
Finished Feb 04 01:15:01 PM PST 24
Peak memory 208160 kb
Host smart-3b6f8389-07b6-4559-b726-bf7556650099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512036006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3512036006
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3812661323
Short name T774
Test name
Test status
Simulation time 2224449447 ps
CPU time 15.27 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:24 PM PST 24
Peak memory 217988 kb
Host smart-732617cf-5d4e-42da-94a0-5602a1f6c566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812661323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3812661323
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2945846093
Short name T865
Test name
Test status
Simulation time 176548018 ps
CPU time 3.95 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:13 PM PST 24
Peak memory 209456 kb
Host smart-703ba9bd-27c8-4b33-a29d-fad7d3219639
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945846093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.2945846093
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2977089617
Short name T593
Test name
Test status
Simulation time 470763762 ps
CPU time 3.86 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:13 PM PST 24
Peak memory 217868 kb
Host smart-f4eef200-8d14-41b3-bec8-9689e5708fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977089617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2977089617
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3802790903
Short name T321
Test name
Test status
Simulation time 208857096 ps
CPU time 10.37 seconds
Started Feb 04 01:14:58 PM PST 24
Finished Feb 04 01:15:10 PM PST 24
Peak memory 217844 kb
Host smart-022b11c5-db76-4b1a-9779-f60c13aaa032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802790903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3802790903
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1186527509
Short name T122
Test name
Test status
Simulation time 342805366 ps
CPU time 12.95 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:22 PM PST 24
Peak memory 217860 kb
Host smart-f0994d81-0773-43ee-bd58-a98e818e47f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186527509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1186527509
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.189879452
Short name T735
Test name
Test status
Simulation time 253057874 ps
CPU time 9.59 seconds
Started Feb 04 01:15:00 PM PST 24
Finished Feb 04 01:15:13 PM PST 24
Peak memory 217820 kb
Host smart-ee1aa578-f04f-48fc-b1d7-95086642dd54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189879452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.189879452
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.645118660
Short name T462
Test name
Test status
Simulation time 677891234 ps
CPU time 12.65 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:21 PM PST 24
Peak memory 217756 kb
Host smart-f419f094-58d4-44cb-9d9a-c99fb280a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645118660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.645118660
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3137224272
Short name T68
Test name
Test status
Simulation time 671855551 ps
CPU time 2.73 seconds
Started Feb 04 01:15:00 PM PST 24
Finished Feb 04 01:15:05 PM PST 24
Peak memory 213840 kb
Host smart-e1314b5c-ec4b-4ccc-9459-6d61fcdc947f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137224272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3137224272
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2056901678
Short name T435
Test name
Test status
Simulation time 345679395 ps
CPU time 30.65 seconds
Started Feb 04 01:15:06 PM PST 24
Finished Feb 04 01:15:39 PM PST 24
Peak memory 250816 kb
Host smart-738f9aae-d8a9-4b6d-bcb4-80153c46e974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056901678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2056901678
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2148934265
Short name T539
Test name
Test status
Simulation time 85572243 ps
CPU time 7.8 seconds
Started Feb 04 01:15:02 PM PST 24
Finished Feb 04 01:15:12 PM PST 24
Peak memory 249356 kb
Host smart-d87c4e63-af09-4e24-8258-607a09860ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148934265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2148934265
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2503940479
Short name T606
Test name
Test status
Simulation time 4428230918 ps
CPU time 82.1 seconds
Started Feb 04 01:15:06 PM PST 24
Finished Feb 04 01:16:31 PM PST 24
Peak memory 251312 kb
Host smart-43610d86-d443-4205-8bdb-965a6ff1dbd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503940479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2503940479
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1608312425
Short name T653
Test name
Test status
Simulation time 38845925 ps
CPU time 0.91 seconds
Started Feb 04 01:15:01 PM PST 24
Finished Feb 04 01:15:04 PM PST 24
Peak memory 207892 kb
Host smart-6d6a3241-90de-4e28-ad0d-bd0e68c10b3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608312425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1608312425
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1530480267
Short name T869
Test name
Test status
Simulation time 38346569 ps
CPU time 0.86 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:17 PM PST 24
Peak memory 209388 kb
Host smart-4fc7907a-f000-4066-a963-cacd21571b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530480267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1530480267
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.861064875
Short name T958
Test name
Test status
Simulation time 347825132 ps
CPU time 12.44 seconds
Started Feb 04 01:15:00 PM PST 24
Finished Feb 04 01:15:16 PM PST 24
Peak memory 217860 kb
Host smart-5d64142a-59c2-4a2b-9a63-c01548e3539b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861064875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.861064875
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1844910866
Short name T499
Test name
Test status
Simulation time 44158799 ps
CPU time 1.2 seconds
Started Feb 04 01:15:05 PM PST 24
Finished Feb 04 01:15:09 PM PST 24
Peak memory 209240 kb
Host smart-608da2dc-5223-4ea8-a680-d6f8a03245b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844910866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.1844910866
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.901541097
Short name T619
Test name
Test status
Simulation time 14559728 ps
CPU time 1.42 seconds
Started Feb 04 01:15:05 PM PST 24
Finished Feb 04 01:15:10 PM PST 24
Peak memory 217668 kb
Host smart-6301da9d-fdf9-4f16-85c9-5c66bbacd882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901541097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.901541097
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2204150863
Short name T546
Test name
Test status
Simulation time 248811724 ps
CPU time 8.39 seconds
Started Feb 04 01:15:00 PM PST 24
Finished Feb 04 01:15:12 PM PST 24
Peak memory 217780 kb
Host smart-fc14aaf9-c95e-4dc9-8b2c-f760bd72bf06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204150863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2204150863
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2462345270
Short name T569
Test name
Test status
Simulation time 1802249909 ps
CPU time 10.15 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:19 PM PST 24
Peak memory 217872 kb
Host smart-4286ae5e-8f0b-4184-8380-cb572f408e13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462345270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2462345270
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2544857456
Short name T348
Test name
Test status
Simulation time 881812476 ps
CPU time 6.07 seconds
Started Feb 04 01:15:05 PM PST 24
Finished Feb 04 01:15:14 PM PST 24
Peak memory 217816 kb
Host smart-25496783-8a33-4f24-8198-75ec2a951c07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544857456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2544857456
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.224277792
Short name T594
Test name
Test status
Simulation time 1107088663 ps
CPU time 7.46 seconds
Started Feb 04 01:14:57 PM PST 24
Finished Feb 04 01:15:07 PM PST 24
Peak memory 217836 kb
Host smart-9835e472-2d77-44e5-b402-2af30035dc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224277792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.224277792
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1337376653
Short name T431
Test name
Test status
Simulation time 190263896 ps
CPU time 3.6 seconds
Started Feb 04 01:15:00 PM PST 24
Finished Feb 04 01:15:07 PM PST 24
Peak memory 214500 kb
Host smart-2d914a3a-098b-49be-a889-e97174cbc6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337376653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1337376653
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2140859771
Short name T649
Test name
Test status
Simulation time 375689150 ps
CPU time 28.42 seconds
Started Feb 04 01:15:06 PM PST 24
Finished Feb 04 01:15:37 PM PST 24
Peak memory 250760 kb
Host smart-5ad2fe11-6a06-4318-a127-5259c96b4374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140859771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2140859771
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3031026284
Short name T420
Test name
Test status
Simulation time 285006107 ps
CPU time 7.51 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:16 PM PST 24
Peak memory 250332 kb
Host smart-0fe574be-516c-4f62-a385-088315b354de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031026284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3031026284
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2672549851
Short name T757
Test name
Test status
Simulation time 10680561295 ps
CPU time 45.09 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 250552 kb
Host smart-9fccb962-4d46-4fd6-986c-b13477e0b6a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672549851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2672549851
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2349569565
Short name T839
Test name
Test status
Simulation time 15038353 ps
CPU time 0.86 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:17 PM PST 24
Peak memory 209224 kb
Host smart-a14a6a87-4815-465f-9b1e-fc8182b9eb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349569565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2349569565
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3594119908
Short name T595
Test name
Test status
Simulation time 2020204837 ps
CPU time 25.78 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:35 PM PST 24
Peak memory 217652 kb
Host smart-14dfd357-4955-42fe-ad7a-22c7f8a52dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594119908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3594119908
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3196556077
Short name T949
Test name
Test status
Simulation time 536556158 ps
CPU time 4.21 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:21 PM PST 24
Peak memory 209452 kb
Host smart-e90e4cd4-7804-4371-a71c-d06b9ac650bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196556077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.3196556077
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.35517193
Short name T198
Test name
Test status
Simulation time 128634143 ps
CPU time 3.22 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:20 PM PST 24
Peak memory 217848 kb
Host smart-94da2dd8-41ff-44e0-9eb6-4adc16925e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35517193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.35517193
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3702331376
Short name T422
Test name
Test status
Simulation time 855571144 ps
CPU time 17.04 seconds
Started Feb 04 01:15:09 PM PST 24
Finished Feb 04 01:15:28 PM PST 24
Peak memory 218484 kb
Host smart-78e91b96-a8f2-4368-8cfd-85a98786c78e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702331376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3702331376
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3364656148
Short name T328
Test name
Test status
Simulation time 4170758058 ps
CPU time 22 seconds
Started Feb 04 01:15:09 PM PST 24
Finished Feb 04 01:15:33 PM PST 24
Peak memory 217916 kb
Host smart-24492ad1-4513-4bb1-a2a4-61d121800a10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364656148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3364656148
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2377153083
Short name T124
Test name
Test status
Simulation time 7708461946 ps
CPU time 13.37 seconds
Started Feb 04 01:15:11 PM PST 24
Finished Feb 04 01:15:26 PM PST 24
Peak memory 217832 kb
Host smart-a998862f-2c6b-43b6-973e-1d08e6a6a0fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377153083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2377153083
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3824684255
Short name T696
Test name
Test status
Simulation time 515642130 ps
CPU time 10.66 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:29 PM PST 24
Peak memory 217536 kb
Host smart-7385eb3f-e416-4f12-a3c8-d09816ad14e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824684255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3824684255
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4276325459
Short name T862
Test name
Test status
Simulation time 35567006 ps
CPU time 2.12 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:18 PM PST 24
Peak memory 213484 kb
Host smart-355cae77-3e2a-4be6-b31d-ab66d0c3e3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276325459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.4276325459
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.607046424
Short name T979
Test name
Test status
Simulation time 817185880 ps
CPU time 20.22 seconds
Started Feb 04 01:15:10 PM PST 24
Finished Feb 04 01:15:32 PM PST 24
Peak memory 250828 kb
Host smart-25e13533-409d-43c3-9d00-8b4ba69f6e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607046424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.607046424
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2330189573
Short name T196
Test name
Test status
Simulation time 297100083 ps
CPU time 8.19 seconds
Started Feb 04 01:15:02 PM PST 24
Finished Feb 04 01:15:12 PM PST 24
Peak memory 250840 kb
Host smart-87e280aa-c476-490d-9fc9-b8f5bcd76ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330189573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2330189573
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3909308384
Short name T721
Test name
Test status
Simulation time 26277855262 ps
CPU time 218.46 seconds
Started Feb 04 01:15:08 PM PST 24
Finished Feb 04 01:18:49 PM PST 24
Peak memory 219292 kb
Host smart-fa37857d-4995-4638-82f5-e031d82d7c5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909308384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3909308384
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2220854724
Short name T528
Test name
Test status
Simulation time 47360113 ps
CPU time 1.1 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:20 PM PST 24
Peak memory 211152 kb
Host smart-c83181e7-44f5-43d1-97cc-6952b7cf74dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220854724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2220854724
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1745127981
Short name T2
Test name
Test status
Simulation time 21705829 ps
CPU time 0.92 seconds
Started Feb 04 01:13:17 PM PST 24
Finished Feb 04 01:13:20 PM PST 24
Peak memory 209444 kb
Host smart-0d1503be-3a57-4dbb-8b9a-53c06414117d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745127981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1745127981
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1033607718
Short name T189
Test name
Test status
Simulation time 10329916 ps
CPU time 0.95 seconds
Started Feb 04 01:12:46 PM PST 24
Finished Feb 04 01:12:49 PM PST 24
Peak memory 209432 kb
Host smart-b317b25c-ed34-4312-9f9a-5c021db78a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033607718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1033607718
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.87628470
Short name T947
Test name
Test status
Simulation time 435901129 ps
CPU time 19.18 seconds
Started Feb 04 01:12:52 PM PST 24
Finished Feb 04 01:13:12 PM PST 24
Peak memory 217644 kb
Host smart-016e4272-f967-4fc8-a556-1a09dd3ad4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87628470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.87628470
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4257509032
Short name T844
Test name
Test status
Simulation time 8974285051 ps
CPU time 23.19 seconds
Started Feb 04 01:12:50 PM PST 24
Finished Feb 04 01:13:15 PM PST 24
Peak memory 209528 kb
Host smart-231de565-f747-4cc0-af9f-b30f47f3a702
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257509032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.4257509032
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.685223557
Short name T423
Test name
Test status
Simulation time 2764741394 ps
CPU time 76.85 seconds
Started Feb 04 01:12:47 PM PST 24
Finished Feb 04 01:14:05 PM PST 24
Peak memory 217940 kb
Host smart-082b7d1f-b12e-4baa-adbd-689756e78e71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685223557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.685223557
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4168409741
Short name T854
Test name
Test status
Simulation time 611516506 ps
CPU time 13.66 seconds
Started Feb 04 01:12:43 PM PST 24
Finished Feb 04 01:12:58 PM PST 24
Peak memory 217680 kb
Host smart-caae3f94-cdec-4ecb-8176-9b3cac10cd4c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168409741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.4168409741
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2266264036
Short name T482
Test name
Test status
Simulation time 345920806 ps
CPU time 2.28 seconds
Started Feb 04 01:12:50 PM PST 24
Finished Feb 04 01:12:53 PM PST 24
Peak memory 217732 kb
Host smart-b0cef273-11a9-4dd4-8678-ea57c8926229
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266264036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2266264036
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3909094134
Short name T359
Test name
Test status
Simulation time 3172885927 ps
CPU time 14.23 seconds
Started Feb 04 01:12:48 PM PST 24
Finished Feb 04 01:13:03 PM PST 24
Peak memory 213112 kb
Host smart-ec69a739-e87a-4261-b7f5-fb4f33958106
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909094134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3909094134
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.541954682
Short name T803
Test name
Test status
Simulation time 251105930 ps
CPU time 4.2 seconds
Started Feb 04 01:12:44 PM PST 24
Finished Feb 04 01:12:50 PM PST 24
Peak memory 213088 kb
Host smart-ae103225-148b-4ee6-9cd8-2956c1c169c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541954682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.541954682
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4239306319
Short name T621
Test name
Test status
Simulation time 1301133510 ps
CPU time 46.07 seconds
Started Feb 04 01:12:45 PM PST 24
Finished Feb 04 01:13:32 PM PST 24
Peak memory 252264 kb
Host smart-6042c4bd-b030-443c-8c91-9aa61dc5ffd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239306319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.4239306319
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.867904490
Short name T600
Test name
Test status
Simulation time 5835290919 ps
CPU time 13.77 seconds
Started Feb 04 01:12:44 PM PST 24
Finished Feb 04 01:12:59 PM PST 24
Peak memory 225080 kb
Host smart-886a19a1-4fce-4087-9063-346e1847cc68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867904490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.867904490
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2589297549
Short name T476
Test name
Test status
Simulation time 827557759 ps
CPU time 4.08 seconds
Started Feb 04 01:12:45 PM PST 24
Finished Feb 04 01:12:50 PM PST 24
Peak memory 217804 kb
Host smart-9e07afd7-35a4-4ef0-a584-86bf4ed70c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589297549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2589297549
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2385184971
Short name T840
Test name
Test status
Simulation time 1490624054 ps
CPU time 12.82 seconds
Started Feb 04 01:12:46 PM PST 24
Finished Feb 04 01:13:01 PM PST 24
Peak memory 213628 kb
Host smart-47218cf8-ab77-4ded-86eb-ad38ff2e344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385184971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2385184971
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4185862373
Short name T811
Test name
Test status
Simulation time 1695858763 ps
CPU time 14 seconds
Started Feb 04 01:12:58 PM PST 24
Finished Feb 04 01:13:14 PM PST 24
Peak memory 217868 kb
Host smart-70b2d690-3311-4a7b-a00c-8e33a8cbd6cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185862373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4185862373
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2637358160
Short name T802
Test name
Test status
Simulation time 605913642 ps
CPU time 12.06 seconds
Started Feb 04 01:13:09 PM PST 24
Finished Feb 04 01:13:24 PM PST 24
Peak memory 217660 kb
Host smart-ade280da-7b83-49cc-b7ad-935d5e385182
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637358160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2637358160
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2221122555
Short name T428
Test name
Test status
Simulation time 780915269 ps
CPU time 16.08 seconds
Started Feb 04 01:12:49 PM PST 24
Finished Feb 04 01:13:06 PM PST 24
Peak memory 217948 kb
Host smart-f8a7d6d1-debd-40dd-8131-026c9b17c3a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221122555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
221122555
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2732817823
Short name T195
Test name
Test status
Simulation time 445987311 ps
CPU time 14.51 seconds
Started Feb 04 01:12:42 PM PST 24
Finished Feb 04 01:12:58 PM PST 24
Peak memory 217848 kb
Host smart-106062e9-df58-419f-98d1-6a47b28a4729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732817823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2732817823
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.138982338
Short name T743
Test name
Test status
Simulation time 24252522 ps
CPU time 1.38 seconds
Started Feb 04 01:12:58 PM PST 24
Finished Feb 04 01:13:02 PM PST 24
Peak memory 213052 kb
Host smart-eeee16f0-19ef-4b19-ad7d-5f58cbea8cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138982338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.138982338
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3722103691
Short name T554
Test name
Test status
Simulation time 185907481 ps
CPU time 22.58 seconds
Started Feb 04 01:12:50 PM PST 24
Finished Feb 04 01:13:14 PM PST 24
Peak memory 250860 kb
Host smart-7a5423fa-2318-4083-b2c8-287271c14588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722103691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3722103691
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2287148136
Short name T553
Test name
Test status
Simulation time 437085507 ps
CPU time 4.32 seconds
Started Feb 04 01:12:43 PM PST 24
Finished Feb 04 01:12:48 PM PST 24
Peak memory 217824 kb
Host smart-879fd72a-c51d-4f38-b075-4ff12b43ce93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287148136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2287148136
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.242259344
Short name T367
Test name
Test status
Simulation time 38494134081 ps
CPU time 204.3 seconds
Started Feb 04 01:13:19 PM PST 24
Finished Feb 04 01:16:45 PM PST 24
Peak memory 252808 kb
Host smart-1af3e0cd-d19a-498c-b4de-9394ed17e33f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242259344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.242259344
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2688837030
Short name T566
Test name
Test status
Simulation time 55515754 ps
CPU time 0.77 seconds
Started Feb 04 01:12:44 PM PST 24
Finished Feb 04 01:12:46 PM PST 24
Peak memory 207292 kb
Host smart-fc5571cb-bb15-4794-9bd8-bd2e54841dff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688837030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2688837030
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3391890625
Short name T444
Test name
Test status
Simulation time 15997426 ps
CPU time 1.05 seconds
Started Feb 04 01:15:10 PM PST 24
Finished Feb 04 01:15:13 PM PST 24
Peak memory 208084 kb
Host smart-8c767260-cb6a-4e60-9663-4fe97165226e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391890625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3391890625
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1260644138
Short name T363
Test name
Test status
Simulation time 259461456 ps
CPU time 11.36 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:28 PM PST 24
Peak memory 217924 kb
Host smart-ba285839-b2a9-48bf-bb7a-d59f8d644d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260644138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1260644138
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3499430483
Short name T542
Test name
Test status
Simulation time 95103636 ps
CPU time 4.18 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:21 PM PST 24
Peak memory 217864 kb
Host smart-39217ebc-f421-485b-94a5-e9e354246578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499430483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3499430483
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1417851380
Short name T410
Test name
Test status
Simulation time 356077170 ps
CPU time 15.8 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:33 PM PST 24
Peak memory 217848 kb
Host smart-cf87fcf4-0991-4f09-b3a1-e33d1940b7de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417851380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1417851380
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2057269123
Short name T618
Test name
Test status
Simulation time 4564915196 ps
CPU time 21.26 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:37 PM PST 24
Peak memory 217880 kb
Host smart-2af20b8d-363f-4f6b-a765-9f84f99089fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057269123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2057269123
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3880188012
Short name T821
Test name
Test status
Simulation time 1015567051 ps
CPU time 10.11 seconds
Started Feb 04 01:15:05 PM PST 24
Finished Feb 04 01:15:18 PM PST 24
Peak memory 217828 kb
Host smart-59acd0a9-7b1e-435e-be55-9c1de996f9d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880188012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3880188012
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3617896405
Short name T457
Test name
Test status
Simulation time 4984159120 ps
CPU time 11.76 seconds
Started Feb 04 01:15:09 PM PST 24
Finished Feb 04 01:15:22 PM PST 24
Peak memory 217816 kb
Host smart-b9c24ee6-d45a-4f20-8ff8-7c56a264a17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617896405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3617896405
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3984084254
Short name T421
Test name
Test status
Simulation time 40260414 ps
CPU time 2 seconds
Started Feb 04 01:15:10 PM PST 24
Finished Feb 04 01:15:14 PM PST 24
Peak memory 213528 kb
Host smart-70bfa426-31cc-4a29-8c5f-d7bbddc870d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984084254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3984084254
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.141797247
Short name T341
Test name
Test status
Simulation time 1127375278 ps
CPU time 31.64 seconds
Started Feb 04 01:15:10 PM PST 24
Finished Feb 04 01:15:43 PM PST 24
Peak memory 250740 kb
Host smart-eb610d5c-ce6a-4584-a8e3-f6eb48149c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141797247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.141797247
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3189383949
Short name T953
Test name
Test status
Simulation time 604458685 ps
CPU time 2.64 seconds
Started Feb 04 01:15:06 PM PST 24
Finished Feb 04 01:15:11 PM PST 24
Peak memory 221740 kb
Host smart-58412e96-d49f-41ce-8671-f486142c494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189383949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3189383949
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1186917003
Short name T573
Test name
Test status
Simulation time 76056295620 ps
CPU time 161.61 seconds
Started Feb 04 01:15:11 PM PST 24
Finished Feb 04 01:17:54 PM PST 24
Peak memory 250888 kb
Host smart-145e2897-377f-4f9c-bc7d-48583cea503b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186917003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1186917003
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2016241409
Short name T454
Test name
Test status
Simulation time 42733505 ps
CPU time 0.82 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:19 PM PST 24
Peak memory 208032 kb
Host smart-f513d169-7a96-4bfd-b98e-f457b15fe2cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016241409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2016241409
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.281696431
Short name T317
Test name
Test status
Simulation time 55725041 ps
CPU time 0.87 seconds
Started Feb 04 01:15:16 PM PST 24
Finished Feb 04 01:15:18 PM PST 24
Peak memory 208016 kb
Host smart-ff9e3b0a-bcba-4c4f-afec-5ac2387e1d28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281696431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.281696431
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1508908685
Short name T586
Test name
Test status
Simulation time 365646051 ps
CPU time 11.75 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:30 PM PST 24
Peak memory 217752 kb
Host smart-49ed6026-b0be-4824-a3c9-0d802c4ab66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508908685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1508908685
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3279129495
Short name T893
Test name
Test status
Simulation time 746133221 ps
CPU time 1.66 seconds
Started Feb 04 01:15:12 PM PST 24
Finished Feb 04 01:15:15 PM PST 24
Peak memory 209596 kb
Host smart-6751c309-e9d1-45c2-93ec-bd17125d473f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279129495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.3279129495
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.723736621
Short name T699
Test name
Test status
Simulation time 274289777 ps
CPU time 2.03 seconds
Started Feb 04 01:15:09 PM PST 24
Finished Feb 04 01:15:13 PM PST 24
Peak memory 217852 kb
Host smart-a8f51cc6-3d95-4165-a57a-dc9623195c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723736621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.723736621
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1185500025
Short name T978
Test name
Test status
Simulation time 460177503 ps
CPU time 11.2 seconds
Started Feb 04 01:15:17 PM PST 24
Finished Feb 04 01:15:29 PM PST 24
Peak memory 217844 kb
Host smart-4a5ed19a-0aa6-4917-b96b-d85aaf8bd906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185500025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1185500025
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2601637482
Short name T324
Test name
Test status
Simulation time 977409912 ps
CPU time 14.09 seconds
Started Feb 04 01:15:24 PM PST 24
Finished Feb 04 01:15:40 PM PST 24
Peak memory 217932 kb
Host smart-330527f0-9e58-4356-983d-ae061ff04619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601637482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2601637482
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1263603467
Short name T939
Test name
Test status
Simulation time 510191185 ps
CPU time 11.56 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:29 PM PST 24
Peak memory 217800 kb
Host smart-33be187d-5551-4478-a8fb-2d7323e53386
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263603467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1263603467
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1480215714
Short name T351
Test name
Test status
Simulation time 1031614632 ps
CPU time 8.82 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:24 PM PST 24
Peak memory 217560 kb
Host smart-975914e9-2587-4527-9a1d-909b11098e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480215714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1480215714
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1578786591
Short name T479
Test name
Test status
Simulation time 539955287 ps
CPU time 2.63 seconds
Started Feb 04 01:15:11 PM PST 24
Finished Feb 04 01:15:15 PM PST 24
Peak memory 214116 kb
Host smart-c77d1ac8-b9e6-4cb2-860c-ee0bf9daca23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578786591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1578786591
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3539473950
Short name T858
Test name
Test status
Simulation time 1436768637 ps
CPU time 32.53 seconds
Started Feb 04 01:15:08 PM PST 24
Finished Feb 04 01:15:43 PM PST 24
Peak memory 250660 kb
Host smart-18c0d489-bfa6-455b-a59a-5d7207b494e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539473950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3539473950
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.267872572
Short name T424
Test name
Test status
Simulation time 419843160 ps
CPU time 6.47 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:15 PM PST 24
Peak memory 246304 kb
Host smart-6f0503c9-8a6e-4bde-b66f-3b1e6758b7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267872572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.267872572
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1268048943
Short name T52
Test name
Test status
Simulation time 6521666126 ps
CPU time 106.88 seconds
Started Feb 04 01:15:17 PM PST 24
Finished Feb 04 01:17:05 PM PST 24
Peak memory 250992 kb
Host smart-e54f9785-5f65-4a0f-8e30-b1876f12f917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268048943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1268048943
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1576078584
Short name T948
Test name
Test status
Simulation time 18080198 ps
CPU time 0.72 seconds
Started Feb 04 01:15:07 PM PST 24
Finished Feb 04 01:15:10 PM PST 24
Peak memory 205752 kb
Host smart-e1e2fb9c-0d09-48ae-a28e-262b73f49f7d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576078584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1576078584
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.262176273
Short name T371
Test name
Test status
Simulation time 15684435 ps
CPU time 0.9 seconds
Started Feb 04 01:15:25 PM PST 24
Finished Feb 04 01:15:28 PM PST 24
Peak memory 208036 kb
Host smart-8d1cab57-68fa-4426-bd4f-e402361d82e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262176273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.262176273
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.323019159
Short name T388
Test name
Test status
Simulation time 608843475 ps
CPU time 12.56 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:32 PM PST 24
Peak memory 217920 kb
Host smart-cad96642-c9cf-4a25-9170-47695855b7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323019159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.323019159
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1993422156
Short name T749
Test name
Test status
Simulation time 1306139870 ps
CPU time 3.44 seconds
Started Feb 04 01:15:22 PM PST 24
Finished Feb 04 01:15:28 PM PST 24
Peak memory 209284 kb
Host smart-4eaa4202-7d17-45a9-86d0-695b4c85985c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993422156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.1993422156
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2993139075
Short name T407
Test name
Test status
Simulation time 315474537 ps
CPU time 3.58 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:19 PM PST 24
Peak memory 217780 kb
Host smart-3848ca2e-b15d-4210-81e2-2bdf1991b289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993139075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2993139075
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1664437675
Short name T931
Test name
Test status
Simulation time 983593830 ps
CPU time 14.7 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:34 PM PST 24
Peak memory 218828 kb
Host smart-36114644-77df-4cd7-bf40-3ac1ec1e0807
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664437675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1664437675
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.68914954
Short name T732
Test name
Test status
Simulation time 1349233510 ps
CPU time 10.77 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:30 PM PST 24
Peak memory 217872 kb
Host smart-7fb45d4d-adaf-45aa-bf38-196c5007e763
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68914954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_dig
est.68914954
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3285930406
Short name T847
Test name
Test status
Simulation time 526653693 ps
CPU time 10.54 seconds
Started Feb 04 01:15:21 PM PST 24
Finished Feb 04 01:15:34 PM PST 24
Peak memory 217652 kb
Host smart-43e55e47-f0dc-4a5d-a52c-f7231ccb8a74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285930406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3285930406
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3358939045
Short name T908
Test name
Test status
Simulation time 104034035 ps
CPU time 1.52 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:20 PM PST 24
Peak memory 213196 kb
Host smart-d0693d9a-f9b8-4b5f-a192-20f2c6506acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358939045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3358939045
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1964594533
Short name T723
Test name
Test status
Simulation time 1462700067 ps
CPU time 29.8 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:49 PM PST 24
Peak memory 246236 kb
Host smart-3f721eef-39be-4dfc-8674-2e213768dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964594533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1964594533
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1380793254
Short name T804
Test name
Test status
Simulation time 144465675 ps
CPU time 3.19 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:22 PM PST 24
Peak memory 221764 kb
Host smart-ea4dc28a-0e9c-402d-ad6b-e2bb7dab120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380793254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1380793254
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1094237585
Short name T7
Test name
Test status
Simulation time 4448461224 ps
CPU time 124.08 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:17:23 PM PST 24
Peak memory 250532 kb
Host smart-2a418b98-705a-4c72-a8d9-53fc1bf10969
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094237585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1094237585
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1399308188
Short name T575
Test name
Test status
Simulation time 21551285 ps
CPU time 0.75 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:16 PM PST 24
Peak memory 207668 kb
Host smart-4b3adf84-197d-4829-87a4-8f89c8e78040
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399308188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1399308188
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1880855514
Short name T683
Test name
Test status
Simulation time 17680790 ps
CPU time 0.93 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:20 PM PST 24
Peak memory 209416 kb
Host smart-7e34af01-d9ba-43a1-b927-34b2b2659d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880855514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1880855514
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3107340205
Short name T57
Test name
Test status
Simulation time 1145512738 ps
CPU time 14.49 seconds
Started Feb 04 01:15:22 PM PST 24
Finished Feb 04 01:15:40 PM PST 24
Peak memory 217804 kb
Host smart-41f9a3e9-96c8-4ff9-aff3-2457edb518d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107340205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3107340205
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3286177723
Short name T682
Test name
Test status
Simulation time 255392891 ps
CPU time 6.55 seconds
Started Feb 04 01:15:24 PM PST 24
Finished Feb 04 01:15:33 PM PST 24
Peak memory 209424 kb
Host smart-bef10548-7085-4896-b675-c3752c020649
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286177723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.3286177723
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3223462924
Short name T505
Test name
Test status
Simulation time 85229716 ps
CPU time 2.86 seconds
Started Feb 04 01:15:17 PM PST 24
Finished Feb 04 01:15:21 PM PST 24
Peak memory 217860 kb
Host smart-3bca3742-d1ac-4cb1-880d-bd551ed14945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223462924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3223462924
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1419845633
Short name T519
Test name
Test status
Simulation time 2146263277 ps
CPU time 13.08 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:32 PM PST 24
Peak memory 217876 kb
Host smart-c643decf-4fe5-4f5a-9cb6-9c8ca07f95c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419845633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1419845633
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2519653417
Short name T309
Test name
Test status
Simulation time 648816754 ps
CPU time 12.42 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:30 PM PST 24
Peak memory 217804 kb
Host smart-13da0940-70b1-4b2b-bc64-6cf30ff32682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519653417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2519653417
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.375001479
Short name T526
Test name
Test status
Simulation time 766745014 ps
CPU time 9.15 seconds
Started Feb 04 01:15:16 PM PST 24
Finished Feb 04 01:15:27 PM PST 24
Peak memory 217820 kb
Host smart-962afcbd-d1f2-4f34-8add-326701f317af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375001479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.375001479
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4179170050
Short name T537
Test name
Test status
Simulation time 80810407 ps
CPU time 2.2 seconds
Started Feb 04 01:15:22 PM PST 24
Finished Feb 04 01:15:28 PM PST 24
Peak memory 213592 kb
Host smart-865ccb1c-d02b-4000-9ba7-201092d3c4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179170050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4179170050
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1037228190
Short name T669
Test name
Test status
Simulation time 376840477 ps
CPU time 22.2 seconds
Started Feb 04 01:15:16 PM PST 24
Finished Feb 04 01:15:40 PM PST 24
Peak memory 250904 kb
Host smart-6431103f-8199-4790-969b-c69e5e85610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037228190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1037228190
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.4281825504
Short name T972
Test name
Test status
Simulation time 130540935 ps
CPU time 8.85 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:24 PM PST 24
Peak memory 250480 kb
Host smart-9bc09d90-94b0-4fd3-bd8d-666820ee9e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281825504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.4281825504
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.130154313
Short name T824
Test name
Test status
Simulation time 1953330029 ps
CPU time 35.16 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:52 PM PST 24
Peak memory 250684 kb
Host smart-41af83b3-6f02-4c96-89aa-6cf27728d4d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130154313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.130154313
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.119227683
Short name T674
Test name
Test status
Simulation time 21061865 ps
CPU time 0.77 seconds
Started Feb 04 01:15:19 PM PST 24
Finished Feb 04 01:15:21 PM PST 24
Peak memory 208116 kb
Host smart-5d65d02b-c8b5-4b3b-b400-f28631102f78
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119227683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.119227683
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2659778190
Short name T665
Test name
Test status
Simulation time 59402355 ps
CPU time 1.13 seconds
Started Feb 04 01:15:17 PM PST 24
Finished Feb 04 01:15:19 PM PST 24
Peak memory 208312 kb
Host smart-d710fb0d-123c-40d4-9b96-c303f743678e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659778190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2659778190
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.934000004
Short name T443
Test name
Test status
Simulation time 2166234831 ps
CPU time 19.89 seconds
Started Feb 04 01:15:28 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 217940 kb
Host smart-6a97a83d-4169-4f59-abaf-2af7543178b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934000004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.934000004
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.395076158
Short name T660
Test name
Test status
Simulation time 4799719227 ps
CPU time 25.59 seconds
Started Feb 04 01:15:21 PM PST 24
Finished Feb 04 01:15:49 PM PST 24
Peak memory 217736 kb
Host smart-da0c37b4-49d1-4f13-8001-f7b5c9f52e7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395076158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_ac
cess.395076158
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1438976767
Short name T644
Test name
Test status
Simulation time 22770604 ps
CPU time 1.58 seconds
Started Feb 04 01:15:29 PM PST 24
Finished Feb 04 01:15:37 PM PST 24
Peak memory 217872 kb
Host smart-ca838b54-a5f1-47b3-afb2-09d00a4b6dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438976767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1438976767
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4262127035
Short name T955
Test name
Test status
Simulation time 1055188434 ps
CPU time 12.36 seconds
Started Feb 04 01:15:23 PM PST 24
Finished Feb 04 01:15:38 PM PST 24
Peak memory 217804 kb
Host smart-6fb4f355-ffb8-40f9-9f2b-81862c741a98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262127035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4262127035
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1302691520
Short name T561
Test name
Test status
Simulation time 1467885051 ps
CPU time 8.43 seconds
Started Feb 04 01:15:20 PM PST 24
Finished Feb 04 01:15:31 PM PST 24
Peak memory 217844 kb
Host smart-c5af6472-17f1-469d-b9fd-f1fc3358d53a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302691520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1302691520
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1279937542
Short name T596
Test name
Test status
Simulation time 479049596 ps
CPU time 8.92 seconds
Started Feb 04 01:15:20 PM PST 24
Finished Feb 04 01:15:32 PM PST 24
Peak memory 217760 kb
Host smart-6ee36c55-6dfc-41ce-a152-ebc4240decc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279937542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1279937542
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4123996298
Short name T842
Test name
Test status
Simulation time 234475901 ps
CPU time 9.81 seconds
Started Feb 04 01:15:20 PM PST 24
Finished Feb 04 01:15:33 PM PST 24
Peak memory 217756 kb
Host smart-71386f73-6b73-40df-b87a-8c6d25c34898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123996298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4123996298
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.589340935
Short name T78
Test name
Test status
Simulation time 43387764 ps
CPU time 2.82 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:22 PM PST 24
Peak memory 213796 kb
Host smart-7e1aff74-1eb2-4352-a69b-485caa24cd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589340935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.589340935
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.328139985
Short name T85
Test name
Test status
Simulation time 1693727764 ps
CPU time 21.09 seconds
Started Feb 04 01:15:20 PM PST 24
Finished Feb 04 01:15:43 PM PST 24
Peak memory 250748 kb
Host smart-3bf589bc-47df-4c4e-89d7-3df2efc7cbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328139985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.328139985
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1509582895
Short name T419
Test name
Test status
Simulation time 83656255 ps
CPU time 8.04 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:27 PM PST 24
Peak memory 250852 kb
Host smart-df5a046e-dc37-4615-b859-30f8137a75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509582895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1509582895
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1683873043
Short name T504
Test name
Test status
Simulation time 97684446419 ps
CPU time 305.23 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:20:24 PM PST 24
Peak memory 300028 kb
Host smart-927b9bfc-6806-4e79-b044-bc4ab923a032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683873043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1683873043
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.964590749
Short name T414
Test name
Test status
Simulation time 113531906 ps
CPU time 0.92 seconds
Started Feb 04 01:15:14 PM PST 24
Finished Feb 04 01:15:17 PM PST 24
Peak memory 208172 kb
Host smart-b058dd4e-6881-4b0d-b254-cf32c8d5aa0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964590749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.964590749
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1593562590
Short name T439
Test name
Test status
Simulation time 133890383 ps
CPU time 0.94 seconds
Started Feb 04 01:15:22 PM PST 24
Finished Feb 04 01:15:26 PM PST 24
Peak memory 209392 kb
Host smart-0c43834a-f439-4821-9416-a21f27b28e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593562590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1593562590
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1062766804
Short name T530
Test name
Test status
Simulation time 215698026 ps
CPU time 8.89 seconds
Started Feb 04 01:15:21 PM PST 24
Finished Feb 04 01:15:33 PM PST 24
Peak memory 217828 kb
Host smart-39216f64-e4fd-47ce-a3df-8657acb43ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062766804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1062766804
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3936051782
Short name T501
Test name
Test status
Simulation time 1204857278 ps
CPU time 7.12 seconds
Started Feb 04 01:15:20 PM PST 24
Finished Feb 04 01:15:31 PM PST 24
Peak memory 209476 kb
Host smart-4b26a51d-8c5f-4aa6-b46a-07fef1faf795
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936051782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.3936051782
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.266312820
Short name T383
Test name
Test status
Simulation time 262954287 ps
CPU time 2.83 seconds
Started Feb 04 01:15:18 PM PST 24
Finished Feb 04 01:15:23 PM PST 24
Peak memory 217860 kb
Host smart-534425de-a7ac-4bbb-a564-a4daf8025bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266312820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.266312820
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4016401697
Short name T599
Test name
Test status
Simulation time 690314013 ps
CPU time 10.46 seconds
Started Feb 04 01:15:19 PM PST 24
Finished Feb 04 01:15:31 PM PST 24
Peak memory 218196 kb
Host smart-c9d8dca3-741e-4e2d-9b98-b1759ac468b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016401697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4016401697
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3266486531
Short name T45
Test name
Test status
Simulation time 5696876263 ps
CPU time 15.66 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 218000 kb
Host smart-96ef239b-a8c4-4f3b-8019-f04592fbdf64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266486531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3266486531
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1496559869
Short name T725
Test name
Test status
Simulation time 755161810 ps
CPU time 14.08 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:51 PM PST 24
Peak memory 217712 kb
Host smart-356e190e-3c08-4e35-8fc2-7b51e9a23cbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496559869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1496559869
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.951988815
Short name T607
Test name
Test status
Simulation time 282741074 ps
CPU time 8.88 seconds
Started Feb 04 01:15:22 PM PST 24
Finished Feb 04 01:15:35 PM PST 24
Peak memory 217808 kb
Host smart-8ec7e5b8-e0a6-42ec-a58e-7a7f0ed97842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951988815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.951988815
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1661410926
Short name T466
Test name
Test status
Simulation time 34731755 ps
CPU time 1.38 seconds
Started Feb 04 01:15:16 PM PST 24
Finished Feb 04 01:15:19 PM PST 24
Peak memory 213084 kb
Host smart-08ff30e5-67dc-4f6b-b595-927b0aa2db0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661410926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1661410926
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.198033321
Short name T485
Test name
Test status
Simulation time 225338329 ps
CPU time 17.01 seconds
Started Feb 04 01:15:15 PM PST 24
Finished Feb 04 01:15:34 PM PST 24
Peak memory 250748 kb
Host smart-1d215b1f-b98f-4674-b7f8-99aebc8c4132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198033321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.198033321
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2832546897
Short name T118
Test name
Test status
Simulation time 98441253 ps
CPU time 6.73 seconds
Started Feb 04 01:15:20 PM PST 24
Finished Feb 04 01:15:30 PM PST 24
Peak memory 246296 kb
Host smart-614dedac-9265-4b2a-a8a5-216c8acd401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832546897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2832546897
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2307317039
Short name T800
Test name
Test status
Simulation time 7584763239 ps
CPU time 365.19 seconds
Started Feb 04 01:15:33 PM PST 24
Finished Feb 04 01:21:41 PM PST 24
Peak memory 496676 kb
Host smart-e46f1beb-730d-489d-8115-aaed890c748c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307317039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2307317039
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.395162335
Short name T452
Test name
Test status
Simulation time 21764262 ps
CPU time 0.71 seconds
Started Feb 04 01:15:19 PM PST 24
Finished Feb 04 01:15:21 PM PST 24
Peak memory 207344 kb
Host smart-b149e8fe-e5df-4423-91cf-5a1a74b2875f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395162335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.395162335
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3139936355
Short name T875
Test name
Test status
Simulation time 17974842 ps
CPU time 1.11 seconds
Started Feb 04 01:15:35 PM PST 24
Finished Feb 04 01:15:38 PM PST 24
Peak memory 209368 kb
Host smart-9d3bb465-6a57-4b34-af80-75b30d8e1195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139936355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3139936355
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1513275658
Short name T550
Test name
Test status
Simulation time 286089292 ps
CPU time 12.7 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:50 PM PST 24
Peak memory 217696 kb
Host smart-898c77fd-d690-49ff-b17c-201d6c172a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513275658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1513275658
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3693003147
Short name T679
Test name
Test status
Simulation time 3488530900 ps
CPU time 4.1 seconds
Started Feb 04 01:15:33 PM PST 24
Finished Feb 04 01:15:40 PM PST 24
Peak memory 209428 kb
Host smart-04edb830-d225-4d0c-b1c2-dc2f71c506b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693003147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.3693003147
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.803371767
Short name T393
Test name
Test status
Simulation time 234355095 ps
CPU time 3.06 seconds
Started Feb 04 01:15:28 PM PST 24
Finished Feb 04 01:15:39 PM PST 24
Peak memory 217792 kb
Host smart-044418a8-9a1b-4e82-80cf-06d6e8705d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803371767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.803371767
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1812701394
Short name T785
Test name
Test status
Simulation time 272464084 ps
CPU time 12.36 seconds
Started Feb 04 01:15:35 PM PST 24
Finished Feb 04 01:15:49 PM PST 24
Peak memory 218788 kb
Host smart-3bf49f17-7dd4-42b7-9702-bb2becc75db9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812701394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1812701394
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1236230970
Short name T318
Test name
Test status
Simulation time 1700146519 ps
CPU time 17.88 seconds
Started Feb 04 01:15:33 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 217612 kb
Host smart-25dbf1de-569c-46d5-8ceb-770b4af4c829
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236230970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1236230970
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2189380070
Short name T680
Test name
Test status
Simulation time 315579034 ps
CPU time 11.47 seconds
Started Feb 04 01:15:30 PM PST 24
Finished Feb 04 01:15:47 PM PST 24
Peak memory 217768 kb
Host smart-0b1fc02a-ade2-434f-8ee2-af6b0134bf6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189380070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2189380070
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2560969963
Short name T82
Test name
Test status
Simulation time 518238528 ps
CPU time 10.79 seconds
Started Feb 04 01:15:32 PM PST 24
Finished Feb 04 01:15:46 PM PST 24
Peak memory 217720 kb
Host smart-daa01c18-11a2-4981-8b7e-f4a7ff9c40ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560969963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2560969963
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1529897441
Short name T716
Test name
Test status
Simulation time 174156973 ps
CPU time 2.03 seconds
Started Feb 04 01:15:31 PM PST 24
Finished Feb 04 01:15:37 PM PST 24
Peak memory 213380 kb
Host smart-009bbcb1-5e15-4112-98da-960396a5db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529897441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1529897441
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.525332566
Short name T567
Test name
Test status
Simulation time 678222549 ps
CPU time 21.43 seconds
Started Feb 04 01:15:31 PM PST 24
Finished Feb 04 01:15:57 PM PST 24
Peak memory 250836 kb
Host smart-ef444b58-da7f-4764-81f9-e7f923689734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525332566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.525332566
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4227198323
Short name T449
Test name
Test status
Simulation time 765752868 ps
CPU time 10.18 seconds
Started Feb 04 01:15:32 PM PST 24
Finished Feb 04 01:15:46 PM PST 24
Peak memory 250840 kb
Host smart-5222e56c-57d9-4a4f-a11f-3cc879a1d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227198323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4227198323
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.32653560
Short name T816
Test name
Test status
Simulation time 27437300535 ps
CPU time 631.08 seconds
Started Feb 04 01:15:28 PM PST 24
Finished Feb 04 01:26:07 PM PST 24
Peak memory 283692 kb
Host smart-9c16b7a2-35e9-4622-86cb-a2f0c12b054b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32653560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.lc_ctrl_stress_all.32653560
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1452261291
Short name T954
Test name
Test status
Simulation time 33906329 ps
CPU time 0.87 seconds
Started Feb 04 01:15:31 PM PST 24
Finished Feb 04 01:15:36 PM PST 24
Peak memory 207792 kb
Host smart-1ad96fd9-3a01-4d6b-9fca-07bc7fe022e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452261291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1452261291
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1597837137
Short name T668
Test name
Test status
Simulation time 42639299 ps
CPU time 0.82 seconds
Started Feb 04 01:15:23 PM PST 24
Finished Feb 04 01:15:27 PM PST 24
Peak memory 207860 kb
Host smart-53710be6-9aab-4e5f-862f-7d1fd05db903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597837137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1597837137
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3748184308
Short name T692
Test name
Test status
Simulation time 1381778029 ps
CPU time 15.71 seconds
Started Feb 04 01:15:29 PM PST 24
Finished Feb 04 01:15:51 PM PST 24
Peak memory 217852 kb
Host smart-428212a9-8a1d-41b3-ba30-b4e9a565f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748184308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3748184308
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2589950555
Short name T886
Test name
Test status
Simulation time 700595252 ps
CPU time 7.34 seconds
Started Feb 04 01:15:24 PM PST 24
Finished Feb 04 01:15:33 PM PST 24
Peak memory 209460 kb
Host smart-b7e9d72c-96c2-478c-9c3d-e0ea76025420
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589950555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.2589950555
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3345099927
Short name T339
Test name
Test status
Simulation time 71115843 ps
CPU time 2.85 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:41 PM PST 24
Peak memory 217832 kb
Host smart-b33831bb-4128-4c36-a100-d1956a1e8aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345099927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3345099927
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3474211643
Short name T513
Test name
Test status
Simulation time 985696265 ps
CPU time 10.95 seconds
Started Feb 04 01:15:33 PM PST 24
Finished Feb 04 01:15:47 PM PST 24
Peak memory 218784 kb
Host smart-e4a633f7-5ffa-48ef-9c42-7c8d3beaefaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474211643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3474211643
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2095466620
Short name T920
Test name
Test status
Simulation time 2275337603 ps
CPU time 13.97 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:51 PM PST 24
Peak memory 217792 kb
Host smart-d769c5d1-f9e8-4ed4-aa4d-65cad1388b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095466620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2095466620
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1037937977
Short name T635
Test name
Test status
Simulation time 832634317 ps
CPU time 7.86 seconds
Started Feb 04 01:15:26 PM PST 24
Finished Feb 04 01:15:35 PM PST 24
Peak memory 217860 kb
Host smart-4b1dd350-f8a8-4676-b539-9b1419be38fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037937977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1037937977
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.214230445
Short name T742
Test name
Test status
Simulation time 949655068 ps
CPU time 10.13 seconds
Started Feb 04 01:15:22 PM PST 24
Finished Feb 04 01:15:36 PM PST 24
Peak memory 217680 kb
Host smart-35c0831e-7326-4549-8e98-6724506cd6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214230445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.214230445
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2051445049
Short name T409
Test name
Test status
Simulation time 23911779 ps
CPU time 1.7 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:39 PM PST 24
Peak memory 213128 kb
Host smart-bb81cd78-6eaf-4801-b508-3c328f219517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051445049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2051445049
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2249118063
Short name T473
Test name
Test status
Simulation time 1329867656 ps
CPU time 28.55 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:16:21 PM PST 24
Peak memory 250744 kb
Host smart-aedbb221-ac7e-433b-b973-8ccac5e0e7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249118063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2249118063
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2999976867
Short name T625
Test name
Test status
Simulation time 85385199 ps
CPU time 8.53 seconds
Started Feb 04 01:15:27 PM PST 24
Finished Feb 04 01:15:44 PM PST 24
Peak memory 250940 kb
Host smart-23ef0990-dbed-4856-a560-5394f7453316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999976867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2999976867
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3286592314
Short name T576
Test name
Test status
Simulation time 42876537715 ps
CPU time 202.76 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:19:00 PM PST 24
Peak memory 271352 kb
Host smart-61506462-f89b-4899-bc9c-9af5be1b8e62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286592314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3286592314
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3037038503
Short name T495
Test name
Test status
Simulation time 12728107 ps
CPU time 0.78 seconds
Started Feb 04 01:15:28 PM PST 24
Finished Feb 04 01:15:36 PM PST 24
Peak memory 207728 kb
Host smart-16c160a8-9081-4135-8da4-a8eafe95b570
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037038503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3037038503
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.417877822
Short name T498
Test name
Test status
Simulation time 19595705 ps
CPU time 0.91 seconds
Started Feb 04 01:15:35 PM PST 24
Finished Feb 04 01:15:38 PM PST 24
Peak memory 209368 kb
Host smart-5f0b668b-8cdc-446b-aa40-e56e4ef43a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417877822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.417877822
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2638622872
Short name T832
Test name
Test status
Simulation time 1259523270 ps
CPU time 11.63 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:49 PM PST 24
Peak memory 217800 kb
Host smart-1228a55f-33ac-414a-80ee-cd7ad89ea335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638622872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2638622872
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1059849461
Short name T480
Test name
Test status
Simulation time 161485536 ps
CPU time 2.78 seconds
Started Feb 04 01:15:27 PM PST 24
Finished Feb 04 01:15:38 PM PST 24
Peak memory 209448 kb
Host smart-3bff937a-3217-4222-bb06-8b5f803c07f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059849461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.1059849461
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3535823762
Short name T516
Test name
Test status
Simulation time 108753776 ps
CPU time 3 seconds
Started Feb 04 01:15:28 PM PST 24
Finished Feb 04 01:15:38 PM PST 24
Peak memory 217820 kb
Host smart-8e847d7f-8ff9-4876-9ff1-96c3af33c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535823762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3535823762
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1322097246
Short name T374
Test name
Test status
Simulation time 4307866155 ps
CPU time 13.16 seconds
Started Feb 04 01:15:24 PM PST 24
Finished Feb 04 01:15:40 PM PST 24
Peak memory 218904 kb
Host smart-fc519f4c-8617-482a-80ef-647d6f709278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322097246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1322097246
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3276662204
Short name T709
Test name
Test status
Simulation time 383293448 ps
CPU time 8.33 seconds
Started Feb 04 01:15:28 PM PST 24
Finished Feb 04 01:15:44 PM PST 24
Peak memory 217768 kb
Host smart-a1899450-1f04-43d1-bf75-c17682924ccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276662204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3276662204
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.723585338
Short name T848
Test name
Test status
Simulation time 769612901 ps
CPU time 13.43 seconds
Started Feb 04 01:15:28 PM PST 24
Finished Feb 04 01:15:49 PM PST 24
Peak memory 217816 kb
Host smart-677a959a-e1a8-407b-9d42-52306c704fc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723585338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.723585338
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1428391277
Short name T193
Test name
Test status
Simulation time 803447534 ps
CPU time 6.37 seconds
Started Feb 04 01:15:33 PM PST 24
Finished Feb 04 01:15:42 PM PST 24
Peak memory 217732 kb
Host smart-8b56c55f-c53b-4b39-ac7f-4e0abd5df84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428391277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1428391277
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.266337037
Short name T901
Test name
Test status
Simulation time 97548577 ps
CPU time 1.14 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 212908 kb
Host smart-8369b400-9602-4dfb-ab49-af6d5e41fa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266337037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.266337037
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.295964871
Short name T496
Test name
Test status
Simulation time 396016475 ps
CPU time 15.79 seconds
Started Feb 04 01:15:30 PM PST 24
Finished Feb 04 01:15:51 PM PST 24
Peak memory 250836 kb
Host smart-a13f655d-ff09-46f3-a255-ddbb710e748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295964871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.295964871
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2347169725
Short name T416
Test name
Test status
Simulation time 60719259 ps
CPU time 3.38 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:41 PM PST 24
Peak memory 222280 kb
Host smart-9458ca4b-b34a-481f-8f5d-f032f370b0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347169725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2347169725
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2206370676
Short name T440
Test name
Test status
Simulation time 5970304982 ps
CPU time 226.48 seconds
Started Feb 04 01:15:26 PM PST 24
Finished Feb 04 01:19:13 PM PST 24
Peak memory 413192 kb
Host smart-79131ef2-4cca-4fc4-aba0-d528b43533bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206370676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2206370676
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2060440592
Short name T32
Test name
Test status
Simulation time 28114997 ps
CPU time 1.21 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 212464 kb
Host smart-484ff3dd-d53f-44c9-bf2a-636a3e4e834a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060440592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2060440592
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3622239825
Short name T849
Test name
Test status
Simulation time 17851521 ps
CPU time 0.91 seconds
Started Feb 04 01:15:40 PM PST 24
Finished Feb 04 01:15:42 PM PST 24
Peak memory 209396 kb
Host smart-6482913b-5f9d-4b49-a400-c5774a066a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622239825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3622239825
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1621181524
Short name T343
Test name
Test status
Simulation time 1049540487 ps
CPU time 9.76 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:48 PM PST 24
Peak memory 217812 kb
Host smart-c53cf535-39a9-4894-8bbd-2f2e81d5148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621181524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1621181524
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.537618334
Short name T548
Test name
Test status
Simulation time 1757094989 ps
CPU time 9.98 seconds
Started Feb 04 01:15:31 PM PST 24
Finished Feb 04 01:15:46 PM PST 24
Peak memory 209480 kb
Host smart-833b93fa-8a89-4688-80b6-9d6fd8aeb9a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537618334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_ac
cess.537618334
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.768462375
Short name T671
Test name
Test status
Simulation time 103836187 ps
CPU time 3.23 seconds
Started Feb 04 01:15:26 PM PST 24
Finished Feb 04 01:15:30 PM PST 24
Peak memory 217832 kb
Host smart-6600c3f0-9a46-4730-bd43-47a6f22bc4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768462375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.768462375
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2721770165
Short name T713
Test name
Test status
Simulation time 1005422520 ps
CPU time 10.82 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:16:03 PM PST 24
Peak memory 217796 kb
Host smart-945618b2-9a57-4897-b330-be5a5f90d2af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721770165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2721770165
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1014660771
Short name T603
Test name
Test status
Simulation time 5885244674 ps
CPU time 11.14 seconds
Started Feb 04 01:15:28 PM PST 24
Finished Feb 04 01:15:47 PM PST 24
Peak memory 217856 kb
Host smart-6f6a8356-006f-48e4-8877-a330f6d4019b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014660771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1014660771
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.4121736650
Short name T864
Test name
Test status
Simulation time 272493761 ps
CPU time 7.27 seconds
Started Feb 04 01:15:26 PM PST 24
Finished Feb 04 01:15:34 PM PST 24
Peak memory 217824 kb
Host smart-bdec8361-1799-428f-b7a6-3804c0ebcf3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121736650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
4121736650
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3139283312
Short name T681
Test name
Test status
Simulation time 390841262 ps
CPU time 10.17 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:16:02 PM PST 24
Peak memory 217744 kb
Host smart-14342f6d-ee8b-41a3-b65d-0e53b87c37f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139283312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3139283312
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3768087372
Short name T80
Test name
Test status
Simulation time 219615876 ps
CPU time 2.82 seconds
Started Feb 04 01:15:33 PM PST 24
Finished Feb 04 01:15:39 PM PST 24
Peak memory 213472 kb
Host smart-feb41800-e526-461a-bb4d-f26303a26fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768087372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3768087372
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3296645886
Short name T500
Test name
Test status
Simulation time 1281608365 ps
CPU time 18.18 seconds
Started Feb 04 01:15:31 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 250852 kb
Host smart-5bac50fb-46b9-43db-9787-356657ce19b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296645886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3296645886
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1614027901
Short name T776
Test name
Test status
Simulation time 107857891 ps
CPU time 9.01 seconds
Started Feb 04 01:15:35 PM PST 24
Finished Feb 04 01:15:46 PM PST 24
Peak memory 250840 kb
Host smart-cf6d8324-47cd-4c5a-8135-9ed45ac25d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614027901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1614027901
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2352930973
Short name T977
Test name
Test status
Simulation time 3741663711 ps
CPU time 104.17 seconds
Started Feb 04 01:15:34 PM PST 24
Finished Feb 04 01:17:20 PM PST 24
Peak memory 248012 kb
Host smart-0a0d8fdb-e8f8-4c1e-92be-7b5a3e4d1a84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352930973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2352930973
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2924821991
Short name T549
Test name
Test status
Simulation time 13743090 ps
CPU time 0.8 seconds
Started Feb 04 01:15:26 PM PST 24
Finished Feb 04 01:15:32 PM PST 24
Peak memory 207864 kb
Host smart-670d2470-1356-4b5a-a490-3f5751a64907
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924821991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2924821991
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2084856697
Short name T98
Test name
Test status
Simulation time 53064541 ps
CPU time 0.87 seconds
Started Feb 04 01:13:16 PM PST 24
Finished Feb 04 01:13:18 PM PST 24
Peak memory 209260 kb
Host smart-70f0c6ed-679d-43c4-ad8d-9a379ad26c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084856697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2084856697
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1356093644
Short name T570
Test name
Test status
Simulation time 12171167 ps
CPU time 0.77 seconds
Started Feb 04 01:13:09 PM PST 24
Finished Feb 04 01:13:12 PM PST 24
Peak memory 209212 kb
Host smart-e50cd654-adb3-4026-8416-047200bc8346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356093644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1356093644
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.26055768
Short name T836
Test name
Test status
Simulation time 1960510684 ps
CPU time 14.71 seconds
Started Feb 04 01:13:14 PM PST 24
Finished Feb 04 01:13:30 PM PST 24
Peak memory 217688 kb
Host smart-8e759b2f-1686-4605-990b-57b9ace770de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26055768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.26055768
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3874328997
Short name T809
Test name
Test status
Simulation time 1219171139 ps
CPU time 6.4 seconds
Started Feb 04 01:13:16 PM PST 24
Finished Feb 04 01:13:23 PM PST 24
Peak memory 209468 kb
Host smart-b819fcbb-0547-4f0c-a1eb-0610176d9d31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874328997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ac
cess.3874328997
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1659253568
Short name T738
Test name
Test status
Simulation time 7067297050 ps
CPU time 43.21 seconds
Started Feb 04 01:13:15 PM PST 24
Finished Feb 04 01:13:59 PM PST 24
Peak memory 218128 kb
Host smart-d182111a-d5a1-48c1-9fa9-c486ee98ea50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659253568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1659253568
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2174386128
Short name T770
Test name
Test status
Simulation time 1736665985 ps
CPU time 37.84 seconds
Started Feb 04 01:13:12 PM PST 24
Finished Feb 04 01:13:51 PM PST 24
Peak memory 217624 kb
Host smart-8720c048-a237-4c2d-b76a-ce1acd31f1f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174386128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.2174386128
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1086917944
Short name T349
Test name
Test status
Simulation time 521103320 ps
CPU time 7.79 seconds
Started Feb 04 01:13:12 PM PST 24
Finished Feb 04 01:13:21 PM PST 24
Peak memory 217704 kb
Host smart-d9f693f0-dd16-4841-b683-2350ea01c494
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086917944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1086917944
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1264454244
Short name T736
Test name
Test status
Simulation time 1929486354 ps
CPU time 24.58 seconds
Started Feb 04 01:13:19 PM PST 24
Finished Feb 04 01:13:45 PM PST 24
Peak memory 212940 kb
Host smart-33cada0c-94a8-474b-a73a-92f3c7536570
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264454244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1264454244
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3173500707
Short name T77
Test name
Test status
Simulation time 3345727313 ps
CPU time 7.69 seconds
Started Feb 04 01:13:11 PM PST 24
Finished Feb 04 01:13:20 PM PST 24
Peak memory 213896 kb
Host smart-1dcfaea8-32be-42f0-a55a-2fc066ea054e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173500707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3173500707
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2492422499
Short name T676
Test name
Test status
Simulation time 1481350009 ps
CPU time 66.63 seconds
Started Feb 04 01:13:12 PM PST 24
Finished Feb 04 01:14:19 PM PST 24
Peak memory 267744 kb
Host smart-e8b03e7a-2add-46af-9a7a-88d329a9ee5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492422499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2492422499
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4250140748
Short name T415
Test name
Test status
Simulation time 851350367 ps
CPU time 12.35 seconds
Started Feb 04 01:13:14 PM PST 24
Finished Feb 04 01:13:28 PM PST 24
Peak memory 223276 kb
Host smart-10683834-810f-427c-b890-6c4ec11e4399
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250140748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4250140748
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3136035743
Short name T402
Test name
Test status
Simulation time 42710578 ps
CPU time 1.67 seconds
Started Feb 04 01:13:11 PM PST 24
Finished Feb 04 01:13:14 PM PST 24
Peak memory 217884 kb
Host smart-13ccfb1b-fe37-4519-b699-d594668ba6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136035743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3136035743
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1196774015
Short name T62
Test name
Test status
Simulation time 2213643387 ps
CPU time 19.35 seconds
Started Feb 04 01:13:10 PM PST 24
Finished Feb 04 01:13:31 PM PST 24
Peak memory 213560 kb
Host smart-03123bf9-29e7-4988-94b0-d97fa2fbdfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196774015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1196774015
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.325295630
Short name T95
Test name
Test status
Simulation time 2255558885 ps
CPU time 40.32 seconds
Started Feb 04 01:13:13 PM PST 24
Finished Feb 04 01:13:54 PM PST 24
Peak memory 269472 kb
Host smart-36341595-923a-4f48-8b98-e0d9f3e8bb17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325295630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.325295630
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3315796253
Short name T47
Test name
Test status
Simulation time 1122741849 ps
CPU time 11.49 seconds
Started Feb 04 01:13:14 PM PST 24
Finished Feb 04 01:13:27 PM PST 24
Peak memory 218892 kb
Host smart-98153bc0-a4c0-4c15-a586-73115cd523f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315796253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3315796253
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1455948931
Short name T591
Test name
Test status
Simulation time 1127086710 ps
CPU time 10.87 seconds
Started Feb 04 01:13:14 PM PST 24
Finished Feb 04 01:13:26 PM PST 24
Peak memory 217820 kb
Host smart-1482598d-f545-4913-a498-f7bd8668b374
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455948931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1455948931
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1546961610
Short name T819
Test name
Test status
Simulation time 1178184125 ps
CPU time 7.22 seconds
Started Feb 04 01:13:16 PM PST 24
Finished Feb 04 01:13:24 PM PST 24
Peak memory 217876 kb
Host smart-9bcce81f-e40f-42a7-abd7-07d9bff4426d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546961610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
546961610
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.880141234
Short name T81
Test name
Test status
Simulation time 1294875345 ps
CPU time 11.79 seconds
Started Feb 04 01:13:11 PM PST 24
Finished Feb 04 01:13:24 PM PST 24
Peak memory 217844 kb
Host smart-bb85f170-5334-46c1-a885-a96fe8dc02e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880141234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.880141234
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1878080645
Short name T873
Test name
Test status
Simulation time 163642669 ps
CPU time 1.89 seconds
Started Feb 04 01:13:15 PM PST 24
Finished Feb 04 01:13:18 PM PST 24
Peak memory 213412 kb
Host smart-dc2bb64f-44a7-493c-afe8-b15fd224f4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878080645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1878080645
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.307277681
Short name T815
Test name
Test status
Simulation time 1371885533 ps
CPU time 29.59 seconds
Started Feb 04 01:13:14 PM PST 24
Finished Feb 04 01:13:45 PM PST 24
Peak memory 250932 kb
Host smart-ba8208a7-d671-4e3d-85d1-50c73bca8d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307277681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.307277681
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3861409385
Short name T634
Test name
Test status
Simulation time 885479230 ps
CPU time 7.54 seconds
Started Feb 04 01:13:11 PM PST 24
Finished Feb 04 01:13:20 PM PST 24
Peak memory 246540 kb
Host smart-73158578-4977-4335-99a4-79a6389a629c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861409385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3861409385
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1327686343
Short name T791
Test name
Test status
Simulation time 3576675617 ps
CPU time 66.21 seconds
Started Feb 04 01:13:14 PM PST 24
Finished Feb 04 01:14:21 PM PST 24
Peak memory 250988 kb
Host smart-dbdb8d96-b056-4b67-bdc1-a255a915f390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327686343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1327686343
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4121160990
Short name T425
Test name
Test status
Simulation time 36322759 ps
CPU time 0.89 seconds
Started Feb 04 01:13:13 PM PST 24
Finished Feb 04 01:13:14 PM PST 24
Peak memory 211344 kb
Host smart-7077d9ae-ab0b-4ba2-a818-c9eb0ddb3742
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121160990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4121160990
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1385073724
Short name T344
Test name
Test status
Simulation time 19043813 ps
CPU time 1.13 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 208068 kb
Host smart-cdc7e2a2-fa12-493a-ad96-b1072fe168b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385073724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1385073724
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1807479245
Short name T797
Test name
Test status
Simulation time 275238274 ps
CPU time 7.73 seconds
Started Feb 04 01:15:41 PM PST 24
Finished Feb 04 01:15:50 PM PST 24
Peak memory 217936 kb
Host smart-05abd528-3f96-403f-8f34-5b280c3e6e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807479245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1807479245
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.785513284
Short name T747
Test name
Test status
Simulation time 333292212 ps
CPU time 4.19 seconds
Started Feb 04 01:15:41 PM PST 24
Finished Feb 04 01:15:46 PM PST 24
Peak memory 209444 kb
Host smart-e743eb40-1bdb-43c7-af44-6b4b1f031812
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785513284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_ac
cess.785513284
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3465560699
Short name T626
Test name
Test status
Simulation time 84921365 ps
CPU time 2.14 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 217824 kb
Host smart-85f06b63-6174-46a7-a82b-8e669415b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465560699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3465560699
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2139496923
Short name T794
Test name
Test status
Simulation time 617167953 ps
CPU time 13.73 seconds
Started Feb 04 01:15:39 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 217844 kb
Host smart-9a603425-bb61-498d-85c7-6deddb2a6bcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139496923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2139496923
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1003077063
Short name T727
Test name
Test status
Simulation time 520823118 ps
CPU time 13.01 seconds
Started Feb 04 01:15:42 PM PST 24
Finished Feb 04 01:15:56 PM PST 24
Peak memory 217684 kb
Host smart-21a6f7cc-36bb-4458-a7ee-88dca5e18e30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003077063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1003077063
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3110061028
Short name T712
Test name
Test status
Simulation time 217826464 ps
CPU time 8.38 seconds
Started Feb 04 01:15:44 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 217812 kb
Host smart-f369787d-9bc3-42f1-a01a-eb182fbab3df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110061028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3110061028
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1707406779
Short name T391
Test name
Test status
Simulation time 486593199 ps
CPU time 11.31 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:04 PM PST 24
Peak memory 217668 kb
Host smart-d1866318-42c2-473f-8e6a-77e2ab7f550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707406779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1707406779
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3709133791
Short name T945
Test name
Test status
Simulation time 122371574 ps
CPU time 1.51 seconds
Started Feb 04 01:15:40 PM PST 24
Finished Feb 04 01:15:43 PM PST 24
Peak memory 213128 kb
Host smart-6573aa77-e9d4-4414-bc74-2c13155f0631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709133791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3709133791
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1618869378
Short name T507
Test name
Test status
Simulation time 1159185566 ps
CPU time 26.8 seconds
Started Feb 04 01:15:41 PM PST 24
Finished Feb 04 01:16:09 PM PST 24
Peak memory 250836 kb
Host smart-f720a93d-f261-4fe4-8937-a535a6749d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618869378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1618869378
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2025118238
Short name T84
Test name
Test status
Simulation time 152020325 ps
CPU time 6.57 seconds
Started Feb 04 01:15:46 PM PST 24
Finished Feb 04 01:15:57 PM PST 24
Peak memory 246476 kb
Host smart-e5920a91-fc80-4357-82a1-802f8ba96427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025118238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2025118238
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.849460693
Short name T448
Test name
Test status
Simulation time 13119180 ps
CPU time 0.97 seconds
Started Feb 04 01:15:41 PM PST 24
Finished Feb 04 01:15:43 PM PST 24
Peak memory 208216 kb
Host smart-17add679-ef20-4233-8bc6-799b5d2889da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849460693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.849460693
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2434013033
Short name T70
Test name
Test status
Simulation time 57165201 ps
CPU time 0.9 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:39 PM PST 24
Peak memory 209424 kb
Host smart-fad06bf9-f712-4e0d-bb38-9a7082dfb869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434013033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2434013033
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1846637208
Short name T325
Test name
Test status
Simulation time 451136037 ps
CPU time 9.21 seconds
Started Feb 04 01:15:44 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 217852 kb
Host smart-9f834c4d-b9ac-4d72-914c-aa32fda025d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846637208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1846637208
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3707374419
Short name T8
Test name
Test status
Simulation time 6626847856 ps
CPU time 8.06 seconds
Started Feb 04 01:15:45 PM PST 24
Finished Feb 04 01:15:56 PM PST 24
Peak memory 209188 kb
Host smart-0bbb5acc-0994-4b96-9a7b-5c7a0fb58ce0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707374419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.3707374419
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1977803274
Short name T313
Test name
Test status
Simulation time 414670640 ps
CPU time 2.59 seconds
Started Feb 04 01:15:44 PM PST 24
Finished Feb 04 01:15:49 PM PST 24
Peak memory 217848 kb
Host smart-3da30e7c-c8b2-4922-9ef3-952bd00c4640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977803274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1977803274
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.668235087
Short name T438
Test name
Test status
Simulation time 748069941 ps
CPU time 13.2 seconds
Started Feb 04 01:15:45 PM PST 24
Finished Feb 04 01:16:01 PM PST 24
Peak memory 218496 kb
Host smart-f29ef574-d818-46c8-bf0c-068616ee132c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668235087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.668235087
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.110569558
Short name T655
Test name
Test status
Simulation time 927484092 ps
CPU time 7.22 seconds
Started Feb 04 01:15:37 PM PST 24
Finished Feb 04 01:15:45 PM PST 24
Peak memory 217828 kb
Host smart-1a60e7f0-03e3-4ab4-bf7c-35b5e68b6677
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110569558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.110569558
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4183121984
Short name T726
Test name
Test status
Simulation time 1050601006 ps
CPU time 10.54 seconds
Started Feb 04 01:15:45 PM PST 24
Finished Feb 04 01:15:58 PM PST 24
Peak memory 217936 kb
Host smart-d694536a-aada-427a-8b45-5eb55c3ad6e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183121984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4183121984
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3229659787
Short name T845
Test name
Test status
Simulation time 284929489 ps
CPU time 11.68 seconds
Started Feb 04 01:15:40 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 217868 kb
Host smart-093327eb-651e-4a5d-87df-f4c20f2358aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229659787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3229659787
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1768486077
Short name T642
Test name
Test status
Simulation time 102452344 ps
CPU time 1.91 seconds
Started Feb 04 01:15:45 PM PST 24
Finished Feb 04 01:15:49 PM PST 24
Peak memory 213500 kb
Host smart-98f3a57e-ea2f-400a-8218-74643dec5d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768486077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1768486077
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.4068693057
Short name T781
Test name
Test status
Simulation time 389855962 ps
CPU time 25.69 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:19 PM PST 24
Peak memory 250760 kb
Host smart-31246e4e-7116-47c2-82f1-5f0b0a07d519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068693057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4068693057
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2498075550
Short name T909
Test name
Test status
Simulation time 59103922 ps
CPU time 3.5 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:15:56 PM PST 24
Peak memory 222124 kb
Host smart-83361340-fd9c-4f84-8bbc-dbeb2671f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498075550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2498075550
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2132706026
Short name T740
Test name
Test status
Simulation time 6887426220 ps
CPU time 194.66 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:19:08 PM PST 24
Peak memory 272048 kb
Host smart-d2f2fd1d-d46b-4b3a-a54b-eb437cfe8678
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132706026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2132706026
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4287293229
Short name T605
Test name
Test status
Simulation time 30208439 ps
CPU time 0.7 seconds
Started Feb 04 01:15:38 PM PST 24
Finished Feb 04 01:15:40 PM PST 24
Peak memory 206308 kb
Host smart-e91b62c8-91d5-4dc5-bcff-96f612487149
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287293229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4287293229
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1208091708
Short name T395
Test name
Test status
Simulation time 50067893 ps
CPU time 0.99 seconds
Started Feb 04 01:15:47 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 209444 kb
Host smart-c0ae0e4a-bd67-4904-b3f9-b9095885f075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208091708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1208091708
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3459260570
Short name T940
Test name
Test status
Simulation time 509323756 ps
CPU time 11.14 seconds
Started Feb 04 01:15:30 PM PST 24
Finished Feb 04 01:15:47 PM PST 24
Peak memory 217828 kb
Host smart-16000f7c-b486-47e4-b123-4dc5d6102547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459260570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3459260570
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3432695241
Short name T65
Test name
Test status
Simulation time 110231719 ps
CPU time 1.52 seconds
Started Feb 04 01:15:44 PM PST 24
Finished Feb 04 01:15:48 PM PST 24
Peak memory 209448 kb
Host smart-f3a3c949-8b37-400b-9c9c-6ab0d53001f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432695241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.3432695241
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1365395405
Short name T581
Test name
Test status
Simulation time 110454091 ps
CPU time 4.5 seconds
Started Feb 04 01:15:39 PM PST 24
Finished Feb 04 01:15:44 PM PST 24
Peak memory 217880 kb
Host smart-843ed722-e1d6-40f5-8d6b-6033b2b9f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365395405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1365395405
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3937064976
Short name T902
Test name
Test status
Simulation time 2730445566 ps
CPU time 14.54 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:08 PM PST 24
Peak memory 218876 kb
Host smart-4e046a2b-17dd-45bd-8a27-0acd9d2c737f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937064976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3937064976
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.295029383
Short name T788
Test name
Test status
Simulation time 336818277 ps
CPU time 12.69 seconds
Started Feb 04 01:15:38 PM PST 24
Finished Feb 04 01:15:52 PM PST 24
Peak memory 217832 kb
Host smart-720a01cc-f568-4d38-8f77-0d2cf6c7f4c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295029383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.295029383
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.404212178
Short name T658
Test name
Test status
Simulation time 998026442 ps
CPU time 8.01 seconds
Started Feb 04 01:15:46 PM PST 24
Finished Feb 04 01:15:59 PM PST 24
Peak memory 217920 kb
Host smart-e0f5476c-6600-4c77-8139-69dd3f5dee01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404212178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.404212178
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.399774845
Short name T588
Test name
Test status
Simulation time 3777267388 ps
CPU time 14.1 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:07 PM PST 24
Peak memory 217860 kb
Host smart-8c6e3e90-ff06-4172-8481-cc08d65fa96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399774845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.399774845
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1442960231
Short name T645
Test name
Test status
Simulation time 271824535 ps
CPU time 2.72 seconds
Started Feb 04 01:15:42 PM PST 24
Finished Feb 04 01:15:46 PM PST 24
Peak memory 214040 kb
Host smart-f09a21d3-77d0-4169-b03e-838cf7632f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442960231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1442960231
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2994488476
Short name T471
Test name
Test status
Simulation time 162903366 ps
CPU time 20.24 seconds
Started Feb 04 01:15:45 PM PST 24
Finished Feb 04 01:16:08 PM PST 24
Peak memory 250840 kb
Host smart-e7f6ff2a-1f03-4d7c-ac6d-e18295d82936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994488476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2994488476
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.314050036
Short name T131
Test name
Test status
Simulation time 99767316 ps
CPU time 8.18 seconds
Started Feb 04 01:15:36 PM PST 24
Finished Feb 04 01:15:45 PM PST 24
Peak memory 250924 kb
Host smart-89cd1e3f-2d3d-4788-9f3b-2ab8fe700295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314050036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.314050036
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.269046248
Short name T465
Test name
Test status
Simulation time 8238320327 ps
CPU time 57.82 seconds
Started Feb 04 01:15:44 PM PST 24
Finished Feb 04 01:16:45 PM PST 24
Peak memory 252540 kb
Host smart-c30afd94-861d-4303-a507-ae060ea21961
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269046248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.269046248
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4017299860
Short name T688
Test name
Test status
Simulation time 27146526 ps
CPU time 0.86 seconds
Started Feb 04 01:15:43 PM PST 24
Finished Feb 04 01:15:46 PM PST 24
Peak memory 208160 kb
Host smart-c9259308-a0c9-4d0d-8c49-60e5b5813b6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017299860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4017299860
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3249675897
Short name T523
Test name
Test status
Simulation time 86486565 ps
CPU time 1.22 seconds
Started Feb 04 01:15:46 PM PST 24
Finished Feb 04 01:15:52 PM PST 24
Peak memory 209372 kb
Host smart-da07bcf3-3348-4ee3-a68e-0b332777c0d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249675897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3249675897
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.153227193
Short name T314
Test name
Test status
Simulation time 1726530091 ps
CPU time 16.47 seconds
Started Feb 04 01:15:37 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 217844 kb
Host smart-e10f8fa5-60b8-4554-aac2-f4aeaf9bcf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153227193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.153227193
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3165102416
Short name T877
Test name
Test status
Simulation time 657561225 ps
CPU time 4.06 seconds
Started Feb 04 01:15:34 PM PST 24
Finished Feb 04 01:15:41 PM PST 24
Peak memory 209420 kb
Host smart-f905ea72-715e-4b60-a4a6-df25de7f1ee3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165102416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.3165102416
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3005167404
Short name T354
Test name
Test status
Simulation time 27262016 ps
CPU time 1.98 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 217828 kb
Host smart-ee6f7a51-cee9-4daf-a6bd-a6540aa48d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005167404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3005167404
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.492487062
Short name T532
Test name
Test status
Simulation time 1215023386 ps
CPU time 15.03 seconds
Started Feb 04 01:15:46 PM PST 24
Finished Feb 04 01:16:06 PM PST 24
Peak memory 218812 kb
Host smart-54e6b889-e191-459d-9c1b-39e4d22d6a52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492487062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.492487062
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3410560821
Short name T132
Test name
Test status
Simulation time 2168802665 ps
CPU time 11.58 seconds
Started Feb 04 01:15:42 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 217900 kb
Host smart-f00cc0a3-8f0e-4d58-935b-d5998e166368
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410560821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3410560821
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2630344725
Short name T396
Test name
Test status
Simulation time 4058387743 ps
CPU time 13.24 seconds
Started Feb 04 01:15:39 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 217932 kb
Host smart-3d5091c0-7808-4ece-a9f4-1bfe9cf44ad5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630344725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2630344725
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2870830158
Short name T441
Test name
Test status
Simulation time 996030552 ps
CPU time 9.71 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:03 PM PST 24
Peak memory 217572 kb
Host smart-89f3f185-cc5d-4ef1-90d7-41d0b98dbc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870830158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2870830158
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2323875341
Short name T911
Test name
Test status
Simulation time 32261953 ps
CPU time 2.14 seconds
Started Feb 04 01:15:37 PM PST 24
Finished Feb 04 01:15:40 PM PST 24
Peak memory 213216 kb
Host smart-d9cf371d-e09a-4099-a52b-060977f672c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323875341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2323875341
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2192339737
Short name T651
Test name
Test status
Simulation time 225667173 ps
CPU time 19.75 seconds
Started Feb 04 01:15:38 PM PST 24
Finished Feb 04 01:15:59 PM PST 24
Peak memory 250884 kb
Host smart-b8aeab73-3226-47f5-b4c5-a9ee288ed00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192339737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2192339737
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2680073632
Short name T759
Test name
Test status
Simulation time 380675777 ps
CPU time 7.79 seconds
Started Feb 04 01:15:39 PM PST 24
Finished Feb 04 01:15:48 PM PST 24
Peak memory 250764 kb
Host smart-50145306-4ae5-4518-a0b0-4c5337e3d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680073632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2680073632
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1311452033
Short name T823
Test name
Test status
Simulation time 6244341725 ps
CPU time 58.46 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:52 PM PST 24
Peak memory 250872 kb
Host smart-34f6907e-c876-40ed-924f-ef995851e605
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311452033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1311452033
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1214868276
Short name T389
Test name
Test status
Simulation time 23300515 ps
CPU time 0.95 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 207916 kb
Host smart-8728368d-a0d2-4d0f-ae4a-86b3d2d40f8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214868276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1214868276
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1683757572
Short name T377
Test name
Test status
Simulation time 21101360 ps
CPU time 1.15 seconds
Started Feb 04 01:15:40 PM PST 24
Finished Feb 04 01:15:43 PM PST 24
Peak memory 209436 kb
Host smart-d3870f28-7f05-409b-aa27-690fbc848509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683757572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1683757572
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1989461925
Short name T622
Test name
Test status
Simulation time 1341176476 ps
CPU time 10.59 seconds
Started Feb 04 01:15:46 PM PST 24
Finished Feb 04 01:16:02 PM PST 24
Peak memory 217848 kb
Host smart-dfdad9d6-6579-4ce9-ac6d-6f37456527ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989461925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1989461925
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2122501818
Short name T538
Test name
Test status
Simulation time 769794136 ps
CPU time 5.47 seconds
Started Feb 04 01:15:41 PM PST 24
Finished Feb 04 01:15:47 PM PST 24
Peak memory 209432 kb
Host smart-c374a19d-a48d-481f-a3e3-05f3e9f68089
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122501818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.2122501818
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2974242541
Short name T338
Test name
Test status
Simulation time 253717166 ps
CPU time 2.71 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:15:56 PM PST 24
Peak memory 217820 kb
Host smart-04d2e022-7b65-43a8-8f51-6d4d79bd2833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974242541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2974242541
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1647666463
Short name T941
Test name
Test status
Simulation time 2605055981 ps
CPU time 16.38 seconds
Started Feb 04 01:15:45 PM PST 24
Finished Feb 04 01:16:07 PM PST 24
Peak memory 218864 kb
Host smart-700133f0-360d-4dba-b573-dc0aa3a2d4f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647666463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1647666463
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3617542801
Short name T400
Test name
Test status
Simulation time 1211552036 ps
CPU time 12.86 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:06 PM PST 24
Peak memory 217736 kb
Host smart-2ecebfec-2d6b-4111-8025-8aad7b348b13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617542801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3617542801
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2397625360
Short name T656
Test name
Test status
Simulation time 921848665 ps
CPU time 7.93 seconds
Started Feb 04 01:15:57 PM PST 24
Finished Feb 04 01:16:10 PM PST 24
Peak memory 217836 kb
Host smart-7b343f8b-155c-4e92-9991-79d958fca76c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397625360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2397625360
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2743051331
Short name T724
Test name
Test status
Simulation time 1636680443 ps
CPU time 15.49 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:09 PM PST 24
Peak memory 217744 kb
Host smart-c7a040a2-6e3f-44a5-801f-a31de922eb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743051331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2743051331
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.191420737
Short name T883
Test name
Test status
Simulation time 981263810 ps
CPU time 2.96 seconds
Started Feb 04 01:15:46 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 214136 kb
Host smart-f83c4f95-1492-4a2a-a5da-be4e37eb1f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191420737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.191420737
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1690166698
Short name T488
Test name
Test status
Simulation time 232427874 ps
CPU time 24.4 seconds
Started Feb 04 01:15:39 PM PST 24
Finished Feb 04 01:16:05 PM PST 24
Peak memory 250840 kb
Host smart-080a1aeb-9cc4-4823-8060-750fdee63cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690166698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1690166698
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2106209867
Short name T453
Test name
Test status
Simulation time 131890359 ps
CPU time 6.42 seconds
Started Feb 04 01:15:41 PM PST 24
Finished Feb 04 01:15:48 PM PST 24
Peak memory 249860 kb
Host smart-707c7f90-4891-4b94-b703-fa8794626f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106209867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2106209867
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2734874445
Short name T121
Test name
Test status
Simulation time 34827391 ps
CPU time 0.98 seconds
Started Feb 04 01:15:43 PM PST 24
Finished Feb 04 01:15:45 PM PST 24
Peak memory 211344 kb
Host smart-25ed2d5c-7a20-426e-b5b4-0a53e2425a56
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734874445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2734874445
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4040518871
Short name T511
Test name
Test status
Simulation time 19058793 ps
CPU time 0.94 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 209392 kb
Host smart-bd2837ae-30c1-445a-a30c-9c52e5b5224d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040518871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4040518871
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.628962565
Short name T544
Test name
Test status
Simulation time 4943259482 ps
CPU time 11.71 seconds
Started Feb 04 01:15:44 PM PST 24
Finished Feb 04 01:15:59 PM PST 24
Peak memory 217928 kb
Host smart-6241f952-f1dc-4294-a7ec-5547c7c657a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628962565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.628962565
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.619356399
Short name T518
Test name
Test status
Simulation time 1467793929 ps
CPU time 30.6 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:16:24 PM PST 24
Peak memory 217644 kb
Host smart-45ff346b-8cac-44ed-960b-e04628cb3cd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619356399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_ac
cess.619356399
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1745646040
Short name T446
Test name
Test status
Simulation time 35062701 ps
CPU time 2.02 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:15:55 PM PST 24
Peak memory 217920 kb
Host smart-e781df5c-e8be-4b77-aac2-86233201816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745646040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1745646040
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1728222347
Short name T855
Test name
Test status
Simulation time 914650325 ps
CPU time 10.94 seconds
Started Feb 04 01:15:56 PM PST 24
Finished Feb 04 01:16:13 PM PST 24
Peak memory 218824 kb
Host smart-497ff8df-cc83-4ac4-a6b0-13a8115b262d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728222347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1728222347
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2564049476
Short name T527
Test name
Test status
Simulation time 614018658 ps
CPU time 20.8 seconds
Started Feb 04 01:15:39 PM PST 24
Finished Feb 04 01:16:02 PM PST 24
Peak memory 217848 kb
Host smart-d0465f87-55e4-4b70-ae38-42037a6d7d62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564049476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2564049476
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.731560546
Short name T334
Test name
Test status
Simulation time 311976554 ps
CPU time 11.42 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:04 PM PST 24
Peak memory 217848 kb
Host smart-d8335ba3-a6b0-4be8-899a-209b313958ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731560546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.731560546
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1237484863
Short name T417
Test name
Test status
Simulation time 842447564 ps
CPU time 10.28 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:16:04 PM PST 24
Peak memory 217824 kb
Host smart-f78c010e-a28d-4997-9d99-0160f51e5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237484863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1237484863
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.836754663
Short name T509
Test name
Test status
Simulation time 46855408 ps
CPU time 3.26 seconds
Started Feb 04 01:15:58 PM PST 24
Finished Feb 04 01:16:05 PM PST 24
Peak memory 214328 kb
Host smart-67598f3f-cc44-4e60-bfb3-a954fe55d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836754663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.836754663
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1589855021
Short name T903
Test name
Test status
Simulation time 974000763 ps
CPU time 27.52 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:21 PM PST 24
Peak memory 250716 kb
Host smart-26903eaf-4d1a-49ad-b6ec-43339806d8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589855021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1589855021
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4147260847
Short name T517
Test name
Test status
Simulation time 192882925 ps
CPU time 5.86 seconds
Started Feb 04 01:15:58 PM PST 24
Finished Feb 04 01:16:08 PM PST 24
Peak memory 246160 kb
Host smart-ab1afac1-6ac2-4a43-a5ec-a19a9f385577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147260847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4147260847
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3120306730
Short name T134
Test name
Test status
Simulation time 3196188691 ps
CPU time 29.08 seconds
Started Feb 04 01:15:39 PM PST 24
Finished Feb 04 01:16:10 PM PST 24
Peak memory 248832 kb
Host smart-a9936c44-8807-42af-9ff1-32a62857c864
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120306730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3120306730
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1488161220
Short name T130
Test name
Test status
Simulation time 131145712 ps
CPU time 1.01 seconds
Started Feb 04 01:15:47 PM PST 24
Finished Feb 04 01:15:53 PM PST 24
Peak memory 212488 kb
Host smart-de4f5bbd-bcde-4768-bd04-ed2fc8127ed7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488161220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1488161220
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3151811708
Short name T853
Test name
Test status
Simulation time 20950751 ps
CPU time 0.91 seconds
Started Feb 04 01:15:58 PM PST 24
Finished Feb 04 01:16:03 PM PST 24
Peak memory 208056 kb
Host smart-ca77b99f-09f6-4ecf-b7fc-f1401069cd4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151811708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3151811708
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2670296794
Short name T777
Test name
Test status
Simulation time 1337142750 ps
CPU time 15.8 seconds
Started Feb 04 01:15:58 PM PST 24
Finished Feb 04 01:16:18 PM PST 24
Peak memory 217772 kb
Host smart-d4c55005-1fac-4fc0-9191-c994f620cab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670296794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2670296794
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.198722277
Short name T25
Test name
Test status
Simulation time 2879573923 ps
CPU time 2.46 seconds
Started Feb 04 01:15:57 PM PST 24
Finished Feb 04 01:16:04 PM PST 24
Peak memory 209444 kb
Host smart-53b8a9d9-2074-4f84-b3a0-1ec1c68fe7a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198722277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_ac
cess.198722277
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4224605627
Short name T965
Test name
Test status
Simulation time 272606086 ps
CPU time 3 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:15:57 PM PST 24
Peak memory 217868 kb
Host smart-21c27272-e49b-410f-a765-eeaeb253218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224605627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4224605627
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3720454649
Short name T783
Test name
Test status
Simulation time 594087196 ps
CPU time 14.28 seconds
Started Feb 04 01:15:52 PM PST 24
Finished Feb 04 01:16:14 PM PST 24
Peak memory 217936 kb
Host smart-021a49ee-5dee-4042-b7aa-cc4260efc408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720454649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3720454649
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2772363134
Short name T918
Test name
Test status
Simulation time 279262536 ps
CPU time 11.11 seconds
Started Feb 04 01:15:47 PM PST 24
Finished Feb 04 01:16:03 PM PST 24
Peak memory 217860 kb
Host smart-613438e5-80f1-47d3-aa21-e09d3f701144
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772363134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2772363134
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3844759587
Short name T353
Test name
Test status
Simulation time 564020336 ps
CPU time 8.37 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:16:03 PM PST 24
Peak memory 217940 kb
Host smart-53866b5b-a68e-46f4-8a5e-78dfafca388f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844759587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3844759587
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.923251751
Short name T604
Test name
Test status
Simulation time 329560501 ps
CPU time 12.78 seconds
Started Feb 04 01:15:47 PM PST 24
Finished Feb 04 01:16:04 PM PST 24
Peak memory 217864 kb
Host smart-df9d758e-707d-4d25-ac7c-348ef76d2b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923251751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.923251751
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.802851446
Short name T710
Test name
Test status
Simulation time 211241017 ps
CPU time 2.28 seconds
Started Feb 04 01:15:47 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 217744 kb
Host smart-7f29ffa0-bb26-4d30-aedb-eb9249eaf97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802851446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.802851446
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2228756657
Short name T691
Test name
Test status
Simulation time 2058466286 ps
CPU time 22.36 seconds
Started Feb 04 01:15:55 PM PST 24
Finished Feb 04 01:16:24 PM PST 24
Peak memory 250808 kb
Host smart-dcb044a3-b27d-48e0-91ce-834605fb05d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228756657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2228756657
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2797463329
Short name T825
Test name
Test status
Simulation time 139473994 ps
CPU time 7.23 seconds
Started Feb 04 01:15:58 PM PST 24
Finished Feb 04 01:16:09 PM PST 24
Peak memory 242464 kb
Host smart-726e8833-d1d4-4306-9304-cf6fec7f9b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797463329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2797463329
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3141761062
Short name T925
Test name
Test status
Simulation time 7535473231 ps
CPU time 80.18 seconds
Started Feb 04 01:15:52 PM PST 24
Finished Feb 04 01:17:20 PM PST 24
Peak memory 246980 kb
Host smart-8e406acd-9dbf-4e9c-bfec-d0693aa5254f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141761062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3141761062
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2384885910
Short name T666
Test name
Test status
Simulation time 12218879 ps
CPU time 0.81 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:15:54 PM PST 24
Peak memory 207872 kb
Host smart-f19e6887-1847-43a1-a9ce-5809dc4c241e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384885910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2384885910
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1025841010
Short name T614
Test name
Test status
Simulation time 31573530 ps
CPU time 0.88 seconds
Started Feb 04 01:15:59 PM PST 24
Finished Feb 04 01:16:03 PM PST 24
Peak memory 208068 kb
Host smart-afcaebd3-cbee-4eec-8d14-6e523ce87c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025841010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1025841010
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1660493964
Short name T520
Test name
Test status
Simulation time 827248030 ps
CPU time 18.62 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:12 PM PST 24
Peak memory 217816 kb
Host smart-5fc8481f-0da0-420c-b982-8663fbff5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660493964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1660493964
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.131827294
Short name T636
Test name
Test status
Simulation time 2324044285 ps
CPU time 5.47 seconds
Started Feb 04 01:16:00 PM PST 24
Finished Feb 04 01:16:08 PM PST 24
Peak memory 209512 kb
Host smart-a6208528-dded-4338-a376-12d5befaca3f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131827294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_ac
cess.131827294
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1441742401
Short name T330
Test name
Test status
Simulation time 278646086 ps
CPU time 2.84 seconds
Started Feb 04 01:16:00 PM PST 24
Finished Feb 04 01:16:05 PM PST 24
Peak memory 217864 kb
Host smart-2cefc8c2-4c54-452c-8694-7cfef00a0f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441742401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1441742401
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3612273528
Short name T871
Test name
Test status
Simulation time 1492304825 ps
CPU time 17.18 seconds
Started Feb 04 01:15:51 PM PST 24
Finished Feb 04 01:16:15 PM PST 24
Peak memory 218784 kb
Host smart-8204bebe-0455-4b78-8801-c969e92d4a67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612273528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3612273528
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3426821165
Short name T631
Test name
Test status
Simulation time 170372993 ps
CPU time 7.89 seconds
Started Feb 04 01:15:53 PM PST 24
Finished Feb 04 01:16:08 PM PST 24
Peak memory 217656 kb
Host smart-21b592e7-dc2a-4592-a8a2-b8db3b2e1fef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426821165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3426821165
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1718486081
Short name T508
Test name
Test status
Simulation time 231274100 ps
CPU time 8.93 seconds
Started Feb 04 01:15:48 PM PST 24
Finished Feb 04 01:16:01 PM PST 24
Peak memory 217864 kb
Host smart-383ec044-77f2-4460-8399-faa08edff9b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718486081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1718486081
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3949987130
Short name T590
Test name
Test status
Simulation time 1016628213 ps
CPU time 9.81 seconds
Started Feb 04 01:15:52 PM PST 24
Finished Feb 04 01:16:09 PM PST 24
Peak memory 217788 kb
Host smart-2fc7fb7b-aa24-4df2-b5fe-304b0bb9e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949987130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3949987130
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2262367599
Short name T514
Test name
Test status
Simulation time 60933482 ps
CPU time 3.18 seconds
Started Feb 04 01:15:51 PM PST 24
Finished Feb 04 01:15:58 PM PST 24
Peak memory 213652 kb
Host smart-c2eec4d4-5a9e-4b71-81df-08b8ef1deaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262367599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2262367599
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.38335336
Short name T812
Test name
Test status
Simulation time 585116593 ps
CPU time 29.4 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:16:23 PM PST 24
Peak memory 250820 kb
Host smart-eefe4236-8c27-4d8a-bc27-f86404ac1af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38335336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.38335336
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1268957114
Short name T565
Test name
Test status
Simulation time 76931538 ps
CPU time 8.16 seconds
Started Feb 04 01:16:00 PM PST 24
Finished Feb 04 01:16:10 PM PST 24
Peak memory 250924 kb
Host smart-29938ab7-7da6-4a7a-97cd-5897f545f72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268957114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1268957114
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1800587496
Short name T577
Test name
Test status
Simulation time 38890386 ps
CPU time 0.97 seconds
Started Feb 04 01:15:59 PM PST 24
Finished Feb 04 01:16:03 PM PST 24
Peak memory 208424 kb
Host smart-000e53dd-9a3e-4991-b1fd-7d2e0c8da739
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800587496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1800587496
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3116462241
Short name T364
Test name
Test status
Simulation time 15450106 ps
CPU time 1.04 seconds
Started Feb 04 01:16:03 PM PST 24
Finished Feb 04 01:16:06 PM PST 24
Peak memory 208160 kb
Host smart-86b140db-548f-42fa-82bb-466634863521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116462241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3116462241
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1588777421
Short name T15
Test name
Test status
Simulation time 1109217785 ps
CPU time 14.92 seconds
Started Feb 04 01:15:52 PM PST 24
Finished Feb 04 01:16:15 PM PST 24
Peak memory 217868 kb
Host smart-c2c748d0-00bc-4e52-b729-128b2e8a3285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588777421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1588777421
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.572841828
Short name T863
Test name
Test status
Simulation time 525292343 ps
CPU time 8.3 seconds
Started Feb 04 01:16:03 PM PST 24
Finished Feb 04 01:16:13 PM PST 24
Peak memory 209448 kb
Host smart-ac8985fd-cd79-4862-9a03-9d4fc255004b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572841828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_ac
cess.572841828
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.816173544
Short name T798
Test name
Test status
Simulation time 239468296 ps
CPU time 2.72 seconds
Started Feb 04 01:15:51 PM PST 24
Finished Feb 04 01:16:01 PM PST 24
Peak memory 217804 kb
Host smart-171f5274-fcad-44a1-9e74-566f8589710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816173544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.816173544
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.628474955
Short name T906
Test name
Test status
Simulation time 257158618 ps
CPU time 8.59 seconds
Started Feb 04 01:16:03 PM PST 24
Finished Feb 04 01:16:14 PM PST 24
Peak memory 217836 kb
Host smart-72020b40-45ae-4f9d-a675-501cfd702fed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628474955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.628474955
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2236351406
Short name T316
Test name
Test status
Simulation time 4794065013 ps
CPU time 15.53 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:16:09 PM PST 24
Peak memory 218104 kb
Host smart-4cf5beeb-b390-4bd6-b9a6-0b557c357f25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236351406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2236351406
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1045898232
Short name T731
Test name
Test status
Simulation time 1869872523 ps
CPU time 10.01 seconds
Started Feb 04 01:16:01 PM PST 24
Finished Feb 04 01:16:14 PM PST 24
Peak memory 217868 kb
Host smart-ceafdbdf-f075-46bf-a92a-aaa77ee6ab75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045898232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1045898232
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.604724850
Short name T690
Test name
Test status
Simulation time 1146679283 ps
CPU time 12.38 seconds
Started Feb 04 01:15:53 PM PST 24
Finished Feb 04 01:16:13 PM PST 24
Peak memory 217868 kb
Host smart-30e14cb6-681c-4eb8-b491-bf69740da6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604724850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.604724850
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1464976106
Short name T487
Test name
Test status
Simulation time 307231754 ps
CPU time 3.22 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:15:56 PM PST 24
Peak memory 214220 kb
Host smart-7d77b648-18e5-4494-93de-a55adde6d341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464976106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1464976106
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2334291382
Short name T870
Test name
Test status
Simulation time 235267607 ps
CPU time 25.34 seconds
Started Feb 04 01:15:49 PM PST 24
Finished Feb 04 01:16:19 PM PST 24
Peak memory 246500 kb
Host smart-edeecbd4-1f37-4cc6-8515-3c8fcfe1e81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334291382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2334291382
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2179462357
Short name T525
Test name
Test status
Simulation time 80739728 ps
CPU time 7.77 seconds
Started Feb 04 01:15:57 PM PST 24
Finished Feb 04 01:16:09 PM PST 24
Peak memory 250936 kb
Host smart-0ad36dd2-59b0-4732-9a38-7df222bcb53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179462357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2179462357
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1340279812
Short name T468
Test name
Test status
Simulation time 3562851394 ps
CPU time 78.01 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:17:11 PM PST 24
Peak memory 274864 kb
Host smart-ae516ba8-c558-4c17-8836-ae70b8f2be4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340279812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1340279812
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2914231039
Short name T37
Test name
Test status
Simulation time 153348824 ps
CPU time 0.75 seconds
Started Feb 04 01:16:00 PM PST 24
Finished Feb 04 01:16:03 PM PST 24
Peak memory 208204 kb
Host smart-cd0891d0-862c-4f2a-9796-2cf38017bb45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914231039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2914231039
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3024373688
Short name T792
Test name
Test status
Simulation time 16964598 ps
CPU time 0.93 seconds
Started Feb 04 01:16:06 PM PST 24
Finished Feb 04 01:16:08 PM PST 24
Peak memory 209312 kb
Host smart-8a9642b6-69ed-4892-b123-ea19d11ad327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024373688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3024373688
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.956185378
Short name T670
Test name
Test status
Simulation time 1398505839 ps
CPU time 11.62 seconds
Started Feb 04 01:15:54 PM PST 24
Finished Feb 04 01:16:12 PM PST 24
Peak memory 217848 kb
Host smart-33ad0bb7-769c-41de-80d7-5347789f0723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956185378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.956185378
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.341898266
Short name T583
Test name
Test status
Simulation time 3327510327 ps
CPU time 6.79 seconds
Started Feb 04 01:16:05 PM PST 24
Finished Feb 04 01:16:13 PM PST 24
Peak memory 209516 kb
Host smart-846344ad-bb49-43a8-b554-df4c9920ce95
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341898266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_ac
cess.341898266
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.4222823323
Short name T467
Test name
Test status
Simulation time 319965128 ps
CPU time 3.36 seconds
Started Feb 04 01:15:56 PM PST 24
Finished Feb 04 01:16:05 PM PST 24
Peak memory 217820 kb
Host smart-b5fff007-7fe9-4594-9aaa-2598d4735e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222823323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.4222823323
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2565587739
Short name T458
Test name
Test status
Simulation time 338688219 ps
CPU time 10.26 seconds
Started Feb 04 01:16:04 PM PST 24
Finished Feb 04 01:16:17 PM PST 24
Peak memory 217864 kb
Host smart-1c646840-f83e-4318-911d-8b262aecb034
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565587739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2565587739
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2939559066
Short name T799
Test name
Test status
Simulation time 912982210 ps
CPU time 7.69 seconds
Started Feb 04 01:16:03 PM PST 24
Finished Feb 04 01:16:13 PM PST 24
Peak memory 217832 kb
Host smart-3516f4c2-cf53-4e51-842d-3dd3e092e1a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939559066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2939559066
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2092033089
Short name T455
Test name
Test status
Simulation time 364436683 ps
CPU time 6.42 seconds
Started Feb 04 01:16:04 PM PST 24
Finished Feb 04 01:16:12 PM PST 24
Peak memory 217816 kb
Host smart-d8ef358d-c0be-48a7-8768-b61e2a59e555
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092033089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2092033089
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.415809710
Short name T640
Test name
Test status
Simulation time 1119969146 ps
CPU time 8.35 seconds
Started Feb 04 01:16:05 PM PST 24
Finished Feb 04 01:16:15 PM PST 24
Peak memory 217840 kb
Host smart-9b0252ff-6a6b-4a4f-91a9-78ba1ec88fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415809710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.415809710
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1068166684
Short name T698
Test name
Test status
Simulation time 146117732 ps
CPU time 2.07 seconds
Started Feb 04 01:15:50 PM PST 24
Finished Feb 04 01:15:56 PM PST 24
Peak memory 213744 kb
Host smart-98611287-f225-4e90-a1b2-dea1a4c2f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068166684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1068166684
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.577730492
Short name T708
Test name
Test status
Simulation time 381938024 ps
CPU time 19.96 seconds
Started Feb 04 01:15:47 PM PST 24
Finished Feb 04 01:16:12 PM PST 24
Peak memory 250928 kb
Host smart-402c319f-085c-419b-a59e-025c2c3c3cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577730492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.577730492
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2230759089
Short name T360
Test name
Test status
Simulation time 165176277 ps
CPU time 6.44 seconds
Started Feb 04 01:15:51 PM PST 24
Finished Feb 04 01:16:06 PM PST 24
Peak memory 245712 kb
Host smart-3de79dcf-2a2b-41c5-963c-80f5eb3f8307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230759089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2230759089
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2889963676
Short name T662
Test name
Test status
Simulation time 17744918700 ps
CPU time 214.32 seconds
Started Feb 04 01:16:02 PM PST 24
Finished Feb 04 01:19:38 PM PST 24
Peak memory 259140 kb
Host smart-07c7c340-512e-434d-91ff-ba15747326df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889963676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2889963676
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3113810596
Short name T617
Test name
Test status
Simulation time 18701720 ps
CPU time 0.89 seconds
Started Feb 04 01:16:03 PM PST 24
Finished Feb 04 01:16:06 PM PST 24
Peak memory 208168 kb
Host smart-5483010a-9012-4893-9e3b-685813f890d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113810596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3113810596
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1074827005
Short name T745
Test name
Test status
Simulation time 52803933 ps
CPU time 0.99 seconds
Started Feb 04 01:13:19 PM PST 24
Finished Feb 04 01:13:22 PM PST 24
Peak memory 209396 kb
Host smart-abd88221-3750-4fd8-981f-74f17d93debf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074827005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1074827005
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3377437074
Short name T378
Test name
Test status
Simulation time 24849185 ps
CPU time 0.82 seconds
Started Feb 04 01:13:21 PM PST 24
Finished Feb 04 01:13:24 PM PST 24
Peak memory 207936 kb
Host smart-a69028d3-64b8-4a6d-b452-7ab3d99e0025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377437074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3377437074
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.201925650
Short name T432
Test name
Test status
Simulation time 4258198785 ps
CPU time 8.27 seconds
Started Feb 04 01:13:28 PM PST 24
Finished Feb 04 01:13:40 PM PST 24
Peak memory 217864 kb
Host smart-450833ea-3ecf-44f9-873f-34443d4f3968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201925650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.201925650
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2507214665
Short name T24
Test name
Test status
Simulation time 1941047730 ps
CPU time 12.1 seconds
Started Feb 04 01:13:19 PM PST 24
Finished Feb 04 01:13:33 PM PST 24
Peak memory 209440 kb
Host smart-3af80705-1c7d-4b5c-894e-09314ce265c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507214665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ac
cess.2507214665
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2748220673
Short name T861
Test name
Test status
Simulation time 2325651005 ps
CPU time 19.74 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:43 PM PST 24
Peak memory 217852 kb
Host smart-775d5b9e-8c73-4699-8d1e-3892c51c6fd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748220673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2748220673
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1543583200
Short name T678
Test name
Test status
Simulation time 1166499398 ps
CPU time 6.11 seconds
Started Feb 04 01:13:24 PM PST 24
Finished Feb 04 01:13:37 PM PST 24
Peak memory 209520 kb
Host smart-7bab6f4b-3b90-4674-8662-e09557b85f98
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543583200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.1543583200
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3172449191
Short name T323
Test name
Test status
Simulation time 1180103637 ps
CPU time 15.79 seconds
Started Feb 04 01:13:30 PM PST 24
Finished Feb 04 01:13:48 PM PST 24
Peak memory 217740 kb
Host smart-78106f34-9e20-42f8-9b3d-e4396233ff67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172449191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3172449191
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.418979032
Short name T119
Test name
Test status
Simulation time 3030772281 ps
CPU time 9.67 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:13:31 PM PST 24
Peak memory 213060 kb
Host smart-58de59e9-9c96-4d85-9a7b-0b4b4fa987c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418979032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.418979032
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1514522027
Short name T524
Test name
Test status
Simulation time 770284865 ps
CPU time 9.7 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:33 PM PST 24
Peak memory 213148 kb
Host smart-03e17621-d0ed-4483-9ce2-a6d2d682f1fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514522027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1514522027
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.4029531107
Short name T892
Test name
Test status
Simulation time 1312921275 ps
CPU time 42.62 seconds
Started Feb 04 01:13:24 PM PST 24
Finished Feb 04 01:14:13 PM PST 24
Peak memory 267176 kb
Host smart-e1c16600-761c-41b5-a64c-32afea35bd18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029531107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.4029531107
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3654051854
Short name T515
Test name
Test status
Simulation time 443130062 ps
CPU time 10.77 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:13:33 PM PST 24
Peak memory 246664 kb
Host smart-40d0de05-3408-4b6a-aced-59d1ee0a3af7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654051854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3654051854
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.882890877
Short name T807
Test name
Test status
Simulation time 33524722 ps
CPU time 1.86 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:25 PM PST 24
Peak memory 217924 kb
Host smart-efa7f9c5-5322-438e-aba6-2c132297d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882890877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.882890877
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2643132913
Short name T522
Test name
Test status
Simulation time 778913160 ps
CPU time 10.13 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:13:32 PM PST 24
Peak memory 214104 kb
Host smart-ec4d6a88-2388-48f9-b423-4bad3fcb6aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643132913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2643132913
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1527664669
Short name T888
Test name
Test status
Simulation time 297711720 ps
CPU time 13.98 seconds
Started Feb 04 01:13:31 PM PST 24
Finished Feb 04 01:13:46 PM PST 24
Peak memory 218824 kb
Host smart-aa7f5d9b-7e7a-4ef9-a848-cc8291af7312
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527664669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1527664669
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3654907569
Short name T601
Test name
Test status
Simulation time 1704942125 ps
CPU time 12.09 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:13:34 PM PST 24
Peak memory 217868 kb
Host smart-d1a7dff6-2244-4358-966d-25ae2dd4b314
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654907569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3654907569
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.641781898
Short name T463
Test name
Test status
Simulation time 3081873428 ps
CPU time 7.85 seconds
Started Feb 04 01:13:24 PM PST 24
Finished Feb 04 01:13:39 PM PST 24
Peak memory 217912 kb
Host smart-9ff4c30e-96c4-450b-81a1-34d2a938781c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641781898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.641781898
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1172960950
Short name T587
Test name
Test status
Simulation time 444616559 ps
CPU time 6.31 seconds
Started Feb 04 01:13:24 PM PST 24
Finished Feb 04 01:13:37 PM PST 24
Peak memory 217840 kb
Host smart-f2b2ef91-3a99-4306-8812-c6a78151d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172960950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1172960950
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3384410444
Short name T429
Test name
Test status
Simulation time 164490136 ps
CPU time 3.02 seconds
Started Feb 04 01:13:11 PM PST 24
Finished Feb 04 01:13:16 PM PST 24
Peak memory 214120 kb
Host smart-d70cc17d-1306-4596-893c-fa0da0ded599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384410444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3384410444
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.614533309
Short name T706
Test name
Test status
Simulation time 588701612 ps
CPU time 28.51 seconds
Started Feb 04 01:13:15 PM PST 24
Finished Feb 04 01:13:45 PM PST 24
Peak memory 250840 kb
Host smart-c0fb90ed-564e-4bb4-8611-5705bce7fd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614533309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.614533309
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4182712591
Short name T545
Test name
Test status
Simulation time 57910416 ps
CPU time 3.12 seconds
Started Feb 04 01:13:09 PM PST 24
Finished Feb 04 01:13:15 PM PST 24
Peak memory 221888 kb
Host smart-edc031f2-e3da-4b6d-9516-ee334c018066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182712591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4182712591
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3669137987
Short name T408
Test name
Test status
Simulation time 1733361879 ps
CPU time 27.56 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:13:49 PM PST 24
Peak memory 217788 kb
Host smart-4f440964-63cc-4d67-bcf5-48613047dc48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669137987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3669137987
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3520401260
Short name T38
Test name
Test status
Simulation time 13941984 ps
CPU time 0.97 seconds
Started Feb 04 01:13:13 PM PST 24
Finished Feb 04 01:13:16 PM PST 24
Peak memory 208264 kb
Host smart-fb701893-e34e-47f3-945e-91d46e281253
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520401260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3520401260
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2459065966
Short name T474
Test name
Test status
Simulation time 50412268 ps
CPU time 1 seconds
Started Feb 04 01:13:23 PM PST 24
Finished Feb 04 01:13:31 PM PST 24
Peak memory 208024 kb
Host smart-4635b16b-de27-4eef-bec1-9e51057f800f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459065966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2459065966
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.4052049182
Short name T192
Test name
Test status
Simulation time 18687049 ps
CPU time 0.78 seconds
Started Feb 04 01:13:29 PM PST 24
Finished Feb 04 01:13:32 PM PST 24
Peak memory 209156 kb
Host smart-7fa1c80b-ef25-4a11-bb3d-2842160c7996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052049182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.4052049182
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4028533701
Short name T42
Test name
Test status
Simulation time 352593847 ps
CPU time 16.03 seconds
Started Feb 04 01:13:23 PM PST 24
Finished Feb 04 01:13:46 PM PST 24
Peak memory 217864 kb
Host smart-b1aa428e-ee9a-4ac9-9de8-75deca1aa2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028533701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4028533701
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1495438138
Short name T654
Test name
Test status
Simulation time 759767791 ps
CPU time 2.47 seconds
Started Feb 04 01:13:19 PM PST 24
Finished Feb 04 01:13:23 PM PST 24
Peak memory 209476 kb
Host smart-5696ea79-9704-4837-aff1-90f0ca97a398
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495438138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.1495438138
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.860044937
Short name T475
Test name
Test status
Simulation time 2869296034 ps
CPU time 32.2 seconds
Started Feb 04 01:13:25 PM PST 24
Finished Feb 04 01:14:03 PM PST 24
Peak memory 217816 kb
Host smart-916946e0-fbef-4f1c-a6d8-751af676f813
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860044937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.860044937
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2284038355
Short name T686
Test name
Test status
Simulation time 2658470243 ps
CPU time 6 seconds
Started Feb 04 01:13:24 PM PST 24
Finished Feb 04 01:13:37 PM PST 24
Peak memory 209592 kb
Host smart-64fe9899-5e83-4ff6-b9a8-188e898295b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284038355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.2284038355
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.518281443
Short name T913
Test name
Test status
Simulation time 1298728091 ps
CPU time 17 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:40 PM PST 24
Peak memory 217772 kb
Host smart-13049353-b9b6-486e-99b3-4f3b2626f99a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518281443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.518281443
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3963508272
Short name T956
Test name
Test status
Simulation time 809974540 ps
CPU time 12.98 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:13:35 PM PST 24
Peak memory 212736 kb
Host smart-5f4afbb9-fcfc-4bac-9855-d7a0d24a6e85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963508272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3963508272
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3263411424
Short name T387
Test name
Test status
Simulation time 406438003 ps
CPU time 9.03 seconds
Started Feb 04 01:13:21 PM PST 24
Finished Feb 04 01:13:32 PM PST 24
Peak memory 213200 kb
Host smart-56af39a3-6185-4a7c-a569-05f113a7dd6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263411424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3263411424
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.351821887
Short name T944
Test name
Test status
Simulation time 1673231179 ps
CPU time 70.31 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:14:32 PM PST 24
Peak memory 275436 kb
Host smart-b9c0ddf5-69db-4822-9e38-7419c0effbcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351821887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.351821887
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2604866471
Short name T843
Test name
Test status
Simulation time 1670195353 ps
CPU time 12.71 seconds
Started Feb 04 01:13:25 PM PST 24
Finished Feb 04 01:13:44 PM PST 24
Peak memory 250788 kb
Host smart-9ee1578c-7137-437f-b046-a86b51478637
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604866471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2604866471
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2550718778
Short name T322
Test name
Test status
Simulation time 168502643 ps
CPU time 4.18 seconds
Started Feb 04 01:13:23 PM PST 24
Finished Feb 04 01:13:34 PM PST 24
Peak memory 217732 kb
Host smart-3a572c66-1df6-4146-b882-825a01ff730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550718778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2550718778
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3527431527
Short name T695
Test name
Test status
Simulation time 215028257 ps
CPU time 14.54 seconds
Started Feb 04 01:13:23 PM PST 24
Finished Feb 04 01:13:44 PM PST 24
Peak memory 213424 kb
Host smart-9cafbe63-7851-4909-85f4-c3dab276e365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527431527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3527431527
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4131759091
Short name T933
Test name
Test status
Simulation time 702431449 ps
CPU time 14.22 seconds
Started Feb 04 01:13:21 PM PST 24
Finished Feb 04 01:13:37 PM PST 24
Peak memory 217860 kb
Host smart-e76892b0-eaa7-463c-ab79-78144c187bc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131759091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4131759091
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4105723968
Short name T719
Test name
Test status
Simulation time 6755316498 ps
CPU time 12.14 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:13:35 PM PST 24
Peak memory 217932 kb
Host smart-dd40157a-dc4a-4dcd-8b8f-bcc44c03f91b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105723968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4105723968
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3661315139
Short name T579
Test name
Test status
Simulation time 1220306547 ps
CPU time 7.24 seconds
Started Feb 04 01:13:21 PM PST 24
Finished Feb 04 01:13:30 PM PST 24
Peak memory 217828 kb
Host smart-52bd339b-4cfa-475f-873f-89b441a82a7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661315139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
661315139
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3611087334
Short name T962
Test name
Test status
Simulation time 486122976 ps
CPU time 10.49 seconds
Started Feb 04 01:13:19 PM PST 24
Finished Feb 04 01:13:31 PM PST 24
Peak memory 217848 kb
Host smart-4ce48e41-95f9-4e79-bbf8-3b77325c97e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611087334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3611087334
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3337075836
Short name T556
Test name
Test status
Simulation time 60980308 ps
CPU time 1.52 seconds
Started Feb 04 01:13:20 PM PST 24
Finished Feb 04 01:13:24 PM PST 24
Peak memory 213152 kb
Host smart-7f84d735-e104-4105-8898-89ac61210476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337075836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3337075836
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3779954454
Short name T835
Test name
Test status
Simulation time 1034838280 ps
CPU time 19.45 seconds
Started Feb 04 01:13:24 PM PST 24
Finished Feb 04 01:13:51 PM PST 24
Peak memory 250820 kb
Host smart-7f69ded5-5c6f-4c8f-88e8-97fa44cdd06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779954454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3779954454
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.902657480
Short name T808
Test name
Test status
Simulation time 280190947 ps
CPU time 9.29 seconds
Started Feb 04 01:13:24 PM PST 24
Finished Feb 04 01:13:40 PM PST 24
Peak memory 250904 kb
Host smart-b63826f0-0923-4fcd-80ef-7fd8aa30303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902657480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.902657480
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3858934048
Short name T975
Test name
Test status
Simulation time 4112207860 ps
CPU time 92.69 seconds
Started Feb 04 01:13:23 PM PST 24
Finished Feb 04 01:14:57 PM PST 24
Peak memory 273852 kb
Host smart-70a29723-76e8-404d-b8a8-2ff4ac04c4d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858934048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3858934048
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4141231195
Short name T563
Test name
Test status
Simulation time 14476799 ps
CPU time 0.98 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:25 PM PST 24
Peak memory 208192 kb
Host smart-733b17e6-c62b-4f99-a06c-ae6a6d3f8986
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141231195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4141231195
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.254531421
Short name T491
Test name
Test status
Simulation time 109814646 ps
CPU time 1.01 seconds
Started Feb 04 01:13:36 PM PST 24
Finished Feb 04 01:13:38 PM PST 24
Peak memory 208232 kb
Host smart-a2d36602-122c-461e-b51e-ec5cb0f25944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254531421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.254531421
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2397651545
Short name T521
Test name
Test status
Simulation time 364673582 ps
CPU time 15.95 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:39 PM PST 24
Peak memory 217832 kb
Host smart-0e828f1f-3035-4a95-a02e-268ad20a09f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397651545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2397651545
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1317289532
Short name T30
Test name
Test status
Simulation time 1440697958 ps
CPU time 7.29 seconds
Started Feb 04 01:13:19 PM PST 24
Finished Feb 04 01:13:28 PM PST 24
Peak memory 209428 kb
Host smart-c7ff6ce6-83f0-4462-8fb3-3954189867f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317289532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.1317289532
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2825040032
Short name T44
Test name
Test status
Simulation time 2085166994 ps
CPU time 28.57 seconds
Started Feb 04 01:13:25 PM PST 24
Finished Feb 04 01:14:00 PM PST 24
Peak memory 217772 kb
Host smart-944f94e4-4104-4013-a0d4-0f06568fc13a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825040032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2825040032
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3811075370
Short name T401
Test name
Test status
Simulation time 138816368 ps
CPU time 2.2 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:49 PM PST 24
Peak memory 209528 kb
Host smart-67bd7c6d-2dfd-434e-8d6c-4f3a7ca2440c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811075370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.3811075370
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1507419030
Short name T560
Test name
Test status
Simulation time 181935248 ps
CPU time 5.65 seconds
Started Feb 04 01:13:25 PM PST 24
Finished Feb 04 01:13:37 PM PST 24
Peak memory 217776 kb
Host smart-01c5009f-d15a-4aa3-9ad4-851b9814f676
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507419030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1507419030
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1187192590
Short name T380
Test name
Test status
Simulation time 1122187138 ps
CPU time 33.44 seconds
Started Feb 04 01:13:46 PM PST 24
Finished Feb 04 01:14:22 PM PST 24
Peak memory 212932 kb
Host smart-5e713df9-4f3c-4ba1-9a53-4c466c793cd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187192590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1187192590
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.939689417
Short name T784
Test name
Test status
Simulation time 373370596 ps
CPU time 8.83 seconds
Started Feb 04 01:13:26 PM PST 24
Finished Feb 04 01:13:40 PM PST 24
Peak memory 212844 kb
Host smart-4323dc8c-a0bf-49c1-b5b0-f07bb571c3bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939689417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.939689417
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1492513286
Short name T481
Test name
Test status
Simulation time 1460877317 ps
CPU time 64.14 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:14:28 PM PST 24
Peak memory 250752 kb
Host smart-dcc2b2e1-1d06-406c-8f22-a31b53a0dda3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492513286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1492513286
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2937920176
Short name T384
Test name
Test status
Simulation time 1505642304 ps
CPU time 16.97 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:41 PM PST 24
Peak memory 250860 kb
Host smart-eefb6581-28ba-4c6d-9517-a72e11942e72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937920176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2937920176
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2480089547
Short name T541
Test name
Test status
Simulation time 361591257 ps
CPU time 3.87 seconds
Started Feb 04 01:13:23 PM PST 24
Finished Feb 04 01:13:28 PM PST 24
Peak memory 217868 kb
Host smart-beda22c4-319a-4779-9b26-7a9f745aa269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480089547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2480089547
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3027240051
Short name T117
Test name
Test status
Simulation time 311831702 ps
CPU time 7.32 seconds
Started Feb 04 01:13:24 PM PST 24
Finished Feb 04 01:13:38 PM PST 24
Peak memory 213976 kb
Host smart-7b7adec2-d5b9-4c3c-abf6-2ec160c646e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027240051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3027240051
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2026267337
Short name T960
Test name
Test status
Simulation time 1939206966 ps
CPU time 18.42 seconds
Started Feb 04 01:13:42 PM PST 24
Finished Feb 04 01:14:05 PM PST 24
Peak memory 218840 kb
Host smart-b4198f98-b936-4865-a51b-a1c01624f027
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026267337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2026267337
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1680443948
Short name T347
Test name
Test status
Simulation time 336825235 ps
CPU time 12.4 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:58 PM PST 24
Peak memory 217860 kb
Host smart-2673b93f-44e2-4963-b127-6dff09f7140b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680443948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1680443948
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2083580959
Short name T555
Test name
Test status
Simulation time 316127976 ps
CPU time 12.32 seconds
Started Feb 04 01:13:44 PM PST 24
Finished Feb 04 01:13:59 PM PST 24
Peak memory 217772 kb
Host smart-0c99c78a-8171-442f-bf01-68c73557f045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083580959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
083580959
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2666143112
Short name T350
Test name
Test status
Simulation time 444068618 ps
CPU time 8.49 seconds
Started Feb 04 01:13:25 PM PST 24
Finished Feb 04 01:13:40 PM PST 24
Peak memory 217816 kb
Host smart-c0328794-2fd3-4227-b49b-bc8107cdce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666143112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2666143112
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.881420675
Short name T340
Test name
Test status
Simulation time 28042296 ps
CPU time 0.97 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:25 PM PST 24
Peak memory 211592 kb
Host smart-8a62115c-1b63-4a9e-abee-992a107bdc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881420675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.881420675
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2366069557
Short name T763
Test name
Test status
Simulation time 968516329 ps
CPU time 27.01 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:51 PM PST 24
Peak memory 250856 kb
Host smart-ff1d53cf-3e66-40d1-8957-4e0f43743d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366069557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2366069557
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3215666986
Short name T677
Test name
Test status
Simulation time 43388024 ps
CPU time 2.62 seconds
Started Feb 04 01:13:22 PM PST 24
Finished Feb 04 01:13:26 PM PST 24
Peak memory 221492 kb
Host smart-0a326405-2976-4e08-83c5-019917205256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215666986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3215666986
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1525174555
Short name T876
Test name
Test status
Simulation time 32798981 ps
CPU time 1.08 seconds
Started Feb 04 01:13:23 PM PST 24
Finished Feb 04 01:13:25 PM PST 24
Peak memory 212872 kb
Host smart-25bffb65-8943-4fbe-a95d-aaef6c9f5f67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525174555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1525174555
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3203094080
Short name T753
Test name
Test status
Simulation time 12892571 ps
CPU time 0.83 seconds
Started Feb 04 01:13:39 PM PST 24
Finished Feb 04 01:13:41 PM PST 24
Peak memory 209216 kb
Host smart-b104547a-a118-4504-8d64-0fffb517d4a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203094080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3203094080
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3613725119
Short name T312
Test name
Test status
Simulation time 59900406 ps
CPU time 0.74 seconds
Started Feb 04 01:13:38 PM PST 24
Finished Feb 04 01:13:40 PM PST 24
Peak memory 209144 kb
Host smart-3cde5b41-5eea-4fea-b4b9-2c79c9ae82a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613725119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3613725119
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1929296794
Short name T472
Test name
Test status
Simulation time 560685456 ps
CPU time 12.89 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:59 PM PST 24
Peak memory 217864 kb
Host smart-dcd4ca26-ef4d-4766-a332-30a2b710d446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929296794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1929296794
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1796523639
Short name T483
Test name
Test status
Simulation time 294973837 ps
CPU time 7.86 seconds
Started Feb 04 01:13:39 PM PST 24
Finished Feb 04 01:13:52 PM PST 24
Peak memory 209472 kb
Host smart-34e080e9-7140-4390-83e1-b047ae4ee018
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796523639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.1796523639
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3427024555
Short name T551
Test name
Test status
Simulation time 3127726719 ps
CPU time 34.68 seconds
Started Feb 04 01:13:39 PM PST 24
Finished Feb 04 01:14:15 PM PST 24
Peak memory 218952 kb
Host smart-ab02fafd-ab9a-44e1-b3cc-b965d35297f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427024555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3427024555
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3211236889
Short name T426
Test name
Test status
Simulation time 156631253 ps
CPU time 4.58 seconds
Started Feb 04 01:13:39 PM PST 24
Finished Feb 04 01:13:50 PM PST 24
Peak memory 209492 kb
Host smart-95d202c4-1c1d-45eb-a1b1-75f2241f377c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211236889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.3211236889
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1289504844
Short name T971
Test name
Test status
Simulation time 117596572 ps
CPU time 3.94 seconds
Started Feb 04 01:13:37 PM PST 24
Finished Feb 04 01:13:43 PM PST 24
Peak memory 217852 kb
Host smart-4df61345-aab6-4858-afd7-16d5f747f6b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289504844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1289504844
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3805170972
Short name T337
Test name
Test status
Simulation time 5537879017 ps
CPU time 17.76 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:14:04 PM PST 24
Peak memory 213572 kb
Host smart-bf21ba35-521a-4dac-b7f9-878b7a22d410
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805170972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3805170972
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1693678552
Short name T895
Test name
Test status
Simulation time 637983837 ps
CPU time 8.44 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:54 PM PST 24
Peak memory 212728 kb
Host smart-7d267ab2-04e8-46f6-98be-2f8cefb4ed04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693678552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1693678552
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2528825493
Short name T490
Test name
Test status
Simulation time 549962010 ps
CPU time 5.96 seconds
Started Feb 04 01:13:37 PM PST 24
Finished Feb 04 01:13:45 PM PST 24
Peak memory 217808 kb
Host smart-7a8135eb-5247-4e31-b65e-fef1f0b5717a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528825493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2528825493
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3974957515
Short name T964
Test name
Test status
Simulation time 256903624 ps
CPU time 2.63 seconds
Started Feb 04 01:13:37 PM PST 24
Finished Feb 04 01:13:41 PM PST 24
Peak memory 217828 kb
Host smart-f316495e-178b-46b1-a65f-45aa330df54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974957515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3974957515
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1222077125
Short name T71
Test name
Test status
Simulation time 802562561 ps
CPU time 11.99 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:58 PM PST 24
Peak memory 213912 kb
Host smart-1887df72-8ff0-4c75-9996-6ce70495ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222077125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1222077125
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.107320072
Short name T602
Test name
Test status
Simulation time 1002262526 ps
CPU time 11.6 seconds
Started Feb 04 01:13:36 PM PST 24
Finished Feb 04 01:13:50 PM PST 24
Peak memory 218856 kb
Host smart-68f729db-2f39-41e0-942c-0f1825255c3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107320072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.107320072
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2272601478
Short name T907
Test name
Test status
Simulation time 324549805 ps
CPU time 8.82 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:55 PM PST 24
Peak memory 217836 kb
Host smart-76eff03d-4e8a-4992-90e4-e272102e6324
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272601478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2272601478
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.687145761
Short name T332
Test name
Test status
Simulation time 1429357316 ps
CPU time 8.17 seconds
Started Feb 04 01:13:39 PM PST 24
Finished Feb 04 01:13:48 PM PST 24
Peak memory 217856 kb
Host smart-f7e78f25-f7af-4802-968f-357457e91ff9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687145761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.687145761
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.4145935844
Short name T700
Test name
Test status
Simulation time 309520213 ps
CPU time 6.55 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:53 PM PST 24
Peak memory 217816 kb
Host smart-5db2f58a-5dd8-4e57-aba4-c1483bf7c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145935844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.4145935844
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.873653114
Short name T718
Test name
Test status
Simulation time 78676219 ps
CPU time 4.72 seconds
Started Feb 04 01:13:42 PM PST 24
Finished Feb 04 01:13:51 PM PST 24
Peak memory 214068 kb
Host smart-18197978-a0f8-467d-a3fb-8d4e0f61fab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873653114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.873653114
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2278625473
Short name T773
Test name
Test status
Simulation time 192317517 ps
CPU time 19.85 seconds
Started Feb 04 01:13:35 PM PST 24
Finished Feb 04 01:13:56 PM PST 24
Peak memory 250888 kb
Host smart-956e6d07-2a94-47e2-ae93-ada31154dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278625473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2278625473
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2238682289
Short name T580
Test name
Test status
Simulation time 78743309 ps
CPU time 9.53 seconds
Started Feb 04 01:13:37 PM PST 24
Finished Feb 04 01:13:48 PM PST 24
Peak memory 250880 kb
Host smart-4b4a59c1-24f1-4f52-8a9c-c942af0d55ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238682289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2238682289
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.255633832
Short name T828
Test name
Test status
Simulation time 10969405702 ps
CPU time 86.87 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:15:13 PM PST 24
Peak memory 250952 kb
Host smart-306e4aee-9a12-47aa-8536-6ea3d937d1c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255633832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.255633832
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.72832470
Short name T917
Test name
Test status
Simulation time 18613339 ps
CPU time 0.77 seconds
Started Feb 04 01:13:45 PM PST 24
Finished Feb 04 01:13:48 PM PST 24
Peak memory 208052 kb
Host smart-bf87287c-c574-4a7c-bd94-de7b4d6ab5f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72832470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_volatile_unlock_smoke.72832470
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2399761039
Short name T734
Test name
Test status
Simulation time 19113139 ps
CPU time 0.97 seconds
Started Feb 04 01:13:48 PM PST 24
Finished Feb 04 01:13:50 PM PST 24
Peak memory 208100 kb
Host smart-b484927f-cd47-4dd8-a21d-e0768650ecd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399761039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2399761039
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.50977100
Short name T445
Test name
Test status
Simulation time 30402921 ps
CPU time 0.77 seconds
Started Feb 04 01:13:48 PM PST 24
Finished Feb 04 01:13:50 PM PST 24
Peak memory 209164 kb
Host smart-cefcb055-c327-4b2e-b2f0-b709c83a5eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50977100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.50977100
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3134977634
Short name T56
Test name
Test status
Simulation time 575759926 ps
CPU time 10.89 seconds
Started Feb 04 01:13:37 PM PST 24
Finished Feb 04 01:13:50 PM PST 24
Peak memory 217824 kb
Host smart-c04858bd-44f5-4161-b4cf-f00786c9e08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134977634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3134977634
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.71575711
Short name T26
Test name
Test status
Simulation time 542753240 ps
CPU time 3.86 seconds
Started Feb 04 01:13:42 PM PST 24
Finished Feb 04 01:13:51 PM PST 24
Peak memory 209396 kb
Host smart-6e9b83b0-a887-4720-a857-66b9502c83ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71575711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_acce
ss.71575711
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.861112075
Short name T881
Test name
Test status
Simulation time 9345400236 ps
CPU time 51.99 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:14:38 PM PST 24
Peak memory 218720 kb
Host smart-0feb1aac-d4b5-4cf0-8c5b-b3090c6e318b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861112075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.861112075
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3862169728
Short name T543
Test name
Test status
Simulation time 159424457 ps
CPU time 2.55 seconds
Started Feb 04 01:13:43 PM PST 24
Finished Feb 04 01:13:49 PM PST 24
Peak memory 209520 kb
Host smart-26e1d895-a453-4f13-9d85-2efc1a9b9a6b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862169728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
priority.3862169728
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3396876187
Short name T935
Test name
Test status
Simulation time 1162128108 ps
CPU time 6.12 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:52 PM PST 24
Peak memory 217728 kb
Host smart-18eb7d9e-7326-4367-bf78-67777e582495
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396876187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3396876187
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2297453132
Short name T643
Test name
Test status
Simulation time 2122582520 ps
CPU time 13.67 seconds
Started Feb 04 01:13:42 PM PST 24
Finished Feb 04 01:14:00 PM PST 24
Peak memory 212888 kb
Host smart-099dcf0d-381e-435c-a587-48a43214aecf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297453132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2297453132
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1622160368
Short name T959
Test name
Test status
Simulation time 795689692 ps
CPU time 19.58 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:14:06 PM PST 24
Peak memory 213544 kb
Host smart-5be4c500-5baa-407c-8d8b-3ae3ece741ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622160368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1622160368
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3973624334
Short name T136
Test name
Test status
Simulation time 7048999413 ps
CPU time 64 seconds
Started Feb 04 01:13:44 PM PST 24
Finished Feb 04 01:14:51 PM PST 24
Peak memory 267264 kb
Host smart-3b31f637-7c4b-4c12-9b19-cec00615155d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973624334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3973624334
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3101167585
Short name T502
Test name
Test status
Simulation time 1386224497 ps
CPU time 12.76 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:59 PM PST 24
Peak memory 250688 kb
Host smart-e691eb19-b359-4a43-be9f-45feb70f2dbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101167585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3101167585
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3941591410
Short name T741
Test name
Test status
Simulation time 230934917 ps
CPU time 2.06 seconds
Started Feb 04 01:13:38 PM PST 24
Finished Feb 04 01:13:41 PM PST 24
Peak memory 217824 kb
Host smart-60786fdd-b368-4cae-a55d-897d04031b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941591410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3941591410
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3171905947
Short name T616
Test name
Test status
Simulation time 1645020779 ps
CPU time 9.88 seconds
Started Feb 04 01:13:48 PM PST 24
Finished Feb 04 01:13:59 PM PST 24
Peak memory 214012 kb
Host smart-74aecb96-128c-43f0-8b56-3c335583abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171905947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3171905947
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1052441471
Short name T685
Test name
Test status
Simulation time 2440129888 ps
CPU time 11.1 seconds
Started Feb 04 01:13:40 PM PST 24
Finished Feb 04 01:13:57 PM PST 24
Peak memory 217876 kb
Host smart-bb4d30df-445b-46e2-b687-e511e99a56a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052441471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1052441471
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1690937651
Short name T705
Test name
Test status
Simulation time 1174717181 ps
CPU time 23.47 seconds
Started Feb 04 01:13:42 PM PST 24
Finished Feb 04 01:14:10 PM PST 24
Peak memory 217868 kb
Host smart-3cd7dee3-be62-4178-ade7-6358cea2c7ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690937651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1690937651
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.166293344
Short name T856
Test name
Test status
Simulation time 505305567 ps
CPU time 8.72 seconds
Started Feb 04 01:13:43 PM PST 24
Finished Feb 04 01:13:55 PM PST 24
Peak memory 217876 kb
Host smart-b8d3a368-41ba-45b3-8ac6-72c07c92af2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166293344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.166293344
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.953305771
Short name T970
Test name
Test status
Simulation time 214938265 ps
CPU time 8.06 seconds
Started Feb 04 01:13:38 PM PST 24
Finished Feb 04 01:13:47 PM PST 24
Peak memory 217868 kb
Host smart-f28061d6-318a-475f-99f6-58c38a2efe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953305771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.953305771
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3067409122
Short name T628
Test name
Test status
Simulation time 102204716 ps
CPU time 3.29 seconds
Started Feb 04 01:13:46 PM PST 24
Finished Feb 04 01:13:52 PM PST 24
Peak memory 213604 kb
Host smart-8bb3e8f0-3ed6-4e85-99f4-bc499367223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067409122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3067409122
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2029243661
Short name T200
Test name
Test status
Simulation time 254417844 ps
CPU time 21.78 seconds
Started Feb 04 01:13:38 PM PST 24
Finished Feb 04 01:14:01 PM PST 24
Peak memory 250804 kb
Host smart-b0811089-66b1-4e4d-9f7c-f1efb1050ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029243661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2029243661
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1562906701
Short name T659
Test name
Test status
Simulation time 154889515 ps
CPU time 7.42 seconds
Started Feb 04 01:13:39 PM PST 24
Finished Feb 04 01:13:47 PM PST 24
Peak memory 250864 kb
Host smart-0715c414-6a54-4450-a808-0e9fc365d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562906701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1562906701
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.538110214
Short name T766
Test name
Test status
Simulation time 11532195 ps
CPU time 0.9 seconds
Started Feb 04 01:13:42 PM PST 24
Finished Feb 04 01:13:48 PM PST 24
Peak memory 208116 kb
Host smart-aecbb5a2-f516-4e7b-81a3-37e9d6542173
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538110214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.538110214
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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