Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82197828

1

T1

1164

T2

32291

T3

25578

auto[1]

1392585

1

T4

1485

T5

10837

T13

7881

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82211273

1

T1

1164

T2

32291

T3

25578

auto[1]

1379140

1

T4

990

T5

9840

T13

7316

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6311792	1			T1	128		T2	8206		T3	7842
auto[IdleSt]	17108387	1			T1	103		T2	7901		T3	2860
auto[ClkMuxSt]	33007	1			T2	88		T3	86		T4	46
auto[CntIncrSt]	32766	1			T2	88		T3	86		T4	46
auto[CntProgSt]	1930060	1			T2	652		T3	172		T4	121
auto[TransCheckSt]	25423	1			T2	88		T3	86		T4	35
auto[TokenHashSt]	31607181	1			T2	1604		T3	893		T4	396
auto[FlashRmaSt]	24994	1			T2	70		T3	72		T4	34
auto[TokenCheck0St]	11336	1			T2	39		T3	33		T4	28
auto[TokenCheck1St]	8149	1			T2	15		T3	7		T4	17
auto[TransProgSt]	429535	1			T4	60		T5	60		T13	30
auto[PostTransSt]	10107852	1			T1	933		T2	13540		T3	13441
auto[ScrapSt]	154251	1			T13	3		T116	699		T117	617
auto[EscalateSt]	6176518	1			T4	3444		T5	67720		T13	11703
auto[InvalidSt]	9627451	1			T4	2403		T5	159870		T7	9877

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1711	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9627451	1			T4	2403		T5	159870		T7	9877
EscalateSt	6176518	1			T4	3444		T5	67720		T13	11703
ScrapSt	154251	1			T13	3		T116	699		T117	617
PostTransSt	10107852	1			T1	933		T2	13540		T3	13441
TransProgSt	429535	1			T4	60		T5	60		T13	30
TokenCheck1St	8149	1			T2	15		T3	7		T4	17
TokenCheck0St	11336	1			T2	39		T3	33		T4	28
FlashRmaSt	24994	1			T2	70		T3	72		T4	34
TokenHashSt	31607181	1			T2	1604		T3	893		T4	396
TransCheckSt	25423	1			T2	88		T3	86		T4	35
CntProgSt	1930060	1			T2	652		T3	172		T4	121
CntIncrSt	32766	1			T2	88		T3	86		T4	46
ClkMuxSt	33007	1			T2	88		T3	86		T4	46
IdleSt	17108387	1			T1	103		T2	7901		T3	2860
ResetSt	6311792	1			T1	128		T2	8206		T3	7842
arcs[ResetSt=>IdleSt]	49210	1			T1	1		T2	89		T3	87
arcs[IdleSt=>ScrapSt]	259	1			T13	1		T116	2		T117	2
arcs[IdleSt=>ClkMuxSt]	32839	1			T2	88		T3	86		T4	46
arcs[ClkMuxSt=>CntIncrSt]	32766	1			T2	88		T3	86		T4	46
arcs[CntIncrSt=>PostTransSt]	1660	1			T17	10		T20	13		T35	12
arcs[CntIncrSt=>CntProgSt]	31044	1			T2	88		T3	86		T4	46
arcs[CntProgSt=>PostTransSt]	4502	1			T4	11		T5	13		T17	11
arcs[CntProgSt=>TransCheckSt]	25423	1			T2	88		T3	86		T4	35
arcs[TransCheckSt=>PostTransSt]	3582	1			T2	42		T3	42		T17	6
arcs[TransCheckSt=>TokenHashSt]	21713	1			T2	46		T3	44		T4	35
arcs[TokenHashSt=>PostTransSt]	9528	1			T2	7		T3	11		T4	7
arcs[TokenHashSt=>FlashRmaSt]	11437	1			T2	39		T3	33		T4	28
arcs[FlashRmaSt=>TokenCheck0St]	11336	1			T2	39		T3	33		T4	28
arcs[TokenCheck0St=>PostTransSt]	3156	1			T2	24		T3	26		T4	11
arcs[TokenCheck0St=>TokenCheck1St]	8149	1			T2	15		T3	7		T4	17
arcs[TokenCheck1St=>PostTransSt]	612	1			T2	15		T3	7		T17	1
arcs[TransProgSt=>PostTransSt]	6618	1			T4	17		T5	30		T13	1
arcs[IdleSt=>EscalateSt]	187	1			T13	7		T16	5		T33	13
arcs[ClkMuxSt=>EscalateSt]	73	1			T13	2		T16	2		T47	2
arcs[CntIncrSt=>EscalateSt]	62	1			T47	2		T33	2		T59	2
arcs[CntProgSt=>EscalateSt]	1117	1			T13	24		T16	11		T47	13
arcs[TransCheckSt=>EscalateSt]	128	1			T16	10		T47	6		T33	1
arcs[TokenHashSt=>EscalateSt]	731	1			T13	1		T16	25		T47	39
arcs[FlashRmaSt=>EscalateSt]	101	1			T13	3		T16	1		T47	4
arcs[TokenCheck0St=>EscalateSt]	31	1			T47	2		T33	3		T63	1
arcs[TokenCheck1St=>EscalateSt]	153	1			T13	3		T16	2		T47	3
arcs[TransProgSt=>EscalateSt]	766	1			T13	13		T16	14		T47	14
arcs[PostTransSt=>EscalateSt]	4760	1			T4	11		T5	13		T13	1
arcs[InvalidSt=>EscalateSt]	13651	1			T4	14		T5	197		T7	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6311604	1			T1	128		T2	8206		T3	7842
auto[0]	auto[IdleSt]	17108270	1			T1	103		T2	7901		T3	2860
auto[0]	auto[ClkMuxSt]	32966	1			T2	88		T3	86		T4	46
auto[0]	auto[CntIncrSt]	32722	1			T2	88		T3	86		T4	46
auto[0]	auto[CntProgSt]	1929320	1			T2	652		T3	172		T4	121
auto[0]	auto[TransCheckSt]	25333	1			T2	88		T3	86		T4	35
auto[0]	auto[TokenHashSt]	31606686	1			T2	1604		T3	893		T4	396
auto[0]	auto[FlashRmaSt]	24929	1			T2	70		T3	72		T4	34
auto[0]	auto[TokenCheck0St]	11312	1			T2	39		T3	33		T4	28
auto[0]	auto[TokenCheck1St]	8047	1			T2	15		T3	7		T4	17
auto[0]	auto[TransProgSt]	429013	1			T4	60		T5	60		T13	19
auto[0]	auto[PostTransSt]	10105444	1			T1	933		T2	13540		T3	13441
auto[0]	auto[ScrapSt]	154204	1			T13	2		T116	699		T117	617
auto[0]	auto[EscalateSt]	4795674	1			T4	1974		T5	56993		T13	3862
auto[0]	auto[InvalidSt]	9620593	1			T4	2395		T5	159765		T7	9874
auto[1]	auto[ResetSt]	188	1			T13	4		T16	2		T47	2
auto[1]	auto[IdleSt]	117	1			T13	5		T16	3		T33	6
auto[1]	auto[ClkMuxSt]	41	1			T13	2		T16	2		T47	1
auto[1]	auto[CntIncrSt]	44	1			T47	2		T33	1		T59	2
auto[1]	auto[CntProgSt]	740	1			T13	11		T16	7		T47	8
auto[1]	auto[TransCheckSt]	90	1			T16	9		T47	6		T33	1
auto[1]	auto[TokenHashSt]	495	1			T13	1		T16	18		T47	26
auto[1]	auto[FlashRmaSt]	65	1			T13	2		T16	1		T47	3
auto[1]	auto[TokenCheck0St]	24	1			T47	2		T33	2		T63	1
auto[1]	auto[TokenCheck1St]	102	1			T13	2		T16	1		T47	2
auto[1]	auto[TransProgSt]	522	1			T13	11		T16	12		T47	10
auto[1]	auto[PostTransSt]	2408	1			T4	7		T5	5		T13	1
auto[1]	auto[ScrapSt]	47	1			T13	1		T47	1		T33	2
auto[1]	auto[EscalateSt]	1380844	1			T4	1470		T5	10727		T13	7841
auto[1]	auto[InvalidSt]	6858	1			T4	8		T5	105		T7	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6311616	1			T1	128		T2	8206		T3	7842
auto[0]	auto[IdleSt]	17108252	1			T1	103		T2	7901		T3	2860
auto[0]	auto[ClkMuxSt]	32955	1			T2	88		T3	86		T4	46
auto[0]	auto[CntIncrSt]	32728	1			T2	88		T3	86		T4	46
auto[0]	auto[CntProgSt]	1929345	1			T2	652		T3	172		T4	121
auto[0]	auto[TransCheckSt]	25346	1			T2	88		T3	86		T4	35
auto[0]	auto[TokenHashSt]	31606688	1			T2	1604		T3	893		T4	396
auto[0]	auto[FlashRmaSt]	24925	1			T2	70		T3	72		T4	34
auto[0]	auto[TokenCheck0St]	11315	1			T2	39		T3	33		T4	28
auto[0]	auto[TokenCheck1St]	8055	1			T2	15		T3	7		T4	17
auto[0]	auto[TransProgSt]	429014	1			T4	60		T5	60		T13	23
auto[0]	auto[PostTransSt]	10105429	1			T1	933		T2	13540		T3	13441
auto[0]	auto[ScrapSt]	154208	1			T13	3		T116	699		T117	617
auto[0]	auto[EscalateSt]	4809028	1			T4	2464		T5	57980		T13	4424
auto[0]	auto[InvalidSt]	9620658	1			T4	2397		T5	159778		T7	9875
auto[1]	auto[ResetSt]	176	1			T13	3		T16	4		T47	3
auto[1]	auto[IdleSt]	135	1			T13	5		T16	4		T33	11
auto[1]	auto[ClkMuxSt]	52	1			T13	1		T16	2		T47	1
auto[1]	auto[CntIncrSt]	38	1			T47	1		T33	1		T59	2
auto[1]	auto[CntProgSt]	715	1			T13	17		T16	6		T47	9
auto[1]	auto[TransCheckSt]	77	1			T16	6		T47	3		T156	5
auto[1]	auto[TokenHashSt]	493	1			T13	1		T16	16		T47	22
auto[1]	auto[FlashRmaSt]	69	1			T13	2		T16	1		T47	4
auto[1]	auto[TokenCheck0St]	21	1			T47	1		T33	2		T63	1
auto[1]	auto[TokenCheck1St]	94	1			T13	1		T16	2		T47	1
auto[1]	auto[TransProgSt]	521	1			T13	7		T16	4		T47	10
auto[1]	auto[PostTransSt]	2423	1			T4	4		T5	8		T16	5
auto[1]	auto[ScrapSt]	43	1			T47	1		T33	2		T59	3
auto[1]	auto[EscalateSt]	1367490	1			T4	980		T5	9740		T13	7279
auto[1]	auto[InvalidSt]	6793	1			T4	6		T5	92		T7	2