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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.43 97.29 95.96 91.98 100.00 96.13 98.48 95.18


Total test records in report: 992
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T759 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1372860779 Feb 07 01:58:37 PM PST 24 Feb 07 01:58:54 PM PST 24 2542467402 ps
T760 /workspace/coverage/default/37.lc_ctrl_alert_test.3555098958 Feb 07 02:00:03 PM PST 24 Feb 07 02:00:09 PM PST 24 128507306 ps
T761 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.197035189 Feb 07 01:58:00 PM PST 24 Feb 07 01:58:20 PM PST 24 1116813357 ps
T762 /workspace/coverage/default/11.lc_ctrl_sec_mubi.1531331006 Feb 07 01:59:00 PM PST 24 Feb 07 01:59:22 PM PST 24 659445557 ps
T763 /workspace/coverage/default/12.lc_ctrl_security_escalation.4014949349 Feb 07 01:59:02 PM PST 24 Feb 07 01:59:27 PM PST 24 2547804367 ps
T187 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3507073367 Feb 07 01:58:33 PM PST 24 Feb 07 01:58:35 PM PST 24 21626389 ps
T764 /workspace/coverage/default/40.lc_ctrl_security_escalation.1630615590 Feb 07 02:00:08 PM PST 24 Feb 07 02:00:18 PM PST 24 1031218666 ps
T765 /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3190554619 Feb 07 01:59:56 PM PST 24 Feb 07 02:00:01 PM PST 24 44927813 ps
T766 /workspace/coverage/default/38.lc_ctrl_security_escalation.1574672110 Feb 07 02:00:06 PM PST 24 Feb 07 02:00:19 PM PST 24 547542702 ps
T767 /workspace/coverage/default/49.lc_ctrl_smoke.1374880412 Feb 07 02:00:30 PM PST 24 Feb 07 02:00:34 PM PST 24 145087708 ps
T768 /workspace/coverage/default/9.lc_ctrl_prog_failure.26494787 Feb 07 01:58:37 PM PST 24 Feb 07 01:58:40 PM PST 24 106123636 ps
T769 /workspace/coverage/default/6.lc_ctrl_errors.4270815189 Feb 07 01:58:34 PM PST 24 Feb 07 01:58:47 PM PST 24 371869008 ps
T770 /workspace/coverage/default/2.lc_ctrl_errors.941844501 Feb 07 01:58:13 PM PST 24 Feb 07 01:58:26 PM PST 24 1284230164 ps
T771 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1388841624 Feb 07 01:58:40 PM PST 24 Feb 07 01:58:49 PM PST 24 1726146255 ps
T772 /workspace/coverage/default/0.lc_ctrl_errors.772371539 Feb 07 01:58:02 PM PST 24 Feb 07 01:58:17 PM PST 24 1185087099 ps
T773 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1932299524 Feb 07 01:59:24 PM PST 24 Feb 07 02:00:10 PM PST 24 2475415822 ps
T774 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4066694648 Feb 07 01:59:24 PM PST 24 Feb 07 01:59:37 PM PST 24 326689419 ps
T775 /workspace/coverage/default/31.lc_ctrl_errors.3544576843 Feb 07 01:59:45 PM PST 24 Feb 07 01:59:55 PM PST 24 399072752 ps
T776 /workspace/coverage/default/21.lc_ctrl_prog_failure.2000989723 Feb 07 01:59:20 PM PST 24 Feb 07 01:59:23 PM PST 24 50377620 ps
T777 /workspace/coverage/default/38.lc_ctrl_prog_failure.247353139 Feb 07 02:00:05 PM PST 24 Feb 07 02:00:11 PM PST 24 85532508 ps
T778 /workspace/coverage/default/14.lc_ctrl_sec_mubi.3384246262 Feb 07 01:59:01 PM PST 24 Feb 07 01:59:19 PM PST 24 1244443319 ps
T779 /workspace/coverage/default/19.lc_ctrl_state_post_trans.430514548 Feb 07 01:59:15 PM PST 24 Feb 07 01:59:26 PM PST 24 241725192 ps
T780 /workspace/coverage/default/33.lc_ctrl_state_failure.1908946119 Feb 07 01:59:59 PM PST 24 Feb 07 02:00:21 PM PST 24 204815168 ps
T781 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1462717660 Feb 07 02:00:00 PM PST 24 Feb 07 02:00:16 PM PST 24 560215253 ps
T782 /workspace/coverage/default/5.lc_ctrl_security_escalation.2974950424 Feb 07 01:58:34 PM PST 24 Feb 07 01:58:48 PM PST 24 908436466 ps
T783 /workspace/coverage/default/3.lc_ctrl_alert_test.2973260929 Feb 07 01:58:21 PM PST 24 Feb 07 01:58:24 PM PST 24 30542213 ps
T784 /workspace/coverage/default/46.lc_ctrl_alert_test.3082479989 Feb 07 02:00:33 PM PST 24 Feb 07 02:00:35 PM PST 24 24904788 ps
T62 /workspace/coverage/default/4.lc_ctrl_sec_cm.1738808889 Feb 07 01:58:19 PM PST 24 Feb 07 01:58:46 PM PST 24 119999412 ps
T785 /workspace/coverage/default/35.lc_ctrl_errors.524331042 Feb 07 02:00:01 PM PST 24 Feb 07 02:00:18 PM PST 24 307938437 ps
T786 /workspace/coverage/default/5.lc_ctrl_state_failure.3571800826 Feb 07 01:58:37 PM PST 24 Feb 07 01:58:59 PM PST 24 160354602 ps
T787 /workspace/coverage/default/33.lc_ctrl_alert_test.3492641113 Feb 07 01:59:56 PM PST 24 Feb 07 02:00:01 PM PST 24 29552532 ps
T788 /workspace/coverage/default/4.lc_ctrl_jtag_access.2250630474 Feb 07 01:58:22 PM PST 24 Feb 07 01:58:24 PM PST 24 94107597 ps
T789 /workspace/coverage/default/36.lc_ctrl_alert_test.3768038969 Feb 07 02:00:12 PM PST 24 Feb 07 02:00:14 PM PST 24 39490852 ps
T790 /workspace/coverage/default/41.lc_ctrl_alert_test.1357437602 Feb 07 02:00:17 PM PST 24 Feb 07 02:00:19 PM PST 24 101342449 ps
T791 /workspace/coverage/default/45.lc_ctrl_alert_test.4193478619 Feb 07 02:00:34 PM PST 24 Feb 07 02:00:36 PM PST 24 28751036 ps
T792 /workspace/coverage/default/43.lc_ctrl_smoke.2516128637 Feb 07 02:00:16 PM PST 24 Feb 07 02:00:19 PM PST 24 286720332 ps
T188 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2516232212 Feb 07 01:58:08 PM PST 24 Feb 07 01:58:09 PM PST 24 39708770 ps
T793 /workspace/coverage/default/20.lc_ctrl_state_failure.3737162296 Feb 07 01:59:24 PM PST 24 Feb 07 02:00:04 PM PST 24 724593161 ps
T794 /workspace/coverage/default/1.lc_ctrl_security_escalation.1731465221 Feb 07 01:58:14 PM PST 24 Feb 07 01:58:28 PM PST 24 306975261 ps
T795 /workspace/coverage/default/44.lc_ctrl_sec_mubi.3867676777 Feb 07 02:00:22 PM PST 24 Feb 07 02:00:39 PM PST 24 4054755933 ps
T796 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3287903068 Feb 07 01:58:06 PM PST 24 Feb 07 01:58:49 PM PST 24 18906967055 ps
T797 /workspace/coverage/default/37.lc_ctrl_jtag_access.3951692485 Feb 07 02:00:03 PM PST 24 Feb 07 02:00:17 PM PST 24 1521752301 ps
T798 /workspace/coverage/default/16.lc_ctrl_errors.1299042113 Feb 07 01:59:14 PM PST 24 Feb 07 01:59:25 PM PST 24 1376611902 ps
T799 /workspace/coverage/default/48.lc_ctrl_sec_mubi.2325808293 Feb 07 02:00:32 PM PST 24 Feb 07 02:00:45 PM PST 24 363712778 ps
T800 /workspace/coverage/default/47.lc_ctrl_prog_failure.28929052 Feb 07 02:00:36 PM PST 24 Feb 07 02:00:40 PM PST 24 126856646 ps
T801 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3788391735 Feb 07 01:58:24 PM PST 24 Feb 07 01:58:38 PM PST 24 835609146 ps
T802 /workspace/coverage/default/41.lc_ctrl_state_failure.1497904721 Feb 07 02:00:12 PM PST 24 Feb 07 02:00:50 PM PST 24 1283111741 ps
T101 /workspace/coverage/default/1.lc_ctrl_sec_cm.4065133933 Feb 07 01:58:15 PM PST 24 Feb 07 01:58:41 PM PST 24 117458948 ps
T803 /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2424123045 Feb 07 01:59:57 PM PST 24 Feb 07 02:00:20 PM PST 24 2448654344 ps
T804 /workspace/coverage/default/49.lc_ctrl_alert_test.4220924760 Feb 07 02:00:34 PM PST 24 Feb 07 02:00:36 PM PST 24 15529092 ps
T805 /workspace/coverage/default/39.lc_ctrl_jtag_access.2626654418 Feb 07 02:00:12 PM PST 24 Feb 07 02:00:16 PM PST 24 222101806 ps
T806 /workspace/coverage/default/41.lc_ctrl_security_escalation.2763411977 Feb 07 02:00:12 PM PST 24 Feb 07 02:00:28 PM PST 24 431228907 ps
T807 /workspace/coverage/default/2.lc_ctrl_jtag_access.443807742 Feb 07 01:58:10 PM PST 24 Feb 07 01:58:20 PM PST 24 5721804994 ps
T808 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2054556670 Feb 07 01:59:01 PM PST 24 Feb 07 01:59:57 PM PST 24 7927324884 ps
T809 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2220844353 Feb 07 01:59:34 PM PST 24 Feb 07 02:02:59 PM PST 24 19236459361 ps
T810 /workspace/coverage/default/15.lc_ctrl_jtag_access.2580321973 Feb 07 01:58:58 PM PST 24 Feb 07 01:59:05 PM PST 24 1232052583 ps
T811 /workspace/coverage/default/38.lc_ctrl_jtag_access.4268666066 Feb 07 01:59:59 PM PST 24 Feb 07 02:00:05 PM PST 24 1078812430 ps
T812 /workspace/coverage/default/29.lc_ctrl_alert_test.3162954034 Feb 07 01:59:48 PM PST 24 Feb 07 01:59:50 PM PST 24 50267461 ps
T813 /workspace/coverage/default/23.lc_ctrl_jtag_access.1735718708 Feb 07 01:59:24 PM PST 24 Feb 07 01:59:26 PM PST 24 181627219 ps
T814 /workspace/coverage/default/13.lc_ctrl_state_failure.1855824958 Feb 07 01:58:56 PM PST 24 Feb 07 01:59:27 PM PST 24 330513330 ps
T815 /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2855460497 Feb 07 01:59:33 PM PST 24 Feb 07 02:21:14 PM PST 24 125349529286 ps
T816 /workspace/coverage/default/8.lc_ctrl_alert_test.1667007087 Feb 07 01:58:40 PM PST 24 Feb 07 01:58:42 PM PST 24 46094952 ps
T817 /workspace/coverage/default/19.lc_ctrl_sec_mubi.3537660265 Feb 07 01:59:24 PM PST 24 Feb 07 01:59:41 PM PST 24 346776393 ps
T818 /workspace/coverage/default/42.lc_ctrl_smoke.628432934 Feb 07 02:00:18 PM PST 24 Feb 07 02:00:22 PM PST 24 64372110 ps
T819 /workspace/coverage/default/44.lc_ctrl_state_failure.3211885675 Feb 07 02:00:23 PM PST 24 Feb 07 02:00:46 PM PST 24 217662035 ps
T820 /workspace/coverage/default/27.lc_ctrl_state_failure.3142704663 Feb 07 01:59:34 PM PST 24 Feb 07 01:59:58 PM PST 24 320783652 ps
T821 /workspace/coverage/default/16.lc_ctrl_jtag_errors.1770685841 Feb 07 01:59:06 PM PST 24 Feb 07 01:59:49 PM PST 24 2642041207 ps
T822 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.174830706 Feb 07 02:00:36 PM PST 24 Feb 07 02:00:47 PM PST 24 1247231855 ps
T823 /workspace/coverage/default/4.lc_ctrl_jtag_errors.2540543117 Feb 07 01:58:19 PM PST 24 Feb 07 02:00:08 PM PST 24 4035416700 ps
T824 /workspace/coverage/default/14.lc_ctrl_stress_all.1185654415 Feb 07 01:58:57 PM PST 24 Feb 07 02:04:19 PM PST 24 86399923795 ps
T825 /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3809185763 Feb 07 02:00:06 PM PST 24 Feb 07 02:00:22 PM PST 24 1410935239 ps
T826 /workspace/coverage/default/3.lc_ctrl_jtag_access.1199847420 Feb 07 01:58:19 PM PST 24 Feb 07 01:58:33 PM PST 24 7138717810 ps
T827 /workspace/coverage/default/36.lc_ctrl_smoke.3756003667 Feb 07 02:00:02 PM PST 24 Feb 07 02:00:11 PM PST 24 374504505 ps
T828 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.879502854 Feb 07 02:00:13 PM PST 24 Feb 07 02:00:15 PM PST 24 111815967 ps
T829 /workspace/coverage/default/43.lc_ctrl_prog_failure.791855588 Feb 07 02:00:24 PM PST 24 Feb 07 02:00:28 PM PST 24 211118109 ps
T830 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3477068372 Feb 07 02:00:04 PM PST 24 Feb 07 02:00:16 PM PST 24 1297174357 ps
T831 /workspace/coverage/default/25.lc_ctrl_smoke.3883031695 Feb 07 01:59:36 PM PST 24 Feb 07 01:59:39 PM PST 24 99218215 ps
T832 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1985956285 Feb 07 02:00:20 PM PST 24 Feb 07 02:00:22 PM PST 24 20772995 ps
T833 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.376945582 Feb 07 01:58:37 PM PST 24 Feb 07 01:58:45 PM PST 24 829899954 ps
T834 /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1758789278 Feb 07 02:00:35 PM PST 24 Feb 07 02:19:50 PM PST 24 64744372670 ps
T835 /workspace/coverage/default/34.lc_ctrl_sec_token_mux.595164558 Feb 07 02:00:02 PM PST 24 Feb 07 02:00:17 PM PST 24 1535037725 ps
T836 /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.509540048 Feb 07 01:59:15 PM PST 24 Feb 07 01:59:20 PM PST 24 212084471 ps
T837 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.390935055 Feb 07 01:58:31 PM PST 24 Feb 07 01:58:46 PM PST 24 613824887 ps
T838 /workspace/coverage/default/24.lc_ctrl_security_escalation.1406940898 Feb 07 01:59:35 PM PST 24 Feb 07 01:59:46 PM PST 24 1506051374 ps
T839 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4205154451 Feb 07 01:58:34 PM PST 24 Feb 07 01:58:41 PM PST 24 1012623597 ps
T840 /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2047816371 Feb 07 01:58:21 PM PST 24 Feb 07 01:58:30 PM PST 24 1369091567 ps
T841 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2790433011 Feb 07 01:59:14 PM PST 24 Feb 07 01:59:24 PM PST 24 807813823 ps
T842 /workspace/coverage/default/7.lc_ctrl_prog_failure.534253671 Feb 07 01:58:33 PM PST 24 Feb 07 01:58:38 PM PST 24 205434472 ps
T843 /workspace/coverage/default/44.lc_ctrl_smoke.1967161121 Feb 07 02:00:23 PM PST 24 Feb 07 02:00:27 PM PST 24 55004780 ps
T844 /workspace/coverage/default/28.lc_ctrl_state_post_trans.3495254040 Feb 07 01:59:39 PM PST 24 Feb 07 01:59:48 PM PST 24 89852617 ps
T845 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2032630303 Feb 07 01:58:54 PM PST 24 Feb 07 01:58:57 PM PST 24 171950580 ps
T846 /workspace/coverage/default/0.lc_ctrl_alert_test.23332814 Feb 07 01:58:12 PM PST 24 Feb 07 01:58:14 PM PST 24 15066022 ps
T847 /workspace/coverage/default/19.lc_ctrl_jtag_errors.2104913462 Feb 07 01:59:14 PM PST 24 Feb 07 01:59:36 PM PST 24 4524303515 ps
T848 /workspace/coverage/default/39.lc_ctrl_prog_failure.273719475 Feb 07 02:00:08 PM PST 24 Feb 07 02:00:13 PM PST 24 181985762 ps
T849 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.194331441 Feb 07 01:58:17 PM PST 24 Feb 07 01:58:22 PM PST 24 931075434 ps
T850 /workspace/coverage/default/31.lc_ctrl_stress_all.3248257066 Feb 07 01:59:48 PM PST 24 Feb 07 02:01:14 PM PST 24 2261236805 ps
T76 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3998998739 Feb 07 01:58:51 PM PST 24 Feb 07 01:58:59 PM PST 24 1835675611 ps
T851 /workspace/coverage/default/22.lc_ctrl_state_post_trans.1756150105 Feb 07 01:59:24 PM PST 24 Feb 07 01:59:28 PM PST 24 172409690 ps
T852 /workspace/coverage/default/10.lc_ctrl_alert_test.2027403843 Feb 07 01:58:55 PM PST 24 Feb 07 01:58:57 PM PST 24 40701404 ps
T853 /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1151197592 Feb 07 01:59:58 PM PST 24 Feb 07 02:04:23 PM PST 24 51835797933 ps
T854 /workspace/coverage/default/15.lc_ctrl_sec_mubi.2094064912 Feb 07 01:58:59 PM PST 24 Feb 07 01:59:22 PM PST 24 2456634785 ps
T855 /workspace/coverage/default/47.lc_ctrl_alert_test.1761067899 Feb 07 02:00:23 PM PST 24 Feb 07 02:00:26 PM PST 24 275064180 ps
T856 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3140630643 Feb 07 01:59:13 PM PST 24 Feb 07 02:00:53 PM PST 24 2815263443 ps
T857 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3721120551 Feb 07 01:59:26 PM PST 24 Feb 07 01:59:39 PM PST 24 1408090937 ps
T858 /workspace/coverage/default/40.lc_ctrl_stress_all.1771282857 Feb 07 02:00:13 PM PST 24 Feb 07 02:02:29 PM PST 24 31220675769 ps
T859 /workspace/coverage/default/27.lc_ctrl_jtag_access.3027402749 Feb 07 01:59:34 PM PST 24 Feb 07 01:59:43 PM PST 24 1140374853 ps
T860 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3898330256 Feb 07 01:58:32 PM PST 24 Feb 07 01:58:44 PM PST 24 1314703169 ps
T861 /workspace/coverage/default/36.lc_ctrl_prog_failure.1590117162 Feb 07 02:00:05 PM PST 24 Feb 07 02:00:11 PM PST 24 95750510 ps
T862 /workspace/coverage/default/14.lc_ctrl_state_post_trans.566854472 Feb 07 01:58:56 PM PST 24 Feb 07 01:59:04 PM PST 24 111489235 ps
T863 /workspace/coverage/default/4.lc_ctrl_sec_mubi.3891454861 Feb 07 01:58:21 PM PST 24 Feb 07 01:58:35 PM PST 24 860978627 ps
T864 /workspace/coverage/default/45.lc_ctrl_security_escalation.3028563785 Feb 07 02:00:37 PM PST 24 Feb 07 02:00:51 PM PST 24 374217476 ps
T865 /workspace/coverage/default/3.lc_ctrl_state_failure.2433729456 Feb 07 01:58:15 PM PST 24 Feb 07 01:58:48 PM PST 24 668867321 ps
T866 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3661258109 Feb 07 01:58:11 PM PST 24 Feb 07 01:58:25 PM PST 24 1870901410 ps
T867 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2939396968 Feb 07 01:58:51 PM PST 24 Feb 07 01:58:56 PM PST 24 824696454 ps
T868 /workspace/coverage/default/10.lc_ctrl_errors.1322605631 Feb 07 01:58:55 PM PST 24 Feb 07 01:59:10 PM PST 24 797442751 ps
T869 /workspace/coverage/default/8.lc_ctrl_security_escalation.3115831199 Feb 07 01:58:37 PM PST 24 Feb 07 01:58:47 PM PST 24 384023891 ps
T870 /workspace/coverage/default/37.lc_ctrl_errors.3863105695 Feb 07 02:00:01 PM PST 24 Feb 07 02:00:24 PM PST 24 401357991 ps
T871 /workspace/coverage/default/3.lc_ctrl_state_post_trans.3145269449 Feb 07 01:58:19 PM PST 24 Feb 07 01:58:28 PM PST 24 329489666 ps
T872 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3729909436 Feb 07 01:58:20 PM PST 24 Feb 07 01:58:31 PM PST 24 458308656 ps
T873 /workspace/coverage/default/22.lc_ctrl_errors.2780685201 Feb 07 01:59:33 PM PST 24 Feb 07 01:59:45 PM PST 24 1843777832 ps
T874 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2927835351 Feb 07 01:59:42 PM PST 24 Feb 07 01:59:55 PM PST 24 1202448542 ps
T875 /workspace/coverage/default/3.lc_ctrl_jtag_errors.2645773702 Feb 07 01:58:22 PM PST 24 Feb 07 01:58:56 PM PST 24 13001949930 ps
T876 /workspace/coverage/default/8.lc_ctrl_sec_mubi.2475170727 Feb 07 01:58:37 PM PST 24 Feb 07 01:58:49 PM PST 24 1208498978 ps
T877 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.564989379 Feb 07 01:59:09 PM PST 24 Feb 07 01:59:40 PM PST 24 1884434121 ps
T878 /workspace/coverage/default/7.lc_ctrl_errors.747568376 Feb 07 01:58:44 PM PST 24 Feb 07 01:59:02 PM PST 24 1511933820 ps
T879 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3763639581 Feb 07 01:59:00 PM PST 24 Feb 07 01:59:17 PM PST 24 749558399 ps
T880 /workspace/coverage/default/1.lc_ctrl_state_post_trans.1962121673 Feb 07 01:58:13 PM PST 24 Feb 07 01:58:18 PM PST 24 380483997 ps
T881 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1365080522 Feb 07 02:00:08 PM PST 24 Feb 07 02:00:23 PM PST 24 307676599 ps
T882 /workspace/coverage/default/13.lc_ctrl_stress_all.3827657532 Feb 07 01:58:58 PM PST 24 Feb 07 02:02:07 PM PST 24 16132598801 ps
T883 /workspace/coverage/default/39.lc_ctrl_errors.3299698665 Feb 07 02:00:06 PM PST 24 Feb 07 02:00:23 PM PST 24 1093985165 ps
T884 /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2086215394 Feb 07 01:58:37 PM PST 24 Feb 07 01:59:14 PM PST 24 5022660200 ps
T885 /workspace/coverage/default/0.lc_ctrl_jtag_priority.1802696999 Feb 07 01:58:04 PM PST 24 Feb 07 01:58:08 PM PST 24 471813770 ps
T886 /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2137324903 Feb 07 01:58:49 PM PST 24 Feb 07 01:59:24 PM PST 24 17479986973 ps
T887 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1819295250 Feb 07 01:59:14 PM PST 24 Feb 07 01:59:21 PM PST 24 219688901 ps
T888 /workspace/coverage/default/10.lc_ctrl_prog_failure.649169852 Feb 07 01:58:49 PM PST 24 Feb 07 01:58:52 PM PST 24 61718987 ps
T889 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1238169478 Feb 07 01:59:01 PM PST 24 Feb 07 01:59:07 PM PST 24 17313645 ps
T890 /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3648268815 Feb 07 01:58:14 PM PST 24 Feb 07 01:58:32 PM PST 24 644364348 ps
T891 /workspace/coverage/default/17.lc_ctrl_prog_failure.2324115667 Feb 07 01:59:03 PM PST 24 Feb 07 01:59:11 PM PST 24 474410630 ps
T892 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.528179460 Feb 07 01:58:54 PM PST 24 Feb 07 01:59:10 PM PST 24 724665288 ps
T893 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3462980776 Feb 07 01:59:28 PM PST 24 Feb 07 01:59:39 PM PST 24 392490387 ps
T894 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3474839709 Feb 07 01:58:53 PM PST 24 Feb 07 01:58:55 PM PST 24 14116967 ps
T895 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.970184626 Feb 07 01:59:18 PM PST 24 Feb 07 01:59:38 PM PST 24 1882335678 ps
T896 /workspace/coverage/default/17.lc_ctrl_jtag_errors.637099557 Feb 07 01:59:16 PM PST 24 Feb 07 01:59:58 PM PST 24 7427729656 ps
T897 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.384837715 Feb 07 01:59:41 PM PST 24 Feb 07 01:59:54 PM PST 24 776824141 ps
T898 /workspace/coverage/default/28.lc_ctrl_stress_all.2669749132 Feb 07 01:59:41 PM PST 24 Feb 07 02:00:18 PM PST 24 1916326295 ps
T899 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2343513199 Feb 07 01:59:33 PM PST 24 Feb 07 01:59:35 PM PST 24 22636514 ps
T900 /workspace/coverage/default/24.lc_ctrl_state_failure.1349564300 Feb 07 01:59:26 PM PST 24 Feb 07 01:59:55 PM PST 24 250852632 ps
T901 /workspace/coverage/default/3.lc_ctrl_smoke.39426767 Feb 07 01:58:17 PM PST 24 Feb 07 01:58:24 PM PST 24 224235294 ps
T902 /workspace/coverage/default/26.lc_ctrl_security_escalation.1452413765 Feb 07 01:59:45 PM PST 24 Feb 07 01:59:57 PM PST 24 2217327121 ps
T903 /workspace/coverage/default/12.lc_ctrl_stress_all.2508683612 Feb 07 01:58:50 PM PST 24 Feb 07 02:02:24 PM PST 24 16869308554 ps
T904 /workspace/coverage/default/19.lc_ctrl_stress_all.381533570 Feb 07 01:59:19 PM PST 24 Feb 07 02:01:17 PM PST 24 3083646476 ps
T905 /workspace/coverage/default/12.lc_ctrl_jtag_access.670531447 Feb 07 01:58:46 PM PST 24 Feb 07 01:58:48 PM PST 24 133650455 ps
T906 /workspace/coverage/default/18.lc_ctrl_smoke.3398592853 Feb 07 01:59:13 PM PST 24 Feb 07 01:59:17 PM PST 24 250714004 ps
T907 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.805440844 Feb 07 01:58:20 PM PST 24 Feb 07 01:58:22 PM PST 24 11971970 ps
T57 /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1911834622 Feb 07 01:59:00 PM PST 24 Feb 07 02:05:02 PM PST 24 67119988762 ps
T908 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4048681593 Feb 07 01:59:35 PM PST 24 Feb 07 01:59:45 PM PST 24 275995868 ps
T909 /workspace/coverage/default/5.lc_ctrl_smoke.614225924 Feb 07 01:58:32 PM PST 24 Feb 07 01:58:35 PM PST 24 88334795 ps
T910 /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3074078583 Feb 07 01:58:17 PM PST 24 Feb 07 01:58:18 PM PST 24 59767727 ps
T911 /workspace/coverage/default/46.lc_ctrl_state_post_trans.3087537650 Feb 07 02:00:23 PM PST 24 Feb 07 02:00:31 PM PST 24 67286521 ps
T912 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2377453382 Feb 07 01:59:04 PM PST 24 Feb 07 01:59:16 PM PST 24 314265150 ps
T913 /workspace/coverage/default/13.lc_ctrl_jtag_access.372314414 Feb 07 01:59:00 PM PST 24 Feb 07 01:59:11 PM PST 24 6628281586 ps
T914 /workspace/coverage/default/5.lc_ctrl_errors.1810067025 Feb 07 01:58:28 PM PST 24 Feb 07 01:58:41 PM PST 24 1400549472 ps
T915 /workspace/coverage/default/18.lc_ctrl_alert_test.1557167976 Feb 07 01:59:14 PM PST 24 Feb 07 01:59:16 PM PST 24 92471177 ps
T916 /workspace/coverage/default/38.lc_ctrl_alert_test.1489582607 Feb 07 02:00:05 PM PST 24 Feb 07 02:00:09 PM PST 24 78475447 ps
T917 /workspace/coverage/default/1.lc_ctrl_sec_mubi.4245467775 Feb 07 01:58:09 PM PST 24 Feb 07 01:58:22 PM PST 24 1628814831 ps
T918 /workspace/coverage/default/21.lc_ctrl_jtag_access.1471625187 Feb 07 01:59:30 PM PST 24 Feb 07 01:59:42 PM PST 24 8839191477 ps
T919 /workspace/coverage/default/39.lc_ctrl_sec_mubi.441414314 Feb 07 02:00:14 PM PST 24 Feb 07 02:00:25 PM PST 24 1148498585 ps
T920 /workspace/coverage/default/20.lc_ctrl_security_escalation.2373378579 Feb 07 01:59:18 PM PST 24 Feb 07 01:59:28 PM PST 24 229161872 ps
T921 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3858638279 Feb 07 01:58:32 PM PST 24 Feb 07 01:58:53 PM PST 24 527055569 ps
T922 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4015533731 Feb 07 02:00:22 PM PST 24 Feb 07 02:00:32 PM PST 24 1431092732 ps
T923 /workspace/coverage/default/20.lc_ctrl_smoke.2522306979 Feb 07 01:59:24 PM PST 24 Feb 07 01:59:27 PM PST 24 48089217 ps
T924 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3853142961 Feb 07 01:58:29 PM PST 24 Feb 07 01:58:38 PM PST 24 218323878 ps
T925 /workspace/coverage/default/19.lc_ctrl_jtag_access.4147234806 Feb 07 01:59:14 PM PST 24 Feb 07 01:59:16 PM PST 24 89341748 ps
T926 /workspace/coverage/default/30.lc_ctrl_jtag_access.1308096874 Feb 07 01:59:50 PM PST 24 Feb 07 02:00:00 PM PST 24 316600780 ps
T927 /workspace/coverage/default/5.lc_ctrl_jtag_priority.737209739 Feb 07 01:58:32 PM PST 24 Feb 07 01:58:35 PM PST 24 159145076 ps
T928 /workspace/coverage/default/25.lc_ctrl_state_post_trans.1200410106 Feb 07 01:59:29 PM PST 24 Feb 07 01:59:34 PM PST 24 244872155 ps
T929 /workspace/coverage/default/31.lc_ctrl_jtag_access.986667077 Feb 07 01:59:50 PM PST 24 Feb 07 01:59:56 PM PST 24 364128312 ps
T930 /workspace/coverage/default/23.lc_ctrl_sec_mubi.2504895535 Feb 07 01:59:30 PM PST 24 Feb 07 01:59:42 PM PST 24 193645268 ps
T931 /workspace/coverage/default/48.lc_ctrl_state_post_trans.3508421023 Feb 07 02:00:50 PM PST 24 Feb 07 02:01:00 PM PST 24 109423609 ps
T932 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2408336973 Feb 07 01:59:13 PM PST 24 Feb 07 01:59:29 PM PST 24 1390677895 ps
T933 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3140172858 Feb 07 01:59:02 PM PST 24 Feb 07 01:59:12 PM PST 24 4098388369 ps
T934 /workspace/coverage/default/32.lc_ctrl_state_failure.1973724992 Feb 07 01:59:57 PM PST 24 Feb 07 02:00:27 PM PST 24 244778136 ps
T935 /workspace/coverage/default/8.lc_ctrl_prog_failure.2688018825 Feb 07 01:58:40 PM PST 24 Feb 07 01:58:45 PM PST 24 189814996 ps
T936 /workspace/coverage/default/27.lc_ctrl_stress_all.1462741939 Feb 07 01:59:41 PM PST 24 Feb 07 02:01:31 PM PST 24 3351412330 ps
T937 /workspace/coverage/default/10.lc_ctrl_sec_mubi.649569087 Feb 07 01:58:54 PM PST 24 Feb 07 01:59:14 PM PST 24 837703271 ps
T938 /workspace/coverage/default/18.lc_ctrl_prog_failure.1629713083 Feb 07 01:59:15 PM PST 24 Feb 07 01:59:20 PM PST 24 93282606 ps
T939 /workspace/coverage/default/12.lc_ctrl_state_failure.3040628207 Feb 07 01:59:01 PM PST 24 Feb 07 01:59:33 PM PST 24 1070615818 ps
T77 /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3807681664 Feb 07 01:58:41 PM PST 24 Feb 07 01:58:56 PM PST 24 3235016651 ps
T940 /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2000566260 Feb 07 01:59:28 PM PST 24 Feb 07 01:59:30 PM PST 24 70215445 ps
T941 /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1862985948 Feb 07 01:59:15 PM PST 24 Feb 07 02:17:43 PM PST 24 82922738117 ps
T942 /workspace/coverage/default/6.lc_ctrl_jtag_priority.1342756890 Feb 07 01:58:31 PM PST 24 Feb 07 01:58:34 PM PST 24 162183519 ps
T943 /workspace/coverage/default/11.lc_ctrl_smoke.4235332528 Feb 07 01:59:01 PM PST 24 Feb 07 01:59:07 PM PST 24 121539054 ps
T944 /workspace/coverage/default/38.lc_ctrl_smoke.3188129247 Feb 07 02:00:06 PM PST 24 Feb 07 02:00:11 PM PST 24 73989817 ps
T945 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2032893388 Feb 07 02:00:00 PM PST 24 Feb 07 02:00:12 PM PST 24 819345866 ps
T946 /workspace/coverage/default/14.lc_ctrl_jtag_access.370662565 Feb 07 01:58:54 PM PST 24 Feb 07 01:58:59 PM PST 24 354877246 ps
T947 /workspace/coverage/default/24.lc_ctrl_sec_mubi.1934579956 Feb 07 01:59:26 PM PST 24 Feb 07 01:59:38 PM PST 24 902727960 ps
T948 /workspace/coverage/default/6.lc_ctrl_security_escalation.1534857429 Feb 07 01:58:36 PM PST 24 Feb 07 01:58:44 PM PST 24 241928176 ps
T949 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2691700674 Feb 07 01:59:59 PM PST 24 Feb 07 02:00:14 PM PST 24 341915375 ps
T950 /workspace/coverage/default/48.lc_ctrl_jtag_access.3682242842 Feb 07 02:00:35 PM PST 24 Feb 07 02:00:39 PM PST 24 177460074 ps
T951 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2011197042 Feb 07 02:00:09 PM PST 24 Feb 07 02:00:21 PM PST 24 933249202 ps
T952 /workspace/coverage/default/28.lc_ctrl_state_failure.1203276421 Feb 07 01:59:46 PM PST 24 Feb 07 02:00:19 PM PST 24 405543148 ps
T55 /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2338894269 Feb 07 01:59:31 PM PST 24 Feb 07 03:06:21 PM PST 24 253089028299 ps
T953 /workspace/coverage/default/17.lc_ctrl_jtag_access.3977484394 Feb 07 01:59:17 PM PST 24 Feb 07 01:59:26 PM PST 24 1595088203 ps
T954 /workspace/coverage/default/3.lc_ctrl_jtag_priority.1824076142 Feb 07 01:58:17 PM PST 24 Feb 07 01:58:21 PM PST 24 902940449 ps
T955 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1815593610 Feb 07 01:58:48 PM PST 24 Feb 07 01:58:52 PM PST 24 560212646 ps
T956 /workspace/coverage/default/16.lc_ctrl_sec_mubi.1607104709 Feb 07 01:59:04 PM PST 24 Feb 07 01:59:17 PM PST 24 338820396 ps
T957 /workspace/coverage/default/2.lc_ctrl_security_escalation.1700468246 Feb 07 01:58:12 PM PST 24 Feb 07 01:58:23 PM PST 24 615127446 ps
T958 /workspace/coverage/default/16.lc_ctrl_state_failure.534933059 Feb 07 01:59:11 PM PST 24 Feb 07 01:59:40 PM PST 24 1131990130 ps
T959 /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2358579846 Feb 07 02:00:20 PM PST 24 Feb 07 02:14:45 PM PST 24 330547383484 ps
T960 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.326109104 Feb 07 01:58:48 PM PST 24 Feb 07 01:58:59 PM PST 24 3142149863 ps
T961 /workspace/coverage/default/27.lc_ctrl_sec_mubi.2632982490 Feb 07 01:59:40 PM PST 24 Feb 07 02:00:00 PM PST 24 438895164 ps
T962 /workspace/coverage/default/33.lc_ctrl_state_post_trans.2745074922 Feb 07 01:59:58 PM PST 24 Feb 07 02:00:08 PM PST 24 63909095 ps
T963 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.103255662 Feb 07 02:00:10 PM PST 24 Feb 07 02:00:13 PM PST 24 24289168 ps
T964 /workspace/coverage/default/34.lc_ctrl_state_post_trans.3527613177 Feb 07 02:00:04 PM PST 24 Feb 07 02:00:11 PM PST 24 286846458 ps
T965 /workspace/coverage/default/29.lc_ctrl_state_post_trans.3838908384 Feb 07 01:59:55 PM PST 24 Feb 07 02:00:07 PM PST 24 96027232 ps
T966 /workspace/coverage/default/24.lc_ctrl_jtag_access.1204336301 Feb 07 01:59:24 PM PST 24 Feb 07 01:59:31 PM PST 24 1237106281 ps
T967 /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2850176365 Feb 07 02:00:26 PM PST 24 Feb 07 02:03:52 PM PST 24 52060460406 ps
T968 /workspace/coverage/default/31.lc_ctrl_sec_mubi.1660773190 Feb 07 01:59:49 PM PST 24 Feb 07 02:00:03 PM PST 24 1214435914 ps
T969 /workspace/coverage/default/36.lc_ctrl_stress_all.138073930 Feb 07 02:00:03 PM PST 24 Feb 07 02:04:11 PM PST 24 15410304759 ps
T970 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1631685365 Feb 07 02:00:17 PM PST 24 Feb 07 02:00:28 PM PST 24 935034543 ps
T971 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3313890359 Feb 07 01:59:48 PM PST 24 Feb 07 01:59:50 PM PST 24 139541928 ps
T972 /workspace/coverage/default/34.lc_ctrl_jtag_access.1476050480 Feb 07 02:00:11 PM PST 24 Feb 07 02:00:18 PM PST 24 1640483873 ps
T973 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1592764114 Feb 07 02:00:18 PM PST 24 Feb 07 02:00:31 PM PST 24 356264321 ps
T974 /workspace/coverage/default/28.lc_ctrl_errors.25477657 Feb 07 01:59:41 PM PST 24 Feb 07 01:59:52 PM PST 24 321683774 ps
T975 /workspace/coverage/default/11.lc_ctrl_state_failure.2322503726 Feb 07 01:58:56 PM PST 24 Feb 07 01:59:21 PM PST 24 291573720 ps
T976 /workspace/coverage/default/46.lc_ctrl_errors.3534186780 Feb 07 02:00:28 PM PST 24 Feb 07 02:00:39 PM PST 24 189638318 ps
T977 /workspace/coverage/default/45.lc_ctrl_stress_all.2013781577 Feb 07 02:00:29 PM PST 24 Feb 07 02:04:19 PM PST 24 25742825243 ps
T978 /workspace/coverage/default/47.lc_ctrl_smoke.3041438661 Feb 07 02:00:28 PM PST 24 Feb 07 02:00:30 PM PST 24 17010387 ps
T979 /workspace/coverage/default/32.lc_ctrl_sec_mubi.990240197 Feb 07 01:59:48 PM PST 24 Feb 07 02:00:03 PM PST 24 341955150 ps
T980 /workspace/coverage/default/14.lc_ctrl_prog_failure.3961998049 Feb 07 01:58:53 PM PST 24 Feb 07 01:58:58 PM PST 24 258720463 ps
T981 /workspace/coverage/default/23.lc_ctrl_stress_all.617773439 Feb 07 01:59:27 PM PST 24 Feb 07 01:59:58 PM PST 24 1737260249 ps
T982 /workspace/coverage/default/32.lc_ctrl_stress_all.1920527844 Feb 07 01:59:49 PM PST 24 Feb 07 02:05:31 PM PST 24 10022452790 ps
T983 /workspace/coverage/default/4.lc_ctrl_prog_failure.3193916670 Feb 07 01:58:19 PM PST 24 Feb 07 01:58:23 PM PST 24 90960152 ps
T984 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4042551234 Feb 07 01:58:36 PM PST 24 Feb 07 01:58:41 PM PST 24 1120875438 ps
T985 /workspace/coverage/default/30.lc_ctrl_smoke.3242032591 Feb 07 01:59:55 PM PST 24 Feb 07 02:00:04 PM PST 24 50875596 ps
T986 /workspace/coverage/default/41.lc_ctrl_jtag_access.3496677259 Feb 07 02:00:15 PM PST 24 Feb 07 02:00:24 PM PST 24 321431653 ps
T987 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.465206934 Feb 07 01:58:21 PM PST 24 Feb 07 01:58:32 PM PST 24 313421336 ps
T988 /workspace/coverage/default/13.lc_ctrl_prog_failure.794315921 Feb 07 01:58:49 PM PST 24 Feb 07 01:58:52 PM PST 24 34194072 ps
T989 /workspace/coverage/default/46.lc_ctrl_sec_mubi.1334500977 Feb 07 02:00:35 PM PST 24 Feb 07 02:00:45 PM PST 24 251750669 ps
T990 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.834025422 Feb 07 01:59:59 PM PST 24 Feb 07 02:00:18 PM PST 24 262850915 ps
T991 /workspace/coverage/default/6.lc_ctrl_state_post_trans.2717777813 Feb 07 01:58:35 PM PST 24 Feb 07 01:58:44 PM PST 24 102149553 ps
T992 /workspace/coverage/default/5.lc_ctrl_alert_test.774662939 Feb 07 01:58:31 PM PST 24 Feb 07 01:58:34 PM PST 24 108091101 ps

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.896482904
Short name T5
Test name
Test status
Simulation time 29399541898 ps
CPU time 152.98 seconds
Started Feb 07 01:58:24 PM PST 24
Finished Feb 07 02:00:58 PM PST 24
Peak memory 275496 kb
Host smart-f0c027db-2bf4-47cd-877d-66e1c98a4ffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896482904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.896482904
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.152017104
Short name T13
Test name
Test status
Simulation time 1219609088 ps
CPU time 7.99 seconds
Started Feb 07 01:59:43 PM PST 24
Finished Feb 07 01:59:52 PM PST 24
Peak memory 217872 kb
Host smart-a0920cf7-d3ba-4de6-a087-af894f136746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152017104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.152017104
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.269772239
Short name T4
Test name
Test status
Simulation time 479158922 ps
CPU time 11.84 seconds
Started Feb 07 02:00:30 PM PST 24
Finished Feb 07 02:00:43 PM PST 24
Peak memory 217892 kb
Host smart-80129ca1-13c5-462b-8341-17d572ea2a54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269772239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.269772239
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.4204237390
Short name T52
Test name
Test status
Simulation time 20750712946 ps
CPU time 355.44 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 02:04:50 PM PST 24
Peak memory 300196 kb
Host smart-14458f60-9c51-4f66-96a4-b99ab49dfc7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4204237390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.4204237390
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.896248941
Short name T96
Test name
Test status
Simulation time 87175827 ps
CPU time 1.9 seconds
Started Feb 07 01:04:52 PM PST 24
Finished Feb 07 01:04:57 PM PST 24
Peak memory 219364 kb
Host smart-9334bdfd-d701-4e7b-8b81-4eac57ce3c3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896248941 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.896248941
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.421959841
Short name T47
Test name
Test status
Simulation time 314761114 ps
CPU time 13.24 seconds
Started Feb 07 02:00:16 PM PST 24
Finished Feb 07 02:00:30 PM PST 24
Peak memory 217780 kb
Host smart-64551c2a-21a4-4c3f-bf2d-72734673cbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421959841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.421959841
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.429616937
Short name T43
Test name
Test status
Simulation time 14257248 ps
CPU time 0.81 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 01:59:14 PM PST 24
Peak memory 208080 kb
Host smart-3d221e0e-4ce5-4ab7-a4d5-1e612a3d05c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429616937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.429616937
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.765641700
Short name T61
Test name
Test status
Simulation time 784713592 ps
CPU time 35.15 seconds
Started Feb 07 01:58:18 PM PST 24
Finished Feb 07 01:58:54 PM PST 24
Peak memory 280892 kb
Host smart-30f343db-749b-4fea-b97b-9a40574d54d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765641700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.765641700
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3358231875
Short name T143
Test name
Test status
Simulation time 56703426 ps
CPU time 1.96 seconds
Started Feb 07 01:04:39 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 210292 kb
Host smart-3dffdd28-dab8-4d6d-a6a7-203438e391de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358231875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3358231875
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3234980614
Short name T3
Test name
Test status
Simulation time 284212960 ps
CPU time 11.26 seconds
Started Feb 07 02:00:31 PM PST 24
Finished Feb 07 02:00:43 PM PST 24
Peak memory 217876 kb
Host smart-7defd28b-4c52-47d3-87cc-572057f949af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234980614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3234980614
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1782900176
Short name T126
Test name
Test status
Simulation time 136661779 ps
CPU time 4.81 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:41 PM PST 24
Peak memory 217440 kb
Host smart-c938ff6a-22f9-44dc-aafa-e624c172e8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782900176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1782900176
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2402465673
Short name T156
Test name
Test status
Simulation time 1999407409 ps
CPU time 14 seconds
Started Feb 07 01:59:43 PM PST 24
Finished Feb 07 01:59:58 PM PST 24
Peak memory 217792 kb
Host smart-c8fb8cec-0fc2-4f20-931d-59c043e1e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402465673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2402465673
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1193623502
Short name T91
Test name
Test status
Simulation time 134949868 ps
CPU time 1.25 seconds
Started Feb 07 01:04:24 PM PST 24
Finished Feb 07 01:04:26 PM PST 24
Peak memory 209160 kb
Host smart-51bda26c-adf5-4d2b-a7f3-daa475442e1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193623502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1193623502
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.618646329
Short name T114
Test name
Test status
Simulation time 114335341 ps
CPU time 2.16 seconds
Started Feb 07 01:05:49 PM PST 24
Finished Feb 07 01:05:52 PM PST 24
Peak memory 219616 kb
Host smart-856e16e0-a9ef-429b-9cb4-b78fef958a96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618646329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.618646329
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1068595247
Short name T40
Test name
Test status
Simulation time 109006637 ps
CPU time 0.9 seconds
Started Feb 07 01:58:12 PM PST 24
Finished Feb 07 01:58:14 PM PST 24
Peak memory 211156 kb
Host smart-ee6a18ef-1e8f-4eeb-af02-8f0e80ddfc96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068595247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1068595247
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.861792159
Short name T20
Test name
Test status
Simulation time 5315958155 ps
CPU time 100.07 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 275964 kb
Host smart-5b69508d-6f36-43a3-9e02-703e01c4c1eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861792159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.861792159
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.800627655
Short name T395
Test name
Test status
Simulation time 116865979 ps
CPU time 1.22 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 01:59:00 PM PST 24
Peak memory 209408 kb
Host smart-96386137-78fa-4c1b-b8f1-2ddd82c9f777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800627655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.800627655
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3473774059
Short name T51
Test name
Test status
Simulation time 5353880555 ps
CPU time 13.77 seconds
Started Feb 07 01:59:29 PM PST 24
Finished Feb 07 01:59:43 PM PST 24
Peak memory 219240 kb
Host smart-d45d739a-c598-440d-9988-2f0c96ecf4df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473774059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3473774059
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2528002665
Short name T25
Test name
Test status
Simulation time 217003031 ps
CPU time 3.66 seconds
Started Feb 07 01:58:05 PM PST 24
Finished Feb 07 01:58:09 PM PST 24
Peak memory 209472 kb
Host smart-5fe9f9ac-45d9-4e6f-b5f4-185404427a09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528002665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.2528002665
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1902929945
Short name T116
Test name
Test status
Simulation time 107835376 ps
CPU time 3.97 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:42 PM PST 24
Peak memory 217420 kb
Host smart-b95e3a5e-7ef7-41a7-ad00-8fc109875555
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902929945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1902929945
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3531663518
Short name T121
Test name
Test status
Simulation time 563582026 ps
CPU time 3.06 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:41 PM PST 24
Peak memory 221568 kb
Host smart-a609ee27-4253-4419-afd2-02f341292eab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531663518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3531663518
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.757518814
Short name T64
Test name
Test status
Simulation time 58097920853 ps
CPU time 141.06 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 02:00:59 PM PST 24
Peak memory 421592 kb
Host smart-0aa460da-507f-4b65-85a1-7732eb831d47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757518814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.757518814
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2345202231
Short name T122
Test name
Test status
Simulation time 563720571 ps
CPU time 2.96 seconds
Started Feb 07 01:05:48 PM PST 24
Finished Feb 07 01:05:52 PM PST 24
Peak memory 221400 kb
Host smart-66dc648f-b377-4553-a063-42c6e96b12ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345202231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2345202231
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3900858075
Short name T12
Test name
Test status
Simulation time 44656402 ps
CPU time 0.86 seconds
Started Feb 07 02:00:21 PM PST 24
Finished Feb 07 02:00:23 PM PST 24
Peak memory 207624 kb
Host smart-b3396d5a-8b61-4538-be86-395177a87201
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900858075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3900858075
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2038592517
Short name T117
Test name
Test status
Simulation time 198949463 ps
CPU time 2.81 seconds
Started Feb 07 01:04:42 PM PST 24
Finished Feb 07 01:04:49 PM PST 24
Peak memory 221532 kb
Host smart-a0c5f403-30f0-4543-9867-25b005f71b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038592517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2038592517
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1032551332
Short name T165
Test name
Test status
Simulation time 109887344 ps
CPU time 1.47 seconds
Started Feb 07 01:04:53 PM PST 24
Finished Feb 07 01:04:57 PM PST 24
Peak memory 211164 kb
Host smart-15b8754e-832f-4aa1-8639-3d1ec613b68c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032551332 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1032551332
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.551173306
Short name T135
Test name
Test status
Simulation time 395511569 ps
CPU time 3.88 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 217364 kb
Host smart-88607c0d-61db-478f-ad2f-9373de508d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551173306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.551173306
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2251113473
Short name T189
Test name
Test status
Simulation time 23779547 ps
CPU time 0.9 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:58:06 PM PST 24
Peak memory 209324 kb
Host smart-31e4a84d-3185-4cf8-a01f-20966c565197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251113473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2251113473
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2516232212
Short name T188
Test name
Test status
Simulation time 39708770 ps
CPU time 0.81 seconds
Started Feb 07 01:58:08 PM PST 24
Finished Feb 07 01:58:09 PM PST 24
Peak memory 209204 kb
Host smart-9ba17b48-fad4-48e6-8ac7-d36f02a35fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516232212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2516232212
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2615622097
Short name T186
Test name
Test status
Simulation time 36559500 ps
CPU time 0.76 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:18 PM PST 24
Peak memory 209140 kb
Host smart-ecef82a1-2d06-467c-b692-7533decd576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615622097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2615622097
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2522297126
Short name T190
Test name
Test status
Simulation time 12291752 ps
CPU time 0.84 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 209116 kb
Host smart-0fca3669-5c53-44f0-8674-f2f90aa0664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522297126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2522297126
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1258269370
Short name T185
Test name
Test status
Simulation time 55452321 ps
CPU time 0.97 seconds
Started Feb 07 01:58:47 PM PST 24
Finished Feb 07 01:58:49 PM PST 24
Peak memory 209380 kb
Host smart-0ead91de-4a52-4225-bc75-3c521fe98840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258269370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1258269370
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3286710005
Short name T231
Test name
Test status
Simulation time 959966762 ps
CPU time 3.13 seconds
Started Feb 07 01:04:29 PM PST 24
Finished Feb 07 01:04:33 PM PST 24
Peak memory 209032 kb
Host smart-aef58ae4-cf9a-472f-8a8b-43ff2f110178
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286710005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3286710005
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1233250641
Short name T123
Test name
Test status
Simulation time 166128098 ps
CPU time 2.05 seconds
Started Feb 07 01:04:29 PM PST 24
Finished Feb 07 01:04:32 PM PST 24
Peak memory 217440 kb
Host smart-a5873150-ec1e-4ed4-9f89-4a6bbaf28af2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233250641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1233250641
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3975237712
Short name T137
Test name
Test status
Simulation time 63252469 ps
CPU time 2.74 seconds
Started Feb 07 01:05:48 PM PST 24
Finished Feb 07 01:05:52 PM PST 24
Peak memory 217380 kb
Host smart-625afd67-3059-46c0-9d90-6880714de820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975237712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3975237712
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2162226460
Short name T128
Test name
Test status
Simulation time 425934830 ps
CPU time 2.85 seconds
Started Feb 07 01:05:48 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 221180 kb
Host smart-1643f057-c722-4209-ad3b-8752244251a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162226460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2162226460
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.189665833
Short name T136
Test name
Test status
Simulation time 427335923 ps
CPU time 1.88 seconds
Started Feb 07 01:05:55 PM PST 24
Finished Feb 07 01:05:58 PM PST 24
Peak memory 221084 kb
Host smart-8172dd02-ca50-49f7-8307-69cd31bf1de9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189665833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.189665833
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4235695202
Short name T139
Test name
Test status
Simulation time 1267532314 ps
CPU time 3.5 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:40 PM PST 24
Peak memory 221564 kb
Host smart-5c9080d2-9394-4343-accb-998910df99c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235695202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.4235695202
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1911834622
Short name T57
Test name
Test status
Simulation time 67119988762 ps
CPU time 355.92 seconds
Started Feb 07 01:59:00 PM PST 24
Finished Feb 07 02:05:02 PM PST 24
Peak memory 281328 kb
Host smart-ab830f80-16e8-425b-9d75-f770e55aa70c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1911834622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.1911834622
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2338894269
Short name T55
Test name
Test status
Simulation time 253089028299 ps
CPU time 4009.12 seconds
Started Feb 07 01:59:31 PM PST 24
Finished Feb 07 03:06:21 PM PST 24
Peak memory 660692 kb
Host smart-7336da51-ac23-49cd-a13e-fad374e3f794
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2338894269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2338894269
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3463291515
Short name T2
Test name
Test status
Simulation time 322925597 ps
CPU time 9.64 seconds
Started Feb 07 01:59:47 PM PST 24
Finished Feb 07 01:59:57 PM PST 24
Peak memory 217412 kb
Host smart-8ec729fe-4415-414a-900f-25765b567b05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463291515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3463291515
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1940313748
Short name T269
Test name
Test status
Simulation time 199676704 ps
CPU time 1.4 seconds
Started Feb 07 01:04:26 PM PST 24
Finished Feb 07 01:04:28 PM PST 24
Peak memory 209136 kb
Host smart-b78de45e-6ad5-4367-835b-1e03fb3552af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940313748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1940313748
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2689410973
Short name T180
Test name
Test status
Simulation time 46557135 ps
CPU time 0.92 seconds
Started Feb 07 01:04:27 PM PST 24
Finished Feb 07 01:04:28 PM PST 24
Peak memory 209296 kb
Host smart-b51e6d49-2fa1-43c1-8bb5-01475803f016
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689410973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2689410973
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3995874701
Short name T195
Test name
Test status
Simulation time 51359094 ps
CPU time 1.12 seconds
Started Feb 07 01:04:28 PM PST 24
Finished Feb 07 01:04:30 PM PST 24
Peak memory 217388 kb
Host smart-77fbf6b6-d397-42a9-b451-76a2d8f9c0a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995874701 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3995874701
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3577891087
Short name T159
Test name
Test status
Simulation time 14985019 ps
CPU time 0.9 seconds
Started Feb 07 01:04:24 PM PST 24
Finished Feb 07 01:04:25 PM PST 24
Peak memory 209044 kb
Host smart-c0625086-561e-48b4-a81a-9c5b925bffb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577891087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3577891087
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2133512414
Short name T266
Test name
Test status
Simulation time 92137842 ps
CPU time 0.91 seconds
Started Feb 07 01:04:24 PM PST 24
Finished Feb 07 01:04:26 PM PST 24
Peak memory 208916 kb
Host smart-6d976edc-4dca-4ba0-b97b-1696abde17db
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133512414 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2133512414
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.292584220
Short name T264
Test name
Test status
Simulation time 430808241 ps
CPU time 11.14 seconds
Started Feb 07 01:04:25 PM PST 24
Finished Feb 07 01:04:37 PM PST 24
Peak memory 208008 kb
Host smart-56242b2b-8dc8-4702-ad43-23ceec143796
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292584220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.292584220
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2720128968
Short name T249
Test name
Test status
Simulation time 3624437455 ps
CPU time 20.45 seconds
Started Feb 07 01:04:25 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 209144 kb
Host smart-6a5f6db8-6050-46ce-8266-3839eb1653a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720128968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2720128968
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1162032912
Short name T284
Test name
Test status
Simulation time 82758306 ps
CPU time 2.51 seconds
Started Feb 07 01:04:25 PM PST 24
Finished Feb 07 01:04:29 PM PST 24
Peak memory 210484 kb
Host smart-603f37ae-4a15-4f45-aded-1bd53a8c2fd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162032912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1162032912
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2013056865
Short name T147
Test name
Test status
Simulation time 46616325 ps
CPU time 1.37 seconds
Started Feb 07 01:04:25 PM PST 24
Finished Feb 07 01:04:27 PM PST 24
Peak memory 218560 kb
Host smart-d35cde05-2174-41bd-91bf-b6febcc5de0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201305
6865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2013056865
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1678372522
Short name T286
Test name
Test status
Simulation time 20718180 ps
CPU time 1.42 seconds
Started Feb 07 01:04:24 PM PST 24
Finished Feb 07 01:04:26 PM PST 24
Peak memory 209288 kb
Host smart-889a5d67-5a6f-4f69-868d-5e9bc853f53d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678372522 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1678372522
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3793372398
Short name T280
Test name
Test status
Simulation time 149147339 ps
CPU time 1.47 seconds
Started Feb 07 01:04:26 PM PST 24
Finished Feb 07 01:04:28 PM PST 24
Peak memory 211252 kb
Host smart-a3d9dc6c-9707-4e21-873b-5b8bf91bf412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793372398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3793372398
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3426324569
Short name T275
Test name
Test status
Simulation time 171214359 ps
CPU time 3.11 seconds
Started Feb 07 01:04:26 PM PST 24
Finished Feb 07 01:04:30 PM PST 24
Peak memory 217984 kb
Host smart-4e385ce8-1738-4246-a829-7c539cad966b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426324569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3426324569
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3861700478
Short name T130
Test name
Test status
Simulation time 131972964 ps
CPU time 2.57 seconds
Started Feb 07 01:04:29 PM PST 24
Finished Feb 07 01:04:33 PM PST 24
Peak memory 217444 kb
Host smart-ea2bb5bc-e8a8-416a-8ef7-a846e0f1ac13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861700478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3861700478
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.505320785
Short name T161
Test name
Test status
Simulation time 14516320 ps
CPU time 1 seconds
Started Feb 07 01:04:36 PM PST 24
Finished Feb 07 01:04:43 PM PST 24
Peak memory 209172 kb
Host smart-35b53d82-0155-477f-a468-36d5c3ddaf9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505320785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.505320785
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1226868146
Short name T242
Test name
Test status
Simulation time 50480450 ps
CPU time 1.97 seconds
Started Feb 07 01:04:27 PM PST 24
Finished Feb 07 01:04:30 PM PST 24
Peak memory 209092 kb
Host smart-1c2b7db0-a3f0-4f06-85bc-498091560267
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226868146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1226868146
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2306276170
Short name T170
Test name
Test status
Simulation time 55475545 ps
CPU time 1.03 seconds
Started Feb 07 01:05:30 PM PST 24
Finished Feb 07 01:05:32 PM PST 24
Peak memory 209088 kb
Host smart-03010ec8-89cc-489d-8439-2d6d5a60642b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306276170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2306276170
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3664239550
Short name T287
Test name
Test status
Simulation time 104994621 ps
CPU time 1.05 seconds
Started Feb 07 01:04:36 PM PST 24
Finished Feb 07 01:04:42 PM PST 24
Peak memory 217464 kb
Host smart-3ff58e3a-1189-4af4-b1a5-e9a12e6d7f7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664239550 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3664239550
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4166521835
Short name T118
Test name
Test status
Simulation time 53166939 ps
CPU time 1.01 seconds
Started Feb 07 01:04:27 PM PST 24
Finished Feb 07 01:04:28 PM PST 24
Peak memory 208400 kb
Host smart-6076f22d-4bb4-436b-b460-54376e0d75f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166521835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.4166521835
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.875905334
Short name T302
Test name
Test status
Simulation time 67885602 ps
CPU time 0.97 seconds
Started Feb 07 01:04:29 PM PST 24
Finished Feb 07 01:04:31 PM PST 24
Peak memory 209068 kb
Host smart-50ea9d4f-1815-4e94-904c-be7fe9ead58b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875905334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.875905334
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1568473044
Short name T244
Test name
Test status
Simulation time 776563254 ps
CPU time 5.85 seconds
Started Feb 07 01:04:32 PM PST 24
Finished Feb 07 01:04:42 PM PST 24
Peak memory 209084 kb
Host smart-9e156d6e-557d-48c0-99c8-b84ba06f3141
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568473044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1568473044
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1081288784
Short name T145
Test name
Test status
Simulation time 1209458102 ps
CPU time 27.38 seconds
Started Feb 07 01:04:28 PM PST 24
Finished Feb 07 01:04:56 PM PST 24
Peak memory 208036 kb
Host smart-b1788ae4-d618-4716-9c99-55448972ece6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081288784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1081288784
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1028212749
Short name T211
Test name
Test status
Simulation time 119016460 ps
CPU time 1.83 seconds
Started Feb 07 01:04:27 PM PST 24
Finished Feb 07 01:04:29 PM PST 24
Peak memory 210420 kb
Host smart-093e3f59-05c2-48b3-bdd5-b5a5b5935980
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028212749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1028212749
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2087093288
Short name T291
Test name
Test status
Simulation time 50384311 ps
CPU time 1.84 seconds
Started Feb 07 01:04:29 PM PST 24
Finished Feb 07 01:04:32 PM PST 24
Peak memory 217492 kb
Host smart-8dd7bf5f-7666-4904-a3a6-049bf7c14788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208709
3288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2087093288
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.680926972
Short name T214
Test name
Test status
Simulation time 159632297 ps
CPU time 2.23 seconds
Started Feb 07 01:04:25 PM PST 24
Finished Feb 07 01:04:28 PM PST 24
Peak memory 208872 kb
Host smart-f2cf1a40-6782-4df4-bb16-6f110adff16c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680926972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.680926972
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2246615285
Short name T245
Test name
Test status
Simulation time 110036006 ps
CPU time 1.08 seconds
Started Feb 07 01:04:29 PM PST 24
Finished Feb 07 01:04:32 PM PST 24
Peak memory 208552 kb
Host smart-a05dc282-9995-4a1b-b069-bdc1df33185e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246615285 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2246615285
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1825180414
Short name T155
Test name
Test status
Simulation time 84436106 ps
CPU time 1.84 seconds
Started Feb 07 01:04:47 PM PST 24
Finished Feb 07 01:04:56 PM PST 24
Peak memory 209256 kb
Host smart-6ab196be-38d3-44eb-b583-f4ca934073b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825180414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1825180414
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4080425075
Short name T209
Test name
Test status
Simulation time 161229371 ps
CPU time 2.48 seconds
Started Feb 07 01:05:30 PM PST 24
Finished Feb 07 01:05:33 PM PST 24
Peak memory 218312 kb
Host smart-e07d9cb0-e30a-4c9b-ad1a-2fc881abc4f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080425075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.4080425075
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4103914609
Short name T228
Test name
Test status
Simulation time 80753645 ps
CPU time 1.21 seconds
Started Feb 07 01:05:47 PM PST 24
Finished Feb 07 01:05:49 PM PST 24
Peak memory 219084 kb
Host smart-20036b01-e813-46fe-8512-ac36fa62fd56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103914609 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4103914609
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3511952811
Short name T216
Test name
Test status
Simulation time 25745793 ps
CPU time 1.02 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 209116 kb
Host smart-7b983fae-b97c-4f58-b131-741cce139704
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511952811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3511952811
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3774094895
Short name T250
Test name
Test status
Simulation time 407621342 ps
CPU time 1.11 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 208872 kb
Host smart-f5dd6d2a-1fe5-4b53-8dec-3ac75a8b267a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774094895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3774094895
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2632655075
Short name T92
Test name
Test status
Simulation time 95545112 ps
CPU time 2.62 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:41 PM PST 24
Peak memory 217416 kb
Host smart-6536b147-8dcb-4653-a03d-1f126ee36a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632655075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2632655075
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1098332971
Short name T219
Test name
Test status
Simulation time 16277451 ps
CPU time 1.24 seconds
Started Feb 07 01:05:54 PM PST 24
Finished Feb 07 01:05:56 PM PST 24
Peak memory 218460 kb
Host smart-3c294add-f7aa-4437-b411-065e6bf346e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098332971 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1098332971
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2202324241
Short name T169
Test name
Test status
Simulation time 28459792 ps
CPU time 0.88 seconds
Started Feb 07 01:05:49 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 208592 kb
Host smart-8806284f-5f61-493d-accb-b28721de1c48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202324241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2202324241
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.73373473
Short name T263
Test name
Test status
Simulation time 96168415 ps
CPU time 1.02 seconds
Started Feb 07 01:05:50 PM PST 24
Finished Feb 07 01:05:52 PM PST 24
Peak memory 209220 kb
Host smart-2400d77f-8c7c-437d-b691-4ae5642e219d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73373473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
same_csr_outstanding.73373473
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3716613245
Short name T300
Test name
Test status
Simulation time 27890008 ps
CPU time 2.13 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:40 PM PST 24
Peak memory 217460 kb
Host smart-0766c009-f36c-4041-862f-894f73460384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716613245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3716613245
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.801008677
Short name T261
Test name
Test status
Simulation time 21444357 ps
CPU time 1.13 seconds
Started Feb 07 01:05:51 PM PST 24
Finished Feb 07 01:05:53 PM PST 24
Peak memory 219180 kb
Host smart-806a6400-af12-426c-a77c-9d0991eede51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801008677 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.801008677
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4231385486
Short name T179
Test name
Test status
Simulation time 14564486 ps
CPU time 0.87 seconds
Started Feb 07 01:05:46 PM PST 24
Finished Feb 07 01:05:47 PM PST 24
Peak memory 209144 kb
Host smart-5c53ec34-7033-4005-8027-da70e6995043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231385486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.4231385486
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.808566078
Short name T150
Test name
Test status
Simulation time 24593084 ps
CPU time 1.16 seconds
Started Feb 07 01:05:50 PM PST 24
Finished Feb 07 01:05:52 PM PST 24
Peak memory 209228 kb
Host smart-d48a3c3a-a5df-4b5e-b5cb-59b058d52bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808566078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.808566078
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.720604055
Short name T217
Test name
Test status
Simulation time 421061920 ps
CPU time 3.07 seconds
Started Feb 07 01:05:54 PM PST 24
Finished Feb 07 01:05:58 PM PST 24
Peak memory 217372 kb
Host smart-19208efb-46d5-482f-be64-ebe4c204c337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720604055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.720604055
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1359378119
Short name T288
Test name
Test status
Simulation time 28373098 ps
CPU time 1.07 seconds
Started Feb 07 01:05:49 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 217544 kb
Host smart-d20d9076-c618-49c8-a438-1ec79c01f0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359378119 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1359378119
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2489974148
Short name T177
Test name
Test status
Simulation time 42722604 ps
CPU time 0.83 seconds
Started Feb 07 01:05:53 PM PST 24
Finished Feb 07 01:05:55 PM PST 24
Peak memory 208972 kb
Host smart-475f1c98-c0fc-46c8-a2a8-f93032b5fa2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489974148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2489974148
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2521067173
Short name T218
Test name
Test status
Simulation time 39444893 ps
CPU time 1.4 seconds
Started Feb 07 01:05:49 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 208952 kb
Host smart-58091e7f-ec22-4a28-bea9-0b3ba59ea43b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521067173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2521067173
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3491154306
Short name T124
Test name
Test status
Simulation time 1651085779 ps
CPU time 4.63 seconds
Started Feb 07 01:05:47 PM PST 24
Finished Feb 07 01:05:52 PM PST 24
Peak memory 217380 kb
Host smart-b848f930-9cb9-46f6-975a-a594d39c99b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491154306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3491154306
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1279019316
Short name T132
Test name
Test status
Simulation time 113402128 ps
CPU time 2.29 seconds
Started Feb 07 01:05:48 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 217480 kb
Host smart-75935542-ec84-4e6b-916c-41e50df8cac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279019316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1279019316
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3271020433
Short name T277
Test name
Test status
Simulation time 27715437 ps
CPU time 1.65 seconds
Started Feb 07 01:05:51 PM PST 24
Finished Feb 07 01:05:54 PM PST 24
Peak memory 217428 kb
Host smart-35f61711-0aa8-4c60-aee7-b022d741ffcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271020433 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3271020433
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.646349594
Short name T196
Test name
Test status
Simulation time 54922872 ps
CPU time 1.02 seconds
Started Feb 07 01:05:54 PM PST 24
Finished Feb 07 01:05:56 PM PST 24
Peak memory 209112 kb
Host smart-fa09048e-9b07-4c0b-90cd-75451afc3b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646349594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.646349594
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.795940118
Short name T237
Test name
Test status
Simulation time 26647464 ps
CPU time 1.01 seconds
Started Feb 07 01:05:49 PM PST 24
Finished Feb 07 01:05:50 PM PST 24
Peak memory 208320 kb
Host smart-503b7ae0-b169-4d2c-94c4-74516575a5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795940118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.795940118
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3443336845
Short name T257
Test name
Test status
Simulation time 437113713 ps
CPU time 3.26 seconds
Started Feb 07 01:05:55 PM PST 24
Finished Feb 07 01:05:59 PM PST 24
Peak memory 217500 kb
Host smart-72132779-704d-45cd-b156-fc36641b633b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443336845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3443336845
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1191968002
Short name T138
Test name
Test status
Simulation time 68942785 ps
CPU time 2.61 seconds
Started Feb 07 01:05:54 PM PST 24
Finished Feb 07 01:05:58 PM PST 24
Peak memory 217024 kb
Host smart-5d44b701-8f8c-4921-b52c-ac72089dbe77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191968002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1191968002
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2744801298
Short name T207
Test name
Test status
Simulation time 45111461 ps
CPU time 1.61 seconds
Started Feb 07 01:05:55 PM PST 24
Finished Feb 07 01:05:58 PM PST 24
Peak memory 217420 kb
Host smart-9047fb1d-ac91-45d0-8186-935fa3046ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744801298 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2744801298
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3653329495
Short name T183
Test name
Test status
Simulation time 11624640 ps
CPU time 0.81 seconds
Started Feb 07 01:05:48 PM PST 24
Finished Feb 07 01:05:49 PM PST 24
Peak memory 208988 kb
Host smart-fb690fc5-cb09-4db9-9f33-9b9ed6f484ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653329495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3653329495
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3326979915
Short name T299
Test name
Test status
Simulation time 52014122 ps
CPU time 1.06 seconds
Started Feb 07 01:05:49 PM PST 24
Finished Feb 07 01:05:50 PM PST 24
Peak memory 209260 kb
Host smart-74d0159c-9ce3-4a42-990d-0219b0ee955c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326979915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3326979915
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2876474177
Short name T115
Test name
Test status
Simulation time 359914194 ps
CPU time 2.73 seconds
Started Feb 07 01:05:48 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 217364 kb
Host smart-f8022c5b-ee32-4739-8843-0374f15d85ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876474177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2876474177
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3506911267
Short name T140
Test name
Test status
Simulation time 522555728 ps
CPU time 1.84 seconds
Started Feb 07 01:05:49 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 220856 kb
Host smart-142a7231-a12b-4148-9396-662f07958057
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506911267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3506911267
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2513875977
Short name T163
Test name
Test status
Simulation time 24551937 ps
CPU time 1.45 seconds
Started Feb 07 01:05:46 PM PST 24
Finished Feb 07 01:05:48 PM PST 24
Peak memory 217456 kb
Host smart-75f87c3a-e2d3-4b50-8d51-4b7944e06cf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513875977 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2513875977
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3546047391
Short name T160
Test name
Test status
Simulation time 13937028 ps
CPU time 0.89 seconds
Started Feb 07 01:05:54 PM PST 24
Finished Feb 07 01:05:56 PM PST 24
Peak memory 209096 kb
Host smart-d932ab25-fb49-4806-a11e-96b04b64bd7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546047391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3546047391
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3285577390
Short name T276
Test name
Test status
Simulation time 23919983 ps
CPU time 1.11 seconds
Started Feb 07 01:05:50 PM PST 24
Finished Feb 07 01:05:53 PM PST 24
Peak memory 209232 kb
Host smart-f3fdf101-6959-4b4d-bf61-fd1a40218aef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285577390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3285577390
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1497188324
Short name T125
Test name
Test status
Simulation time 50290237 ps
CPU time 1.47 seconds
Started Feb 07 01:05:50 PM PST 24
Finished Feb 07 01:05:53 PM PST 24
Peak memory 209220 kb
Host smart-935c52f3-3da1-454c-a108-aa7fcdeccca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497188324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1497188324
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.4208023016
Short name T212
Test name
Test status
Simulation time 183196030 ps
CPU time 1.69 seconds
Started Feb 07 01:05:50 PM PST 24
Finished Feb 07 01:05:52 PM PST 24
Peak memory 217612 kb
Host smart-48105f4a-9549-4c02-8e41-b1d7f72d7326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208023016 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.4208023016
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.894526653
Short name T221
Test name
Test status
Simulation time 11357273 ps
CPU time 0.87 seconds
Started Feb 07 01:05:49 PM PST 24
Finished Feb 07 01:05:50 PM PST 24
Peak memory 209028 kb
Host smart-61ba46dd-55ce-40ae-b13c-21f4acf82e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894526653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.894526653
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2498957105
Short name T182
Test name
Test status
Simulation time 22556215 ps
CPU time 1.46 seconds
Started Feb 07 01:05:48 PM PST 24
Finished Feb 07 01:05:50 PM PST 24
Peak memory 209188 kb
Host smart-62893c3b-8851-4f6b-9f58-593700811fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498957105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2498957105
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.147614893
Short name T267
Test name
Test status
Simulation time 401576771 ps
CPU time 4.31 seconds
Started Feb 07 01:05:54 PM PST 24
Finished Feb 07 01:05:59 PM PST 24
Peak memory 217492 kb
Host smart-329c9461-8110-4099-84e3-54a9fa435519
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147614893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.147614893
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.345713702
Short name T133
Test name
Test status
Simulation time 321203376 ps
CPU time 2.77 seconds
Started Feb 07 01:05:44 PM PST 24
Finished Feb 07 01:05:47 PM PST 24
Peak memory 212808 kb
Host smart-ce15df7a-4d66-400c-95d0-fed1d2886376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345713702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.345713702
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3168905541
Short name T239
Test name
Test status
Simulation time 108515647 ps
CPU time 1.53 seconds
Started Feb 07 01:05:51 PM PST 24
Finished Feb 07 01:05:53 PM PST 24
Peak memory 219056 kb
Host smart-851c8ab7-8f02-45f9-be93-29b114442ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168905541 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3168905541
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3047621477
Short name T174
Test name
Test status
Simulation time 128360139 ps
CPU time 0.85 seconds
Started Feb 07 01:05:55 PM PST 24
Finished Feb 07 01:05:56 PM PST 24
Peak memory 209064 kb
Host smart-b0798e4f-7424-47e9-a55a-4c88bb42dd83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047621477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3047621477
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3155200867
Short name T246
Test name
Test status
Simulation time 26128294 ps
CPU time 1.25 seconds
Started Feb 07 01:05:51 PM PST 24
Finished Feb 07 01:05:53 PM PST 24
Peak memory 210816 kb
Host smart-6a84f020-96a5-40d8-8151-c463eccaa660
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155200867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3155200867
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2097108559
Short name T202
Test name
Test status
Simulation time 68688151 ps
CPU time 2.39 seconds
Started Feb 07 01:05:48 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 217848 kb
Host smart-bdd16420-fc08-4007-9688-514dc86eaa63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097108559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2097108559
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1569241602
Short name T129
Test name
Test status
Simulation time 216611679 ps
CPU time 1.89 seconds
Started Feb 07 01:05:54 PM PST 24
Finished Feb 07 01:05:57 PM PST 24
Peak memory 221264 kb
Host smart-d871e095-b95c-483b-be28-6c76bc567ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569241602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1569241602
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.406724286
Short name T97
Test name
Test status
Simulation time 115917636 ps
CPU time 1.57 seconds
Started Feb 07 01:05:55 PM PST 24
Finished Feb 07 01:05:57 PM PST 24
Peak memory 218988 kb
Host smart-4a36dc65-433e-4aeb-83ec-02b615d9c999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406724286 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.406724286
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.850474165
Short name T220
Test name
Test status
Simulation time 46580019 ps
CPU time 0.93 seconds
Started Feb 07 01:05:51 PM PST 24
Finished Feb 07 01:05:53 PM PST 24
Peak memory 209164 kb
Host smart-dafdb391-adb0-4e63-b052-5b15b4ddd21a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850474165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.850474165
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1345816170
Short name T151
Test name
Test status
Simulation time 61668678 ps
CPU time 1.31 seconds
Started Feb 07 01:05:55 PM PST 24
Finished Feb 07 01:05:57 PM PST 24
Peak memory 209260 kb
Host smart-42b091ca-a60e-4fff-b34a-597d61e80c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345816170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1345816170
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.700874557
Short name T223
Test name
Test status
Simulation time 167034128 ps
CPU time 3.37 seconds
Started Feb 07 01:05:54 PM PST 24
Finished Feb 07 01:05:59 PM PST 24
Peak memory 216968 kb
Host smart-668c0833-7204-4d50-a351-ae66460d971d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700874557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.700874557
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1839900092
Short name T166
Test name
Test status
Simulation time 57058899 ps
CPU time 1.54 seconds
Started Feb 07 01:04:37 PM PST 24
Finished Feb 07 01:04:45 PM PST 24
Peak memory 209104 kb
Host smart-f5c09863-2343-4acc-b794-d6ab6385ad41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839900092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1839900092
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1554362495
Short name T273
Test name
Test status
Simulation time 105068284 ps
CPU time 1.45 seconds
Started Feb 07 01:04:39 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 209112 kb
Host smart-b969a567-12e1-4040-a629-0e275c267ca4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554362495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1554362495
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1488157912
Short name T162
Test name
Test status
Simulation time 23040556 ps
CPU time 0.89 seconds
Started Feb 07 01:04:41 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 209056 kb
Host smart-e0ffbc95-c28a-4737-b36d-ec1a1dfee3a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488157912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1488157912
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3340754944
Short name T215
Test name
Test status
Simulation time 13523839 ps
CPU time 1.1 seconds
Started Feb 07 01:04:37 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 217580 kb
Host smart-f581f712-04f6-4019-81c8-0fca0cc207b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340754944 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3340754944
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3349903607
Short name T230
Test name
Test status
Simulation time 15109183 ps
CPU time 0.89 seconds
Started Feb 07 01:04:38 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 208572 kb
Host smart-328d4a37-ab53-4c35-bfb5-c5a1fe831208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349903607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3349903607
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4232863123
Short name T297
Test name
Test status
Simulation time 103815434 ps
CPU time 1.05 seconds
Started Feb 07 01:04:41 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 209016 kb
Host smart-51e6a0fc-61cc-4cdd-a6fe-e684c35a7303
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232863123 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4232863123
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2995602223
Short name T149
Test name
Test status
Simulation time 3010658619 ps
CPU time 22.96 seconds
Started Feb 07 01:04:36 PM PST 24
Finished Feb 07 01:05:04 PM PST 24
Peak memory 208172 kb
Host smart-bd736492-4eb4-43a6-a3cb-3f54e9a08c3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995602223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2995602223
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1537130293
Short name T222
Test name
Test status
Simulation time 815712083 ps
CPU time 4.62 seconds
Started Feb 07 01:04:37 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 209040 kb
Host smart-6119836d-d683-49f7-868a-3cd325709955
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537130293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1537130293
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1778700701
Short name T294
Test name
Test status
Simulation time 847694263 ps
CPU time 1.99 seconds
Started Feb 07 01:04:45 PM PST 24
Finished Feb 07 01:04:56 PM PST 24
Peak memory 210164 kb
Host smart-aca1976a-3733-4c40-9933-af4e33f2d4cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778700701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1778700701
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2671719677
Short name T232
Test name
Test status
Simulation time 64944247 ps
CPU time 1.72 seconds
Started Feb 07 01:04:39 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 218392 kb
Host smart-7a0391f2-9158-40c5-9a0e-ff252bb0b8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267171
9677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2671719677
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2051545589
Short name T240
Test name
Test status
Simulation time 141974784 ps
CPU time 2.08 seconds
Started Feb 07 01:04:39 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 209080 kb
Host smart-8f2f9f82-6fee-4b5a-bb4a-aa24501f085a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051545589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2051545589
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2130861045
Short name T260
Test name
Test status
Simulation time 58897221 ps
CPU time 1.03 seconds
Started Feb 07 01:04:42 PM PST 24
Finished Feb 07 01:04:49 PM PST 24
Peak memory 209244 kb
Host smart-e75fd4a4-b9ac-4024-86d9-0687e70bad13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130861045 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2130861045
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3996787868
Short name T119
Test name
Test status
Simulation time 286943416 ps
CPU time 1.87 seconds
Started Feb 07 01:04:39 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 209168 kb
Host smart-d4621d33-1b6c-4885-b353-119128cd2da2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996787868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3996787868
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3519107175
Short name T90
Test name
Test status
Simulation time 156457866 ps
CPU time 3.07 seconds
Started Feb 07 01:04:47 PM PST 24
Finished Feb 07 01:04:58 PM PST 24
Peak memory 217348 kb
Host smart-43718c2b-48e9-4d6c-b298-9a4df8e4fb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519107175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3519107175
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.796996054
Short name T131
Test name
Test status
Simulation time 83783910 ps
CPU time 1.89 seconds
Started Feb 07 01:04:38 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 220820 kb
Host smart-f6915b53-722b-40f0-a1bb-405dffbee702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796996054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.796996054
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4256198135
Short name T181
Test name
Test status
Simulation time 108370894 ps
CPU time 0.95 seconds
Started Feb 07 01:04:36 PM PST 24
Finished Feb 07 01:04:42 PM PST 24
Peak memory 208392 kb
Host smart-ccad2b91-fa0e-49ef-8732-117fc774e905
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256198135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4256198135
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2726685336
Short name T154
Test name
Test status
Simulation time 599375888 ps
CPU time 1.71 seconds
Started Feb 07 01:04:39 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 209220 kb
Host smart-9b0ff8cf-83b5-4b5f-a38f-e4b681dbedfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726685336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2726685336
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1239424867
Short name T171
Test name
Test status
Simulation time 53826461 ps
CPU time 0.95 seconds
Started Feb 07 01:04:37 PM PST 24
Finished Feb 07 01:04:44 PM PST 24
Peak memory 209300 kb
Host smart-8ccfef5f-ffde-45b3-9bf1-5f19902a11ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239424867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1239424867
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1593348253
Short name T283
Test name
Test status
Simulation time 92880614 ps
CPU time 0.91 seconds
Started Feb 07 01:04:39 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 208608 kb
Host smart-f9699e82-8500-4892-8a60-db5526f8942c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593348253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1593348253
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1973829563
Short name T274
Test name
Test status
Simulation time 36650711 ps
CPU time 1.19 seconds
Started Feb 07 01:04:38 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 209028 kb
Host smart-cff4035b-8f91-4ca1-a393-a09d7e1ac563
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973829563 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1973829563
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2985402574
Short name T164
Test name
Test status
Simulation time 1644135119 ps
CPU time 10.03 seconds
Started Feb 07 01:04:45 PM PST 24
Finished Feb 07 01:05:04 PM PST 24
Peak memory 209052 kb
Host smart-9e325821-5ce1-4911-b841-fc2a68a30c8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985402574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2985402574
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.851843459
Short name T213
Test name
Test status
Simulation time 343459747 ps
CPU time 8.85 seconds
Started Feb 07 01:04:46 PM PST 24
Finished Feb 07 01:05:03 PM PST 24
Peak memory 209116 kb
Host smart-e647a4f2-9e53-45aa-aa05-ff83b874d414
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851843459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.851843459
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1145513350
Short name T201
Test name
Test status
Simulation time 34426110 ps
CPU time 1.34 seconds
Started Feb 07 01:04:38 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 217552 kb
Host smart-6d6d02d0-a261-422f-af42-7c33890bde1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114551
3350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1145513350
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.319121660
Short name T293
Test name
Test status
Simulation time 376883908 ps
CPU time 1.46 seconds
Started Feb 07 01:04:41 PM PST 24
Finished Feb 07 01:04:47 PM PST 24
Peak memory 209048 kb
Host smart-d8faad18-62b2-40e5-b54c-1b494cdbb169
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319121660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.319121660
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2660954852
Short name T281
Test name
Test status
Simulation time 68688015 ps
CPU time 1.19 seconds
Started Feb 07 01:04:41 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 208816 kb
Host smart-ec67f2a2-aedc-47d6-acd8-e7d2f5ebadd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660954852 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2660954852
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1779069081
Short name T285
Test name
Test status
Simulation time 83626352 ps
CPU time 1.03 seconds
Started Feb 07 01:04:41 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 209260 kb
Host smart-f72ad3c7-774c-4ba4-90fc-c61edf76629d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779069081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1779069081
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1489999701
Short name T270
Test name
Test status
Simulation time 127298449 ps
CPU time 3.32 seconds
Started Feb 07 01:04:41 PM PST 24
Finished Feb 07 01:04:49 PM PST 24
Peak memory 217364 kb
Host smart-5e8217a2-f9bf-426e-80b6-5db7e66da8c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489999701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1489999701
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.741912238
Short name T298
Test name
Test status
Simulation time 20804464 ps
CPU time 1.24 seconds
Started Feb 07 01:04:55 PM PST 24
Finished Feb 07 01:04:59 PM PST 24
Peak memory 209124 kb
Host smart-74e1da55-dc11-444c-94d2-b8c5d8017786
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741912238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.741912238
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1694832054
Short name T225
Test name
Test status
Simulation time 122055775 ps
CPU time 1.96 seconds
Started Feb 07 01:04:50 PM PST 24
Finished Feb 07 01:04:57 PM PST 24
Peak memory 209156 kb
Host smart-96565003-049d-4038-a6f1-a1bee634ac1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694832054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1694832054
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1656635059
Short name T176
Test name
Test status
Simulation time 131898785 ps
CPU time 0.91 seconds
Started Feb 07 01:04:57 PM PST 24
Finished Feb 07 01:05:00 PM PST 24
Peak memory 209228 kb
Host smart-864edb91-f73e-4e3d-b76d-e658acf82940
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656635059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1656635059
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2347524424
Short name T100
Test name
Test status
Simulation time 36593031 ps
CPU time 1.42 seconds
Started Feb 07 01:04:51 PM PST 24
Finished Feb 07 01:04:57 PM PST 24
Peak memory 218016 kb
Host smart-389aa25f-4dff-4928-b140-382475b2a7fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347524424 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2347524424
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1290273503
Short name T172
Test name
Test status
Simulation time 20421634 ps
CPU time 0.87 seconds
Started Feb 07 01:04:50 PM PST 24
Finished Feb 07 01:04:56 PM PST 24
Peak memory 209100 kb
Host smart-45c8a199-eff2-4872-8c6b-6a3ad641270e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290273503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1290273503
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2863241153
Short name T142
Test name
Test status
Simulation time 167746630 ps
CPU time 0.95 seconds
Started Feb 07 01:04:57 PM PST 24
Finished Feb 07 01:05:00 PM PST 24
Peak memory 207448 kb
Host smart-81acade8-b079-4506-892c-363f32c10274
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863241153 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2863241153
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.624651679
Short name T238
Test name
Test status
Simulation time 392904181 ps
CPU time 9.17 seconds
Started Feb 07 01:04:53 PM PST 24
Finished Feb 07 01:05:04 PM PST 24
Peak memory 207372 kb
Host smart-179b0141-be0e-40b3-89c3-e948cabbe3e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624651679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.624651679
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3978403167
Short name T278
Test name
Test status
Simulation time 1460554481 ps
CPU time 31.31 seconds
Started Feb 07 01:04:51 PM PST 24
Finished Feb 07 01:05:26 PM PST 24
Peak memory 208084 kb
Host smart-c40ad695-4d7f-46f1-8048-a3497e02fdb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978403167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3978403167
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.243198530
Short name T253
Test name
Test status
Simulation time 179983509 ps
CPU time 1.77 seconds
Started Feb 07 01:04:55 PM PST 24
Finished Feb 07 01:05:00 PM PST 24
Peak memory 209052 kb
Host smart-67d96e5b-c532-4cdf-86a8-32a101e812ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243198530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.243198530
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3659347649
Short name T262
Test name
Test status
Simulation time 218514800 ps
CPU time 2.05 seconds
Started Feb 07 01:04:55 PM PST 24
Finished Feb 07 01:05:00 PM PST 24
Peak memory 218608 kb
Host smart-c73493f2-85e8-4044-a35c-28f9381af7ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365934
7649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3659347649
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2697167407
Short name T268
Test name
Test status
Simulation time 42081313 ps
CPU time 1.68 seconds
Started Feb 07 01:04:56 PM PST 24
Finished Feb 07 01:05:00 PM PST 24
Peak memory 209036 kb
Host smart-36b6397e-358b-49f3-84cf-1a5ea49a690c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697167407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2697167407
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3846965605
Short name T272
Test name
Test status
Simulation time 62852801 ps
CPU time 1.16 seconds
Started Feb 07 01:04:56 PM PST 24
Finished Feb 07 01:05:00 PM PST 24
Peak memory 209220 kb
Host smart-fe7ac068-adea-4ff1-b2f5-68779a1f55ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846965605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3846965605
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3731514346
Short name T292
Test name
Test status
Simulation time 50787926 ps
CPU time 1.89 seconds
Started Feb 07 01:04:51 PM PST 24
Finished Feb 07 01:04:57 PM PST 24
Peak memory 217388 kb
Host smart-63220592-8ceb-41cc-a6c9-32c53ec1fb39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731514346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3731514346
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.761416951
Short name T134
Test name
Test status
Simulation time 75307187 ps
CPU time 3.17 seconds
Started Feb 07 01:04:52 PM PST 24
Finished Feb 07 01:04:58 PM PST 24
Peak memory 217420 kb
Host smart-4dd8f146-db36-4197-8d4b-1074d0d565a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761416951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.761416951
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3850642799
Short name T210
Test name
Test status
Simulation time 13736525 ps
CPU time 1.14 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 217536 kb
Host smart-2f4b228c-0fab-4415-aaf1-b5282bb3ff28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850642799 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3850642799
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1059064862
Short name T178
Test name
Test status
Simulation time 45107157 ps
CPU time 0.9 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 209036 kb
Host smart-fabed481-9d76-4417-976e-f4c0ce7e0edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059064862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1059064862
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1472630770
Short name T200
Test name
Test status
Simulation time 53742740 ps
CPU time 1.94 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 209040 kb
Host smart-fbc895fd-ff37-440d-a9d9-d479327b8d29
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472630770 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1472630770
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2243852974
Short name T206
Test name
Test status
Simulation time 1102417659 ps
CPU time 12.44 seconds
Started Feb 07 01:04:54 PM PST 24
Finished Feb 07 01:05:10 PM PST 24
Peak memory 208032 kb
Host smart-5d9db503-bb2c-4010-8e36-459335112643
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243852974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2243852974
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3405553682
Short name T233
Test name
Test status
Simulation time 3625625778 ps
CPU time 21.54 seconds
Started Feb 07 01:04:52 PM PST 24
Finished Feb 07 01:05:17 PM PST 24
Peak memory 208088 kb
Host smart-db3604e5-556f-4a5f-a301-ac6ce31c8154
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405553682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3405553682
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3829391021
Short name T146
Test name
Test status
Simulation time 87579590 ps
CPU time 2.69 seconds
Started Feb 07 01:04:53 PM PST 24
Finished Feb 07 01:04:58 PM PST 24
Peak memory 210304 kb
Host smart-617045d1-2392-46d7-8518-a37d87e14f5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829391021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3829391021
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3382948688
Short name T144
Test name
Test status
Simulation time 68892137 ps
CPU time 1.25 seconds
Started Feb 07 01:04:50 PM PST 24
Finished Feb 07 01:04:56 PM PST 24
Peak memory 217576 kb
Host smart-9e6d7214-d8c3-4a5d-9651-4ee8547785ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338294
8688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3382948688
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.62242090
Short name T258
Test name
Test status
Simulation time 405702829 ps
CPU time 1.52 seconds
Started Feb 07 01:04:51 PM PST 24
Finished Feb 07 01:04:57 PM PST 24
Peak memory 208996 kb
Host smart-b5153804-b887-4a72-8dc8-31988b8767c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62242090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 5.lc_ctrl_jtag_csr_rw.62242090
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3586490647
Short name T282
Test name
Test status
Simulation time 168897191 ps
CPU time 1.38 seconds
Started Feb 07 01:04:51 PM PST 24
Finished Feb 07 01:04:56 PM PST 24
Peak memory 208828 kb
Host smart-28b20676-e842-4a76-ac19-ee94f3ba91b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586490647 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3586490647
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4215499720
Short name T251
Test name
Test status
Simulation time 18506250 ps
CPU time 1.23 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 209172 kb
Host smart-efd39886-09b1-4979-838a-fddf73376d1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215499720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.4215499720
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1850842530
Short name T127
Test name
Test status
Simulation time 210503756 ps
CPU time 3.1 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:40 PM PST 24
Peak memory 217364 kb
Host smart-5d5a22ca-175e-4063-8d81-4c82be8f8e96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850842530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1850842530
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2080227698
Short name T224
Test name
Test status
Simulation time 137165227 ps
CPU time 2.19 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 219092 kb
Host smart-55c274c3-e0f4-440e-963e-39db522a788e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080227698 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2080227698
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1858544683
Short name T197
Test name
Test status
Simulation time 153280505 ps
CPU time 0.89 seconds
Started Feb 07 01:05:32 PM PST 24
Finished Feb 07 01:05:33 PM PST 24
Peak memory 209020 kb
Host smart-121b40f1-402d-4b39-b354-5cdb013e2b1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858544683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1858544683
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.913956690
Short name T205
Test name
Test status
Simulation time 116958998 ps
CPU time 3.32 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 207532 kb
Host smart-df7a73f2-54fc-4815-a336-550a5fae1f03
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913956690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.913956690
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2294128488
Short name T243
Test name
Test status
Simulation time 365743500 ps
CPU time 9.71 seconds
Started Feb 07 01:05:32 PM PST 24
Finished Feb 07 01:05:42 PM PST 24
Peak memory 209060 kb
Host smart-1ef2cfb8-cc0c-4625-a050-22161eeba427
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294128488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2294128488
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.568475144
Short name T203
Test name
Test status
Simulation time 879086763 ps
CPU time 6.09 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:41 PM PST 24
Peak memory 209052 kb
Host smart-b4eb1888-8751-45e5-ab18-14d02a5e886a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568475144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.568475144
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4237253788
Short name T226
Test name
Test status
Simulation time 194245036 ps
CPU time 1.93 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 210384 kb
Host smart-d3bb2722-9418-4be9-a224-042fd4c8e514
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237253788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4237253788
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1319528700
Short name T259
Test name
Test status
Simulation time 55723982 ps
CPU time 1.15 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 217784 kb
Host smart-eb73c38d-d0ee-4179-97f3-d141236db351
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131952
8700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1319528700
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2033476717
Short name T296
Test name
Test status
Simulation time 65035076 ps
CPU time 2.04 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:40 PM PST 24
Peak memory 209040 kb
Host smart-0bec0f7a-aa46-4fc2-b288-2f3cfbd52d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033476717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2033476717
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.907769032
Short name T295
Test name
Test status
Simulation time 22901264 ps
CPU time 1.42 seconds
Started Feb 07 01:05:32 PM PST 24
Finished Feb 07 01:05:34 PM PST 24
Peak memory 211140 kb
Host smart-d89da79b-3214-41c2-a00f-2de5bb6bc2aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907769032 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.907769032
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2359703280
Short name T252
Test name
Test status
Simulation time 21891024 ps
CPU time 1.19 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 209200 kb
Host smart-a5890599-d0b1-4e60-824c-c6e333105e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359703280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2359703280
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2572795466
Short name T120
Test name
Test status
Simulation time 218038424 ps
CPU time 3.37 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:40 PM PST 24
Peak memory 217392 kb
Host smart-c06a485d-3397-4e9b-abcf-1b2a5658871f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572795466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2572795466
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1534527852
Short name T204
Test name
Test status
Simulation time 17438716 ps
CPU time 1.49 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 218536 kb
Host smart-b1c9592f-8ddb-48d0-83fa-92e01ed0be04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534527852 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1534527852
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2449457620
Short name T168
Test name
Test status
Simulation time 22883637 ps
CPU time 0.97 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:36 PM PST 24
Peak memory 209120 kb
Host smart-37838fbe-1dda-4dcd-96b7-70256731f03d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449457620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2449457620
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1425625961
Short name T248
Test name
Test status
Simulation time 38322782 ps
CPU time 1.52 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 209048 kb
Host smart-ef777f5f-a526-4dae-aafc-bb1c49374df2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425625961 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1425625961
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.599265253
Short name T256
Test name
Test status
Simulation time 1964607727 ps
CPU time 5.24 seconds
Started Feb 07 01:05:44 PM PST 24
Finished Feb 07 01:05:49 PM PST 24
Peak memory 208044 kb
Host smart-1bd19d89-cd32-4da1-abc9-0aee26bed949
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599265253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.599265253
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2464559846
Short name T99
Test name
Test status
Simulation time 8026631582 ps
CPU time 15.87 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:51 PM PST 24
Peak memory 209236 kb
Host smart-d0f14e1d-27b2-43bd-87fc-f55232d46cb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464559846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2464559846
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.215025218
Short name T208
Test name
Test status
Simulation time 234086747 ps
CPU time 2.02 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 210384 kb
Host smart-3fa7891e-bbf4-4595-b4a6-49375ceed8d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215025218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.215025218
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2766748644
Short name T141
Test name
Test status
Simulation time 37711778 ps
CPU time 1.83 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 217448 kb
Host smart-248b93b3-72e3-4ef3-8d0b-50e14dba3435
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276674
8644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2766748644
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2931618025
Short name T279
Test name
Test status
Simulation time 168951659 ps
CPU time 1.96 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 209028 kb
Host smart-d646c274-2919-48ac-a07e-7a2af99d96cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931618025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2931618025
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3089450959
Short name T184
Test name
Test status
Simulation time 90422006 ps
CPU time 1.34 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:36 PM PST 24
Peak memory 209220 kb
Host smart-f98bdea0-cb8c-4cd4-978e-83c62022360a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089450959 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3089450959
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4093540968
Short name T148
Test name
Test status
Simulation time 29475647 ps
CPU time 1.14 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 209124 kb
Host smart-6d40abd1-7faa-432e-9645-e11d19a179b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093540968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4093540968
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1656740319
Short name T247
Test name
Test status
Simulation time 84367121 ps
CPU time 2.55 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 217404 kb
Host smart-ae9957ed-ff42-4d81-be99-a12a89ce3f92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656740319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1656740319
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.720201421
Short name T175
Test name
Test status
Simulation time 91318222 ps
CPU time 1.25 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 218736 kb
Host smart-a7161dea-42d8-461d-9d64-b9ddafa87ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720201421 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.720201421
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3414768029
Short name T289
Test name
Test status
Simulation time 52273591 ps
CPU time 0.96 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 209148 kb
Host smart-63913e3e-b2e6-4d14-9dd6-8632e2f86cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414768029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3414768029
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1885619301
Short name T290
Test name
Test status
Simulation time 66156467 ps
CPU time 2.05 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 209016 kb
Host smart-9d241df3-6eda-45e2-b2fa-b7155bb260fa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885619301 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1885619301
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2398570560
Short name T98
Test name
Test status
Simulation time 904750238 ps
CPU time 2.94 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:40 PM PST 24
Peak memory 209076 kb
Host smart-200a4184-fe95-4091-84de-8e5d0281a47d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398570560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2398570560
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.143600440
Short name T271
Test name
Test status
Simulation time 5627902343 ps
CPU time 9.86 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:47 PM PST 24
Peak memory 208964 kb
Host smart-93a7e20d-90a1-4ebc-938a-9455c1274203
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143600440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.143600440
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.839878283
Short name T152
Test name
Test status
Simulation time 409546901 ps
CPU time 2.47 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:40 PM PST 24
Peak memory 210404 kb
Host smart-95adcc9a-9e1d-4cc0-ae7e-981fe508ff87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839878283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.839878283
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3624037409
Short name T255
Test name
Test status
Simulation time 124042085 ps
CPU time 2.15 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 217488 kb
Host smart-2c274928-dded-4b61-9be3-0d403b73dc7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362403
7409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3624037409
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.783642546
Short name T303
Test name
Test status
Simulation time 357744121 ps
CPU time 2.21 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 209012 kb
Host smart-fa6cbd1d-ca77-4e38-8407-87c454509344
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783642546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.783642546
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2622393034
Short name T254
Test name
Test status
Simulation time 85680382 ps
CPU time 1.35 seconds
Started Feb 07 01:05:32 PM PST 24
Finished Feb 07 01:05:34 PM PST 24
Peak memory 209320 kb
Host smart-fa2d5756-3ee5-4c5c-91fb-dac240c6298e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622393034 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2622393034
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4249158774
Short name T167
Test name
Test status
Simulation time 41366783 ps
CPU time 1.35 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:36 PM PST 24
Peak memory 210896 kb
Host smart-d9f95df9-8a0e-43c0-ba23-3c86cb062f1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249158774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4249158774
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1548607672
Short name T265
Test name
Test status
Simulation time 363353926 ps
CPU time 1.79 seconds
Started Feb 07 01:05:34 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 217368 kb
Host smart-26022f30-ce3b-4719-a4f0-3f883b21bcf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548607672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1548607672
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.257472191
Short name T229
Test name
Test status
Simulation time 172676234 ps
CPU time 1.8 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 217176 kb
Host smart-1b74bf62-0a31-4813-a62e-0d682853140f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257472191 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.257472191
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2874973778
Short name T173
Test name
Test status
Simulation time 16295496 ps
CPU time 0.9 seconds
Started Feb 07 01:05:42 PM PST 24
Finished Feb 07 01:05:43 PM PST 24
Peak memory 208400 kb
Host smart-69163be9-ca57-40a4-a08e-e60b67149120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874973778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2874973778
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4273557765
Short name T235
Test name
Test status
Simulation time 466482414 ps
CPU time 1.11 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 207472 kb
Host smart-e7e5cc7f-bbd9-4e37-bdbd-e4079268df26
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273557765 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.4273557765
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.739095701
Short name T153
Test name
Test status
Simulation time 362517677 ps
CPU time 9.39 seconds
Started Feb 07 01:05:33 PM PST 24
Finished Feb 07 01:05:44 PM PST 24
Peak memory 209088 kb
Host smart-91f06f7e-4427-46be-80bc-9d181aa3a117
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739095701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.739095701
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3065754556
Short name T227
Test name
Test status
Simulation time 3260654053 ps
CPU time 6.8 seconds
Started Feb 07 01:05:37 PM PST 24
Finished Feb 07 01:05:45 PM PST 24
Peak memory 208108 kb
Host smart-099e76dc-5255-4ebf-b0a4-daecbd71d602
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065754556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3065754556
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2771695852
Short name T301
Test name
Test status
Simulation time 285387313 ps
CPU time 4.84 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:41 PM PST 24
Peak memory 210536 kb
Host smart-6e0e702e-0f22-4037-b5ed-c287da65a09d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771695852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2771695852
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3801492264
Short name T236
Test name
Test status
Simulation time 51068365 ps
CPU time 2.01 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 217928 kb
Host smart-c69a14cc-3fbd-4d10-b6c9-ef648020cda0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380149
2264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3801492264
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3497043689
Short name T198
Test name
Test status
Simulation time 68533485 ps
CPU time 1.33 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:38 PM PST 24
Peak memory 209036 kb
Host smart-09373af5-7680-4f4f-b67b-53abf898a1e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497043689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3497043689
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4290353086
Short name T234
Test name
Test status
Simulation time 35680797 ps
CPU time 1.76 seconds
Started Feb 07 01:05:36 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 210908 kb
Host smart-dad12856-b50d-463c-a048-b92d6df5ac4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290353086 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.4290353086
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.323170093
Short name T241
Test name
Test status
Simulation time 16019503 ps
CPU time 1 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 208728 kb
Host smart-82590d74-3689-4e6b-b708-a512438730b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323170093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.323170093
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2445942818
Short name T199
Test name
Test status
Simulation time 77998972 ps
CPU time 2.1 seconds
Started Feb 07 01:05:35 PM PST 24
Finished Feb 07 01:05:39 PM PST 24
Peak memory 217332 kb
Host smart-b11d1638-6193-46ca-a3fa-076b7a58c0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445942818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2445942818
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.23332814
Short name T846
Test name
Test status
Simulation time 15066022 ps
CPU time 0.82 seconds
Started Feb 07 01:58:12 PM PST 24
Finished Feb 07 01:58:14 PM PST 24
Peak memory 209152 kb
Host smart-962f0493-c899-48ab-93e4-93c323f99879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.23332814
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.772371539
Short name T772
Test name
Test status
Simulation time 1185087099 ps
CPU time 13.28 seconds
Started Feb 07 01:58:02 PM PST 24
Finished Feb 07 01:58:17 PM PST 24
Peak memory 217820 kb
Host smart-df83cf84-3bec-4b3d-88a8-60b2ac287e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772371539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.772371539
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3891526544
Short name T547
Test name
Test status
Simulation time 9039980350 ps
CPU time 70.42 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:59:15 PM PST 24
Peak memory 217872 kb
Host smart-555423b3-bf58-44ea-85db-3bbb4d76fc23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891526544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3891526544
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1802696999
Short name T885
Test name
Test status
Simulation time 471813770 ps
CPU time 2.11 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:58:08 PM PST 24
Peak memory 209488 kb
Host smart-c5087910-a1e7-41d9-a986-6b30e6c10d18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802696999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.1802696999
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.703068127
Short name T588
Test name
Test status
Simulation time 2260809236 ps
CPU time 8.3 seconds
Started Feb 07 01:57:59 PM PST 24
Finished Feb 07 01:58:09 PM PST 24
Peak memory 217856 kb
Host smart-9c090c93-f225-452c-9bef-0b2ed938d490
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703068127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.703068127
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.197035189
Short name T761
Test name
Test status
Simulation time 1116813357 ps
CPU time 18.32 seconds
Started Feb 07 01:58:00 PM PST 24
Finished Feb 07 01:58:20 PM PST 24
Peak memory 212856 kb
Host smart-c5c5d22b-96ae-4237-9f0d-4466702d2f20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197035189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.197035189
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1105707329
Short name T85
Test name
Test status
Simulation time 296565847 ps
CPU time 5.06 seconds
Started Feb 07 01:58:00 PM PST 24
Finished Feb 07 01:58:06 PM PST 24
Peak memory 213124 kb
Host smart-5cb4f95c-c5a8-4b88-8340-e6e6ec4f80a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105707329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1105707329
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1566995649
Short name T679
Test name
Test status
Simulation time 15247531069 ps
CPU time 69.06 seconds
Started Feb 07 01:58:02 PM PST 24
Finished Feb 07 01:59:13 PM PST 24
Peak memory 283604 kb
Host smart-fc44a64b-a96a-47d9-87de-838bf79331b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566995649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1566995649
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4173348189
Short name T410
Test name
Test status
Simulation time 3763946495 ps
CPU time 28.17 seconds
Started Feb 07 01:58:03 PM PST 24
Finished Feb 07 01:58:33 PM PST 24
Peak memory 245648 kb
Host smart-6d686a27-cc93-4d19-b2b4-2109a8971ed7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173348189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.4173348189
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.640375416
Short name T392
Test name
Test status
Simulation time 224619796 ps
CPU time 2.57 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:04 PM PST 24
Peak memory 217804 kb
Host smart-731ca7cc-d8f3-4950-9b82-668100f072e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640375416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.640375416
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.742390290
Short name T626
Test name
Test status
Simulation time 978775099 ps
CPU time 9.88 seconds
Started Feb 07 01:58:02 PM PST 24
Finished Feb 07 01:58:14 PM PST 24
Peak memory 213936 kb
Host smart-61a2e07a-693d-42e0-a189-c486e360e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742390290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.742390290
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2690048352
Short name T60
Test name
Test status
Simulation time 391067569 ps
CPU time 34.53 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 268856 kb
Host smart-2a858d9f-c73e-4713-b3ac-2a144cba82ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690048352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2690048352
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1578810635
Short name T363
Test name
Test status
Simulation time 4843743009 ps
CPU time 13.61 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:58:19 PM PST 24
Peak memory 219040 kb
Host smart-05429ddb-ce39-4024-90f6-15f24b2ebe6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578810635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1578810635
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3349920072
Short name T32
Test name
Test status
Simulation time 179177164 ps
CPU time 8.81 seconds
Started Feb 07 01:58:03 PM PST 24
Finished Feb 07 01:58:13 PM PST 24
Peak memory 217884 kb
Host smart-6412752a-9585-4d17-8bc2-c1b2a6f67640
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349920072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3349920072
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3680138130
Short name T532
Test name
Test status
Simulation time 470534413 ps
CPU time 6.66 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:58:12 PM PST 24
Peak memory 217792 kb
Host smart-20bcb8a8-d115-4c8a-84f8-3d68900c036b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680138130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
680138130
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.196505720
Short name T672
Test name
Test status
Simulation time 1310276698 ps
CPU time 9.23 seconds
Started Feb 07 01:58:00 PM PST 24
Finished Feb 07 01:58:10 PM PST 24
Peak memory 217848 kb
Host smart-ff359d2d-9868-4968-922d-22c2c08e1924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196505720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.196505720
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3704886368
Short name T360
Test name
Test status
Simulation time 328473882 ps
CPU time 3.66 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:58:09 PM PST 24
Peak memory 214252 kb
Host smart-1b199ad4-65c1-4eee-8cac-c9e4e0e17a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704886368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3704886368
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3457758313
Short name T462
Test name
Test status
Simulation time 263654564 ps
CPU time 31.12 seconds
Started Feb 07 01:58:03 PM PST 24
Finished Feb 07 01:58:36 PM PST 24
Peak memory 250012 kb
Host smart-c771452f-b264-460c-9dcf-e772649ec712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457758313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3457758313
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1728073275
Short name T738
Test name
Test status
Simulation time 60733302 ps
CPU time 7.53 seconds
Started Feb 07 01:58:02 PM PST 24
Finished Feb 07 01:58:12 PM PST 24
Peak memory 250884 kb
Host smart-29d57e0a-f877-4f7f-9285-c0391dc0ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728073275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1728073275
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3259034069
Short name T713
Test name
Test status
Simulation time 2533822522 ps
CPU time 10.07 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:58:15 PM PST 24
Peak memory 217732 kb
Host smart-165267e4-5adf-481d-85dc-114d733f8db9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259034069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3259034069
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.366027396
Short name T492
Test name
Test status
Simulation time 71689737 ps
CPU time 1.01 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:03 PM PST 24
Peak memory 212320 kb
Host smart-1ce646a3-5ecb-47b8-b740-0d622a940e19
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366027396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.366027396
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3261083388
Short name T689
Test name
Test status
Simulation time 387460413 ps
CPU time 1.21 seconds
Started Feb 07 01:58:13 PM PST 24
Finished Feb 07 01:58:15 PM PST 24
Peak memory 208240 kb
Host smart-8376c04d-eb12-4a8a-bbd4-f68438ef19e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261083388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3261083388
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2654575235
Short name T105
Test name
Test status
Simulation time 100655229 ps
CPU time 0.81 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:18 PM PST 24
Peak memory 209212 kb
Host smart-b5b30377-17f0-4b8e-8bc0-12c4c261c509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654575235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2654575235
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1942217838
Short name T536
Test name
Test status
Simulation time 606529552 ps
CPU time 12.2 seconds
Started Feb 07 01:58:18 PM PST 24
Finished Feb 07 01:58:31 PM PST 24
Peak memory 217800 kb
Host smart-fb4449ae-679b-4a83-a5b6-bfe87445bef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942217838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1942217838
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1292410123
Short name T28
Test name
Test status
Simulation time 6703790209 ps
CPU time 8.12 seconds
Started Feb 07 01:58:15 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 209524 kb
Host smart-2c57207b-8b63-4896-bcb5-e51e828dc2e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292410123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.1292410123
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.821643998
Short name T421
Test name
Test status
Simulation time 4674711107 ps
CPU time 32.06 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 217172 kb
Host smart-61e4da35-6c7f-48e2-adc8-ef4e42e67e9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821643998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.821643998
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1834247669
Short name T461
Test name
Test status
Simulation time 4905003906 ps
CPU time 9.48 seconds
Started Feb 07 01:58:09 PM PST 24
Finished Feb 07 01:58:19 PM PST 24
Peak memory 217780 kb
Host smart-3e582feb-48a0-4f9f-927c-7b92e2a595e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834247669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.1834247669
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3648268815
Short name T890
Test name
Test status
Simulation time 644364348 ps
CPU time 17.38 seconds
Started Feb 07 01:58:14 PM PST 24
Finished Feb 07 01:58:32 PM PST 24
Peak memory 217740 kb
Host smart-177af519-8de5-4468-bf1d-7bd99eebbe73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648268815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3648268815
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3661258109
Short name T866
Test name
Test status
Simulation time 1870901410 ps
CPU time 13.59 seconds
Started Feb 07 01:58:11 PM PST 24
Finished Feb 07 01:58:25 PM PST 24
Peak memory 212712 kb
Host smart-67e745e2-47e3-46c5-9fd1-6b22eae0fbb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661258109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3661258109
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2612312138
Short name T381
Test name
Test status
Simulation time 710653554 ps
CPU time 7.83 seconds
Started Feb 07 01:58:10 PM PST 24
Finished Feb 07 01:58:18 PM PST 24
Peak memory 213236 kb
Host smart-6170cfc2-8a5c-4f4c-b193-f1c12624b97b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612312138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2612312138
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1133753236
Short name T19
Test name
Test status
Simulation time 16412207091 ps
CPU time 47.03 seconds
Started Feb 07 01:58:07 PM PST 24
Finished Feb 07 01:58:55 PM PST 24
Peak memory 268020 kb
Host smart-c848535f-35d8-49aa-a8e1-c8b1834a9961
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133753236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1133753236
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.883788604
Short name T724
Test name
Test status
Simulation time 346236684 ps
CPU time 12.16 seconds
Started Feb 07 01:58:09 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 250788 kb
Host smart-2188467b-e548-4ab2-b950-a665de20dfa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883788604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.883788604
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.993775337
Short name T457
Test name
Test status
Simulation time 56054393 ps
CPU time 2.64 seconds
Started Feb 07 01:58:11 PM PST 24
Finished Feb 07 01:58:14 PM PST 24
Peak memory 217824 kb
Host smart-ee1fd598-9002-45a3-930c-491565a6da02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993775337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.993775337
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3085635322
Short name T86
Test name
Test status
Simulation time 1151604293 ps
CPU time 11.45 seconds
Started Feb 07 01:58:11 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 213972 kb
Host smart-af2f49e9-c71d-456d-9396-9c76841b112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085635322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3085635322
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4065133933
Short name T101
Test name
Test status
Simulation time 117458948 ps
CPU time 24.96 seconds
Started Feb 07 01:58:15 PM PST 24
Finished Feb 07 01:58:41 PM PST 24
Peak memory 281604 kb
Host smart-aef50ff5-ce83-4f3c-98ef-63246b5da95f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065133933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4065133933
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4245467775
Short name T917
Test name
Test status
Simulation time 1628814831 ps
CPU time 12.48 seconds
Started Feb 07 01:58:09 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 218280 kb
Host smart-4f29d14a-5f83-462e-80ff-b9bd9c26a795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245467775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4245467775
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3284884815
Short name T657
Test name
Test status
Simulation time 328608387 ps
CPU time 10.81 seconds
Started Feb 07 01:58:07 PM PST 24
Finished Feb 07 01:58:19 PM PST 24
Peak memory 217836 kb
Host smart-961e8e28-7171-4b8d-98fa-576b200412e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284884815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3284884815
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1029819628
Short name T384
Test name
Test status
Simulation time 190636476 ps
CPU time 7.71 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:25 PM PST 24
Peak memory 217820 kb
Host smart-edf84a5a-9778-4bab-96f3-206ead23167f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029819628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
029819628
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1731465221
Short name T794
Test name
Test status
Simulation time 306975261 ps
CPU time 13.15 seconds
Started Feb 07 01:58:14 PM PST 24
Finished Feb 07 01:58:28 PM PST 24
Peak memory 217776 kb
Host smart-16e5682a-b3f5-4e17-87bb-0fb787269335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731465221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1731465221
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3377391936
Short name T449
Test name
Test status
Simulation time 1161607655 ps
CPU time 5.07 seconds
Started Feb 07 01:58:11 PM PST 24
Finished Feb 07 01:58:16 PM PST 24
Peak memory 214160 kb
Host smart-5a3a10c8-7e88-4746-b621-68616f4fc5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377391936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3377391936
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2971342601
Short name T456
Test name
Test status
Simulation time 260860360 ps
CPU time 24.84 seconds
Started Feb 07 01:58:12 PM PST 24
Finished Feb 07 01:58:37 PM PST 24
Peak memory 250820 kb
Host smart-ba874602-b0d8-421a-9ce7-c77f0ab9bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971342601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2971342601
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1962121673
Short name T880
Test name
Test status
Simulation time 380483997 ps
CPU time 3.62 seconds
Started Feb 07 01:58:13 PM PST 24
Finished Feb 07 01:58:18 PM PST 24
Peak memory 221660 kb
Host smart-d830dd8f-c902-4d1a-ad1b-ba9d4abd47d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962121673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1962121673
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.135702244
Short name T593
Test name
Test status
Simulation time 6565696952 ps
CPU time 222.66 seconds
Started Feb 07 01:58:15 PM PST 24
Finished Feb 07 02:01:58 PM PST 24
Peak memory 250792 kb
Host smart-7aefae8b-b847-40e2-b0c5-c28e36c90af4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135702244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.135702244
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2956550107
Short name T346
Test name
Test status
Simulation time 12324088 ps
CPU time 0.84 seconds
Started Feb 07 01:58:13 PM PST 24
Finished Feb 07 01:58:14 PM PST 24
Peak memory 208104 kb
Host smart-72c7c9e4-8350-4a09-b8d6-362fc454f340
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956550107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2956550107
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2027403843
Short name T852
Test name
Test status
Simulation time 40701404 ps
CPU time 0.84 seconds
Started Feb 07 01:58:55 PM PST 24
Finished Feb 07 01:58:57 PM PST 24
Peak memory 209208 kb
Host smart-2f96f70c-fc3a-47e6-9a80-3800bd13501f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027403843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2027403843
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1322605631
Short name T868
Test name
Test status
Simulation time 797442751 ps
CPU time 14.42 seconds
Started Feb 07 01:58:55 PM PST 24
Finished Feb 07 01:59:10 PM PST 24
Peak memory 217780 kb
Host smart-1a7eb9c0-49ab-4b3f-8d80-8c40390b1cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322605631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1322605631
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.763897771
Short name T586
Test name
Test status
Simulation time 508693860 ps
CPU time 6.51 seconds
Started Feb 07 01:58:50 PM PST 24
Finished Feb 07 01:58:57 PM PST 24
Peak memory 209480 kb
Host smart-b1ec5b5b-ebda-4505-bc70-ca4778bfe724
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763897771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_ac
cess.763897771
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.669648019
Short name T680
Test name
Test status
Simulation time 10816266466 ps
CPU time 64.28 seconds
Started Feb 07 01:58:50 PM PST 24
Finished Feb 07 01:59:55 PM PST 24
Peak memory 218360 kb
Host smart-bf5658ac-f16e-45ed-b69b-aad17646ec10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669648019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.669648019
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1815593610
Short name T955
Test name
Test status
Simulation time 560212646 ps
CPU time 3.35 seconds
Started Feb 07 01:58:48 PM PST 24
Finished Feb 07 01:58:52 PM PST 24
Peak memory 217804 kb
Host smart-8b04b226-7341-4155-9fce-ad687835cbbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815593610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1815593610
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3998998739
Short name T76
Test name
Test status
Simulation time 1835675611 ps
CPU time 7.65 seconds
Started Feb 07 01:58:51 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 213332 kb
Host smart-a03ffd25-c259-4c49-a6e2-792e7f4aad39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998998739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3998998739
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2137324903
Short name T886
Test name
Test status
Simulation time 17479986973 ps
CPU time 33.97 seconds
Started Feb 07 01:58:49 PM PST 24
Finished Feb 07 01:59:24 PM PST 24
Peak memory 250812 kb
Host smart-6214a53e-2c34-4506-b098-3c561aebe7b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137324903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2137324903
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.528179460
Short name T892
Test name
Test status
Simulation time 724665288 ps
CPU time 15.38 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 01:59:10 PM PST 24
Peak memory 250664 kb
Host smart-d511438f-086b-427b-8191-80286b606e71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528179460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.528179460
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.649169852
Short name T888
Test name
Test status
Simulation time 61718987 ps
CPU time 2.43 seconds
Started Feb 07 01:58:49 PM PST 24
Finished Feb 07 01:58:52 PM PST 24
Peak memory 217852 kb
Host smart-a910de63-f652-4185-91f9-151fd7f5f87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649169852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.649169852
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.649569087
Short name T937
Test name
Test status
Simulation time 837703271 ps
CPU time 19.53 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 01:59:14 PM PST 24
Peak memory 218804 kb
Host smart-8c2334cc-a337-4798-98f2-d7f495c95b7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649569087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.649569087
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.179626513
Short name T351
Test name
Test status
Simulation time 685215294 ps
CPU time 9.89 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 01:59:05 PM PST 24
Peak memory 217752 kb
Host smart-9bc41962-fdeb-4b4a-b5ee-b1490b327f84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179626513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.179626513
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.745308297
Short name T578
Test name
Test status
Simulation time 364360067 ps
CPU time 10.32 seconds
Started Feb 07 01:58:55 PM PST 24
Finished Feb 07 01:59:06 PM PST 24
Peak memory 217820 kb
Host smart-3da5b1e6-fd76-409f-8de8-985cc75c9073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745308297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.745308297
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1695632301
Short name T59
Test name
Test status
Simulation time 333495210 ps
CPU time 12.31 seconds
Started Feb 07 01:58:49 PM PST 24
Finished Feb 07 01:59:02 PM PST 24
Peak memory 217760 kb
Host smart-04dc2890-617b-4194-8458-611f0efc987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695632301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1695632301
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2332489551
Short name T71
Test name
Test status
Simulation time 452958236 ps
CPU time 2.95 seconds
Started Feb 07 01:58:50 PM PST 24
Finished Feb 07 01:58:53 PM PST 24
Peak memory 213912 kb
Host smart-3207030c-9e3b-448c-bf71-f91613863ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332489551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2332489551
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1129926640
Short name T329
Test name
Test status
Simulation time 245973954 ps
CPU time 20.6 seconds
Started Feb 07 01:58:46 PM PST 24
Finished Feb 07 01:59:07 PM PST 24
Peak memory 250808 kb
Host smart-4e2183f8-bb39-4e5c-a3d7-9d8a0093d368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129926640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1129926640
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3617164674
Short name T730
Test name
Test status
Simulation time 83174998 ps
CPU time 7.47 seconds
Started Feb 07 01:58:49 PM PST 24
Finished Feb 07 01:58:57 PM PST 24
Peak memory 250444 kb
Host smart-761d19f1-1f62-49b6-85d4-f710d2cce9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617164674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3617164674
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2587716213
Short name T751
Test name
Test status
Simulation time 863257265 ps
CPU time 34.38 seconds
Started Feb 07 01:58:52 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 250160 kb
Host smart-d44b3050-1fe3-4c8c-99d3-04db5b43faa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587716213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2587716213
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1270771415
Short name T48
Test name
Test status
Simulation time 53837437 ps
CPU time 0.9 seconds
Started Feb 07 01:58:47 PM PST 24
Finished Feb 07 01:58:49 PM PST 24
Peak memory 212236 kb
Host smart-9dadc706-41c3-49e4-82df-6f1da1efa088
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270771415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1270771415
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1130762163
Short name T710
Test name
Test status
Simulation time 28325116 ps
CPU time 1.26 seconds
Started Feb 07 01:59:00 PM PST 24
Finished Feb 07 01:59:07 PM PST 24
Peak memory 209412 kb
Host smart-a0ea7d63-e35b-4890-bcb6-eaf6fb0b61cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130762163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1130762163
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2682749936
Short name T583
Test name
Test status
Simulation time 274014893 ps
CPU time 11.24 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:17 PM PST 24
Peak memory 217860 kb
Host smart-aec62bbf-3f62-45b9-aadb-65f18f092894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682749936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2682749936
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1677371616
Short name T608
Test name
Test status
Simulation time 3202275395 ps
CPU time 7.91 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:13 PM PST 24
Peak memory 209528 kb
Host smart-61118cd7-2f67-4203-b323-b49b63cc81cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677371616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.1677371616
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.177683090
Short name T412
Test name
Test status
Simulation time 3823015883 ps
CPU time 27.53 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:33 PM PST 24
Peak memory 217792 kb
Host smart-6b1a985a-39cf-4d05-9292-f59a8b9aff82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177683090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.177683090
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4200047736
Short name T477
Test name
Test status
Simulation time 415855186 ps
CPU time 12.52 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 01:59:15 PM PST 24
Peak memory 217776 kb
Host smart-2e27e6a9-60d7-4c87-b585-ae33cb99ea20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200047736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4200047736
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3140172858
Short name T933
Test name
Test status
Simulation time 4098388369 ps
CPU time 5.83 seconds
Started Feb 07 01:59:02 PM PST 24
Finished Feb 07 01:59:12 PM PST 24
Peak memory 213396 kb
Host smart-4e667d52-80c2-44b3-b580-666ed11861e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140172858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3140172858
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2330119531
Short name T21
Test name
Test status
Simulation time 1495174525 ps
CPU time 45.25 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:51 PM PST 24
Peak memory 276672 kb
Host smart-c8a7a7c0-e140-430d-b277-d60eec1785b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330119531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2330119531
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.163447517
Short name T590
Test name
Test status
Simulation time 616796553 ps
CPU time 17.56 seconds
Started Feb 07 01:59:03 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 249528 kb
Host smart-2ad222a8-fc79-4c22-b69c-c6d60c5d1fc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163447517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.163447517
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3361089419
Short name T733
Test name
Test status
Simulation time 92135172 ps
CPU time 2.19 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:08 PM PST 24
Peak memory 217756 kb
Host smart-da40e334-354a-42b5-a900-a266a0cb262c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361089419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3361089419
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1531331006
Short name T762
Test name
Test status
Simulation time 659445557 ps
CPU time 16.1 seconds
Started Feb 07 01:59:00 PM PST 24
Finished Feb 07 01:59:22 PM PST 24
Peak memory 218368 kb
Host smart-080eca8a-755b-4188-8f15-036e9292489c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531331006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1531331006
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3763639581
Short name T879
Test name
Test status
Simulation time 749558399 ps
CPU time 10.77 seconds
Started Feb 07 01:59:00 PM PST 24
Finished Feb 07 01:59:17 PM PST 24
Peak memory 217808 kb
Host smart-e720d530-9a09-44da-af5e-0a6ba843fd88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763639581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3763639581
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.49732263
Short name T616
Test name
Test status
Simulation time 1620893164 ps
CPU time 10.96 seconds
Started Feb 07 01:59:03 PM PST 24
Finished Feb 07 01:59:17 PM PST 24
Peak memory 217760 kb
Host smart-117cd3a1-5fa5-4631-b85a-97094b75f5ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49732263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.49732263
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3920446827
Short name T362
Test name
Test status
Simulation time 164159996 ps
CPU time 7.61 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:13 PM PST 24
Peak memory 217452 kb
Host smart-951316fd-80ad-4668-b6f6-0d2450383b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920446827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3920446827
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4235332528
Short name T943
Test name
Test status
Simulation time 121539054 ps
CPU time 1.27 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:07 PM PST 24
Peak memory 213064 kb
Host smart-53e2551d-cfc8-4e9f-a23d-57807c824ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235332528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4235332528
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2322503726
Short name T975
Test name
Test status
Simulation time 291573720 ps
CPU time 22.76 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:59:21 PM PST 24
Peak memory 250752 kb
Host smart-4494e060-0ac9-4457-b6e5-aed70f581f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322503726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2322503726
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2572592124
Short name T610
Test name
Test status
Simulation time 1153716540 ps
CPU time 6.61 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:12 PM PST 24
Peak memory 249520 kb
Host smart-888b7e05-a7ff-4897-af4f-14874f96fa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572592124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2572592124
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4222549908
Short name T618
Test name
Test status
Simulation time 32132611 ps
CPU time 0.73 seconds
Started Feb 07 01:58:57 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 207600 kb
Host smart-a0ff7de3-d016-4b54-aa61-5f2e25952a6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222549908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4222549908
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.434252084
Short name T634
Test name
Test status
Simulation time 89059966 ps
CPU time 0.97 seconds
Started Feb 07 01:58:57 PM PST 24
Finished Feb 07 01:59:00 PM PST 24
Peak memory 208092 kb
Host smart-f859f7a1-86ed-49d5-bec8-5ed1a6661bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434252084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.434252084
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3191072785
Short name T406
Test name
Test status
Simulation time 1238944570 ps
CPU time 10.8 seconds
Started Feb 07 01:58:48 PM PST 24
Finished Feb 07 01:59:00 PM PST 24
Peak memory 217812 kb
Host smart-2b87fde3-62f6-463f-a4e5-e2e89c3289ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191072785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3191072785
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.670531447
Short name T905
Test name
Test status
Simulation time 133650455 ps
CPU time 1.1 seconds
Started Feb 07 01:58:46 PM PST 24
Finished Feb 07 01:58:48 PM PST 24
Peak memory 209480 kb
Host smart-c06a8988-5a9a-4a53-9171-856bdde7a1ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670531447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_ac
cess.670531447
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.912099569
Short name T394
Test name
Test status
Simulation time 8593209068 ps
CPU time 60.99 seconds
Started Feb 07 01:58:50 PM PST 24
Finished Feb 07 01:59:51 PM PST 24
Peak memory 218896 kb
Host smart-2dba0df1-5639-4c5c-9a8b-7e009e44b893
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912099569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.912099569
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1557045303
Short name T539
Test name
Test status
Simulation time 1337712896 ps
CPU time 4.1 seconds
Started Feb 07 01:58:46 PM PST 24
Finished Feb 07 01:58:51 PM PST 24
Peak memory 217768 kb
Host smart-366ec077-b505-40a0-a0fa-4f8dde95e998
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557045303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1557045303
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2939396968
Short name T867
Test name
Test status
Simulation time 824696454 ps
CPU time 4.26 seconds
Started Feb 07 01:58:51 PM PST 24
Finished Feb 07 01:58:56 PM PST 24
Peak memory 213136 kb
Host smart-21f424cb-889b-4abb-88fe-c5ed1272c9f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939396968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2939396968
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2448436606
Short name T597
Test name
Test status
Simulation time 4610704124 ps
CPU time 90.29 seconds
Started Feb 07 01:58:50 PM PST 24
Finished Feb 07 02:00:21 PM PST 24
Peak memory 279596 kb
Host smart-2e0308eb-9d54-4e80-961c-53d9521bddd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448436606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2448436606
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1750516820
Short name T18
Test name
Test status
Simulation time 2464775390 ps
CPU time 21.86 seconds
Started Feb 07 01:58:50 PM PST 24
Finished Feb 07 01:59:13 PM PST 24
Peak memory 248292 kb
Host smart-8f947301-fea8-4bcf-9ac1-9a5d200148f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750516820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1750516820
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.448835285
Short name T562
Test name
Test status
Simulation time 46604141 ps
CPU time 2.22 seconds
Started Feb 07 01:59:00 PM PST 24
Finished Feb 07 01:59:08 PM PST 24
Peak memory 217848 kb
Host smart-996630a0-415d-48fb-8325-e13d93dee290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448835285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.448835285
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.680020631
Short name T445
Test name
Test status
Simulation time 1051176273 ps
CPU time 11.75 seconds
Started Feb 07 01:58:46 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 218876 kb
Host smart-5ec28084-f10c-4354-b163-34f45e85f1f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680020631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.680020631
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.806300701
Short name T438
Test name
Test status
Simulation time 942029187 ps
CPU time 10.61 seconds
Started Feb 07 01:58:49 PM PST 24
Finished Feb 07 01:59:01 PM PST 24
Peak memory 217856 kb
Host smart-880a2ca9-355d-458f-bcb8-e7ea1c3fcfb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806300701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.806300701
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3689814903
Short name T455
Test name
Test status
Simulation time 226658781 ps
CPU time 9.54 seconds
Started Feb 07 01:58:47 PM PST 24
Finished Feb 07 01:58:57 PM PST 24
Peak memory 217860 kb
Host smart-578bfc6a-ca51-423b-9054-6f6ed2866b63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689814903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3689814903
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.4014949349
Short name T763
Test name
Test status
Simulation time 2547804367 ps
CPU time 21.09 seconds
Started Feb 07 01:59:02 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 217836 kb
Host smart-a4ae1cad-8ea6-420f-91b4-1917e788cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014949349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.4014949349
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2046985044
Short name T484
Test name
Test status
Simulation time 24975108 ps
CPU time 1.45 seconds
Started Feb 07 01:59:00 PM PST 24
Finished Feb 07 01:59:07 PM PST 24
Peak memory 213028 kb
Host smart-a481be10-1cc7-4c91-8f13-a16586cc88b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046985044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2046985044
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3040628207
Short name T939
Test name
Test status
Simulation time 1070615818 ps
CPU time 26.68 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:33 PM PST 24
Peak memory 250840 kb
Host smart-e88347b9-35f4-426b-b08a-92a89b00e767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040628207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3040628207
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3298891331
Short name T612
Test name
Test status
Simulation time 123682162 ps
CPU time 8.6 seconds
Started Feb 07 01:59:02 PM PST 24
Finished Feb 07 01:59:14 PM PST 24
Peak memory 250904 kb
Host smart-b49bee65-8242-41fd-86fc-ab510f136e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298891331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3298891331
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2508683612
Short name T903
Test name
Test status
Simulation time 16869308554 ps
CPU time 212.86 seconds
Started Feb 07 01:58:50 PM PST 24
Finished Feb 07 02:02:24 PM PST 24
Peak memory 444036 kb
Host smart-799a8cff-cbb4-4f63-be67-17b66bc35aab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508683612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2508683612
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2344487917
Short name T311
Test name
Test status
Simulation time 13126940 ps
CPU time 0.75 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:05 PM PST 24
Peak memory 207340 kb
Host smart-19d7ffb6-bc1e-439e-baaa-4c5df51cf3e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344487917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2344487917
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2634767841
Short name T415
Test name
Test status
Simulation time 1569999523 ps
CPU time 15.77 seconds
Started Feb 07 01:58:57 PM PST 24
Finished Feb 07 01:59:15 PM PST 24
Peak memory 217848 kb
Host smart-f9a04b84-4332-41e7-9092-7d64d6dec17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634767841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2634767841
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.372314414
Short name T913
Test name
Test status
Simulation time 6628281586 ps
CPU time 5.08 seconds
Started Feb 07 01:59:00 PM PST 24
Finished Feb 07 01:59:11 PM PST 24
Peak memory 209468 kb
Host smart-e038247d-75f2-41d5-b893-66806df3606a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372314414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ac
cess.372314414
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.752540111
Short name T425
Test name
Test status
Simulation time 9716489634 ps
CPU time 30.1 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:59:28 PM PST 24
Peak memory 218872 kb
Host smart-44dce590-2af1-4990-8979-a9b865f99a87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752540111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.752540111
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2258107615
Short name T535
Test name
Test status
Simulation time 1025159688 ps
CPU time 5.86 seconds
Started Feb 07 01:58:53 PM PST 24
Finished Feb 07 01:59:00 PM PST 24
Peak memory 217724 kb
Host smart-79bfd509-5875-4996-a7b7-388f9a277b86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258107615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2258107615
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2032630303
Short name T845
Test name
Test status
Simulation time 171950580 ps
CPU time 3 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 01:58:57 PM PST 24
Peak memory 212612 kb
Host smart-7de63e8c-e721-486b-b363-ed1dd4a666e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032630303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2032630303
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1556032119
Short name T414
Test name
Test status
Simulation time 8403325362 ps
CPU time 68.23 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 02:00:03 PM PST 24
Peak memory 275600 kb
Host smart-f58a4817-374e-42a0-9117-66a85f7dc5f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556032119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1556032119
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1973863266
Short name T747
Test name
Test status
Simulation time 942141139 ps
CPU time 14.42 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:19 PM PST 24
Peak memory 223584 kb
Host smart-f855fa7e-c5bc-4770-b021-4acecba1801b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973863266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1973863266
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.794315921
Short name T988
Test name
Test status
Simulation time 34194072 ps
CPU time 1.82 seconds
Started Feb 07 01:58:49 PM PST 24
Finished Feb 07 01:58:52 PM PST 24
Peak memory 217808 kb
Host smart-5544b984-904f-4eee-9e2c-f064df759afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794315921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.794315921
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3829001264
Short name T575
Test name
Test status
Simulation time 268079639 ps
CPU time 10.35 seconds
Started Feb 07 01:59:00 PM PST 24
Finished Feb 07 01:59:16 PM PST 24
Peak memory 218836 kb
Host smart-c5216ed0-fd6c-4b8a-afa7-66a106daffed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829001264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3829001264
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1178914684
Short name T36
Test name
Test status
Simulation time 418345546 ps
CPU time 15.88 seconds
Started Feb 07 01:58:57 PM PST 24
Finished Feb 07 01:59:15 PM PST 24
Peak memory 217852 kb
Host smart-d9c7590c-98d0-45f9-8a89-185e9e075a3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178914684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1178914684
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.468100863
Short name T613
Test name
Test status
Simulation time 1563458973 ps
CPU time 14.39 seconds
Started Feb 07 01:58:55 PM PST 24
Finished Feb 07 01:59:10 PM PST 24
Peak memory 217856 kb
Host smart-987d656f-5296-4d5b-8e84-1aa9161b5690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468100863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.468100863
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3309318635
Short name T519
Test name
Test status
Simulation time 2056196662 ps
CPU time 9.49 seconds
Started Feb 07 01:58:57 PM PST 24
Finished Feb 07 01:59:08 PM PST 24
Peak memory 217812 kb
Host smart-ef458340-2de1-407b-a9ed-1c4edd9be603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309318635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3309318635
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2554905965
Short name T509
Test name
Test status
Simulation time 27873058 ps
CPU time 1.59 seconds
Started Feb 07 01:58:53 PM PST 24
Finished Feb 07 01:58:56 PM PST 24
Peak memory 213292 kb
Host smart-741acb93-5149-4197-9c40-fcbf0a92a254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554905965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2554905965
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1855824958
Short name T814
Test name
Test status
Simulation time 330513330 ps
CPU time 28.65 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 250808 kb
Host smart-1c8f9b23-c633-4951-bb97-5a1ce640030a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855824958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1855824958
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.837159723
Short name T314
Test name
Test status
Simulation time 213009420 ps
CPU time 2.87 seconds
Started Feb 07 01:58:55 PM PST 24
Finished Feb 07 01:59:00 PM PST 24
Peak memory 221812 kb
Host smart-e96bca6a-ee0d-40c9-bc97-026fa84a6e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837159723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.837159723
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3827657532
Short name T882
Test name
Test status
Simulation time 16132598801 ps
CPU time 188.46 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 02:02:07 PM PST 24
Peak memory 226032 kb
Host smart-cc5f3829-0338-475e-934a-3f9da8a9e68b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827657532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3827657532
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3474839709
Short name T894
Test name
Test status
Simulation time 14116967 ps
CPU time 0.8 seconds
Started Feb 07 01:58:53 PM PST 24
Finished Feb 07 01:58:55 PM PST 24
Peak memory 208116 kb
Host smart-add625a0-30ac-4078-b229-2523a503a027
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474839709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3474839709
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2881102342
Short name T661
Test name
Test status
Simulation time 20745430 ps
CPU time 1.18 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 208168 kb
Host smart-d7ce2013-f02d-4db7-b1c2-40f34ad1df3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881102342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2881102342
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.463741825
Short name T53
Test name
Test status
Simulation time 565741649 ps
CPU time 15.08 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:20 PM PST 24
Peak memory 217868 kb
Host smart-cc036b07-4d51-4d12-8c4c-f091dc99499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463741825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.463741825
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.370662565
Short name T946
Test name
Test status
Simulation time 354877246 ps
CPU time 4.78 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 209388 kb
Host smart-cb0046ad-dff4-46b0-925e-cadf22c5dce4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370662565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_ac
cess.370662565
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1012179371
Short name T377
Test name
Test status
Simulation time 2891980903 ps
CPU time 76.12 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 02:00:15 PM PST 24
Peak memory 217820 kb
Host smart-bf3630cc-8b40-4c73-ad65-05a1c2d1ad28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012179371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1012179371
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.75932093
Short name T193
Test name
Test status
Simulation time 6567598999 ps
CPU time 7.89 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:59:06 PM PST 24
Peak memory 217828 kb
Host smart-8e1ed5ae-a0c3-4a41-abe9-4d219bfe41b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75932093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_
prog_failure.75932093
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3290714999
Short name T37
Test name
Test status
Simulation time 384959287 ps
CPU time 5.99 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 01:59:05 PM PST 24
Peak memory 213484 kb
Host smart-f9380e50-d3b4-4269-b1ed-9092b844cf5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290714999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3290714999
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1147292956
Short name T428
Test name
Test status
Simulation time 6776742876 ps
CPU time 68.91 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 02:00:06 PM PST 24
Peak memory 268036 kb
Host smart-7696779f-4246-4318-adff-92fa207e4330
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147292956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1147292956
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.27206250
Short name T497
Test name
Test status
Simulation time 2602607462 ps
CPU time 13.33 seconds
Started Feb 07 01:58:53 PM PST 24
Finished Feb 07 01:59:07 PM PST 24
Peak memory 246904 kb
Host smart-a5c9c206-6781-4db7-a674-8a73a2973c5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27206250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_j
tag_state_post_trans.27206250
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3961998049
Short name T980
Test name
Test status
Simulation time 258720463 ps
CPU time 4.48 seconds
Started Feb 07 01:58:53 PM PST 24
Finished Feb 07 01:58:58 PM PST 24
Peak memory 217824 kb
Host smart-2dd8b685-80e3-4023-8227-90a4b04293bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961998049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3961998049
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3384246262
Short name T778
Test name
Test status
Simulation time 1244443319 ps
CPU time 13.22 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:19 PM PST 24
Peak memory 217900 kb
Host smart-e4b2d4af-b28b-4155-a947-c6a9423ff0a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384246262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3384246262
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2389788272
Short name T506
Test name
Test status
Simulation time 4657513377 ps
CPU time 16.59 seconds
Started Feb 07 01:58:52 PM PST 24
Finished Feb 07 01:59:09 PM PST 24
Peak memory 217920 kb
Host smart-92fb4c6f-5a13-4517-9f5f-abb0e59afb77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389788272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2389788272
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2362257460
Short name T602
Test name
Test status
Simulation time 522233012 ps
CPU time 10.13 seconds
Started Feb 07 01:58:53 PM PST 24
Finished Feb 07 01:59:04 PM PST 24
Peak memory 217832 kb
Host smart-6f582d7d-090c-4092-89b5-da26631e9425
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362257460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2362257460
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3119006821
Short name T577
Test name
Test status
Simulation time 447670302 ps
CPU time 7.7 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 01:59:02 PM PST 24
Peak memory 217816 kb
Host smart-b2724338-5e1f-4e83-ad23-f0be39834e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119006821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3119006821
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1075735245
Short name T340
Test name
Test status
Simulation time 149948172 ps
CPU time 2.5 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:59:00 PM PST 24
Peak memory 213756 kb
Host smart-c3773f90-db97-4474-ad1b-6da6d02d6a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075735245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1075735245
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.4223702440
Short name T560
Test name
Test status
Simulation time 1040676722 ps
CPU time 30.83 seconds
Started Feb 07 01:58:52 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 250828 kb
Host smart-ded1179c-3e9c-418d-ad8e-3dcb0b45bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223702440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.4223702440
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.566854472
Short name T862
Test name
Test status
Simulation time 111489235 ps
CPU time 6.56 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:59:04 PM PST 24
Peak memory 250436 kb
Host smart-4a71a8f9-c135-4627-ac75-67b3e4cd6b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566854472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.566854472
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1185654415
Short name T824
Test name
Test status
Simulation time 86399923795 ps
CPU time 320.57 seconds
Started Feb 07 01:58:57 PM PST 24
Finished Feb 07 02:04:19 PM PST 24
Peak memory 267400 kb
Host smart-daadc035-07d1-4c07-b900-13a774f82821
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185654415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1185654415
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3780806498
Short name T628
Test name
Test status
Simulation time 34577713 ps
CPU time 0.84 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 01:58:56 PM PST 24
Peak memory 207856 kb
Host smart-f172d0ae-b388-444d-b827-03334cad4482
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780806498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3780806498
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2367835651
Short name T472
Test name
Test status
Simulation time 16463241 ps
CPU time 0.87 seconds
Started Feb 07 01:59:04 PM PST 24
Finished Feb 07 01:59:08 PM PST 24
Peak memory 209488 kb
Host smart-61a3ec5c-ed45-4d81-a4a1-9a80a58ad430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367835651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2367835651
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1756802466
Short name T419
Test name
Test status
Simulation time 577324390 ps
CPU time 13.96 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 01:59:13 PM PST 24
Peak memory 217748 kb
Host smart-695fb251-12b1-41ae-825d-8a996ebb7d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756802466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1756802466
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2580321973
Short name T810
Test name
Test status
Simulation time 1232052583 ps
CPU time 5.74 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 01:59:05 PM PST 24
Peak memory 209432 kb
Host smart-3bdf16f2-022d-43f3-9ce7-8e171e7da380
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580321973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.2580321973
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1815204832
Short name T678
Test name
Test status
Simulation time 1643929754 ps
CPU time 50.01 seconds
Started Feb 07 01:59:03 PM PST 24
Finished Feb 07 01:59:56 PM PST 24
Peak memory 217668 kb
Host smart-e8062a3b-415a-426d-ac7a-6e61e3dc4d77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815204832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1815204832
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.963800800
Short name T748
Test name
Test status
Simulation time 235300323 ps
CPU time 8.4 seconds
Started Feb 07 01:58:57 PM PST 24
Finished Feb 07 01:59:07 PM PST 24
Peak memory 217696 kb
Host smart-05b96794-1e68-4126-ae72-d8e763ac9251
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963800800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.963800800
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1022606247
Short name T6
Test name
Test status
Simulation time 8231773090 ps
CPU time 7.89 seconds
Started Feb 07 01:58:55 PM PST 24
Finished Feb 07 01:59:03 PM PST 24
Peak memory 214004 kb
Host smart-56e7c419-cabc-46c9-8730-498a00b63158
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022606247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1022606247
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2054556670
Short name T808
Test name
Test status
Simulation time 7927324884 ps
CPU time 51.31 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:57 PM PST 24
Peak memory 275384 kb
Host smart-a4049279-956f-4f1b-944a-a84993e6721f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054556670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2054556670
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2144097826
Short name T647
Test name
Test status
Simulation time 583380562 ps
CPU time 13.46 seconds
Started Feb 07 01:58:54 PM PST 24
Finished Feb 07 01:59:08 PM PST 24
Peak memory 250860 kb
Host smart-94fb81cb-f002-4351-91ee-10da2ce8b690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144097826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2144097826
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3604958683
Short name T643
Test name
Test status
Simulation time 194899945 ps
CPU time 1.54 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 01:59:04 PM PST 24
Peak memory 217852 kb
Host smart-c62de99b-ac3b-4034-bd3b-d12c43b54594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604958683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3604958683
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2094064912
Short name T854
Test name
Test status
Simulation time 2456634785 ps
CPU time 16.29 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:22 PM PST 24
Peak memory 217928 kb
Host smart-3a6bd514-9336-4f80-b23e-5fce26763299
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094064912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2094064912
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.4194392147
Short name T466
Test name
Test status
Simulation time 261654189 ps
CPU time 12.32 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:18 PM PST 24
Peak memory 217824 kb
Host smart-bcd1f6c8-abc0-4fc5-8426-b73b4457fc45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194392147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.4194392147
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1627687367
Short name T656
Test name
Test status
Simulation time 3652394515 ps
CPU time 13.14 seconds
Started Feb 07 01:59:02 PM PST 24
Finished Feb 07 01:59:19 PM PST 24
Peak memory 217876 kb
Host smart-456a5ee7-dd4b-44ae-84c5-1f402d4c3fa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627687367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1627687367
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.4025839159
Short name T413
Test name
Test status
Simulation time 1107405391 ps
CPU time 13.68 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:19 PM PST 24
Peak memory 217756 kb
Host smart-bf45a1d0-47cd-4fdc-9085-d46ca522cbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025839159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4025839159
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2108212424
Short name T744
Test name
Test status
Simulation time 99257150 ps
CPU time 1.95 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 213360 kb
Host smart-0f9a37be-7bdf-4e33-8806-cab22f91461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108212424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2108212424
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.4286647036
Short name T651
Test name
Test status
Simulation time 458572275 ps
CPU time 32.26 seconds
Started Feb 07 01:58:56 PM PST 24
Finished Feb 07 01:59:30 PM PST 24
Peak memory 250792 kb
Host smart-b94761af-fe5b-4b1f-bbf4-0056ff4ce7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286647036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4286647036
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2570378801
Short name T378
Test name
Test status
Simulation time 67671659 ps
CPU time 3.6 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:09 PM PST 24
Peak memory 221860 kb
Host smart-71fb70af-f6f6-453f-b24a-68c3845d36cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570378801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2570378801
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4032502989
Short name T372
Test name
Test status
Simulation time 12192668576 ps
CPU time 151.03 seconds
Started Feb 07 01:59:04 PM PST 24
Finished Feb 07 02:01:38 PM PST 24
Peak memory 223508 kb
Host smart-203af6a1-7a19-4f43-81b6-f4cfb58b0e7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032502989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4032502989
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3957926588
Short name T41
Test name
Test status
Simulation time 39801086 ps
CPU time 1.17 seconds
Started Feb 07 01:58:58 PM PST 24
Finished Feb 07 01:59:00 PM PST 24
Peak memory 212312 kb
Host smart-4b5cd767-32b8-4c8f-b6ca-218e8f924ccd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957926588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3957926588
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.4199655856
Short name T422
Test name
Test status
Simulation time 76148784 ps
CPU time 0.95 seconds
Started Feb 07 01:59:08 PM PST 24
Finished Feb 07 01:59:10 PM PST 24
Peak memory 209396 kb
Host smart-27c88a6c-4db3-4af5-94d5-ae86e2887e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199655856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.4199655856
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1299042113
Short name T798
Test name
Test status
Simulation time 1376611902 ps
CPU time 10.65 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 01:59:25 PM PST 24
Peak memory 217820 kb
Host smart-1b6b5fc4-3786-4eb0-9efd-8de155b0e0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299042113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1299042113
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2621954893
Short name T26
Test name
Test status
Simulation time 6947067016 ps
CPU time 14.44 seconds
Started Feb 07 01:59:07 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 209468 kb
Host smart-7a1c107b-773f-4455-81de-2d90746a3071
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621954893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.2621954893
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1770685841
Short name T821
Test name
Test status
Simulation time 2642041207 ps
CPU time 39.97 seconds
Started Feb 07 01:59:06 PM PST 24
Finished Feb 07 01:59:49 PM PST 24
Peak memory 217860 kb
Host smart-d7d758a3-2bfb-482e-8318-7e0296a1f7e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770685841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1770685841
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.376335937
Short name T424
Test name
Test status
Simulation time 149593093 ps
CPU time 2.92 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 01:59:18 PM PST 24
Peak memory 217708 kb
Host smart-67c5b52e-0af6-494d-9f47-240f89619a40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376335937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.376335937
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2377453382
Short name T912
Test name
Test status
Simulation time 314265150 ps
CPU time 9.73 seconds
Started Feb 07 01:59:04 PM PST 24
Finished Feb 07 01:59:16 PM PST 24
Peak memory 213228 kb
Host smart-38629381-6f0f-430f-977b-4439c60aa3c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377453382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2377453382
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.282852988
Short name T735
Test name
Test status
Simulation time 1987122017 ps
CPU time 58.07 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 02:00:13 PM PST 24
Peak memory 267148 kb
Host smart-09d87517-f8df-46b5-a999-6f8c1143416f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282852988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.282852988
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.564989379
Short name T877
Test name
Test status
Simulation time 1884434121 ps
CPU time 29.74 seconds
Started Feb 07 01:59:09 PM PST 24
Finished Feb 07 01:59:40 PM PST 24
Peak memory 247376 kb
Host smart-aac1d9f3-04cc-4d6d-863b-46ca47888225
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564989379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.564989379
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.942712235
Short name T306
Test name
Test status
Simulation time 230447171 ps
CPU time 4.65 seconds
Started Feb 07 01:59:06 PM PST 24
Finished Feb 07 01:59:13 PM PST 24
Peak memory 217820 kb
Host smart-66b56043-7151-4117-a2eb-fcd8691847e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942712235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.942712235
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1607104709
Short name T956
Test name
Test status
Simulation time 338820396 ps
CPU time 11.03 seconds
Started Feb 07 01:59:04 PM PST 24
Finished Feb 07 01:59:17 PM PST 24
Peak memory 217808 kb
Host smart-632b5ec7-ca7b-47e0-9881-16ca501339aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607104709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1607104709
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2408336973
Short name T932
Test name
Test status
Simulation time 1390677895 ps
CPU time 15.35 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 01:59:29 PM PST 24
Peak memory 217860 kb
Host smart-486caaba-1550-464b-b26f-acef4c162e28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408336973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2408336973
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.242432875
Short name T323
Test name
Test status
Simulation time 299527466 ps
CPU time 6.47 seconds
Started Feb 07 01:59:09 PM PST 24
Finished Feb 07 01:59:17 PM PST 24
Peak memory 217804 kb
Host smart-f8c6c654-85dd-4303-9619-33e0d6626a9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242432875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.242432875
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3045805619
Short name T33
Test name
Test status
Simulation time 900123659 ps
CPU time 15.79 seconds
Started Feb 07 01:59:07 PM PST 24
Finished Feb 07 01:59:25 PM PST 24
Peak memory 217864 kb
Host smart-23b3f847-eba6-4288-9c97-d2802e43abaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045805619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3045805619
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2445257026
Short name T707
Test name
Test status
Simulation time 902130703 ps
CPU time 3.05 seconds
Started Feb 07 01:58:59 PM PST 24
Finished Feb 07 01:59:07 PM PST 24
Peak memory 213896 kb
Host smart-dc9364a1-8ea6-4ebc-b89c-e2f194510b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445257026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2445257026
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.534933059
Short name T958
Test name
Test status
Simulation time 1131990130 ps
CPU time 28.16 seconds
Started Feb 07 01:59:11 PM PST 24
Finished Feb 07 01:59:40 PM PST 24
Peak memory 250812 kb
Host smart-0f426d80-2864-4a08-a4f4-e442787a2bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534933059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.534933059
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.992075711
Short name T432
Test name
Test status
Simulation time 120882378 ps
CPU time 6.8 seconds
Started Feb 07 01:59:08 PM PST 24
Finished Feb 07 01:59:16 PM PST 24
Peak memory 242680 kb
Host smart-0253eb3d-42d4-40a9-9a0d-b6aff5cee4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992075711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.992075711
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1836422195
Short name T641
Test name
Test status
Simulation time 2624174276 ps
CPU time 64.37 seconds
Started Feb 07 01:59:12 PM PST 24
Finished Feb 07 02:00:17 PM PST 24
Peak memory 275732 kb
Host smart-258ec5d5-2179-49a6-a97f-a2df73ba6e75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836422195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1836422195
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1238169478
Short name T889
Test name
Test status
Simulation time 17313645 ps
CPU time 0.86 seconds
Started Feb 07 01:59:01 PM PST 24
Finished Feb 07 01:59:07 PM PST 24
Peak memory 208116 kb
Host smart-e21287ed-d1c8-47c5-8641-8d2581dd5c72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238169478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1238169478
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1350144733
Short name T696
Test name
Test status
Simulation time 21802904 ps
CPU time 0.82 seconds
Started Feb 07 01:59:19 PM PST 24
Finished Feb 07 01:59:21 PM PST 24
Peak memory 209188 kb
Host smart-3df3fa13-eb7b-4c75-8831-ddb74170d625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350144733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1350144733
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3253326746
Short name T550
Test name
Test status
Simulation time 458572198 ps
CPU time 13.75 seconds
Started Feb 07 01:59:10 PM PST 24
Finished Feb 07 01:59:24 PM PST 24
Peak memory 217812 kb
Host smart-82de48d1-b56a-46f0-9bea-bf99db0a34fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253326746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3253326746
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3977484394
Short name T953
Test name
Test status
Simulation time 1595088203 ps
CPU time 8.35 seconds
Started Feb 07 01:59:17 PM PST 24
Finished Feb 07 01:59:26 PM PST 24
Peak memory 209396 kb
Host smart-7d240825-57da-4e44-8ab0-da23d8dd60d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977484394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.3977484394
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.637099557
Short name T896
Test name
Test status
Simulation time 7427729656 ps
CPU time 40.98 seconds
Started Feb 07 01:59:16 PM PST 24
Finished Feb 07 01:59:58 PM PST 24
Peak memory 218264 kb
Host smart-c14d8026-d929-456e-add6-16b71b9e812f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637099557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.637099557
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2744382023
Short name T720
Test name
Test status
Simulation time 1138132593 ps
CPU time 9.12 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 217792 kb
Host smart-29f2c9a2-d713-4c56-bb65-054861aef971
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744382023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2744382023
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.4003489094
Short name T718
Test name
Test status
Simulation time 103716844 ps
CPU time 2.28 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:18 PM PST 24
Peak memory 212728 kb
Host smart-a82dbec2-c565-4938-8a79-853460c3c5e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003489094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.4003489094
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1932299524
Short name T773
Test name
Test status
Simulation time 2475415822 ps
CPU time 45.28 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 02:00:10 PM PST 24
Peak memory 252000 kb
Host smart-7ff7c908-4db7-41b4-bddc-dedbc8e138d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932299524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1932299524
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3985487315
Short name T652
Test name
Test status
Simulation time 725081838 ps
CPU time 16.99 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 01:59:31 PM PST 24
Peak memory 250828 kb
Host smart-78890f67-573c-40f6-b572-dbb9d0387f8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985487315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3985487315
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2324115667
Short name T891
Test name
Test status
Simulation time 474410630 ps
CPU time 5.23 seconds
Started Feb 07 01:59:03 PM PST 24
Finished Feb 07 01:59:11 PM PST 24
Peak memory 217824 kb
Host smart-1b52f1f0-d797-4fda-b131-14e20612475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324115667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2324115667
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1753298644
Short name T665
Test name
Test status
Simulation time 1195820257 ps
CPU time 9.48 seconds
Started Feb 07 01:59:12 PM PST 24
Finished Feb 07 01:59:22 PM PST 24
Peak memory 217872 kb
Host smart-da1f812d-db58-4ace-9104-0e17423648d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753298644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1753298644
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3419197238
Short name T609
Test name
Test status
Simulation time 212961313 ps
CPU time 7.65 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 01:59:21 PM PST 24
Peak memory 217832 kb
Host smart-33050a39-b1fb-437f-8ded-2c24b3f3a183
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419197238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3419197238
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2790433011
Short name T841
Test name
Test status
Simulation time 807813823 ps
CPU time 9.17 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 01:59:24 PM PST 24
Peak memory 217800 kb
Host smart-f4698d68-c274-4abb-b561-23399599c19f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790433011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2790433011
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2129626356
Short name T483
Test name
Test status
Simulation time 755556900 ps
CPU time 13.71 seconds
Started Feb 07 01:59:07 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 217812 kb
Host smart-81e18788-3939-4b58-a204-20bc6f084a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129626356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2129626356
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3550764600
Short name T67
Test name
Test status
Simulation time 344065455 ps
CPU time 5.09 seconds
Started Feb 07 01:59:09 PM PST 24
Finished Feb 07 01:59:15 PM PST 24
Peak memory 214396 kb
Host smart-f72f80d5-5534-4af0-8a61-b4b3657fffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550764600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3550764600
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4180699509
Short name T332
Test name
Test status
Simulation time 380636706 ps
CPU time 41.5 seconds
Started Feb 07 01:59:09 PM PST 24
Finished Feb 07 01:59:52 PM PST 24
Peak memory 250816 kb
Host smart-6516b893-a09a-48e3-b8a5-7d34a892d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180699509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4180699509
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4169251101
Short name T684
Test name
Test status
Simulation time 70495238 ps
CPU time 6.16 seconds
Started Feb 07 01:59:08 PM PST 24
Finished Feb 07 01:59:16 PM PST 24
Peak memory 243728 kb
Host smart-ac78fb95-dcee-44a7-b636-e6c760f0f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169251101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4169251101
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2392436113
Short name T448
Test name
Test status
Simulation time 24429342297 ps
CPU time 706.48 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 02:11:11 PM PST 24
Peak memory 283740 kb
Host smart-865615e1-6375-4b0d-9622-5d38f7254407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392436113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2392436113
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1862985948
Short name T941
Test name
Test status
Simulation time 82922738117 ps
CPU time 1106.72 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 02:17:43 PM PST 24
Peak memory 309288 kb
Host smart-590b1219-d9ff-48ac-9ddc-cb26e1cffd80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1862985948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1862985948
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3162969350
Short name T39
Test name
Test status
Simulation time 29183526 ps
CPU time 0.94 seconds
Started Feb 07 01:59:10 PM PST 24
Finished Feb 07 01:59:11 PM PST 24
Peak memory 211244 kb
Host smart-c16a24be-43e0-4aa6-9f30-200595018c4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162969350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3162969350
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1557167976
Short name T915
Test name
Test status
Simulation time 92471177 ps
CPU time 1.14 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 01:59:16 PM PST 24
Peak memory 209412 kb
Host smart-11f3e8b9-b102-45ee-83a7-f4d161478466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557167976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1557167976
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2127855458
Short name T569
Test name
Test status
Simulation time 3086387584 ps
CPU time 18.93 seconds
Started Feb 07 01:59:16 PM PST 24
Finished Feb 07 01:59:36 PM PST 24
Peak memory 217940 kb
Host smart-795a5246-cc86-464d-a858-441b4fbdd8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127855458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2127855458
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1989089048
Short name T694
Test name
Test status
Simulation time 3752783449 ps
CPU time 8.32 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:25 PM PST 24
Peak memory 209556 kb
Host smart-b7554026-3412-4dbf-a97a-c22547f4c5b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989089048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.1989089048
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1265345971
Short name T371
Test name
Test status
Simulation time 14159760953 ps
CPU time 30.25 seconds
Started Feb 07 01:59:19 PM PST 24
Finished Feb 07 01:59:51 PM PST 24
Peak memory 218056 kb
Host smart-a2b2b5fb-a962-4b35-b0aa-ebb879c9f2ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265345971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1265345971
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2492572514
Short name T636
Test name
Test status
Simulation time 4017085753 ps
CPU time 12.79 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 01:59:28 PM PST 24
Peak memory 217780 kb
Host smart-940756bc-5d57-49ff-92c3-73e8aea11686
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492572514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2492572514
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3570616441
Short name T354
Test name
Test status
Simulation time 318276863 ps
CPU time 8.31 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:24 PM PST 24
Peak memory 212960 kb
Host smart-5f575994-1cd8-4a3d-a60f-ae200e804537
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570616441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3570616441
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3140630643
Short name T856
Test name
Test status
Simulation time 2815263443 ps
CPU time 99.83 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 02:00:53 PM PST 24
Peak memory 278440 kb
Host smart-07240555-52eb-4df8-9450-03895fe81be6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140630643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3140630643
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2592987754
Short name T7
Test name
Test status
Simulation time 1160207187 ps
CPU time 13.38 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:30 PM PST 24
Peak memory 246892 kb
Host smart-f6f77fb7-486a-49a6-bc7a-0d27286d43b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592987754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2592987754
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1629713083
Short name T938
Test name
Test status
Simulation time 93282606 ps
CPU time 3.34 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:20 PM PST 24
Peak memory 217892 kb
Host smart-8d7b63f0-750b-4274-bf65-f5a0e99b7cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629713083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1629713083
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1797961102
Short name T571
Test name
Test status
Simulation time 403518351 ps
CPU time 9.57 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:25 PM PST 24
Peak memory 217856 kb
Host smart-237baa8f-cce0-42f0-87b1-a603327635c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797961102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1797961102
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.970184626
Short name T895
Test name
Test status
Simulation time 1882335678 ps
CPU time 18.86 seconds
Started Feb 07 01:59:18 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 217788 kb
Host smart-498582c3-ac05-4351-a19e-7ee90467bfcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970184626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.970184626
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1819295250
Short name T887
Test name
Test status
Simulation time 219688901 ps
CPU time 5.96 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 01:59:21 PM PST 24
Peak memory 217852 kb
Host smart-4a8220df-034e-4187-92ac-e746a63c3de9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819295250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1819295250
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.465870497
Short name T102
Test name
Test status
Simulation time 358329400 ps
CPU time 13.44 seconds
Started Feb 07 01:59:19 PM PST 24
Finished Feb 07 01:59:34 PM PST 24
Peak memory 217768 kb
Host smart-57e5d6f8-1457-412a-b462-0741b0b33d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465870497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.465870497
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3398592853
Short name T906
Test name
Test status
Simulation time 250714004 ps
CPU time 3.24 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 01:59:17 PM PST 24
Peak memory 213700 kb
Host smart-2553c45c-e4d6-4a9a-86e0-834849941b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398592853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3398592853
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1561845559
Short name T325
Test name
Test status
Simulation time 4812376576 ps
CPU time 30.23 seconds
Started Feb 07 01:59:19 PM PST 24
Finished Feb 07 01:59:51 PM PST 24
Peak memory 250820 kb
Host smart-94698ca8-893f-4a94-8c32-6044c7257c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561845559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1561845559
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3909003065
Short name T508
Test name
Test status
Simulation time 618219204 ps
CPU time 6.58 seconds
Started Feb 07 01:59:16 PM PST 24
Finished Feb 07 01:59:24 PM PST 24
Peak memory 221924 kb
Host smart-9306a87a-8435-49dc-8143-09b88c585944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909003065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3909003065
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2867026931
Short name T635
Test name
Test status
Simulation time 2959260976 ps
CPU time 48.78 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 02:00:05 PM PST 24
Peak memory 250864 kb
Host smart-cc1c7e60-9974-4ac9-9e1a-0afb36316e34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867026931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2867026931
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.756717171
Short name T692
Test name
Test status
Simulation time 41501134 ps
CPU time 0.77 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 01:59:14 PM PST 24
Peak memory 207704 kb
Host smart-30227df4-a3ca-4ea4-aa3f-3f3fca5f82da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756717171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.756717171
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2535618011
Short name T754
Test name
Test status
Simulation time 81178522 ps
CPU time 1.09 seconds
Started Feb 07 01:59:18 PM PST 24
Finished Feb 07 01:59:21 PM PST 24
Peak memory 208224 kb
Host smart-32ea75ad-73f9-40bb-8951-990c9013db64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535618011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2535618011
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1227878355
Short name T666
Test name
Test status
Simulation time 2225958093 ps
CPU time 11.95 seconds
Started Feb 07 01:59:17 PM PST 24
Finished Feb 07 01:59:29 PM PST 24
Peak memory 217864 kb
Host smart-16fd9b5d-baa8-466c-adef-303ec87904ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227878355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1227878355
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.4147234806
Short name T925
Test name
Test status
Simulation time 89341748 ps
CPU time 1.25 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 01:59:16 PM PST 24
Peak memory 209400 kb
Host smart-87b6c2c0-a542-4004-93f8-18cff3558800
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147234806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_a
ccess.4147234806
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2104913462
Short name T847
Test name
Test status
Simulation time 4524303515 ps
CPU time 20.97 seconds
Started Feb 07 01:59:14 PM PST 24
Finished Feb 07 01:59:36 PM PST 24
Peak memory 218164 kb
Host smart-d309fd2f-43cc-49e0-9630-063f751d1ed2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104913462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2104913462
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.509540048
Short name T836
Test name
Test status
Simulation time 212084471 ps
CPU time 4.51 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:20 PM PST 24
Peak memory 217764 kb
Host smart-779c314e-79e9-4780-ab95-01c6a930a3a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509540048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.509540048
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1657317278
Short name T676
Test name
Test status
Simulation time 442229621 ps
CPU time 6.98 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 213128 kb
Host smart-7f477627-1667-4e13-97a2-6f2109e23f8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657317278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1657317278
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4261194376
Short name T627
Test name
Test status
Simulation time 2010251897 ps
CPU time 48.89 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 02:00:14 PM PST 24
Peak memory 268412 kb
Host smart-99aa10b5-82c6-45a8-aca1-1ed78cb1fcf4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261194376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.4261194376
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1102962867
Short name T662
Test name
Test status
Simulation time 333781727 ps
CPU time 15.73 seconds
Started Feb 07 01:59:19 PM PST 24
Finished Feb 07 01:59:36 PM PST 24
Peak memory 250956 kb
Host smart-48047c4f-131d-4ef8-bb9a-92bf11da21e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102962867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1102962867
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4122284730
Short name T741
Test name
Test status
Simulation time 394070765 ps
CPU time 3.33 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:19 PM PST 24
Peak memory 217840 kb
Host smart-4eaca6e4-9d4c-4ae8-b132-f7a1cc6084ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122284730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4122284730
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3537660265
Short name T817
Test name
Test status
Simulation time 346776393 ps
CPU time 15.64 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:41 PM PST 24
Peak memory 218880 kb
Host smart-bef05fa2-a923-4a3f-a743-4f189e7c1cc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537660265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3537660265
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1718264304
Short name T481
Test name
Test status
Simulation time 4284385549 ps
CPU time 9.46 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:35 PM PST 24
Peak memory 217796 kb
Host smart-0eeb7b85-b68c-4863-9f90-3f1e82661cfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718264304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1718264304
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.523437063
Short name T640
Test name
Test status
Simulation time 232777518 ps
CPU time 9.17 seconds
Started Feb 07 01:59:17 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 217796 kb
Host smart-ed871968-1034-4f46-90ec-bf571e297562
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523437063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.523437063
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.430952769
Short name T677
Test name
Test status
Simulation time 458173367 ps
CPU time 6.75 seconds
Started Feb 07 01:59:13 PM PST 24
Finished Feb 07 01:59:20 PM PST 24
Peak memory 217876 kb
Host smart-dd7a54f1-daab-4d01-ae3c-49e9d61274fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430952769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.430952769
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1320227988
Short name T496
Test name
Test status
Simulation time 57679401 ps
CPU time 3.7 seconds
Started Feb 07 01:59:18 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 214384 kb
Host smart-04d8eeb7-0296-44f7-8d0e-8108da2725af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320227988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1320227988
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.243162012
Short name T557
Test name
Test status
Simulation time 224250027 ps
CPU time 22.14 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 250760 kb
Host smart-1960bba8-8559-41a8-bdc4-ec1b12e5a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243162012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.243162012
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.430514548
Short name T779
Test name
Test status
Simulation time 241725192 ps
CPU time 9.31 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:26 PM PST 24
Peak memory 250892 kb
Host smart-3e21ef7e-ff75-43c9-a5e0-75957a52e082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430514548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.430514548
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.381533570
Short name T904
Test name
Test status
Simulation time 3083646476 ps
CPU time 117.34 seconds
Started Feb 07 01:59:19 PM PST 24
Finished Feb 07 02:01:17 PM PST 24
Peak memory 250832 kb
Host smart-8857543a-69fc-4def-a95d-2e77412ca5f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381533570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.381533570
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2098657706
Short name T157
Test name
Test status
Simulation time 38185526374 ps
CPU time 272.76 seconds
Started Feb 07 01:59:16 PM PST 24
Finished Feb 07 02:03:50 PM PST 24
Peak memory 281812 kb
Host smart-3caa1b21-1fd9-4e87-b80e-cd2d04cc6157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2098657706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2098657706
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1984124631
Short name T742
Test name
Test status
Simulation time 17193770 ps
CPU time 1.2 seconds
Started Feb 07 01:58:20 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 209420 kb
Host smart-137ec0a5-ceee-449f-b3eb-a657adf39e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984124631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1984124631
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.941844501
Short name T770
Test name
Test status
Simulation time 1284230164 ps
CPU time 11.86 seconds
Started Feb 07 01:58:13 PM PST 24
Finished Feb 07 01:58:26 PM PST 24
Peak memory 217776 kb
Host smart-7eff35e4-3c36-40e9-90be-a42530677931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941844501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.941844501
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.443807742
Short name T807
Test name
Test status
Simulation time 5721804994 ps
CPU time 9.2 seconds
Started Feb 07 01:58:10 PM PST 24
Finished Feb 07 01:58:20 PM PST 24
Peak memory 209504 kb
Host smart-fc3baba3-e443-4c0f-9585-a6297f66eaf3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443807742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_acc
ess.443807742
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.240824856
Short name T659
Test name
Test status
Simulation time 11976446480 ps
CPU time 68.34 seconds
Started Feb 07 01:58:10 PM PST 24
Finished Feb 07 01:59:19 PM PST 24
Peak memory 218252 kb
Host smart-595a6fef-2a48-485d-ab50-b6a1a86ad1e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240824856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.240824856
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2053539082
Short name T104
Test name
Test status
Simulation time 1060145191 ps
CPU time 10.36 seconds
Started Feb 07 01:58:12 PM PST 24
Finished Feb 07 01:58:23 PM PST 24
Peak memory 209468 kb
Host smart-e92d3e5c-36d8-4993-b0a9-5bb74540e6aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053539082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.2053539082
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.194331441
Short name T849
Test name
Test status
Simulation time 931075434 ps
CPU time 5.01 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 217768 kb
Host smart-03a71303-9156-408b-b1bb-b5835b733900
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194331441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.194331441
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.69968355
Short name T72
Test name
Test status
Simulation time 2410794540 ps
CPU time 31.97 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:51 PM PST 24
Peak memory 212996 kb
Host smart-7f8b66ae-3e88-43dc-b29d-411b43302793
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69968355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jt
ag_regwen_during_op.69968355
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.948162885
Short name T540
Test name
Test status
Simulation time 2155665305 ps
CPU time 11.4 seconds
Started Feb 07 01:58:11 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 213196 kb
Host smart-f127250e-0cfd-4cb3-aeec-3c62f0202a1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948162885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.948162885
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3287903068
Short name T796
Test name
Test status
Simulation time 18906967055 ps
CPU time 42.89 seconds
Started Feb 07 01:58:06 PM PST 24
Finished Feb 07 01:58:49 PM PST 24
Peak memory 275500 kb
Host smart-62c5e065-1c57-41c9-a96c-18c9663b6796
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287903068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3287903068
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2666424978
Short name T637
Test name
Test status
Simulation time 358052276 ps
CPU time 12.3 seconds
Started Feb 07 01:58:10 PM PST 24
Finished Feb 07 01:58:23 PM PST 24
Peak memory 250792 kb
Host smart-32844bea-58a3-493f-90bf-8f8209a15cbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666424978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2666424978
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3950391218
Short name T400
Test name
Test status
Simulation time 381890517 ps
CPU time 4.61 seconds
Started Feb 07 01:58:08 PM PST 24
Finished Feb 07 01:58:13 PM PST 24
Peak memory 217808 kb
Host smart-79b9aa9c-5e44-49cd-9430-f4c27189b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950391218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3950391218
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3000545672
Short name T344
Test name
Test status
Simulation time 454625259 ps
CPU time 8.64 seconds
Started Feb 07 01:58:06 PM PST 24
Finished Feb 07 01:58:15 PM PST 24
Peak memory 217956 kb
Host smart-f405e75e-d97b-4f81-852d-2a36c5bc2795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000545672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3000545672
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1140416460
Short name T93
Test name
Test status
Simulation time 229445377 ps
CPU time 37.63 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:56 PM PST 24
Peak memory 281384 kb
Host smart-775156a4-fbf8-4506-9a70-6c6edde96bcc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140416460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1140416460
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.189170218
Short name T739
Test name
Test status
Simulation time 403944389 ps
CPU time 8.49 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:26 PM PST 24
Peak memory 217820 kb
Host smart-ec2111a0-d25a-49d1-aa22-ceb0ee1349fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189170218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.189170218
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2334426346
Short name T383
Test name
Test status
Simulation time 1142764836 ps
CPU time 13.59 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 217816 kb
Host smart-8825efdd-d9a4-4a90-8c84-3b5cdca410ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334426346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2334426346
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3152386607
Short name T732
Test name
Test status
Simulation time 374566242 ps
CPU time 10.13 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:30 PM PST 24
Peak memory 217776 kb
Host smart-46fc5949-06ff-4bae-bacf-62bbf9f11e55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152386607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
152386607
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1700468246
Short name T957
Test name
Test status
Simulation time 615127446 ps
CPU time 10.29 seconds
Started Feb 07 01:58:12 PM PST 24
Finished Feb 07 01:58:23 PM PST 24
Peak memory 217804 kb
Host smart-075081fa-d8a7-466c-9fe9-73cec9944e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700468246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1700468246
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2444392292
Short name T349
Test name
Test status
Simulation time 97498510 ps
CPU time 0.98 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:19 PM PST 24
Peak memory 212648 kb
Host smart-dfefbe58-e56d-4cd0-a701-1eb4d8544f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444392292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2444392292
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.61362355
Short name T38
Test name
Test status
Simulation time 1601767953 ps
CPU time 34.08 seconds
Started Feb 07 01:58:18 PM PST 24
Finished Feb 07 01:58:53 PM PST 24
Peak memory 250796 kb
Host smart-e33a1672-7ba5-4b5d-b5ce-e9dd7368fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61362355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.61362355
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3716314084
Short name T389
Test name
Test status
Simulation time 361748041 ps
CPU time 6.99 seconds
Started Feb 07 01:58:18 PM PST 24
Finished Feb 07 01:58:26 PM PST 24
Peak memory 249808 kb
Host smart-bd5af5ea-f13e-45db-8af4-4e225d8e9895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716314084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3716314084
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1950908510
Short name T537
Test name
Test status
Simulation time 1765969309 ps
CPU time 78.43 seconds
Started Feb 07 01:58:18 PM PST 24
Finished Feb 07 01:59:37 PM PST 24
Peak memory 227460 kb
Host smart-71a2b4f4-ff60-44b3-a2b6-f99c02d56fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950908510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1950908510
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3514016681
Short name T549
Test name
Test status
Simulation time 158930904 ps
CPU time 1.55 seconds
Started Feb 07 01:59:22 PM PST 24
Finished Feb 07 01:59:24 PM PST 24
Peak memory 208100 kb
Host smart-28f6856e-abf9-44fd-9818-b6e2bfb50c34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514016681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3514016681
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2837804082
Short name T54
Test name
Test status
Simulation time 909129988 ps
CPU time 20.59 seconds
Started Feb 07 01:59:15 PM PST 24
Finished Feb 07 01:59:36 PM PST 24
Peak memory 217760 kb
Host smart-5ff31941-3463-4877-9fe9-41a9037a821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837804082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2837804082
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.909788014
Short name T544
Test name
Test status
Simulation time 776282237 ps
CPU time 5.06 seconds
Started Feb 07 01:59:17 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 209412 kb
Host smart-8036a40d-2e7a-4f5b-a76f-e2c12e420045
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909788014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_ac
cess.909788014
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3344038713
Short name T731
Test name
Test status
Simulation time 1318203617 ps
CPU time 4.56 seconds
Started Feb 07 01:59:19 PM PST 24
Finished Feb 07 01:59:25 PM PST 24
Peak memory 217804 kb
Host smart-0257a501-5aeb-4cad-9360-91b2fb1722de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344038713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3344038713
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1076894185
Short name T442
Test name
Test status
Simulation time 1644894266 ps
CPU time 14.07 seconds
Started Feb 07 01:59:23 PM PST 24
Finished Feb 07 01:59:37 PM PST 24
Peak memory 217752 kb
Host smart-84752b61-7d78-4490-9c6b-ec1426c6ea89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076894185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1076894185
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3488327790
Short name T463
Test name
Test status
Simulation time 2691205969 ps
CPU time 18.11 seconds
Started Feb 07 01:59:16 PM PST 24
Finished Feb 07 01:59:35 PM PST 24
Peak memory 217888 kb
Host smart-221d25ee-3236-4700-87fa-52c56927fc11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488327790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3488327790
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3356217904
Short name T368
Test name
Test status
Simulation time 1571606088 ps
CPU time 8.48 seconds
Started Feb 07 01:59:17 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 217780 kb
Host smart-76c39995-c7ce-4a1f-a765-674006976ba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356217904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3356217904
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2373378579
Short name T920
Test name
Test status
Simulation time 229161872 ps
CPU time 9.18 seconds
Started Feb 07 01:59:18 PM PST 24
Finished Feb 07 01:59:28 PM PST 24
Peak memory 217816 kb
Host smart-c2008f96-c7ad-4113-aa14-fd54085b5c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373378579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2373378579
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2522306979
Short name T923
Test name
Test status
Simulation time 48089217 ps
CPU time 2.34 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 213684 kb
Host smart-972c5cef-8edf-462e-9fae-22a472d0a677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522306979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2522306979
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3737162296
Short name T793
Test name
Test status
Simulation time 724593161 ps
CPU time 38.52 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 02:00:04 PM PST 24
Peak memory 250668 kb
Host smart-26583a3b-e307-4cd4-99a4-fec46413c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737162296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3737162296
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.32463971
Short name T89
Test name
Test status
Simulation time 94373129 ps
CPU time 9.15 seconds
Started Feb 07 01:59:16 PM PST 24
Finished Feb 07 01:59:26 PM PST 24
Peak memory 250872 kb
Host smart-cf421a73-1437-429e-9d52-205f7962d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32463971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.32463971
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1888442190
Short name T523
Test name
Test status
Simulation time 13728707262 ps
CPU time 113.8 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 02:01:18 PM PST 24
Peak memory 273376 kb
Host smart-931b07e1-8eff-4611-b29d-9a74d0de0839
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888442190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1888442190
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.584608372
Short name T451
Test name
Test status
Simulation time 72818962 ps
CPU time 0.72 seconds
Started Feb 07 01:59:17 PM PST 24
Finished Feb 07 01:59:18 PM PST 24
Peak memory 206228 kb
Host smart-9a7f4483-f12f-4bc5-b090-4ac6cc18cdee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584608372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.584608372
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2304160471
Short name T440
Test name
Test status
Simulation time 228393756 ps
CPU time 1.26 seconds
Started Feb 07 01:59:28 PM PST 24
Finished Feb 07 01:59:30 PM PST 24
Peak memory 209412 kb
Host smart-3091fcd9-43fe-4eb9-b595-cadd9fdc29b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304160471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2304160471
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1671786381
Short name T49
Test name
Test status
Simulation time 416052210 ps
CPU time 18.13 seconds
Started Feb 07 01:59:26 PM PST 24
Finished Feb 07 01:59:45 PM PST 24
Peak memory 217816 kb
Host smart-8e16acce-4ad7-4e7d-82df-d55889292598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671786381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1671786381
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1471625187
Short name T918
Test name
Test status
Simulation time 8839191477 ps
CPU time 11.58 seconds
Started Feb 07 01:59:30 PM PST 24
Finished Feb 07 01:59:42 PM PST 24
Peak memory 209440 kb
Host smart-2171a3c5-d3ac-4855-bfc7-b0490092235a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471625187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.1471625187
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2000989723
Short name T776
Test name
Test status
Simulation time 50377620 ps
CPU time 2.63 seconds
Started Feb 07 01:59:20 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 217824 kb
Host smart-4844413a-2f05-4585-97cb-d21e05995ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000989723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2000989723
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3016336174
Short name T318
Test name
Test status
Simulation time 1441388366 ps
CPU time 13.68 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:39 PM PST 24
Peak memory 217852 kb
Host smart-b18dd4d3-88ec-4bff-b990-e9375c4df144
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016336174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3016336174
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4066694648
Short name T774
Test name
Test status
Simulation time 326689419 ps
CPU time 11.23 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:37 PM PST 24
Peak memory 217824 kb
Host smart-df181ccd-ab99-406b-90e8-6dba33054fbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066694648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4066694648
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1358604343
Short name T564
Test name
Test status
Simulation time 324370347 ps
CPU time 7.28 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 01:59:41 PM PST 24
Peak memory 217840 kb
Host smart-3ec9a2d1-c229-4c43-9f38-96b9606a54e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358604343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1358604343
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.981006586
Short name T350
Test name
Test status
Simulation time 120840269 ps
CPU time 3.96 seconds
Started Feb 07 01:59:23 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 214348 kb
Host smart-7fb89889-9ad3-44f1-8599-cba38f33c2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981006586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.981006586
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3430667867
Short name T391
Test name
Test status
Simulation time 210597963 ps
CPU time 23.76 seconds
Started Feb 07 01:59:23 PM PST 24
Finished Feb 07 01:59:47 PM PST 24
Peak memory 250828 kb
Host smart-8c3fb479-3378-46d9-8849-830bf87ca37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430667867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3430667867
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.192490096
Short name T534
Test name
Test status
Simulation time 137877189 ps
CPU time 5.82 seconds
Started Feb 07 01:59:17 PM PST 24
Finished Feb 07 01:59:24 PM PST 24
Peak memory 243820 kb
Host smart-585f863b-8ad7-494b-b90f-52b1ce8dbca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192490096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.192490096
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.32306817
Short name T405
Test name
Test status
Simulation time 6073804200 ps
CPU time 133.87 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 02:01:39 PM PST 24
Peak memory 277388 kb
Host smart-bc4da1fb-e1d4-4f4d-8d1e-ee0965d11890
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32306817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.lc_ctrl_stress_all.32306817
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1499528229
Short name T495
Test name
Test status
Simulation time 18755869 ps
CPU time 0.77 seconds
Started Feb 07 01:59:25 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 207680 kb
Host smart-901a6448-2dbe-4a6a-90aa-b70d2eee587e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499528229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1499528229
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4108107548
Short name T429
Test name
Test status
Simulation time 53537282 ps
CPU time 1.38 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 208284 kb
Host smart-542df7e5-007e-4c8d-872f-e2b9b9b8fb67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108107548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4108107548
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2780685201
Short name T873
Test name
Test status
Simulation time 1843777832 ps
CPU time 11.35 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 01:59:45 PM PST 24
Peak memory 217780 kb
Host smart-da98b9e3-6137-430a-be6e-0474297064ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780685201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2780685201
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2158176021
Short name T585
Test name
Test status
Simulation time 3251750126 ps
CPU time 3.76 seconds
Started Feb 07 01:59:21 PM PST 24
Finished Feb 07 01:59:26 PM PST 24
Peak memory 209476 kb
Host smart-d4fa6b8e-511b-4058-96a9-976f6f4c11b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158176021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.2158176021
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1454102166
Short name T624
Test name
Test status
Simulation time 82165939 ps
CPU time 3.17 seconds
Started Feb 07 01:59:29 PM PST 24
Finished Feb 07 01:59:33 PM PST 24
Peak memory 218000 kb
Host smart-696bce36-e21f-4e48-90fc-a0caf2c8c130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454102166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1454102166
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1126893419
Short name T327
Test name
Test status
Simulation time 1155713640 ps
CPU time 15.2 seconds
Started Feb 07 01:59:29 PM PST 24
Finished Feb 07 01:59:45 PM PST 24
Peak memory 217800 kb
Host smart-d78b06a1-bd92-4067-b4fa-577c49d3576e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126893419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1126893419
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1831655357
Short name T369
Test name
Test status
Simulation time 410068654 ps
CPU time 15.93 seconds
Started Feb 07 01:59:28 PM PST 24
Finished Feb 07 01:59:44 PM PST 24
Peak memory 217824 kb
Host smart-a04fbe04-4512-4bb8-a2f5-52bd8b42e56e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831655357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1831655357
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3940026493
Short name T734
Test name
Test status
Simulation time 270750885 ps
CPU time 10.46 seconds
Started Feb 07 01:59:29 PM PST 24
Finished Feb 07 01:59:40 PM PST 24
Peak memory 217828 kb
Host smart-c00fc508-ba1b-4545-a3d1-2366d2d5436e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940026493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3940026493
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.890391939
Short name T475
Test name
Test status
Simulation time 603824128 ps
CPU time 9.43 seconds
Started Feb 07 01:59:22 PM PST 24
Finished Feb 07 01:59:32 PM PST 24
Peak memory 217808 kb
Host smart-50766758-089b-4fe1-b75d-1389af347543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890391939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.890391939
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1682106943
Short name T82
Test name
Test status
Simulation time 126977052 ps
CPU time 2.38 seconds
Started Feb 07 01:59:30 PM PST 24
Finished Feb 07 01:59:33 PM PST 24
Peak memory 213740 kb
Host smart-189b025c-e1f5-4d57-873a-6124760f4b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682106943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1682106943
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1299109636
Short name T489
Test name
Test status
Simulation time 208262253 ps
CPU time 17.09 seconds
Started Feb 07 01:59:30 PM PST 24
Finished Feb 07 01:59:48 PM PST 24
Peak memory 250780 kb
Host smart-87b0bda5-1e7b-482c-844f-f7fa1b372276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299109636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1299109636
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1756150105
Short name T851
Test name
Test status
Simulation time 172409690 ps
CPU time 2.84 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:28 PM PST 24
Peak memory 221876 kb
Host smart-088b1dd7-110b-4657-b581-f752ec644eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756150105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1756150105
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3706877005
Short name T615
Test name
Test status
Simulation time 10649708700 ps
CPU time 93.07 seconds
Started Feb 07 01:59:30 PM PST 24
Finished Feb 07 02:01:04 PM PST 24
Peak memory 250936 kb
Host smart-7f489dcb-0e75-4364-ba3d-9a6da262968e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706877005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3706877005
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2855460497
Short name T815
Test name
Test status
Simulation time 125349529286 ps
CPU time 1300.27 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 02:21:14 PM PST 24
Peak memory 349340 kb
Host smart-3f2cfd41-6492-4f2a-9a10-8b19c8e144a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2855460497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2855460497
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.859313423
Short name T568
Test name
Test status
Simulation time 23321242 ps
CPU time 0.91 seconds
Started Feb 07 01:59:21 PM PST 24
Finished Feb 07 01:59:23 PM PST 24
Peak memory 211248 kb
Host smart-de42aa42-73cd-49d0-9bb7-aacad58a8350
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859313423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.859313423
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2694774034
Short name T398
Test name
Test status
Simulation time 21830390 ps
CPU time 1.33 seconds
Started Feb 07 01:59:32 PM PST 24
Finished Feb 07 01:59:34 PM PST 24
Peak memory 209400 kb
Host smart-2c227375-b8b1-4e12-a04d-f5a460322a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694774034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2694774034
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.721262994
Short name T505
Test name
Test status
Simulation time 606112763 ps
CPU time 15.88 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 217784 kb
Host smart-6c63eaff-f854-4b36-823a-eb7358f10a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721262994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.721262994
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1735718708
Short name T813
Test name
Test status
Simulation time 181627219 ps
CPU time 1.33 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:26 PM PST 24
Peak memory 209460 kb
Host smart-c545c58c-e824-42d1-890f-d6f17577193f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735718708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.1735718708
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3261588655
Short name T338
Test name
Test status
Simulation time 87760594 ps
CPU time 3.88 seconds
Started Feb 07 01:59:34 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 217800 kb
Host smart-cf1286f1-e85c-4a82-9456-50f380336db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261588655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3261588655
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2504895535
Short name T930
Test name
Test status
Simulation time 193645268 ps
CPU time 10.82 seconds
Started Feb 07 01:59:30 PM PST 24
Finished Feb 07 01:59:42 PM PST 24
Peak memory 217872 kb
Host smart-ef4b5719-c0d7-4288-979b-7a3870f9157d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504895535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2504895535
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.635100931
Short name T103
Test name
Test status
Simulation time 395830826 ps
CPU time 10.85 seconds
Started Feb 07 01:59:27 PM PST 24
Finished Feb 07 01:59:39 PM PST 24
Peak memory 217844 kb
Host smart-f2d4c9ee-d113-4fef-9b60-9179a96f49a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635100931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.635100931
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2416744181
Short name T443
Test name
Test status
Simulation time 1160443221 ps
CPU time 13.51 seconds
Started Feb 07 01:59:23 PM PST 24
Finished Feb 07 01:59:37 PM PST 24
Peak memory 217816 kb
Host smart-4102d3d4-1405-452c-a16d-9ba06dd0d356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416744181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2416744181
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3122670472
Short name T594
Test name
Test status
Simulation time 314676669 ps
CPU time 13.07 seconds
Started Feb 07 01:59:36 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 217820 kb
Host smart-6afbfad3-1ae4-49a2-a5da-86c877107588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122670472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3122670472
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1789151619
Short name T83
Test name
Test status
Simulation time 151860100 ps
CPU time 2.6 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:27 PM PST 24
Peak memory 213960 kb
Host smart-5f5d5991-1f32-442c-a9d8-a0a3171ff1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789151619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1789151619
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3583635695
Short name T722
Test name
Test status
Simulation time 261681033 ps
CPU time 22.31 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 01:59:58 PM PST 24
Peak memory 250784 kb
Host smart-d48112ee-eb06-4a0d-8de0-153979b3c93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583635695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3583635695
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3586315621
Short name T417
Test name
Test status
Simulation time 96591050 ps
CPU time 7.13 seconds
Started Feb 07 01:59:30 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 250320 kb
Host smart-2778450a-205d-4fdd-9100-9a4b574648c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586315621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3586315621
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.617773439
Short name T981
Test name
Test status
Simulation time 1737260249 ps
CPU time 30.38 seconds
Started Feb 07 01:59:27 PM PST 24
Finished Feb 07 01:59:58 PM PST 24
Peak memory 245620 kb
Host smart-42b47c37-8a61-4f63-8ef0-a7bce1a4a230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617773439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.617773439
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2220844353
Short name T809
Test name
Test status
Simulation time 19236459361 ps
CPU time 204.71 seconds
Started Feb 07 01:59:34 PM PST 24
Finished Feb 07 02:02:59 PM PST 24
Peak memory 316588 kb
Host smart-84b24d1c-e1c6-4064-be7b-1d475c5de985
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2220844353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2220844353
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3282418465
Short name T45
Test name
Test status
Simulation time 13843015 ps
CPU time 1.01 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 01:59:37 PM PST 24
Peak memory 208160 kb
Host smart-e7c526f1-83df-43e0-ac02-638dccab29b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282418465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3282418465
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.468060797
Short name T667
Test name
Test status
Simulation time 83159253 ps
CPU time 0.96 seconds
Started Feb 07 01:59:27 PM PST 24
Finished Feb 07 01:59:29 PM PST 24
Peak memory 208176 kb
Host smart-2a1e10f7-bf14-4aab-8345-991fdd3903a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468060797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.468060797
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3352818470
Short name T701
Test name
Test status
Simulation time 343414843 ps
CPU time 13.99 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 01:59:47 PM PST 24
Peak memory 217788 kb
Host smart-87544a5b-5ebb-4484-be35-237961326b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352818470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3352818470
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1204336301
Short name T966
Test name
Test status
Simulation time 1237106281 ps
CPU time 6.28 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:31 PM PST 24
Peak memory 209416 kb
Host smart-222ba7df-a1c9-42e5-8666-5b82a1e8c2b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204336301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_a
ccess.1204336301
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.985215810
Short name T632
Test name
Test status
Simulation time 85051430 ps
CPU time 1.93 seconds
Started Feb 07 01:59:29 PM PST 24
Finished Feb 07 01:59:32 PM PST 24
Peak memory 217820 kb
Host smart-836dce73-338a-4394-ac16-b7f0abc127ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985215810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.985215810
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1934579956
Short name T947
Test name
Test status
Simulation time 902727960 ps
CPU time 10.5 seconds
Started Feb 07 01:59:26 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 217860 kb
Host smart-720042b6-7988-43a8-b302-2036fa449dfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934579956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1934579956
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1680758920
Short name T725
Test name
Test status
Simulation time 193759990 ps
CPU time 7.39 seconds
Started Feb 07 01:59:29 PM PST 24
Finished Feb 07 01:59:37 PM PST 24
Peak memory 217800 kb
Host smart-3823a73d-b934-478a-9063-177abcf1e28c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680758920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1680758920
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3721120551
Short name T857
Test name
Test status
Simulation time 1408090937 ps
CPU time 12.15 seconds
Started Feb 07 01:59:26 PM PST 24
Finished Feb 07 01:59:39 PM PST 24
Peak memory 217788 kb
Host smart-7c88dc46-b197-42d7-9073-7989031454e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721120551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3721120551
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1406940898
Short name T838
Test name
Test status
Simulation time 1506051374 ps
CPU time 10.6 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 01:59:46 PM PST 24
Peak memory 217764 kb
Host smart-d1dac0bf-39b7-41ed-8ed7-fb9b2cadbd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406940898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1406940898
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1062190248
Short name T34
Test name
Test status
Simulation time 21512609 ps
CPU time 1.7 seconds
Started Feb 07 01:59:25 PM PST 24
Finished Feb 07 01:59:28 PM PST 24
Peak memory 213328 kb
Host smart-269fe758-bc94-4baa-8b80-e09e66b25584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062190248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1062190248
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1349564300
Short name T900
Test name
Test status
Simulation time 250852632 ps
CPU time 27.53 seconds
Started Feb 07 01:59:26 PM PST 24
Finished Feb 07 01:59:55 PM PST 24
Peak memory 250788 kb
Host smart-f9514cfb-1e80-4ad6-8570-333ce652f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349564300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1349564300
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2814812020
Short name T106
Test name
Test status
Simulation time 248398172 ps
CPU time 8.77 seconds
Started Feb 07 01:59:30 PM PST 24
Finished Feb 07 01:59:40 PM PST 24
Peak memory 249612 kb
Host smart-efe5b71e-53f5-4939-835a-87be56744ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814812020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2814812020
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.4284469654
Short name T705
Test name
Test status
Simulation time 5133895026 ps
CPU time 27.61 seconds
Started Feb 07 01:59:24 PM PST 24
Finished Feb 07 01:59:53 PM PST 24
Peak memory 226032 kb
Host smart-673fb51b-2314-4373-87d0-5d62e8380256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284469654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.4284469654
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2000566260
Short name T940
Test name
Test status
Simulation time 70215445 ps
CPU time 0.91 seconds
Started Feb 07 01:59:28 PM PST 24
Finished Feb 07 01:59:30 PM PST 24
Peak memory 211280 kb
Host smart-5c830a4e-b162-4555-a741-3514f77618ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000566260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2000566260
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.472340804
Short name T73
Test name
Test status
Simulation time 25051959 ps
CPU time 0.97 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 01:59:51 PM PST 24
Peak memory 208084 kb
Host smart-ffcd6798-e99e-4e61-b1cf-598509e972da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472340804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.472340804
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.4176870723
Short name T538
Test name
Test status
Simulation time 819591501 ps
CPU time 17.38 seconds
Started Feb 07 01:59:31 PM PST 24
Finished Feb 07 01:59:49 PM PST 24
Peak memory 217808 kb
Host smart-06f6f6f1-8e14-47ef-9199-3e610d13f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176870723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.4176870723
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1291973517
Short name T494
Test name
Test status
Simulation time 2787550506 ps
CPU time 7.74 seconds
Started Feb 07 01:59:27 PM PST 24
Finished Feb 07 01:59:35 PM PST 24
Peak memory 209472 kb
Host smart-4d6da5c6-9104-44db-9846-f369c9610d7c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291973517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_a
ccess.1291973517
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2839393458
Short name T320
Test name
Test status
Simulation time 308344706 ps
CPU time 3.06 seconds
Started Feb 07 01:59:39 PM PST 24
Finished Feb 07 01:59:43 PM PST 24
Peak memory 217868 kb
Host smart-1756ac96-9f16-4d9e-aca6-5b21d48b86fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839393458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2839393458
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2753434420
Short name T614
Test name
Test status
Simulation time 1267531659 ps
CPU time 16.03 seconds
Started Feb 07 01:59:31 PM PST 24
Finished Feb 07 01:59:48 PM PST 24
Peak memory 218808 kb
Host smart-776b458f-bd84-4128-bb99-4b1cd11a63a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753434420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2753434420
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3462980776
Short name T893
Test name
Test status
Simulation time 392490387 ps
CPU time 10.45 seconds
Started Feb 07 01:59:28 PM PST 24
Finished Feb 07 01:59:39 PM PST 24
Peak memory 217876 kb
Host smart-474c8081-68b1-427c-a26a-1b96a39b6ab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462980776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3462980776
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.833358164
Short name T650
Test name
Test status
Simulation time 1038438107 ps
CPU time 10.57 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 01:59:47 PM PST 24
Peak memory 217676 kb
Host smart-7fce163c-bbde-47ef-83e3-45216f34d59d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833358164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.833358164
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1410787994
Short name T682
Test name
Test status
Simulation time 2073828749 ps
CPU time 10.39 seconds
Started Feb 07 01:59:26 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 217812 kb
Host smart-cbe5a38a-58b4-4320-8dc9-74bfa7bca19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410787994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1410787994
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3883031695
Short name T831
Test name
Test status
Simulation time 99218215 ps
CPU time 1.68 seconds
Started Feb 07 01:59:36 PM PST 24
Finished Feb 07 01:59:39 PM PST 24
Peak memory 213136 kb
Host smart-b7ecff90-fa0e-41af-817b-589ce5efc919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883031695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3883031695
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.871345898
Short name T470
Test name
Test status
Simulation time 177534249 ps
CPU time 17.13 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 01:59:53 PM PST 24
Peak memory 250676 kb
Host smart-89882ad3-c501-4897-ae5c-09ae7c80b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871345898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.871345898
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1200410106
Short name T928
Test name
Test status
Simulation time 244872155 ps
CPU time 3.57 seconds
Started Feb 07 01:59:29 PM PST 24
Finished Feb 07 01:59:34 PM PST 24
Peak memory 217800 kb
Host smart-145f832d-8ddd-4ddd-a59b-b3f1eb49e4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200410106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1200410106
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.109232068
Short name T524
Test name
Test status
Simulation time 43467949345 ps
CPU time 175.21 seconds
Started Feb 07 01:59:44 PM PST 24
Finished Feb 07 02:02:40 PM PST 24
Peak memory 421912 kb
Host smart-4af4496e-44a4-4fd7-84f0-9eb5d0d74ffa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109232068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.109232068
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.992726673
Short name T717
Test name
Test status
Simulation time 13286288 ps
CPU time 0.95 seconds
Started Feb 07 01:59:27 PM PST 24
Finished Feb 07 01:59:29 PM PST 24
Peak memory 207964 kb
Host smart-1ab6d34a-366d-485e-93aa-5ecc1190ca97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992726673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.992726673
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.4236406185
Short name T95
Test name
Test status
Simulation time 78334697 ps
CPU time 1.14 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 01:59:36 PM PST 24
Peak memory 209400 kb
Host smart-13de8aa7-6229-4b79-88f3-80e8bb3169b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236406185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.4236406185
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3251043367
Short name T727
Test name
Test status
Simulation time 340113659 ps
CPU time 11.54 seconds
Started Feb 07 01:59:42 PM PST 24
Finished Feb 07 01:59:55 PM PST 24
Peak memory 217860 kb
Host smart-a3ed8d3c-8629-4317-a7ff-3d6dc44935d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251043367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3251043367
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.4236881643
Short name T600
Test name
Test status
Simulation time 1563864184 ps
CPU time 10.6 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 01:59:52 PM PST 24
Peak memory 209356 kb
Host smart-a0b53ce9-dde6-4974-a1d8-860401737485
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236881643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.4236881643
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1934513794
Short name T454
Test name
Test status
Simulation time 91527494 ps
CPU time 3.31 seconds
Started Feb 07 01:59:42 PM PST 24
Finished Feb 07 01:59:47 PM PST 24
Peak memory 217836 kb
Host smart-160c90d3-2d65-4425-b13a-bdc85c3e6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934513794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1934513794
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1856240171
Short name T22
Test name
Test status
Simulation time 870460457 ps
CPU time 9.82 seconds
Started Feb 07 01:59:34 PM PST 24
Finished Feb 07 01:59:45 PM PST 24
Peak memory 218812 kb
Host smart-b18cfd3f-812a-493e-965e-9299338b1cf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856240171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1856240171
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.384837715
Short name T897
Test name
Test status
Simulation time 776824141 ps
CPU time 13.01 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 01:59:54 PM PST 24
Peak memory 217760 kb
Host smart-15249bb9-a3fc-4401-a59c-f6795a327067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384837715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.384837715
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2271825249
Short name T553
Test name
Test status
Simulation time 527957115 ps
CPU time 18.47 seconds
Started Feb 07 01:59:40 PM PST 24
Finished Feb 07 01:59:59 PM PST 24
Peak memory 217892 kb
Host smart-a6aaf575-9bb1-4333-ac31-bb4921fc63a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271825249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2271825249
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1452413765
Short name T902
Test name
Test status
Simulation time 2217327121 ps
CPU time 11.06 seconds
Started Feb 07 01:59:45 PM PST 24
Finished Feb 07 01:59:57 PM PST 24
Peak memory 217872 kb
Host smart-2d40b63f-f7b6-40cb-b2c2-569368955b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452413765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1452413765
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.4275868204
Short name T409
Test name
Test status
Simulation time 91044707 ps
CPU time 1.02 seconds
Started Feb 07 01:59:47 PM PST 24
Finished Feb 07 01:59:49 PM PST 24
Peak memory 211616 kb
Host smart-23402823-05ef-4e40-b52e-47380d045fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275868204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.4275868204
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.4082955863
Short name T658
Test name
Test status
Simulation time 1815618294 ps
CPU time 22.58 seconds
Started Feb 07 01:59:43 PM PST 24
Finished Feb 07 02:00:06 PM PST 24
Peak memory 250812 kb
Host smart-404c2721-7795-456f-a0f1-138700a81766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082955863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.4082955863
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2808122742
Short name T515
Test name
Test status
Simulation time 78969233 ps
CPU time 10.5 seconds
Started Feb 07 01:59:39 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 250924 kb
Host smart-f6216d4b-b829-4180-8559-01b71b41499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808122742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2808122742
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2857746587
Short name T56
Test name
Test status
Simulation time 6931725442 ps
CPU time 156.88 seconds
Started Feb 07 01:59:32 PM PST 24
Finished Feb 07 02:02:09 PM PST 24
Peak memory 332344 kb
Host smart-829c41c0-d684-414e-8af6-be41730f6097
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857746587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2857746587
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2343513199
Short name T899
Test name
Test status
Simulation time 22636514 ps
CPU time 0.93 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 01:59:35 PM PST 24
Peak memory 207920 kb
Host smart-eba43792-89ad-4ee7-a757-f8073056efd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343513199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2343513199
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4240076991
Short name T373
Test name
Test status
Simulation time 64377626 ps
CPU time 0.91 seconds
Started Feb 07 01:59:47 PM PST 24
Finished Feb 07 01:59:48 PM PST 24
Peak memory 208952 kb
Host smart-37ad57dd-2dbd-43bc-951f-2c443a4edf40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240076991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4240076991
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3240387500
Short name T356
Test name
Test status
Simulation time 451978084 ps
CPU time 8.86 seconds
Started Feb 07 01:59:40 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 217748 kb
Host smart-82b1b13d-c1f8-4cd2-b024-c840095993af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240387500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3240387500
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3027402749
Short name T859
Test name
Test status
Simulation time 1140374853 ps
CPU time 8.12 seconds
Started Feb 07 01:59:34 PM PST 24
Finished Feb 07 01:59:43 PM PST 24
Peak memory 209432 kb
Host smart-4313ebe6-9c31-4a25-86a9-36ee24c87acc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027402749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.3027402749
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3653364648
Short name T444
Test name
Test status
Simulation time 258402590 ps
CPU time 3.43 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 01:59:37 PM PST 24
Peak memory 217776 kb
Host smart-b298ca34-2570-4738-8cd9-a40f13166e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653364648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3653364648
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2632982490
Short name T961
Test name
Test status
Simulation time 438895164 ps
CPU time 19.12 seconds
Started Feb 07 01:59:40 PM PST 24
Finished Feb 07 02:00:00 PM PST 24
Peak memory 217856 kb
Host smart-68df3e9c-783a-43af-a738-89109513b86e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632982490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2632982490
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4048681593
Short name T908
Test name
Test status
Simulation time 275995868 ps
CPU time 9.33 seconds
Started Feb 07 01:59:35 PM PST 24
Finished Feb 07 01:59:45 PM PST 24
Peak memory 217876 kb
Host smart-f80f8754-4723-4497-a94f-067b1f704733
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048681593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4048681593
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2927835351
Short name T874
Test name
Test status
Simulation time 1202448542 ps
CPU time 11.71 seconds
Started Feb 07 01:59:42 PM PST 24
Finished Feb 07 01:59:55 PM PST 24
Peak memory 217820 kb
Host smart-d79879eb-e4fd-41a4-8b32-645c80c8f120
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927835351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2927835351
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1847336822
Short name T587
Test name
Test status
Simulation time 220309333 ps
CPU time 3.02 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 01:59:45 PM PST 24
Peak memory 213900 kb
Host smart-33167328-a294-4040-af59-fa369b0edaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847336822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1847336822
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3142704663
Short name T820
Test name
Test status
Simulation time 320783652 ps
CPU time 23.66 seconds
Started Feb 07 01:59:34 PM PST 24
Finished Feb 07 01:59:58 PM PST 24
Peak memory 250832 kb
Host smart-92265c09-604c-49c6-ae36-76a37175f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142704663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3142704663
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3921312144
Short name T576
Test name
Test status
Simulation time 1631094091 ps
CPU time 6.81 seconds
Started Feb 07 01:59:42 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 246916 kb
Host smart-0cfd7408-c411-4eb8-927d-7c45bdb93ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921312144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3921312144
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1462741939
Short name T936
Test name
Test status
Simulation time 3351412330 ps
CPU time 108.62 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 02:01:31 PM PST 24
Peak memory 236376 kb
Host smart-704aac7e-5f27-4d1f-8840-00411312efe0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462741939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1462741939
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3552283852
Short name T110
Test name
Test status
Simulation time 82341476001 ps
CPU time 493.69 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 02:07:48 PM PST 24
Peak memory 480404 kb
Host smart-13eb5a74-622f-44b3-8050-01fb4f66e096
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3552283852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3552283852
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.387990814
Short name T660
Test name
Test status
Simulation time 22609079 ps
CPU time 0.84 seconds
Started Feb 07 01:59:40 PM PST 24
Finished Feb 07 01:59:42 PM PST 24
Peak memory 208372 kb
Host smart-0bfa0657-d0c5-4917-8d0f-c29ee6528f72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387990814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.387990814
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.328827223
Short name T493
Test name
Test status
Simulation time 51476464 ps
CPU time 0.8 seconds
Started Feb 07 01:59:44 PM PST 24
Finished Feb 07 01:59:45 PM PST 24
Peak memory 207760 kb
Host smart-f5fdd5e7-aabb-4df0-88e7-5f43895d26ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328827223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.328827223
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.25477657
Short name T974
Test name
Test status
Simulation time 321683774 ps
CPU time 11.13 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 01:59:52 PM PST 24
Peak memory 217816 kb
Host smart-c9fa8b5e-a5ff-4654-be96-cc77a9487401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25477657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.25477657
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.679692257
Short name T695
Test name
Test status
Simulation time 704957811 ps
CPU time 5 seconds
Started Feb 07 01:59:33 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 209476 kb
Host smart-63107c50-53ea-4a3a-a137-bd4faaab6c15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679692257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_ac
cess.679692257
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.896677784
Short name T342
Test name
Test status
Simulation time 263583364 ps
CPU time 3.78 seconds
Started Feb 07 01:59:42 PM PST 24
Finished Feb 07 01:59:47 PM PST 24
Peak memory 217500 kb
Host smart-cb3bac0f-541d-4533-a28b-9d3471661a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896677784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.896677784
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.4138954278
Short name T683
Test name
Test status
Simulation time 1070696200 ps
CPU time 9.45 seconds
Started Feb 07 01:59:47 PM PST 24
Finished Feb 07 01:59:57 PM PST 24
Peak memory 218300 kb
Host smart-85c75aee-19ab-4d6c-a348-da736ab81ff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138954278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.4138954278
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4003277181
Short name T559
Test name
Test status
Simulation time 1407449790 ps
CPU time 13.57 seconds
Started Feb 07 01:59:45 PM PST 24
Finished Feb 07 01:59:59 PM PST 24
Peak memory 217824 kb
Host smart-be3fecf7-617f-47d3-872c-1eab6a521912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003277181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4003277181
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2771587149
Short name T546
Test name
Test status
Simulation time 1752330145 ps
CPU time 15.56 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 01:59:58 PM PST 24
Peak memory 217816 kb
Host smart-8d249aad-b6e0-4b4c-9916-497bf59a25a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771587149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2771587149
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2313804151
Short name T14
Test name
Test status
Simulation time 19359294 ps
CPU time 1.72 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 01:59:43 PM PST 24
Peak memory 213288 kb
Host smart-25f0c70e-4b89-47b1-a8e4-ea753f86188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313804151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2313804151
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1203276421
Short name T952
Test name
Test status
Simulation time 405543148 ps
CPU time 31.63 seconds
Started Feb 07 01:59:46 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 250792 kb
Host smart-5c5372d2-b642-406b-b0f9-2b43a9dd24ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203276421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1203276421
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3495254040
Short name T844
Test name
Test status
Simulation time 89852617 ps
CPU time 7.86 seconds
Started Feb 07 01:59:39 PM PST 24
Finished Feb 07 01:59:48 PM PST 24
Peak memory 250404 kb
Host smart-2ee71068-ad07-4e23-814a-a836a2a675d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495254040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3495254040
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2669749132
Short name T898
Test name
Test status
Simulation time 1916326295 ps
CPU time 36.96 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 247148 kb
Host smart-8b9a2650-2f3b-4dc7-8f01-3dc40c779a70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669749132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2669749132
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2337046479
Short name T423
Test name
Test status
Simulation time 13295215 ps
CPU time 0.85 seconds
Started Feb 07 01:59:38 PM PST 24
Finished Feb 07 01:59:39 PM PST 24
Peak memory 207872 kb
Host smart-3e15bde2-52ca-4cd5-a6e3-f68a69204282
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337046479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2337046479
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3162954034
Short name T812
Test name
Test status
Simulation time 50267461 ps
CPU time 1 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 209356 kb
Host smart-111cd061-4594-4a5f-b9ef-7f82b4e10abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162954034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3162954034
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.224211196
Short name T426
Test name
Test status
Simulation time 706940547 ps
CPU time 17.65 seconds
Started Feb 07 02:00:00 PM PST 24
Finished Feb 07 02:00:23 PM PST 24
Peak memory 217824 kb
Host smart-4f7af9f3-8288-4948-b197-e917debaf256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224211196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.224211196
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2952130596
Short name T476
Test name
Test status
Simulation time 962590089 ps
CPU time 5.86 seconds
Started Feb 07 01:59:47 PM PST 24
Finished Feb 07 01:59:54 PM PST 24
Peak memory 209460 kb
Host smart-7ab17027-3cbb-4ffe-a7e7-8defd046a725
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952130596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.2952130596
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2623505017
Short name T304
Test name
Test status
Simulation time 77649023 ps
CPU time 3.13 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 01:59:46 PM PST 24
Peak memory 217804 kb
Host smart-db70bc9b-78e2-4a58-8dd3-7c8e95c8047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623505017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2623505017
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1755827653
Short name T416
Test name
Test status
Simulation time 3933965951 ps
CPU time 12.54 seconds
Started Feb 07 01:59:54 PM PST 24
Finished Feb 07 02:00:13 PM PST 24
Peak memory 218848 kb
Host smart-50213882-b747-497f-b032-af666cf7fb78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755827653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1755827653
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2095697766
Short name T453
Test name
Test status
Simulation time 1366474365 ps
CPU time 12.13 seconds
Started Feb 07 01:59:54 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 217824 kb
Host smart-34fa4599-faad-4fa0-8d71-edfe99d34233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095697766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2095697766
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.842653874
Short name T305
Test name
Test status
Simulation time 422495733 ps
CPU time 9.94 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 01:59:59 PM PST 24
Peak memory 217856 kb
Host smart-4eddcaee-5c19-4944-98ab-611a802df2f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842653874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.842653874
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2567015573
Short name T711
Test name
Test status
Simulation time 1531709826 ps
CPU time 9.62 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 02:00:00 PM PST 24
Peak memory 217912 kb
Host smart-bbff5be8-77ea-4213-9a8c-1946da75e78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567015573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2567015573
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1674049618
Short name T15
Test name
Test status
Simulation time 134880135 ps
CPU time 1.82 seconds
Started Feb 07 01:59:51 PM PST 24
Finished Feb 07 01:59:53 PM PST 24
Peak memory 213404 kb
Host smart-c8bbc465-fb32-4495-a16f-5853811d9bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674049618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1674049618
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2558184846
Short name T112
Test name
Test status
Simulation time 1588339515 ps
CPU time 41.61 seconds
Started Feb 07 01:59:52 PM PST 24
Finished Feb 07 02:00:34 PM PST 24
Peak memory 250840 kb
Host smart-f39bd464-6c64-4fed-b116-2fefa25a0119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558184846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2558184846
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3838908384
Short name T965
Test name
Test status
Simulation time 96027232 ps
CPU time 6.58 seconds
Started Feb 07 01:59:55 PM PST 24
Finished Feb 07 02:00:07 PM PST 24
Peak memory 249576 kb
Host smart-13d6acf9-57df-4d91-a455-c70bc3ed487a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838908384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3838908384
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1838442826
Short name T479
Test name
Test status
Simulation time 3868172454 ps
CPU time 37.05 seconds
Started Feb 07 01:59:47 PM PST 24
Finished Feb 07 02:00:25 PM PST 24
Peak memory 250952 kb
Host smart-88b7e5ed-cddd-4ffb-8a80-3112e7d645c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838442826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1838442826
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3313890359
Short name T971
Test name
Test status
Simulation time 139541928 ps
CPU time 0.86 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 211152 kb
Host smart-7e345461-322d-4ecd-917a-97e1b0c96198
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313890359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3313890359
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2973260929
Short name T783
Test name
Test status
Simulation time 30542213 ps
CPU time 1.19 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 208288 kb
Host smart-0c0b5489-8eae-4d40-8425-c76386657a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973260929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2973260929
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3074078583
Short name T910
Test name
Test status
Simulation time 59767727 ps
CPU time 0.86 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:18 PM PST 24
Peak memory 209204 kb
Host smart-bb678627-ecda-4ed7-97f7-bf828d205cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074078583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3074078583
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3558888437
Short name T674
Test name
Test status
Simulation time 317003992 ps
CPU time 15.17 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:33 PM PST 24
Peak memory 217852 kb
Host smart-ed4fcd83-5b6e-4606-bdc0-9e6b9620daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558888437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3558888437
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1199847420
Short name T826
Test name
Test status
Simulation time 7138717810 ps
CPU time 13.16 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:33 PM PST 24
Peak memory 209484 kb
Host smart-f36bb77d-2898-4baa-837e-7c380d90ebce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199847420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.1199847420
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2645773702
Short name T875
Test name
Test status
Simulation time 13001949930 ps
CPU time 33.51 seconds
Started Feb 07 01:58:22 PM PST 24
Finished Feb 07 01:58:56 PM PST 24
Peak memory 218820 kb
Host smart-a57d14e5-5f5c-4505-b92c-ab0999c838e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645773702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2645773702
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1824076142
Short name T954
Test name
Test status
Simulation time 902940449 ps
CPU time 3.01 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:21 PM PST 24
Peak memory 209536 kb
Host smart-69de599a-48b5-4c33-a46a-8e8fd8efae9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824076142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.1824076142
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1933582884
Short name T387
Test name
Test status
Simulation time 142946830 ps
CPU time 3.09 seconds
Started Feb 07 01:58:16 PM PST 24
Finished Feb 07 01:58:20 PM PST 24
Peak memory 217844 kb
Host smart-72074f86-30cb-4dac-8a10-4626aa6e4bdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933582884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1933582884
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2047816371
Short name T840
Test name
Test status
Simulation time 1369091567 ps
CPU time 8.34 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:30 PM PST 24
Peak memory 212660 kb
Host smart-7b3c7cb8-1a15-4cc6-a3d2-9ce0f672b69c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047816371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2047816371
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3504301589
Short name T79
Test name
Test status
Simulation time 428179504 ps
CPU time 11.54 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:31 PM PST 24
Peak memory 213288 kb
Host smart-d3897023-ca38-4be7-8b91-098dabf8bcc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504301589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3504301589
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.443075637
Short name T490
Test name
Test status
Simulation time 3176284052 ps
CPU time 59.46 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:59:21 PM PST 24
Peak memory 277276 kb
Host smart-2615469e-186f-48bb-a538-e8f0e8f34c2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443075637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.443075637
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3981469612
Short name T486
Test name
Test status
Simulation time 940778569 ps
CPU time 13.62 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 250820 kb
Host smart-8f4a5847-f9e1-4be3-8a6c-1f84a6bf83f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981469612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3981469612
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4087923265
Short name T430
Test name
Test status
Simulation time 24611210 ps
CPU time 1.93 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 217864 kb
Host smart-d948150b-c880-42f5-95cd-5a69e99f4721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087923265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4087923265
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.934510554
Short name T726
Test name
Test status
Simulation time 1491361071 ps
CPU time 12.82 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:32 PM PST 24
Peak memory 214096 kb
Host smart-b3b0d5d1-fe13-48d3-8b50-0b87e6a3829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934510554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.934510554
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3175374913
Short name T685
Test name
Test status
Simulation time 1357355203 ps
CPU time 18.67 seconds
Started Feb 07 01:58:18 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 218052 kb
Host smart-d10e8f31-af1a-4642-8b64-4afc95d6cf98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175374913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3175374913
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3550347712
Short name T639
Test name
Test status
Simulation time 3791795447 ps
CPU time 10.29 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:30 PM PST 24
Peak memory 217884 kb
Host smart-9d9f7c39-7f9d-4047-bc6f-bcc873e2f0ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550347712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3550347712
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3729909436
Short name T872
Test name
Test status
Simulation time 458308656 ps
CPU time 10.78 seconds
Started Feb 07 01:58:20 PM PST 24
Finished Feb 07 01:58:31 PM PST 24
Peak memory 217872 kb
Host smart-9f340d25-9b2b-4bb7-9205-2e6d5fef35ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729909436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
729909436
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4279696660
Short name T502
Test name
Test status
Simulation time 1231972003 ps
CPU time 12.46 seconds
Started Feb 07 01:58:15 PM PST 24
Finished Feb 07 01:58:28 PM PST 24
Peak memory 217872 kb
Host smart-dae3442b-1d0a-40ef-906c-933f63a396e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279696660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4279696660
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.39426767
Short name T901
Test name
Test status
Simulation time 224235294 ps
CPU time 6 seconds
Started Feb 07 01:58:17 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 214276 kb
Host smart-73f53e12-2957-4d06-8a02-88a85f571dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39426767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.39426767
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2433729456
Short name T865
Test name
Test status
Simulation time 668867321 ps
CPU time 32.84 seconds
Started Feb 07 01:58:15 PM PST 24
Finished Feb 07 01:58:48 PM PST 24
Peak memory 250824 kb
Host smart-0cac255c-b38d-45f4-b80c-e9aa9be77d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433729456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2433729456
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3145269449
Short name T871
Test name
Test status
Simulation time 329489666 ps
CPU time 7.57 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:28 PM PST 24
Peak memory 250764 kb
Host smart-6aa3d1f2-eff6-44c3-b640-aaf81eafc929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145269449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3145269449
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3673772591
Short name T158
Test name
Test status
Simulation time 52328978622 ps
CPU time 209.72 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 02:01:51 PM PST 24
Peak memory 226092 kb
Host smart-29458e1e-16dd-4972-8594-ef9fbcc59120
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673772591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3673772591
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.805440844
Short name T907
Test name
Test status
Simulation time 11971970 ps
CPU time 0.93 seconds
Started Feb 07 01:58:20 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 207904 kb
Host smart-a8d211a8-691a-4cb2-9d33-4b14d53ef025
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805440844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.805440844
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3092793713
Short name T561
Test name
Test status
Simulation time 79404959 ps
CPU time 1.04 seconds
Started Feb 07 01:59:55 PM PST 24
Finished Feb 07 02:00:01 PM PST 24
Peak memory 209400 kb
Host smart-bc2d3229-7288-4392-9613-18752bc8a39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092793713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3092793713
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.4109201866
Short name T420
Test name
Test status
Simulation time 657009096 ps
CPU time 15.79 seconds
Started Feb 07 01:59:42 PM PST 24
Finished Feb 07 01:59:59 PM PST 24
Peak memory 217828 kb
Host smart-a0e81449-24ff-4365-a876-058e8def48ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109201866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.4109201866
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1308096874
Short name T926
Test name
Test status
Simulation time 316600780 ps
CPU time 8.55 seconds
Started Feb 07 01:59:50 PM PST 24
Finished Feb 07 02:00:00 PM PST 24
Peak memory 209408 kb
Host smart-120af166-c00c-4ec6-8587-24d955ccada5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308096874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.1308096874
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1542562126
Short name T750
Test name
Test status
Simulation time 797947242 ps
CPU time 2.88 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 01:59:52 PM PST 24
Peak memory 217828 kb
Host smart-89a504f1-ccd9-49df-9202-bc04002461b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542562126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1542562126
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.981902440
Short name T638
Test name
Test status
Simulation time 4201917794 ps
CPU time 10.99 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 02:00:00 PM PST 24
Peak memory 217860 kb
Host smart-71fcbd66-d1f3-4bb5-99ac-863dd312de70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981902440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.981902440
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1414241826
Short name T46
Test name
Test status
Simulation time 586479840 ps
CPU time 13.69 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 02:00:04 PM PST 24
Peak memory 217812 kb
Host smart-f73f16d1-aa82-490b-9346-7bfe295fea3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414241826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1414241826
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1974662858
Short name T316
Test name
Test status
Simulation time 628131891 ps
CPU time 13.48 seconds
Started Feb 07 01:59:50 PM PST 24
Finished Feb 07 02:00:04 PM PST 24
Peak memory 217792 kb
Host smart-ce360677-e46d-4edf-a124-3c1b6c33117d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974662858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1974662858
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.480980580
Short name T376
Test name
Test status
Simulation time 315412998 ps
CPU time 9.42 seconds
Started Feb 07 01:59:51 PM PST 24
Finished Feb 07 02:00:01 PM PST 24
Peak memory 217820 kb
Host smart-9dc44e74-6238-4b53-a06d-53cd975d05d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480980580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.480980580
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3242032591
Short name T985
Test name
Test status
Simulation time 50875596 ps
CPU time 3.54 seconds
Started Feb 07 01:59:55 PM PST 24
Finished Feb 07 02:00:04 PM PST 24
Peak memory 214356 kb
Host smart-b3957f91-0caa-4a58-9c4a-2e367b019079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242032591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3242032591
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.674425228
Short name T310
Test name
Test status
Simulation time 206093599 ps
CPU time 21.65 seconds
Started Feb 07 01:59:47 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 250816 kb
Host smart-491466aa-6f3d-44e5-a52e-3f8b0df6368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674425228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.674425228
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2077819426
Short name T758
Test name
Test status
Simulation time 1321536417 ps
CPU time 8.55 seconds
Started Feb 07 01:59:41 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 250912 kb
Host smart-4bfc07f6-fa7e-46a7-8158-5b4330d44ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077819426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2077819426
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.4058525207
Short name T699
Test name
Test status
Simulation time 16140606897 ps
CPU time 64.28 seconds
Started Feb 07 01:59:50 PM PST 24
Finished Feb 07 02:00:55 PM PST 24
Peak memory 277512 kb
Host smart-53039c81-634c-4fa5-9eaa-f93179d3b6cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058525207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.4058525207
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1370343550
Short name T631
Test name
Test status
Simulation time 11185059 ps
CPU time 0.81 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 208064 kb
Host smart-4a728a94-7030-47ed-a415-501ec3918f61
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370343550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1370343550
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2856535759
Short name T23
Test name
Test status
Simulation time 23204438 ps
CPU time 1.26 seconds
Started Feb 07 01:59:57 PM PST 24
Finished Feb 07 02:00:02 PM PST 24
Peak memory 209364 kb
Host smart-a46dd31e-ad44-47c6-9a5a-fea5312fad5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856535759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2856535759
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3544576843
Short name T775
Test name
Test status
Simulation time 399072752 ps
CPU time 8.8 seconds
Started Feb 07 01:59:45 PM PST 24
Finished Feb 07 01:59:55 PM PST 24
Peak memory 217784 kb
Host smart-f30e89eb-993b-403d-97e2-d1552bed2f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544576843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3544576843
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.986667077
Short name T929
Test name
Test status
Simulation time 364128312 ps
CPU time 4.99 seconds
Started Feb 07 01:59:50 PM PST 24
Finished Feb 07 01:59:56 PM PST 24
Peak memory 209432 kb
Host smart-8ca37633-82a4-4e19-938d-a244f10d87ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986667077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_ac
cess.986667077
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2894909302
Short name T418
Test name
Test status
Simulation time 117567051 ps
CPU time 2.06 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 01:59:51 PM PST 24
Peak memory 217788 kb
Host smart-8bd87c0f-1c83-4e1f-89d2-a55da7f86877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894909302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2894909302
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1660773190
Short name T968
Test name
Test status
Simulation time 1214435914 ps
CPU time 12.44 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 02:00:03 PM PST 24
Peak memory 217784 kb
Host smart-e8c8f617-6f7b-4a3c-a337-da29123ca077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660773190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1660773190
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2466157433
Short name T399
Test name
Test status
Simulation time 204684926 ps
CPU time 9.42 seconds
Started Feb 07 01:59:58 PM PST 24
Finished Feb 07 02:00:10 PM PST 24
Peak memory 217868 kb
Host smart-8f8f5d5e-d64e-4bd1-a286-a48302120b51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466157433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2466157433
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2691700674
Short name T949
Test name
Test status
Simulation time 341915375 ps
CPU time 12.6 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:14 PM PST 24
Peak memory 217888 kb
Host smart-2f8cbe95-9132-4cee-bacb-2a1852154a5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691700674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2691700674
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3616770249
Short name T341
Test name
Test status
Simulation time 31252834 ps
CPU time 2.42 seconds
Started Feb 07 01:59:57 PM PST 24
Finished Feb 07 02:00:03 PM PST 24
Peak memory 213304 kb
Host smart-67f8e30a-df11-43b7-82f3-140332b9e749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616770249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3616770249
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3609515829
Short name T450
Test name
Test status
Simulation time 174258733 ps
CPU time 19.53 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 250864 kb
Host smart-ed97f189-be36-438d-9f30-673c092e2d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609515829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3609515829
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1705554739
Short name T485
Test name
Test status
Simulation time 91388420 ps
CPU time 2.71 seconds
Started Feb 07 01:59:42 PM PST 24
Finished Feb 07 01:59:45 PM PST 24
Peak memory 222768 kb
Host smart-364581e3-7731-4c54-9364-291f2a9035e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705554739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1705554739
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3248257066
Short name T850
Test name
Test status
Simulation time 2261236805 ps
CPU time 85.56 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 02:01:14 PM PST 24
Peak memory 268188 kb
Host smart-de1a85b0-e915-4845-9ade-def09774a060
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248257066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3248257066
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.103866157
Short name T361
Test name
Test status
Simulation time 26597660 ps
CPU time 1.22 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 01:59:50 PM PST 24
Peak memory 212476 kb
Host smart-b62c5a3e-81e8-4c6d-9961-901fda121bb2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103866157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.103866157
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3191320589
Short name T621
Test name
Test status
Simulation time 31385365 ps
CPU time 0.97 seconds
Started Feb 07 01:59:50 PM PST 24
Finished Feb 07 01:59:52 PM PST 24
Peak memory 209392 kb
Host smart-d3f4e30d-eaf4-4d3b-b52e-e6252f802729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191320589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3191320589
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1884072963
Short name T439
Test name
Test status
Simulation time 1149786700 ps
CPU time 12.78 seconds
Started Feb 07 01:59:54 PM PST 24
Finished Feb 07 02:00:13 PM PST 24
Peak memory 217824 kb
Host smart-97770a34-cb97-420c-bcd6-372e85a43d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884072963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1884072963
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2908929268
Short name T617
Test name
Test status
Simulation time 282662567 ps
CPU time 3.71 seconds
Started Feb 07 01:59:58 PM PST 24
Finished Feb 07 02:00:05 PM PST 24
Peak memory 209476 kb
Host smart-889a9a47-67ad-4294-99a5-da30aa0ed860
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908929268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.2908929268
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.485133220
Short name T478
Test name
Test status
Simulation time 351240349 ps
CPU time 3.11 seconds
Started Feb 07 01:59:50 PM PST 24
Finished Feb 07 01:59:54 PM PST 24
Peak memory 217768 kb
Host smart-80a6ccda-4a13-4dad-9b37-20953871ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485133220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.485133220
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.990240197
Short name T979
Test name
Test status
Simulation time 341955150 ps
CPU time 15.03 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 02:00:03 PM PST 24
Peak memory 217912 kb
Host smart-d20113e6-aca5-4833-84ce-b84f806d7564
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990240197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.990240197
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2564936636
Short name T604
Test name
Test status
Simulation time 1325058336 ps
CPU time 10.86 seconds
Started Feb 07 01:59:57 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 217812 kb
Host smart-352bd563-35c0-4a4a-82eb-3043be7e7a64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564936636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2564936636
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1628602022
Short name T58
Test name
Test status
Simulation time 484399137 ps
CPU time 10.99 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:17 PM PST 24
Peak memory 217756 kb
Host smart-1a6bff58-f545-4641-a792-8abaad1bf172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628602022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1628602022
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4252987529
Short name T513
Test name
Test status
Simulation time 712111088 ps
CPU time 10.09 seconds
Started Feb 07 01:59:54 PM PST 24
Finished Feb 07 02:00:10 PM PST 24
Peak memory 217804 kb
Host smart-511d3e63-21ed-4d65-8208-c4a0e4dd9b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252987529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4252987529
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2963898850
Short name T343
Test name
Test status
Simulation time 52125736 ps
CPU time 3.13 seconds
Started Feb 07 01:59:58 PM PST 24
Finished Feb 07 02:00:04 PM PST 24
Peak memory 213744 kb
Host smart-4db9eb2e-fe7d-4079-baf6-bc0c35308ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963898850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2963898850
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1973724992
Short name T934
Test name
Test status
Simulation time 244778136 ps
CPU time 26.67 seconds
Started Feb 07 01:59:57 PM PST 24
Finished Feb 07 02:00:27 PM PST 24
Peak memory 250808 kb
Host smart-04a8507b-1597-4a22-b474-7502c1ac2e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973724992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1973724992
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1356634442
Short name T567
Test name
Test status
Simulation time 255495250 ps
CPU time 6.57 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 01:59:57 PM PST 24
Peak memory 246448 kb
Host smart-118db64f-a7c1-4f4c-aafa-7b8293f1faa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356634442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1356634442
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1920527844
Short name T982
Test name
Test status
Simulation time 10022452790 ps
CPU time 340.6 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 02:05:31 PM PST 24
Peak memory 254820 kb
Host smart-a108881e-9680-4fc6-98bd-bbca3e9243a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920527844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1920527844
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.451021752
Short name T723
Test name
Test status
Simulation time 32998689 ps
CPU time 0.87 seconds
Started Feb 07 01:59:49 PM PST 24
Finished Feb 07 01:59:51 PM PST 24
Peak memory 207908 kb
Host smart-0a439126-9a0c-432e-89b6-6e23049ae4e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451021752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.451021752
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3492641113
Short name T787
Test name
Test status
Simulation time 29552532 ps
CPU time 0.9 seconds
Started Feb 07 01:59:56 PM PST 24
Finished Feb 07 02:00:01 PM PST 24
Peak memory 209368 kb
Host smart-26e7f3fd-c1a8-435d-bbda-a8dd52e54866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492641113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3492641113
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3220630476
Short name T480
Test name
Test status
Simulation time 4325356783 ps
CPU time 26.42 seconds
Started Feb 07 01:59:56 PM PST 24
Finished Feb 07 02:00:27 PM PST 24
Peak memory 218008 kb
Host smart-8dde95cc-28a5-4a76-aa50-e22d2ee67b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220630476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3220630476
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2590052211
Short name T8
Test name
Test status
Simulation time 348601799 ps
CPU time 9.37 seconds
Started Feb 07 01:59:52 PM PST 24
Finished Feb 07 02:00:03 PM PST 24
Peak memory 209460 kb
Host smart-96616c57-2f2d-4ffd-b3b3-2e53041b1930
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590052211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.2590052211
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2278499513
Short name T307
Test name
Test status
Simulation time 222566282 ps
CPU time 3.33 seconds
Started Feb 07 01:59:50 PM PST 24
Finished Feb 07 01:59:54 PM PST 24
Peak memory 217876 kb
Host smart-0b608aeb-ea0b-415b-bd4a-91e8a8fddb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278499513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2278499513
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.772283763
Short name T24
Test name
Test status
Simulation time 912631956 ps
CPU time 20.19 seconds
Started Feb 07 01:59:48 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 218844 kb
Host smart-29661628-cc6c-4557-9b1c-8602bd5d6614
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772283763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.772283763
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1462717660
Short name T781
Test name
Test status
Simulation time 560215253 ps
CPU time 9.86 seconds
Started Feb 07 02:00:00 PM PST 24
Finished Feb 07 02:00:16 PM PST 24
Peak memory 217812 kb
Host smart-30610f3f-23e3-45a9-ba9b-8f8a1f8a8702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462717660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1462717660
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3971924962
Short name T749
Test name
Test status
Simulation time 235267227 ps
CPU time 9.37 seconds
Started Feb 07 01:59:58 PM PST 24
Finished Feb 07 02:00:10 PM PST 24
Peak memory 217856 kb
Host smart-a87e71d7-8255-451d-bd89-75c4db71eb15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971924962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3971924962
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3915091434
Short name T88
Test name
Test status
Simulation time 561503073 ps
CPU time 9.07 seconds
Started Feb 07 01:59:55 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 217860 kb
Host smart-8259022a-ed00-446f-bdd6-22a16e8bc7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915091434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3915091434
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.533302533
Short name T644
Test name
Test status
Simulation time 99350761 ps
CPU time 4.92 seconds
Started Feb 07 01:59:57 PM PST 24
Finished Feb 07 02:00:05 PM PST 24
Peak memory 217632 kb
Host smart-794604be-82f1-4ebc-b90e-8076155e1b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533302533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.533302533
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1908946119
Short name T780
Test name
Test status
Simulation time 204815168 ps
CPU time 16.76 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:21 PM PST 24
Peak memory 250852 kb
Host smart-228e649d-e31e-4f7a-bce2-72441855498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908946119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1908946119
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2745074922
Short name T962
Test name
Test status
Simulation time 63909095 ps
CPU time 6.71 seconds
Started Feb 07 01:59:58 PM PST 24
Finished Feb 07 02:00:08 PM PST 24
Peak memory 243720 kb
Host smart-2b0a797f-b0b2-448e-b910-dbfa4bf4c969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745074922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2745074922
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4218039802
Short name T113
Test name
Test status
Simulation time 10814084274 ps
CPU time 366.13 seconds
Started Feb 07 01:59:57 PM PST 24
Finished Feb 07 02:06:07 PM PST 24
Peak memory 251288 kb
Host smart-09adf490-0307-4daa-903e-b3feadd56674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218039802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4218039802
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3190554619
Short name T765
Test name
Test status
Simulation time 44927813 ps
CPU time 0.92 seconds
Started Feb 07 01:59:56 PM PST 24
Finished Feb 07 02:00:01 PM PST 24
Peak memory 207912 kb
Host smart-945aa867-c23b-4610-8691-12cab9c23a47
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190554619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3190554619
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3374594288
Short name T501
Test name
Test status
Simulation time 52624484 ps
CPU time 1.08 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 209368 kb
Host smart-131a975f-cefb-40c4-b2a5-f09f77aaef5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374594288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3374594288
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2328523861
Short name T330
Test name
Test status
Simulation time 262680370 ps
CPU time 13.83 seconds
Started Feb 07 02:00:01 PM PST 24
Finished Feb 07 02:00:20 PM PST 24
Peak memory 217776 kb
Host smart-b13c0a3a-7e51-4f83-8a1a-791962f3d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328523861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2328523861
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1476050480
Short name T972
Test name
Test status
Simulation time 1640483873 ps
CPU time 5.85 seconds
Started Feb 07 02:00:11 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 209424 kb
Host smart-47c5a552-6f9c-4cbd-bb89-85c6627798bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476050480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.1476050480
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.318610728
Short name T545
Test name
Test status
Simulation time 69281623 ps
CPU time 2.93 seconds
Started Feb 07 01:59:54 PM PST 24
Finished Feb 07 02:00:03 PM PST 24
Peak memory 217892 kb
Host smart-68bff748-4638-40f9-8583-a5c406f0f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318610728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.318610728
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2437309719
Short name T397
Test name
Test status
Simulation time 279056912 ps
CPU time 10.07 seconds
Started Feb 07 02:00:14 PM PST 24
Finished Feb 07 02:00:25 PM PST 24
Peak memory 218832 kb
Host smart-fb7115a4-0fd0-4b94-839f-c68eedbcccd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437309719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2437309719
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3459239005
Short name T518
Test name
Test status
Simulation time 460811761 ps
CPU time 12.17 seconds
Started Feb 07 02:00:02 PM PST 24
Finished Feb 07 02:00:20 PM PST 24
Peak memory 217876 kb
Host smart-6ccb6189-0b29-472c-8467-c27aa1beaa6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459239005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3459239005
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.595164558
Short name T835
Test name
Test status
Simulation time 1535037725 ps
CPU time 9.73 seconds
Started Feb 07 02:00:02 PM PST 24
Finished Feb 07 02:00:17 PM PST 24
Peak memory 217804 kb
Host smart-bf9ae598-31b6-438c-8a0e-1288bedd7044
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595164558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.595164558
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.665971762
Short name T16
Test name
Test status
Simulation time 1449951847 ps
CPU time 13.67 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:00:21 PM PST 24
Peak memory 217748 kb
Host smart-c56a6017-f735-4643-8706-d75d15995dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665971762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.665971762
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4290743712
Short name T499
Test name
Test status
Simulation time 62632390 ps
CPU time 2.35 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:08 PM PST 24
Peak memory 213524 kb
Host smart-dfbedb40-2a51-4664-b4ab-61442d8e9229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290743712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4290743712
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1099584608
Short name T663
Test name
Test status
Simulation time 742556271 ps
CPU time 33.6 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:43 PM PST 24
Peak memory 250740 kb
Host smart-aff5550b-9daa-49b4-ac1a-beadb5c08559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099584608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1099584608
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3527613177
Short name T964
Test name
Test status
Simulation time 286846458 ps
CPU time 2.82 seconds
Started Feb 07 02:00:04 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 220364 kb
Host smart-4814f2dc-ef61-4cf3-9f50-1520864d793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527613177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3527613177
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3796691896
Short name T87
Test name
Test status
Simulation time 1774762377 ps
CPU time 91.36 seconds
Started Feb 07 02:00:05 PM PST 24
Finished Feb 07 02:01:39 PM PST 24
Peak memory 250680 kb
Host smart-19ca9539-75f3-4a9c-84ec-65dedb3ca3ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796691896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3796691896
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2509067176
Short name T435
Test name
Test status
Simulation time 32533868 ps
CPU time 0.87 seconds
Started Feb 07 02:00:00 PM PST 24
Finished Feb 07 02:00:07 PM PST 24
Peak memory 207864 kb
Host smart-818b4242-4fd4-4cd1-afe8-650190459eeb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509067176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2509067176
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3832647255
Short name T94
Test name
Test status
Simulation time 21031327 ps
CPU time 0.9 seconds
Started Feb 07 02:00:00 PM PST 24
Finished Feb 07 02:00:07 PM PST 24
Peak memory 209336 kb
Host smart-0c71c3eb-5890-4a45-a560-86ec3e221d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832647255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3832647255
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.524331042
Short name T785
Test name
Test status
Simulation time 307938437 ps
CPU time 11.5 seconds
Started Feb 07 02:00:01 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 217744 kb
Host smart-5a80ac82-bcbb-4fa3-a32e-c61a0ff8ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524331042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.524331042
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4161673629
Short name T565
Test name
Test status
Simulation time 1639491631 ps
CPU time 3.75 seconds
Started Feb 07 02:00:07 PM PST 24
Finished Feb 07 02:00:14 PM PST 24
Peak memory 209540 kb
Host smart-d558e776-9cf2-4661-8527-f377968cf84c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161673629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.4161673629
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4086718200
Short name T382
Test name
Test status
Simulation time 436242588 ps
CPU time 2.99 seconds
Started Feb 07 02:00:01 PM PST 24
Finished Feb 07 02:00:10 PM PST 24
Peak memory 217824 kb
Host smart-5b76a1ff-ba64-4999-a04a-54d409661497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086718200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4086718200
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.414802009
Short name T108
Test name
Test status
Simulation time 938420718 ps
CPU time 9.58 seconds
Started Feb 07 02:00:02 PM PST 24
Finished Feb 07 02:00:17 PM PST 24
Peak memory 217808 kb
Host smart-cdac875a-a75c-49cb-87a4-9ba71364d1ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414802009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.414802009
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2509625269
Short name T714
Test name
Test status
Simulation time 1275237034 ps
CPU time 11.34 seconds
Started Feb 07 02:00:01 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 217780 kb
Host smart-05cdac80-afb1-46e2-ba03-91e30795f3ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509625269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2509625269
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3809185763
Short name T825
Test name
Test status
Simulation time 1410935239 ps
CPU time 13.08 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:22 PM PST 24
Peak memory 217820 kb
Host smart-0a0bec96-9e99-4bc5-a573-8fc3c4f75654
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809185763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3809185763
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3487965122
Short name T401
Test name
Test status
Simulation time 214432876 ps
CPU time 6.45 seconds
Started Feb 07 02:00:05 PM PST 24
Finished Feb 07 02:00:14 PM PST 24
Peak memory 217704 kb
Host smart-7a8de45b-608a-4084-bd43-007dd18c086a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487965122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3487965122
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1737044027
Short name T566
Test name
Test status
Simulation time 52352673 ps
CPU time 2.94 seconds
Started Feb 07 02:00:00 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 213664 kb
Host smart-e7a79f79-90ff-4236-9ad0-fa9846023da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737044027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1737044027
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.348952971
Short name T313
Test name
Test status
Simulation time 1045051809 ps
CPU time 20.49 seconds
Started Feb 07 02:00:05 PM PST 24
Finished Feb 07 02:00:28 PM PST 24
Peak memory 250804 kb
Host smart-cfd9817d-c0e0-449d-b20a-62c626831aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348952971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.348952971
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.819984634
Short name T337
Test name
Test status
Simulation time 249571972 ps
CPU time 3.54 seconds
Started Feb 07 02:00:04 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 221936 kb
Host smart-7c3aa065-7375-481d-a52e-1ee33b0fa494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819984634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.819984634
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1916748199
Short name T746
Test name
Test status
Simulation time 467009629 ps
CPU time 24.03 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:33 PM PST 24
Peak memory 250880 kb
Host smart-1785b220-40be-4536-8579-e58468a17552
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916748199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1916748199
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.316070332
Short name T42
Test name
Test status
Simulation time 38235534 ps
CPU time 0.81 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:07 PM PST 24
Peak memory 207668 kb
Host smart-a7145af7-d378-4204-910a-0256d08afc05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316070332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.316070332
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3768038969
Short name T789
Test name
Test status
Simulation time 39490852 ps
CPU time 0.77 seconds
Started Feb 07 02:00:12 PM PST 24
Finished Feb 07 02:00:14 PM PST 24
Peak memory 209244 kb
Host smart-e2cd5b87-3ecd-485a-8e15-8b7e493fbbb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768038969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3768038969
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2766225628
Short name T584
Test name
Test status
Simulation time 519160603 ps
CPU time 21.2 seconds
Started Feb 07 01:59:58 PM PST 24
Finished Feb 07 02:00:22 PM PST 24
Peak memory 217852 kb
Host smart-aabb49e5-d86d-4fae-a7a5-7bb5c8bde7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766225628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2766225628
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3407037657
Short name T491
Test name
Test status
Simulation time 37651091 ps
CPU time 1.16 seconds
Started Feb 07 02:00:01 PM PST 24
Finished Feb 07 02:00:08 PM PST 24
Peak memory 209384 kb
Host smart-057e7c4e-7f34-4df4-8d97-6410aefdac3f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407037657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.3407037657
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1590117162
Short name T861
Test name
Test status
Simulation time 95750510 ps
CPU time 3.13 seconds
Started Feb 07 02:00:05 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 217824 kb
Host smart-28d50dc9-9429-446a-b463-8b246b6b71db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590117162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1590117162
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.157701948
Short name T526
Test name
Test status
Simulation time 260081851 ps
CPU time 10.26 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 218104 kb
Host smart-fbb7d34e-7ad4-44b5-8622-e6a2f4873912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157701948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.157701948
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.834025422
Short name T990
Test name
Test status
Simulation time 262850915 ps
CPU time 12.32 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 217864 kb
Host smart-dd255b2a-5ae2-41d0-a943-335da57674e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834025422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.834025422
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2424123045
Short name T803
Test name
Test status
Simulation time 2448654344 ps
CPU time 19.15 seconds
Started Feb 07 01:59:57 PM PST 24
Finished Feb 07 02:00:20 PM PST 24
Peak memory 217880 kb
Host smart-4061078a-876f-427d-b307-2797e0c8d527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424123045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2424123045
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4013874428
Short name T709
Test name
Test status
Simulation time 1470044208 ps
CPU time 10.55 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:20 PM PST 24
Peak memory 217868 kb
Host smart-be92fa70-4d92-46c4-b9b4-f8ccaf200c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013874428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4013874428
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3756003667
Short name T827
Test name
Test status
Simulation time 374504505 ps
CPU time 3.22 seconds
Started Feb 07 02:00:02 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 214112 kb
Host smart-bfb233b7-8837-4a84-adc1-d06b31690ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756003667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3756003667
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1800897215
Short name T528
Test name
Test status
Simulation time 387977070 ps
CPU time 21.45 seconds
Started Feb 07 02:00:02 PM PST 24
Finished Feb 07 02:00:29 PM PST 24
Peak memory 243764 kb
Host smart-1e1618b1-1fe8-4dc0-9232-90cb21e922e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800897215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1800897215
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.197882784
Short name T555
Test name
Test status
Simulation time 92319068 ps
CPU time 3.08 seconds
Started Feb 07 02:00:01 PM PST 24
Finished Feb 07 02:00:10 PM PST 24
Peak memory 221828 kb
Host smart-d05214cb-aa8c-4398-8061-220f44b46933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197882784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.197882784
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.138073930
Short name T969
Test name
Test status
Simulation time 15410304759 ps
CPU time 243.75 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:04:11 PM PST 24
Peak memory 250800 kb
Host smart-520d3da7-b232-428e-ad04-a64f1a048147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138073930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.138073930
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1151197592
Short name T853
Test name
Test status
Simulation time 51835797933 ps
CPU time 261.75 seconds
Started Feb 07 01:59:58 PM PST 24
Finished Feb 07 02:04:23 PM PST 24
Peak memory 283840 kb
Host smart-83a9a767-60c7-45b8-809d-b583def196b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1151197592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1151197592
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2891592882
Short name T603
Test name
Test status
Simulation time 84750705 ps
CPU time 0.83 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:00:08 PM PST 24
Peak memory 207872 kb
Host smart-1ca1918b-0980-4f6b-a6aa-d102cb75cf18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891592882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2891592882
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3555098958
Short name T760
Test name
Test status
Simulation time 128507306 ps
CPU time 1.16 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 209344 kb
Host smart-1e36c414-9c48-4ac9-9cd9-fe4c3f2a1a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555098958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3555098958
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3863105695
Short name T870
Test name
Test status
Simulation time 401357991 ps
CPU time 17.38 seconds
Started Feb 07 02:00:01 PM PST 24
Finished Feb 07 02:00:24 PM PST 24
Peak memory 217824 kb
Host smart-3a9480f1-3c2d-4960-a65e-f7640b00bcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863105695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3863105695
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3951692485
Short name T797
Test name
Test status
Simulation time 1521752301 ps
CPU time 9.68 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:00:17 PM PST 24
Peak memory 209308 kb
Host smart-6c5f197d-f7c0-41a9-8548-b242ff103f54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951692485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.3951692485
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4204316694
Short name T66
Test name
Test status
Simulation time 399393767 ps
CPU time 3.38 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 217868 kb
Host smart-4416a51a-a086-4d2c-90a5-753b1b2f9cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204316694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4204316694
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2775236418
Short name T619
Test name
Test status
Simulation time 329308787 ps
CPU time 12.2 seconds
Started Feb 07 01:59:57 PM PST 24
Finished Feb 07 02:00:13 PM PST 24
Peak memory 217760 kb
Host smart-6f2e1a40-8ee0-45c8-b0dc-71c5060902b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775236418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2775236418
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1280241244
Short name T312
Test name
Test status
Simulation time 348389524 ps
CPU time 14.11 seconds
Started Feb 07 02:00:02 PM PST 24
Finished Feb 07 02:00:22 PM PST 24
Peak memory 217880 kb
Host smart-9654d88a-ba20-4385-9fe8-84cc27e4dc94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280241244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1280241244
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3477068372
Short name T830
Test name
Test status
Simulation time 1297174357 ps
CPU time 8.47 seconds
Started Feb 07 02:00:04 PM PST 24
Finished Feb 07 02:00:16 PM PST 24
Peak memory 217796 kb
Host smart-66524de2-acc5-47aa-9b76-94af5d96810d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477068372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3477068372
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2495046208
Short name T622
Test name
Test status
Simulation time 188259638 ps
CPU time 8.7 seconds
Started Feb 07 02:00:13 PM PST 24
Finished Feb 07 02:00:23 PM PST 24
Peak memory 217856 kb
Host smart-2a340079-1b78-4732-a1fc-7af7f825d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495046208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2495046208
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2976147869
Short name T447
Test name
Test status
Simulation time 43989478 ps
CPU time 2.47 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:03 PM PST 24
Peak memory 213544 kb
Host smart-31ca6feb-f930-4777-ab6a-6bf08bdb41a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976147869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2976147869
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2246571383
Short name T691
Test name
Test status
Simulation time 281042757 ps
CPU time 29.45 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:00:37 PM PST 24
Peak memory 250656 kb
Host smart-6e6c59b5-f14e-4f88-9623-ef85cc5a8274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246571383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2246571383
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2658845625
Short name T558
Test name
Test status
Simulation time 158888754 ps
CPU time 2.75 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:00:10 PM PST 24
Peak memory 221696 kb
Host smart-3e0b04d9-d5ce-49b2-8277-5bc2b0c05aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658845625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2658845625
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3722947408
Short name T570
Test name
Test status
Simulation time 113317354939 ps
CPU time 233.3 seconds
Started Feb 07 02:00:01 PM PST 24
Finished Feb 07 02:04:00 PM PST 24
Peak memory 286508 kb
Host smart-7c52cce1-650d-4a9d-8282-6590c0867928
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722947408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3722947408
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1602316262
Short name T386
Test name
Test status
Simulation time 21361780 ps
CPU time 0.76 seconds
Started Feb 07 02:00:03 PM PST 24
Finished Feb 07 02:00:08 PM PST 24
Peak memory 207696 kb
Host smart-0b60ac41-dd62-465e-a6ac-c2d9a7f351c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602316262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1602316262
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1489582607
Short name T916
Test name
Test status
Simulation time 78475447 ps
CPU time 0.89 seconds
Started Feb 07 02:00:05 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 208160 kb
Host smart-74ab29aa-82cd-4516-872c-251614d81e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489582607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1489582607
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2164661193
Short name T655
Test name
Test status
Simulation time 1753669943 ps
CPU time 8.6 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 217868 kb
Host smart-67ec3220-5501-40fe-a37d-aa6a85e91689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164661193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2164661193
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4268666066
Short name T811
Test name
Test status
Simulation time 1078812430 ps
CPU time 3.93 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:05 PM PST 24
Peak memory 209488 kb
Host smart-5a689b2a-91ae-401e-92b2-3c82ae254ab9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268666066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.4268666066
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.247353139
Short name T777
Test name
Test status
Simulation time 85532508 ps
CPU time 2.84 seconds
Started Feb 07 02:00:05 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 217824 kb
Host smart-8ac6b991-989d-439e-b461-4fad8b02d624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247353139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.247353139
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4266925666
Short name T324
Test name
Test status
Simulation time 688916546 ps
CPU time 14.63 seconds
Started Feb 07 02:00:00 PM PST 24
Finished Feb 07 02:00:21 PM PST 24
Peak memory 218804 kb
Host smart-ad76d925-4bbf-4383-af3a-d3e98fa4f310
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266925666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4266925666
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3124884934
Short name T333
Test name
Test status
Simulation time 804698863 ps
CPU time 10.31 seconds
Started Feb 07 02:00:02 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 217804 kb
Host smart-3cab955d-27ea-4b87-bbaa-dae3ac6ebd94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124884934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3124884934
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2032893388
Short name T945
Test name
Test status
Simulation time 819345866 ps
CPU time 6.06 seconds
Started Feb 07 02:00:00 PM PST 24
Finished Feb 07 02:00:12 PM PST 24
Peak memory 217836 kb
Host smart-1cba37ef-5836-446e-a743-841aa3e255de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032893388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2032893388
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1574672110
Short name T766
Test name
Test status
Simulation time 547542702 ps
CPU time 10.53 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 217796 kb
Host smart-70c6fc91-c1eb-4a48-bf39-e6348d2b6d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574672110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1574672110
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3188129247
Short name T944
Test name
Test status
Simulation time 73989817 ps
CPU time 1.85 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:11 PM PST 24
Peak memory 213656 kb
Host smart-bb30a95f-c71b-48c2-a5e6-725c85e91cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188129247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3188129247
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2525724121
Short name T308
Test name
Test status
Simulation time 1805569503 ps
CPU time 32.83 seconds
Started Feb 07 02:00:11 PM PST 24
Finished Feb 07 02:00:45 PM PST 24
Peak memory 250832 kb
Host smart-677cfa70-2a67-4f79-9710-5c0658dc28bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525724121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2525724121
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1141842001
Short name T404
Test name
Test status
Simulation time 89035000 ps
CPU time 6.84 seconds
Started Feb 07 02:00:11 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 245436 kb
Host smart-cf519b9b-8108-4772-bf74-9e668fa91049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141842001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1141842001
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.661407264
Short name T17
Test name
Test status
Simulation time 1744130759 ps
CPU time 113.57 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:02:03 PM PST 24
Peak memory 268480 kb
Host smart-c6dce225-7d07-4d25-a1fc-57b670160ebb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661407264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.661407264
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.720541658
Short name T107
Test name
Test status
Simulation time 12624246 ps
CPU time 0.92 seconds
Started Feb 07 02:00:05 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 207952 kb
Host smart-d886d372-b2b4-4c23-836a-651c361c477b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720541658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.720541658
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1001292278
Short name T379
Test name
Test status
Simulation time 25808567 ps
CPU time 0.99 seconds
Started Feb 07 02:00:08 PM PST 24
Finished Feb 07 02:00:12 PM PST 24
Peak memory 209380 kb
Host smart-044cbad5-7930-4268-b6ce-8dca8ed705e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001292278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1001292278
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3299698665
Short name T883
Test name
Test status
Simulation time 1093985165 ps
CPU time 13.94 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:23 PM PST 24
Peak memory 217796 kb
Host smart-f61a1d98-70af-4df4-9eed-b442c96fbec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299698665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3299698665
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2626654418
Short name T805
Test name
Test status
Simulation time 222101806 ps
CPU time 3.67 seconds
Started Feb 07 02:00:12 PM PST 24
Finished Feb 07 02:00:16 PM PST 24
Peak memory 209432 kb
Host smart-a63480d0-917f-49d6-b96d-8eecca4b3b56
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626654418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.2626654418
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.273719475
Short name T848
Test name
Test status
Simulation time 181985762 ps
CPU time 2.65 seconds
Started Feb 07 02:00:08 PM PST 24
Finished Feb 07 02:00:13 PM PST 24
Peak memory 217824 kb
Host smart-2fa0fd70-ea72-4b9d-a1ee-d8ede0c62f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273719475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.273719475
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.441414314
Short name T919
Test name
Test status
Simulation time 1148498585 ps
CPU time 10.08 seconds
Started Feb 07 02:00:14 PM PST 24
Finished Feb 07 02:00:25 PM PST 24
Peak memory 217788 kb
Host smart-a070785c-f47a-46b6-a44c-cb00b0dfa2af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441414314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.441414314
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3023352968
Short name T595
Test name
Test status
Simulation time 181780764 ps
CPU time 8.52 seconds
Started Feb 07 02:00:10 PM PST 24
Finished Feb 07 02:00:20 PM PST 24
Peak memory 217824 kb
Host smart-68f54a78-b4d6-4daf-a3ad-928054adede6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023352968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3023352968
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3619111357
Short name T712
Test name
Test status
Simulation time 1092947305 ps
CPU time 8.03 seconds
Started Feb 07 02:00:07 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 217812 kb
Host smart-b2b1c617-2557-461a-9a00-61a3132c2931
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619111357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3619111357
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1327921109
Short name T63
Test name
Test status
Simulation time 1099360762 ps
CPU time 11.1 seconds
Started Feb 07 02:00:21 PM PST 24
Finished Feb 07 02:00:33 PM PST 24
Peak memory 217700 kb
Host smart-917565ec-1cee-4b6f-b279-9905dab9004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327921109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1327921109
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1140137126
Short name T68
Test name
Test status
Simulation time 39538310 ps
CPU time 2.56 seconds
Started Feb 07 02:00:05 PM PST 24
Finished Feb 07 02:00:10 PM PST 24
Peak memory 214044 kb
Host smart-23e3ac2c-a919-45d5-86fd-f4f040a82aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140137126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1140137126
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.253269831
Short name T527
Test name
Test status
Simulation time 1056364620 ps
CPU time 29.72 seconds
Started Feb 07 01:59:59 PM PST 24
Finished Feb 07 02:00:34 PM PST 24
Peak memory 250728 kb
Host smart-9892799a-927d-4fbe-b211-2f08051fe9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253269831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.253269831
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1389701512
Short name T482
Test name
Test status
Simulation time 64782017 ps
CPU time 7.07 seconds
Started Feb 07 02:00:15 PM PST 24
Finished Feb 07 02:00:22 PM PST 24
Peak memory 250848 kb
Host smart-67c1aee2-8a35-433d-a381-0fa4d77006de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389701512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1389701512
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.225113245
Short name T402
Test name
Test status
Simulation time 4535088180 ps
CPU time 91.04 seconds
Started Feb 07 02:00:14 PM PST 24
Finished Feb 07 02:01:46 PM PST 24
Peak memory 283724 kb
Host smart-fbfd67a4-5a80-4f9d-bc86-5f990c6f0fde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225113245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.225113245
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.379684646
Short name T582
Test name
Test status
Simulation time 22789823 ps
CPU time 0.84 seconds
Started Feb 07 02:00:13 PM PST 24
Finished Feb 07 02:00:15 PM PST 24
Peak memory 207664 kb
Host smart-9e45bbad-f4a7-4d01-98c1-1a572f27631d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379684646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.379684646
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2118130836
Short name T752
Test name
Test status
Simulation time 72140978 ps
CPU time 1.02 seconds
Started Feb 07 01:58:30 PM PST 24
Finished Feb 07 01:58:31 PM PST 24
Peak memory 209428 kb
Host smart-1337ce3b-e4b2-4504-a6e7-f17b33b21615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118130836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2118130836
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.795459652
Short name T563
Test name
Test status
Simulation time 2154742120 ps
CPU time 13.25 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 217872 kb
Host smart-6126cff8-cb04-4bdd-892c-3d23e8934226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795459652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.795459652
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2250630474
Short name T788
Test name
Test status
Simulation time 94107597 ps
CPU time 1.35 seconds
Started Feb 07 01:58:22 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 209372 kb
Host smart-20bc5a16-c54f-4254-a3e2-1b73af680090
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250630474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ac
cess.2250630474
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2540543117
Short name T823
Test name
Test status
Simulation time 4035416700 ps
CPU time 108.04 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 02:00:08 PM PST 24
Peak memory 218264 kb
Host smart-a9d64717-5144-4522-9ff6-df66327abe54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540543117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2540543117
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.533157324
Short name T408
Test name
Test status
Simulation time 3173838503 ps
CPU time 7.8 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:28 PM PST 24
Peak memory 209592 kb
Host smart-c0d84683-7393-417c-bea5-df7b74568e46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533157324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_p
riority.533157324
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1533725106
Short name T572
Test name
Test status
Simulation time 627830266 ps
CPU time 3.64 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:25 PM PST 24
Peak memory 217788 kb
Host smart-8cb7fffe-d85d-46dd-a206-f549da7cec20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533725106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1533725106
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3788391735
Short name T801
Test name
Test status
Simulation time 835609146 ps
CPU time 13.11 seconds
Started Feb 07 01:58:24 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 212780 kb
Host smart-21e00e96-d5d7-447a-9912-3dc55d213164
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788391735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3788391735
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2193554569
Short name T507
Test name
Test status
Simulation time 213534521 ps
CPU time 4.04 seconds
Started Feb 07 01:58:20 PM PST 24
Finished Feb 07 01:58:25 PM PST 24
Peak memory 212680 kb
Host smart-73fc86f1-d63a-4ebe-9edb-5424281fd816
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193554569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2193554569
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1259401216
Short name T359
Test name
Test status
Simulation time 5499545431 ps
CPU time 62.66 seconds
Started Feb 07 01:58:24 PM PST 24
Finished Feb 07 01:59:28 PM PST 24
Peak memory 267240 kb
Host smart-e7c2a0dd-3cb2-4dd8-ba6d-f4a365c43c34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259401216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1259401216
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.740916245
Short name T474
Test name
Test status
Simulation time 1520463093 ps
CPU time 16.02 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 249936 kb
Host smart-8baaeca0-55c6-45c5-97d6-6ef6c853fe29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740916245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.740916245
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3193916670
Short name T983
Test name
Test status
Simulation time 90960152 ps
CPU time 2.76 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:23 PM PST 24
Peak memory 217820 kb
Host smart-916f0645-fc67-4ba9-b0a9-2fa9eb59d9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193916670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3193916670
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.995504673
Short name T500
Test name
Test status
Simulation time 1147623918 ps
CPU time 13.6 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:34 PM PST 24
Peak memory 213188 kb
Host smart-085cf5ce-6585-48da-b488-3bf93d683214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995504673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.995504673
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1738808889
Short name T62
Test name
Test status
Simulation time 119999412 ps
CPU time 26.01 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:46 PM PST 24
Peak memory 281684 kb
Host smart-9759e7e3-69e6-40e5-a500-6be60e00124d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738808889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1738808889
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3891454861
Short name T863
Test name
Test status
Simulation time 860978627 ps
CPU time 13.36 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 218880 kb
Host smart-224d97ea-1506-48de-9953-0b50c6a5b768
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891454861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3891454861
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2640783850
Short name T487
Test name
Test status
Simulation time 206824604 ps
CPU time 9.75 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:32 PM PST 24
Peak memory 217864 kb
Host smart-e2dc85c9-bf09-44fb-a088-a52ea44897c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640783850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2640783850
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.465206934
Short name T987
Test name
Test status
Simulation time 313421336 ps
CPU time 9.96 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:32 PM PST 24
Peak memory 217868 kb
Host smart-8a03e756-1a50-4c30-a41a-f9ee1510fdff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465206934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.465206934
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.608747836
Short name T522
Test name
Test status
Simulation time 499991506 ps
CPU time 8.58 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:29 PM PST 24
Peak memory 217872 kb
Host smart-61de30e6-070a-4570-9b45-730c4f2208d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608747836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.608747836
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.4201851448
Short name T411
Test name
Test status
Simulation time 132547640 ps
CPU time 1.45 seconds
Started Feb 07 01:58:20 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 212696 kb
Host smart-aa505c89-4ecf-44f8-bad2-8d439e31c462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201851448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.4201851448
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.698173561
Short name T347
Test name
Test status
Simulation time 2192007411 ps
CPU time 27.72 seconds
Started Feb 07 01:58:21 PM PST 24
Finished Feb 07 01:58:50 PM PST 24
Peak memory 250864 kb
Host smart-f72b07cb-068d-44ae-b8bb-31a1c97a3495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698173561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.698173561
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1765974019
Short name T633
Test name
Test status
Simulation time 237534175 ps
CPU time 3.61 seconds
Started Feb 07 01:58:19 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 221840 kb
Host smart-97011a27-92a7-416a-a048-d7209387971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765974019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1765974019
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3125229
Short name T708
Test name
Test status
Simulation time 11007986 ps
CPU time 0.88 seconds
Started Feb 07 01:58:18 PM PST 24
Finished Feb 07 01:58:20 PM PST 24
Peak memory 208380 kb
Host smart-1a3055bf-5082-4a4b-a1aa-5aefa9934449
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola
tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
volatile_unlock_smoke.3125229
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2287430951
Short name T719
Test name
Test status
Simulation time 115749820 ps
CPU time 0.92 seconds
Started Feb 07 02:00:15 PM PST 24
Finished Feb 07 02:00:17 PM PST 24
Peak memory 209352 kb
Host smart-7f621055-4263-441b-b4c4-c68d1ba6ee5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287430951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2287430951
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.205374755
Short name T716
Test name
Test status
Simulation time 403715078 ps
CPU time 13.45 seconds
Started Feb 07 02:00:10 PM PST 24
Finished Feb 07 02:00:25 PM PST 24
Peak memory 217820 kb
Host smart-ed65ee53-d401-4d16-98a5-866a1f193d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205374755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.205374755
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2789758230
Short name T9
Test name
Test status
Simulation time 313434930 ps
CPU time 4.4 seconds
Started Feb 07 02:00:12 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 209444 kb
Host smart-9f0b37b4-6af9-43f0-af56-c4e54934221b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789758230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.2789758230
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2230942123
Short name T465
Test name
Test status
Simulation time 45719524 ps
CPU time 2.35 seconds
Started Feb 07 02:00:10 PM PST 24
Finished Feb 07 02:00:14 PM PST 24
Peak memory 217876 kb
Host smart-f3e14af7-083c-4fdc-9f35-4795115a8955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230942123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2230942123
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2768364388
Short name T50
Test name
Test status
Simulation time 842987000 ps
CPU time 9.19 seconds
Started Feb 07 02:00:10 PM PST 24
Finished Feb 07 02:00:21 PM PST 24
Peak memory 218784 kb
Host smart-29aad273-df87-4cbc-ad65-3896d6510060
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768364388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2768364388
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1365080522
Short name T881
Test name
Test status
Simulation time 307676599 ps
CPU time 12.49 seconds
Started Feb 07 02:00:08 PM PST 24
Finished Feb 07 02:00:23 PM PST 24
Peak memory 217812 kb
Host smart-3b2eccce-ae40-4958-bd62-1194705dc397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365080522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1365080522
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.501431760
Short name T504
Test name
Test status
Simulation time 2007091812 ps
CPU time 9.54 seconds
Started Feb 07 02:00:08 PM PST 24
Finished Feb 07 02:00:20 PM PST 24
Peak memory 217784 kb
Host smart-2028028a-f95f-452c-8c07-607d8964f9b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501431760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.501431760
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1630615590
Short name T764
Test name
Test status
Simulation time 1031218666 ps
CPU time 7.16 seconds
Started Feb 07 02:00:08 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 217984 kb
Host smart-c322fcd0-99fa-45a0-9476-58154fe197ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630615590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1630615590
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.170004786
Short name T431
Test name
Test status
Simulation time 121219496 ps
CPU time 2.54 seconds
Started Feb 07 02:00:09 PM PST 24
Finished Feb 07 02:00:14 PM PST 24
Peak memory 213780 kb
Host smart-4cee378a-3262-42af-80c1-001b7cc1b7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170004786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.170004786
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1764930696
Short name T574
Test name
Test status
Simulation time 711159162 ps
CPU time 24.56 seconds
Started Feb 07 02:00:10 PM PST 24
Finished Feb 07 02:00:36 PM PST 24
Peak memory 243840 kb
Host smart-8f0d2994-5321-44b2-b7ff-0a891e55cbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764930696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1764930696
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2458087960
Short name T334
Test name
Test status
Simulation time 54887561 ps
CPU time 6.6 seconds
Started Feb 07 02:00:10 PM PST 24
Finished Feb 07 02:00:18 PM PST 24
Peak memory 250512 kb
Host smart-1d2290b8-4292-486f-9cb6-4126a302c484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458087960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2458087960
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1771282857
Short name T858
Test name
Test status
Simulation time 31220675769 ps
CPU time 135.43 seconds
Started Feb 07 02:00:13 PM PST 24
Finished Feb 07 02:02:29 PM PST 24
Peak memory 282444 kb
Host smart-37d6bbeb-27dc-4d6d-bad7-0840bf58212a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771282857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1771282857
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2358579846
Short name T959
Test name
Test status
Simulation time 330547383484 ps
CPU time 863.74 seconds
Started Feb 07 02:00:20 PM PST 24
Finished Feb 07 02:14:45 PM PST 24
Peak memory 562360 kb
Host smart-f2b2fc65-0189-4cac-bb47-135f88a569d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2358579846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.2358579846
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3983347188
Short name T390
Test name
Test status
Simulation time 24866160 ps
CPU time 0.96 seconds
Started Feb 07 02:00:06 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 207944 kb
Host smart-64122d6f-47c7-4c6f-b668-f55d0d7e498c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983347188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3983347188
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1357437602
Short name T790
Test name
Test status
Simulation time 101342449 ps
CPU time 0.88 seconds
Started Feb 07 02:00:17 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 209388 kb
Host smart-a393dfc8-52b6-43bb-b93f-0e6c7f633238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357437602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1357437602
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.801246925
Short name T729
Test name
Test status
Simulation time 1099081923 ps
CPU time 12.7 seconds
Started Feb 07 02:00:17 PM PST 24
Finished Feb 07 02:00:32 PM PST 24
Peak memory 217816 kb
Host smart-3fffd8f5-301b-4fac-9aa1-388d61b29ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801246925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.801246925
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3496677259
Short name T986
Test name
Test status
Simulation time 321431653 ps
CPU time 8.3 seconds
Started Feb 07 02:00:15 PM PST 24
Finished Feb 07 02:00:24 PM PST 24
Peak memory 209388 kb
Host smart-52c6fb49-e1c7-4b1d-b159-3b1117021c5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496677259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.3496677259
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1330031015
Short name T407
Test name
Test status
Simulation time 90640371 ps
CPU time 4.13 seconds
Started Feb 07 02:00:14 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 217888 kb
Host smart-6a72460a-d445-49cd-a449-29d0eec4a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330031015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1330031015
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3590378129
Short name T446
Test name
Test status
Simulation time 264462985 ps
CPU time 13.94 seconds
Started Feb 07 02:00:19 PM PST 24
Finished Feb 07 02:00:34 PM PST 24
Peak memory 217880 kb
Host smart-a5387879-d551-4856-89df-8160cd46433b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590378129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3590378129
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1631685365
Short name T970
Test name
Test status
Simulation time 935034543 ps
CPU time 10.19 seconds
Started Feb 07 02:00:17 PM PST 24
Finished Feb 07 02:00:28 PM PST 24
Peak memory 217820 kb
Host smart-c99afe11-5c8f-4945-b31c-c91feb6526b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631685365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1631685365
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2011197042
Short name T951
Test name
Test status
Simulation time 933249202 ps
CPU time 10.22 seconds
Started Feb 07 02:00:09 PM PST 24
Finished Feb 07 02:00:21 PM PST 24
Peak memory 217800 kb
Host smart-95651d56-5c61-4079-b554-85de21b596a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011197042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2011197042
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2763411977
Short name T806
Test name
Test status
Simulation time 431228907 ps
CPU time 14.34 seconds
Started Feb 07 02:00:12 PM PST 24
Finished Feb 07 02:00:28 PM PST 24
Peak memory 217848 kb
Host smart-bbf0cb47-4f0e-44fe-ac03-76b87df613f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763411977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2763411977
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3947772633
Short name T434
Test name
Test status
Simulation time 39159474 ps
CPU time 2.05 seconds
Started Feb 07 02:00:13 PM PST 24
Finished Feb 07 02:00:16 PM PST 24
Peak memory 213720 kb
Host smart-10591c23-4995-4ba1-ad92-a83d00b0a1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947772633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3947772633
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1497904721
Short name T802
Test name
Test status
Simulation time 1283111741 ps
CPU time 37.69 seconds
Started Feb 07 02:00:12 PM PST 24
Finished Feb 07 02:00:50 PM PST 24
Peak memory 250804 kb
Host smart-790b3eee-75af-4c52-8d0b-d1417878b6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497904721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1497904721
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.457170355
Short name T654
Test name
Test status
Simulation time 48481431 ps
CPU time 6.99 seconds
Started Feb 07 02:00:10 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 250864 kb
Host smart-153b6c45-dd4e-42c8-a545-2934cd01a8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457170355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.457170355
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3740406743
Short name T345
Test name
Test status
Simulation time 6509190945 ps
CPU time 99.83 seconds
Started Feb 07 02:00:07 PM PST 24
Finished Feb 07 02:01:50 PM PST 24
Peak memory 250928 kb
Host smart-0be1a633-4e61-4374-bfcb-072cf7ae3749
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740406743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3740406743
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.103255662
Short name T963
Test name
Test status
Simulation time 24289168 ps
CPU time 0.85 seconds
Started Feb 07 02:00:10 PM PST 24
Finished Feb 07 02:00:13 PM PST 24
Peak memory 208140 kb
Host smart-b21b5a0c-7701-4388-8a0b-82a0ddb36a2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103255662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.103255662
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3458865919
Short name T353
Test name
Test status
Simulation time 40606991 ps
CPU time 0.82 seconds
Started Feb 07 02:00:17 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 209220 kb
Host smart-32f5968f-177f-488a-879d-736aa888d31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458865919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3458865919
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2042082314
Short name T573
Test name
Test status
Simulation time 519586799 ps
CPU time 9.16 seconds
Started Feb 07 02:00:24 PM PST 24
Finished Feb 07 02:00:34 PM PST 24
Peak memory 217780 kb
Host smart-a47ad7cc-8a0f-4b85-867c-273700c3eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042082314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2042082314
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1558958821
Short name T11
Test name
Test status
Simulation time 1828348087 ps
CPU time 10.55 seconds
Started Feb 07 02:00:21 PM PST 24
Finished Feb 07 02:00:33 PM PST 24
Peak memory 209468 kb
Host smart-9d84f83b-1b34-440c-aa6f-2fde1f5b2bd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558958821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.1558958821
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.156635328
Short name T322
Test name
Test status
Simulation time 84468257 ps
CPU time 2.07 seconds
Started Feb 07 02:00:21 PM PST 24
Finished Feb 07 02:00:24 PM PST 24
Peak memory 217824 kb
Host smart-8c1e86b4-3203-4dd4-81a5-472dd7120293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156635328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.156635328
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3247801375
Short name T357
Test name
Test status
Simulation time 656328756 ps
CPU time 13.02 seconds
Started Feb 07 02:00:12 PM PST 24
Finished Feb 07 02:00:26 PM PST 24
Peak memory 218892 kb
Host smart-0b7e4242-fdcc-47be-92eb-970eadf8504f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247801375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3247801375
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1464735097
Short name T319
Test name
Test status
Simulation time 14885384437 ps
CPU time 22.96 seconds
Started Feb 07 02:00:15 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 217976 kb
Host smart-39ae838c-ad1f-4032-ae4c-cfc4a55e8669
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464735097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1464735097
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.953410396
Short name T533
Test name
Test status
Simulation time 774963920 ps
CPU time 10.01 seconds
Started Feb 07 02:00:19 PM PST 24
Finished Feb 07 02:00:30 PM PST 24
Peak memory 217852 kb
Host smart-e412802a-7b96-47f3-a676-ce6146f2f43b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953410396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.953410396
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3164578732
Short name T596
Test name
Test status
Simulation time 929147565 ps
CPU time 8.89 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:33 PM PST 24
Peak memory 217764 kb
Host smart-f4a0e0d1-b5b8-432e-88e9-a60843319684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164578732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3164578732
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.628432934
Short name T818
Test name
Test status
Simulation time 64372110 ps
CPU time 2.4 seconds
Started Feb 07 02:00:18 PM PST 24
Finished Feb 07 02:00:22 PM PST 24
Peak memory 213664 kb
Host smart-cfb10d1a-df8f-4d6a-8363-c23baa5fa7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628432934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.628432934
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3712539521
Short name T743
Test name
Test status
Simulation time 1347935591 ps
CPU time 28.89 seconds
Started Feb 07 02:00:21 PM PST 24
Finished Feb 07 02:00:51 PM PST 24
Peak memory 246476 kb
Host smart-821b1c7a-4086-4640-a443-a719a8ac9501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712539521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3712539521
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.4276763099
Short name T441
Test name
Test status
Simulation time 209889811 ps
CPU time 8.05 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:31 PM PST 24
Peak memory 250864 kb
Host smart-88201656-4e33-47bb-b3a4-a6b9fc29ecfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276763099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.4276763099
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3666409120
Short name T521
Test name
Test status
Simulation time 1869944702 ps
CPU time 68.76 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:01:33 PM PST 24
Peak memory 249496 kb
Host smart-95ec09c9-86a4-4a5e-ab18-8791cbea7251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666409120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3666409120
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3465829032
Short name T471
Test name
Test status
Simulation time 180367779 ps
CPU time 1.15 seconds
Started Feb 07 02:00:26 PM PST 24
Finished Feb 07 02:00:29 PM PST 24
Peak memory 209272 kb
Host smart-f9f24eb7-4df6-4bab-a01b-271bb6c7130a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465829032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3465829032
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.121354607
Short name T468
Test name
Test status
Simulation time 1901259591 ps
CPU time 18.11 seconds
Started Feb 07 02:00:16 PM PST 24
Finished Feb 07 02:00:35 PM PST 24
Peak memory 217812 kb
Host smart-750ba11c-b592-43d2-9df5-68f24099fdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121354607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.121354607
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2521623147
Short name T27
Test name
Test status
Simulation time 2135280527 ps
CPU time 9.68 seconds
Started Feb 07 02:00:17 PM PST 24
Finished Feb 07 02:00:27 PM PST 24
Peak memory 209416 kb
Host smart-7f41c02c-4165-4513-9e91-f7622154541d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521623147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.2521623147
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.791855588
Short name T829
Test name
Test status
Simulation time 211118109 ps
CPU time 3.26 seconds
Started Feb 07 02:00:24 PM PST 24
Finished Feb 07 02:00:28 PM PST 24
Peak memory 217820 kb
Host smart-5c14fcb4-aa49-4c3d-adb5-e500eb58ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791855588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.791855588
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1748209843
Short name T598
Test name
Test status
Simulation time 950287269 ps
CPU time 13.74 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:38 PM PST 24
Peak memory 217736 kb
Host smart-bffa9641-6992-40c0-aa3e-1e984d7d80f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748209843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1748209843
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2757457853
Short name T436
Test name
Test status
Simulation time 324602942 ps
CPU time 13.03 seconds
Started Feb 07 02:00:18 PM PST 24
Finished Feb 07 02:00:33 PM PST 24
Peak memory 217920 kb
Host smart-aa2df438-0d21-42b5-86b3-e6cf4198f67e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757457853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2757457853
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3336334157
Short name T396
Test name
Test status
Simulation time 1132917100 ps
CPU time 11.92 seconds
Started Feb 07 02:00:16 PM PST 24
Finished Feb 07 02:00:28 PM PST 24
Peak memory 217868 kb
Host smart-592ac420-4929-4089-9d4a-c9f12fc54336
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336334157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3336334157
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2516128637
Short name T792
Test name
Test status
Simulation time 286720332 ps
CPU time 2.97 seconds
Started Feb 07 02:00:16 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 213892 kb
Host smart-b8351a22-b109-4378-8dbf-9b6930a8c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516128637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2516128637
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1143456388
Short name T529
Test name
Test status
Simulation time 162577885 ps
CPU time 22.43 seconds
Started Feb 07 02:00:18 PM PST 24
Finished Feb 07 02:00:42 PM PST 24
Peak memory 250980 kb
Host smart-f6498e4b-09ea-43e9-b8df-63e5c26cc11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143456388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1143456388
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.703079522
Short name T581
Test name
Test status
Simulation time 59943025 ps
CPU time 7.01 seconds
Started Feb 07 02:00:16 PM PST 24
Finished Feb 07 02:00:24 PM PST 24
Peak memory 250648 kb
Host smart-b49e546a-cff7-406d-8f60-246c5057cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703079522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.703079522
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2199790624
Short name T74
Test name
Test status
Simulation time 6501629643 ps
CPU time 43.77 seconds
Started Feb 07 02:00:17 PM PST 24
Finished Feb 07 02:01:02 PM PST 24
Peak memory 250928 kb
Host smart-d895ceed-01a7-4b98-9943-a1b182945126
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199790624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2199790624
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2850176365
Short name T967
Test name
Test status
Simulation time 52060460406 ps
CPU time 204.27 seconds
Started Feb 07 02:00:26 PM PST 24
Finished Feb 07 02:03:52 PM PST 24
Peak memory 332888 kb
Host smart-26cd91b6-e4b7-4364-93fe-4afd844c906a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2850176365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2850176365
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.879502854
Short name T828
Test name
Test status
Simulation time 111815967 ps
CPU time 0.92 seconds
Started Feb 07 02:00:13 PM PST 24
Finished Feb 07 02:00:15 PM PST 24
Peak memory 211244 kb
Host smart-2efbdcd1-9758-46b7-8b5e-0b786ea28475
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879502854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.879502854
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4239022223
Short name T649
Test name
Test status
Simulation time 19226922 ps
CPU time 0.9 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:24 PM PST 24
Peak memory 208012 kb
Host smart-46031153-1dcc-4855-86c3-5cbfb77ea86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239022223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4239022223
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2379560950
Short name T688
Test name
Test status
Simulation time 282092810 ps
CPU time 14.52 seconds
Started Feb 07 02:00:17 PM PST 24
Finished Feb 07 02:00:33 PM PST 24
Peak memory 217812 kb
Host smart-18d138b0-482d-48c0-84ee-287919344214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379560950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2379560950
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1505944009
Short name T525
Test name
Test status
Simulation time 66540754 ps
CPU time 1.47 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:24 PM PST 24
Peak memory 209360 kb
Host smart-144d6b23-1533-4edd-b8e8-246676e8581f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505944009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.1505944009
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1579881246
Short name T671
Test name
Test status
Simulation time 216872848 ps
CPU time 3.23 seconds
Started Feb 07 02:00:18 PM PST 24
Finished Feb 07 02:00:23 PM PST 24
Peak memory 217876 kb
Host smart-7975fd55-6d9c-4bc0-9662-0145672fc895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579881246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1579881246
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3867676777
Short name T795
Test name
Test status
Simulation time 4054755933 ps
CPU time 15.1 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 218888 kb
Host smart-fb813c95-3a4e-48e0-b243-3ee205db5469
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867676777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3867676777
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1592764114
Short name T973
Test name
Test status
Simulation time 356264321 ps
CPU time 11.66 seconds
Started Feb 07 02:00:18 PM PST 24
Finished Feb 07 02:00:31 PM PST 24
Peak memory 217752 kb
Host smart-da0d8894-8d56-4a5a-a295-c33e6e9f3c84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592764114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1592764114
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2018268530
Short name T510
Test name
Test status
Simulation time 503244289 ps
CPU time 6.8 seconds
Started Feb 07 02:00:24 PM PST 24
Finished Feb 07 02:00:32 PM PST 24
Peak memory 217792 kb
Host smart-a8a2a21c-12ce-42ac-a993-4f77a30a8a95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018268530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2018268530
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1228321341
Short name T542
Test name
Test status
Simulation time 491177312 ps
CPU time 11.88 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:35 PM PST 24
Peak memory 217740 kb
Host smart-ecacff68-31f3-4957-bb36-e4321c60c3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228321341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1228321341
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1967161121
Short name T843
Test name
Test status
Simulation time 55004780 ps
CPU time 2.79 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:27 PM PST 24
Peak memory 213680 kb
Host smart-9b53c8d8-8d29-4795-ab62-b0e430856f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967161121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1967161121
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3211885675
Short name T819
Test name
Test status
Simulation time 217662035 ps
CPU time 21.57 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:46 PM PST 24
Peak memory 250660 kb
Host smart-0be91ade-dd58-4b15-b38e-7cfdeb150164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211885675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3211885675
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3677213387
Short name T469
Test name
Test status
Simulation time 76727869 ps
CPU time 3.21 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:28 PM PST 24
Peak memory 222040 kb
Host smart-06ac4606-60dd-43ee-b558-b92c6e99629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677213387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3677213387
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.453977298
Short name T192
Test name
Test status
Simulation time 6110815924 ps
CPU time 129.96 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:02:34 PM PST 24
Peak memory 283620 kb
Host smart-b0e5d060-c0a9-45f5-92ba-f016c1d677cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453977298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.453977298
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.606888949
Short name T365
Test name
Test status
Simulation time 32765348 ps
CPU time 0.73 seconds
Started Feb 07 02:00:21 PM PST 24
Finished Feb 07 02:00:23 PM PST 24
Peak memory 207600 kb
Host smart-ad5a820b-e9ad-424e-bd28-be2124a35584
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606888949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.606888949
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4193478619
Short name T791
Test name
Test status
Simulation time 28751036 ps
CPU time 1.06 seconds
Started Feb 07 02:00:34 PM PST 24
Finished Feb 07 02:00:36 PM PST 24
Peak memory 209368 kb
Host smart-7aadd444-bedb-45dd-b0e0-354fafb9e9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193478619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4193478619
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1707451679
Short name T488
Test name
Test status
Simulation time 455993442 ps
CPU time 12.09 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:36 PM PST 24
Peak memory 217848 kb
Host smart-7926a94e-364b-49c6-a8ea-d4cf3c415ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707451679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1707451679
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3288428989
Short name T29
Test name
Test status
Simulation time 2424811588 ps
CPU time 5.98 seconds
Started Feb 07 02:00:29 PM PST 24
Finished Feb 07 02:00:36 PM PST 24
Peak memory 209484 kb
Host smart-30d16436-8150-4cfd-960a-80098b9aa04b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288428989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.3288428989
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.870304344
Short name T65
Test name
Test status
Simulation time 114141145 ps
CPU time 2.57 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:26 PM PST 24
Peak memory 217848 kb
Host smart-3d931871-6bd4-4831-828d-e16ad60a5664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870304344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.870304344
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1063711256
Short name T648
Test name
Test status
Simulation time 1678891856 ps
CPU time 10.9 seconds
Started Feb 07 02:00:21 PM PST 24
Finished Feb 07 02:00:33 PM PST 24
Peak memory 217824 kb
Host smart-32cbd4de-0214-4819-b52b-d136308fd23c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063711256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1063711256
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1746564408
Short name T531
Test name
Test status
Simulation time 814048628 ps
CPU time 14.83 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 217812 kb
Host smart-9c6a5736-4443-4303-8fc0-fa4d8af98ae2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746564408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1746564408
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3028563785
Short name T864
Test name
Test status
Simulation time 374217476 ps
CPU time 13.3 seconds
Started Feb 07 02:00:37 PM PST 24
Finished Feb 07 02:00:51 PM PST 24
Peak memory 217764 kb
Host smart-030055ca-8f4d-471c-b4e2-f240546eaace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028563785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3028563785
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1900461495
Short name T70
Test name
Test status
Simulation time 39532850 ps
CPU time 1.47 seconds
Started Feb 07 02:00:17 PM PST 24
Finished Feb 07 02:00:20 PM PST 24
Peak memory 212956 kb
Host smart-80cac3ed-ef85-44a8-972d-1f0352ccd66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900461495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1900461495
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2734125925
Short name T556
Test name
Test status
Simulation time 418239699 ps
CPU time 17.76 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:41 PM PST 24
Peak memory 250768 kb
Host smart-4cf516ba-570f-418c-86f7-06eeaf69a376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734125925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2734125925
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2070355855
Short name T366
Test name
Test status
Simulation time 121416630 ps
CPU time 6.82 seconds
Started Feb 07 02:00:26 PM PST 24
Finished Feb 07 02:00:35 PM PST 24
Peak memory 250312 kb
Host smart-2c5a209e-9a9d-42ae-898b-2a892cb53300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070355855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2070355855
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2013781577
Short name T977
Test name
Test status
Simulation time 25742825243 ps
CPU time 228.92 seconds
Started Feb 07 02:00:29 PM PST 24
Finished Feb 07 02:04:19 PM PST 24
Peak memory 280176 kb
Host smart-53bd077a-640c-4acc-8c5e-d3c476313867
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013781577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2013781577
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1865763346
Short name T625
Test name
Test status
Simulation time 14954751 ps
CPU time 0.96 seconds
Started Feb 07 02:00:33 PM PST 24
Finished Feb 07 02:00:35 PM PST 24
Peak memory 211200 kb
Host smart-ce98aee1-4c08-4394-a91a-bc6ed1d0fb65
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865763346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1865763346
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3082479989
Short name T784
Test name
Test status
Simulation time 24904788 ps
CPU time 0.83 seconds
Started Feb 07 02:00:33 PM PST 24
Finished Feb 07 02:00:35 PM PST 24
Peak memory 209184 kb
Host smart-30531b31-e956-4c13-b6c7-2910816331b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082479989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3082479989
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3534186780
Short name T976
Test name
Test status
Simulation time 189638318 ps
CPU time 10.16 seconds
Started Feb 07 02:00:28 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 217820 kb
Host smart-c5738b8d-da4e-4d4f-8a74-3eb3e271fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534186780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3534186780
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1840299294
Short name T30
Test name
Test status
Simulation time 1185866217 ps
CPU time 3.59 seconds
Started Feb 07 02:00:57 PM PST 24
Finished Feb 07 02:01:02 PM PST 24
Peak memory 209412 kb
Host smart-ccad8b49-9eb5-42e0-93ed-44e09eee184d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840299294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_a
ccess.1840299294
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4053212395
Short name T464
Test name
Test status
Simulation time 286401320 ps
CPU time 2.81 seconds
Started Feb 07 02:00:26 PM PST 24
Finished Feb 07 02:00:31 PM PST 24
Peak memory 217856 kb
Host smart-f8e5f598-846c-42d2-ad85-d5d0ee2482de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053212395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4053212395
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1334500977
Short name T989
Test name
Test status
Simulation time 251750669 ps
CPU time 9.49 seconds
Started Feb 07 02:00:35 PM PST 24
Finished Feb 07 02:00:45 PM PST 24
Peak memory 217808 kb
Host smart-acba5fb4-023c-4457-a757-4e689e804bc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334500977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1334500977
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3094960394
Short name T548
Test name
Test status
Simulation time 349371533 ps
CPU time 14.82 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:38 PM PST 24
Peak memory 217820 kb
Host smart-d7568b6e-5e08-4923-9336-0cbfd91c8ea9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094960394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3094960394
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4015533731
Short name T922
Test name
Test status
Simulation time 1431092732 ps
CPU time 9.21 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:32 PM PST 24
Peak memory 217816 kb
Host smart-30a089bd-c1ba-4372-aea5-978dd1f944ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015533731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4015533731
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3711701785
Short name T706
Test name
Test status
Simulation time 322744752 ps
CPU time 10.49 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:34 PM PST 24
Peak memory 217792 kb
Host smart-24872ea7-e3f0-4656-98dd-bd8cc540559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711701785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3711701785
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1368922604
Short name T403
Test name
Test status
Simulation time 111026857 ps
CPU time 2.94 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:28 PM PST 24
Peak memory 213988 kb
Host smart-c57fa95b-bf2c-4d68-8576-a9338b5d85df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368922604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1368922604
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1092975447
Short name T364
Test name
Test status
Simulation time 1525262893 ps
CPU time 32.99 seconds
Started Feb 07 02:00:24 PM PST 24
Finished Feb 07 02:00:58 PM PST 24
Peak memory 250836 kb
Host smart-234656c9-e2b7-46ff-8dfd-30a8230900f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092975447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1092975447
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3087537650
Short name T911
Test name
Test status
Simulation time 67286521 ps
CPU time 6.61 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:31 PM PST 24
Peak memory 250664 kb
Host smart-2500a8b6-2f28-432a-9cd7-19ae17c6226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087537650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3087537650
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2759233098
Short name T81
Test name
Test status
Simulation time 64627503633 ps
CPU time 86.03 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:01:49 PM PST 24
Peak memory 267344 kb
Host smart-6cdb29e2-688d-40d5-9104-c421ca916c59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759233098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2759233098
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1985956285
Short name T832
Test name
Test status
Simulation time 20772995 ps
CPU time 0.84 seconds
Started Feb 07 02:00:20 PM PST 24
Finished Feb 07 02:00:22 PM PST 24
Peak memory 208120 kb
Host smart-ecdee423-0c1d-4de5-b7df-b7f0e3b4056b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985956285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1985956285
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1761067899
Short name T855
Test name
Test status
Simulation time 275064180 ps
CPU time 1.03 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:26 PM PST 24
Peak memory 209452 kb
Host smart-095f8c85-656f-4b58-ba89-a585f3f1a81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761067899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1761067899
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3134795976
Short name T459
Test name
Test status
Simulation time 4266583349 ps
CPU time 9 seconds
Started Feb 07 02:00:25 PM PST 24
Finished Feb 07 02:00:36 PM PST 24
Peak memory 217856 kb
Host smart-8f46ac35-6d8c-463b-9161-8094fbf75ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134795976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3134795976
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3891461109
Short name T698
Test name
Test status
Simulation time 2345981829 ps
CPU time 4.47 seconds
Started Feb 07 02:00:29 PM PST 24
Finished Feb 07 02:00:35 PM PST 24
Peak memory 209476 kb
Host smart-03ea7f34-677d-4629-a522-00111086a62f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891461109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_a
ccess.3891461109
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.28929052
Short name T800
Test name
Test status
Simulation time 126856646 ps
CPU time 3.67 seconds
Started Feb 07 02:00:36 PM PST 24
Finished Feb 07 02:00:40 PM PST 24
Peak memory 217772 kb
Host smart-8aabe7ff-3070-468a-b9a9-07ea698e3bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28929052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.28929052
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3076995246
Short name T512
Test name
Test status
Simulation time 3008160677 ps
CPU time 12.42 seconds
Started Feb 07 02:00:50 PM PST 24
Finished Feb 07 02:01:05 PM PST 24
Peak memory 218968 kb
Host smart-31cf7343-6557-4d75-9b35-8d825e02a86a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076995246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3076995246
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.584134952
Short name T551
Test name
Test status
Simulation time 528996091 ps
CPU time 18.17 seconds
Started Feb 07 02:00:26 PM PST 24
Finished Feb 07 02:00:47 PM PST 24
Peak memory 217764 kb
Host smart-cef6601d-c78b-453d-856f-2c0898644a4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584134952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.584134952
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3063625477
Short name T757
Test name
Test status
Simulation time 618186777 ps
CPU time 10.36 seconds
Started Feb 07 02:00:36 PM PST 24
Finished Feb 07 02:00:47 PM PST 24
Peak memory 217756 kb
Host smart-6483f64d-1a2e-48d2-b927-091899f4e5b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063625477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3063625477
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3718345908
Short name T554
Test name
Test status
Simulation time 322633210 ps
CPU time 7.92 seconds
Started Feb 07 02:00:23 PM PST 24
Finished Feb 07 02:00:32 PM PST 24
Peak memory 217848 kb
Host smart-e5d19d6b-fbee-4eb7-a969-9b27221d62cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718345908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3718345908
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3041438661
Short name T978
Test name
Test status
Simulation time 17010387 ps
CPU time 1.04 seconds
Started Feb 07 02:00:28 PM PST 24
Finished Feb 07 02:00:30 PM PST 24
Peak memory 211472 kb
Host smart-772a0cb7-af7b-4f96-8784-899316e0c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041438661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3041438661
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.987116756
Short name T352
Test name
Test status
Simulation time 702396570 ps
CPU time 30.5 seconds
Started Feb 07 02:00:21 PM PST 24
Finished Feb 07 02:00:52 PM PST 24
Peak memory 250840 kb
Host smart-10f38b54-3d52-44d4-b587-46d79c1f9c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987116756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.987116756
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2492142175
Short name T601
Test name
Test status
Simulation time 92691135 ps
CPU time 3.97 seconds
Started Feb 07 02:00:24 PM PST 24
Finished Feb 07 02:00:29 PM PST 24
Peak memory 221916 kb
Host smart-91bac9d2-4fc9-4002-90b5-85c903d47c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492142175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2492142175
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3712904666
Short name T503
Test name
Test status
Simulation time 28550390692 ps
CPU time 459.86 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:08:20 PM PST 24
Peak memory 226032 kb
Host smart-2f96daf3-646f-4880-af82-c6663daf23c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712904666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3712904666
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1758789278
Short name T834
Test name
Test status
Simulation time 64744372670 ps
CPU time 1154.14 seconds
Started Feb 07 02:00:35 PM PST 24
Finished Feb 07 02:19:50 PM PST 24
Peak memory 283656 kb
Host smart-ed6a9705-dbce-46e4-a26a-a6a19ff42e77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1758789278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1758789278
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2550943769
Short name T702
Test name
Test status
Simulation time 14624506 ps
CPU time 0.97 seconds
Started Feb 07 02:00:26 PM PST 24
Finished Feb 07 02:00:29 PM PST 24
Peak memory 207880 kb
Host smart-adff8fdf-78ec-43e5-a942-80469f267a71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550943769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2550943769
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3253056571
Short name T498
Test name
Test status
Simulation time 30392561 ps
CPU time 0.94 seconds
Started Feb 07 02:00:38 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 209376 kb
Host smart-34a351dc-782f-475a-9a8c-47a47f3a1540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253056571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3253056571
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2192113542
Short name T358
Test name
Test status
Simulation time 579218627 ps
CPU time 17.06 seconds
Started Feb 07 02:00:35 PM PST 24
Finished Feb 07 02:00:53 PM PST 24
Peak memory 217824 kb
Host smart-320849d7-6f30-4cac-9d04-d8e2d8ef5900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192113542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2192113542
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3682242842
Short name T950
Test name
Test status
Simulation time 177460074 ps
CPU time 2.84 seconds
Started Feb 07 02:00:35 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 209396 kb
Host smart-9ab84882-4fb2-40e7-a724-6979078b3465
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682242842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.3682242842
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.4208922321
Short name T606
Test name
Test status
Simulation time 158718498 ps
CPU time 2.71 seconds
Started Feb 07 02:00:35 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 217832 kb
Host smart-47a9941e-2476-45a6-ae48-4a9e03aec58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208922321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.4208922321
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2325808293
Short name T799
Test name
Test status
Simulation time 363712778 ps
CPU time 11.06 seconds
Started Feb 07 02:00:32 PM PST 24
Finished Feb 07 02:00:45 PM PST 24
Peak memory 218824 kb
Host smart-ad2073cb-9b36-439e-bfff-e4b33ce3149c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325808293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2325808293
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2806510340
Short name T745
Test name
Test status
Simulation time 221552336 ps
CPU time 7.97 seconds
Started Feb 07 02:00:32 PM PST 24
Finished Feb 07 02:00:41 PM PST 24
Peak memory 217808 kb
Host smart-a130dd85-6134-455a-a91a-3a3a66171412
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806510340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2806510340
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3092000578
Short name T380
Test name
Test status
Simulation time 610918932 ps
CPU time 8.28 seconds
Started Feb 07 02:00:36 PM PST 24
Finished Feb 07 02:00:45 PM PST 24
Peak memory 217764 kb
Host smart-0e03b679-8ac5-4b11-b363-4a44210a6cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092000578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3092000578
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3195180995
Short name T78
Test name
Test status
Simulation time 123744678 ps
CPU time 4.14 seconds
Started Feb 07 02:00:24 PM PST 24
Finished Feb 07 02:00:29 PM PST 24
Peak memory 217700 kb
Host smart-f4cba634-9ceb-4d32-93fb-c82b5d2b4205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195180995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3195180995
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1668272411
Short name T753
Test name
Test status
Simulation time 985231028 ps
CPU time 27.73 seconds
Started Feb 07 02:00:22 PM PST 24
Finished Feb 07 02:00:51 PM PST 24
Peak memory 250800 kb
Host smart-9c691720-c894-49ce-b5a4-ba76a6f3a032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668272411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1668272411
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3508421023
Short name T931
Test name
Test status
Simulation time 109423609 ps
CPU time 7.1 seconds
Started Feb 07 02:00:50 PM PST 24
Finished Feb 07 02:01:00 PM PST 24
Peak memory 246452 kb
Host smart-ccc024e2-f8c3-4cb3-a959-d2f84cc870e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508421023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3508421023
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1332955252
Short name T703
Test name
Test status
Simulation time 13714454515 ps
CPU time 397.4 seconds
Started Feb 07 02:00:31 PM PST 24
Finished Feb 07 02:07:09 PM PST 24
Peak memory 273112 kb
Host smart-8cb765ca-01c4-40c3-82b7-5d62d5f1c703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332955252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1332955252
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3231321286
Short name T645
Test name
Test status
Simulation time 11077758 ps
CPU time 0.79 seconds
Started Feb 07 02:00:36 PM PST 24
Finished Feb 07 02:00:37 PM PST 24
Peak memory 207776 kb
Host smart-3ffd8894-4eb5-4e6c-9a64-893f51740380
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231321286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3231321286
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4220924760
Short name T804
Test name
Test status
Simulation time 15529092 ps
CPU time 1.06 seconds
Started Feb 07 02:00:34 PM PST 24
Finished Feb 07 02:00:36 PM PST 24
Peak memory 209388 kb
Host smart-1fe5353c-9bd9-411b-b189-37cab8c5f552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220924760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4220924760
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.957684267
Short name T385
Test name
Test status
Simulation time 330222279 ps
CPU time 13.98 seconds
Started Feb 07 02:00:30 PM PST 24
Finished Feb 07 02:00:45 PM PST 24
Peak memory 217780 kb
Host smart-fc6a135e-58a7-446d-94ba-c3698b9d3481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957684267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.957684267
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.469401312
Short name T755
Test name
Test status
Simulation time 201015484 ps
CPU time 1.54 seconds
Started Feb 07 02:00:31 PM PST 24
Finished Feb 07 02:00:34 PM PST 24
Peak memory 209408 kb
Host smart-29ab4879-e13f-4cea-bd3f-a2517dae2120
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469401312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_ac
cess.469401312
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3706312066
Short name T511
Test name
Test status
Simulation time 75853642 ps
CPU time 3.2 seconds
Started Feb 07 02:00:33 PM PST 24
Finished Feb 07 02:00:37 PM PST 24
Peak memory 217876 kb
Host smart-32d61258-b433-4cb3-957f-88a3d71dbfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706312066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3706312066
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1286358323
Short name T530
Test name
Test status
Simulation time 885907459 ps
CPU time 18.1 seconds
Started Feb 07 02:00:31 PM PST 24
Finished Feb 07 02:00:50 PM PST 24
Peak memory 218884 kb
Host smart-a1d6d4ad-f5f0-4f6e-849b-8bc777c2b07f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286358323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1286358323
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2992390244
Short name T543
Test name
Test status
Simulation time 238015249 ps
CPU time 9.29 seconds
Started Feb 07 02:00:37 PM PST 24
Finished Feb 07 02:00:47 PM PST 24
Peak memory 217804 kb
Host smart-5a6e1dac-a1f3-4bae-86f1-8a23bb5406aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992390244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2992390244
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.174830706
Short name T822
Test name
Test status
Simulation time 1247231855 ps
CPU time 10.69 seconds
Started Feb 07 02:00:36 PM PST 24
Finished Feb 07 02:00:47 PM PST 24
Peak memory 217776 kb
Host smart-ef2352b7-d328-4cb1-82c0-e6c5e4f9e619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174830706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.174830706
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1861675409
Short name T669
Test name
Test status
Simulation time 777963596 ps
CPU time 9.1 seconds
Started Feb 07 02:00:29 PM PST 24
Finished Feb 07 02:00:39 PM PST 24
Peak memory 217864 kb
Host smart-d6f604db-6c9f-4a20-9c5d-a2303d522943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861675409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1861675409
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1374880412
Short name T767
Test name
Test status
Simulation time 145087708 ps
CPU time 2.84 seconds
Started Feb 07 02:00:30 PM PST 24
Finished Feb 07 02:00:34 PM PST 24
Peak memory 213908 kb
Host smart-2154c4cc-c9a0-4868-bd17-b62f606252bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374880412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1374880412
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3837518885
Short name T673
Test name
Test status
Simulation time 357989476 ps
CPU time 23.35 seconds
Started Feb 07 02:00:32 PM PST 24
Finished Feb 07 02:00:57 PM PST 24
Peak memory 250828 kb
Host smart-833fe865-09bb-4244-b95c-c704e88e42cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837518885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3837518885
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3924697603
Short name T393
Test name
Test status
Simulation time 300285449 ps
CPU time 7.95 seconds
Started Feb 07 02:00:31 PM PST 24
Finished Feb 07 02:00:41 PM PST 24
Peak memory 246000 kb
Host smart-2b3482cd-5c65-48c2-b82a-9256e6aadd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924697603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3924697603
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1956116554
Short name T620
Test name
Test status
Simulation time 3542867542 ps
CPU time 14.71 seconds
Started Feb 07 02:00:30 PM PST 24
Finished Feb 07 02:00:46 PM PST 24
Peak memory 217848 kb
Host smart-99c18830-fc78-4d36-90bf-d76b26b1f97e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956116554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1956116554
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1544213532
Short name T721
Test name
Test status
Simulation time 12636373 ps
CPU time 0.79 seconds
Started Feb 07 02:00:30 PM PST 24
Finished Feb 07 02:00:32 PM PST 24
Peak memory 207840 kb
Host smart-b05fc512-d1f3-470c-9ef5-26fa77024e25
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544213532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1544213532
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.774662939
Short name T992
Test name
Test status
Simulation time 108091101 ps
CPU time 1.34 seconds
Started Feb 07 01:58:31 PM PST 24
Finished Feb 07 01:58:34 PM PST 24
Peak memory 208384 kb
Host smart-67b4b91d-787b-4071-adc5-3b6bb2a082d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774662939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.774662939
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3294387927
Short name T309
Test name
Test status
Simulation time 155235765 ps
CPU time 0.84 seconds
Started Feb 07 01:58:33 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 209084 kb
Host smart-6c72d160-1eb2-4dde-9764-079edb6f851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294387927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3294387927
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1810067025
Short name T914
Test name
Test status
Simulation time 1400549472 ps
CPU time 11.72 seconds
Started Feb 07 01:58:28 PM PST 24
Finished Feb 07 01:58:41 PM PST 24
Peak memory 217776 kb
Host smart-43c52c79-9b89-4f2a-9405-cd9051e35431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810067025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1810067025
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3359354691
Short name T520
Test name
Test status
Simulation time 115161573 ps
CPU time 3.36 seconds
Started Feb 07 01:58:35 PM PST 24
Finished Feb 07 01:58:39 PM PST 24
Peak memory 209408 kb
Host smart-6bde3d61-a195-423f-b3c3-89ddbc70f97a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359354691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ac
cess.3359354691
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1198443830
Short name T664
Test name
Test status
Simulation time 6525364006 ps
CPU time 50.34 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:59:26 PM PST 24
Peak memory 218156 kb
Host smart-4cfc597c-869a-4f88-8c31-326c051f74bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198443830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1198443830
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.737209739
Short name T927
Test name
Test status
Simulation time 159145076 ps
CPU time 2.68 seconds
Started Feb 07 01:58:32 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 209536 kb
Host smart-aa33fd62-4270-46eb-9e97-9bcaca218430
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737209739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_p
riority.737209739
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3422530782
Short name T737
Test name
Test status
Simulation time 718043765 ps
CPU time 3.09 seconds
Started Feb 07 01:58:33 PM PST 24
Finished Feb 07 01:58:37 PM PST 24
Peak memory 217752 kb
Host smart-e43f30c7-2f46-4eb0-8d09-acb3eb68596a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422530782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3422530782
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.390935055
Short name T837
Test name
Test status
Simulation time 613824887 ps
CPU time 14.86 seconds
Started Feb 07 01:58:31 PM PST 24
Finished Feb 07 01:58:46 PM PST 24
Peak memory 212896 kb
Host smart-8f65ffce-353a-460f-a0a7-ad3e49a4bae4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390935055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.390935055
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3415480226
Short name T736
Test name
Test status
Simulation time 1716225287 ps
CPU time 6.83 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:58:42 PM PST 24
Peak memory 212976 kb
Host smart-28d398c8-a29c-4500-8326-4d462f532523
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415480226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3415480226
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2468589710
Short name T592
Test name
Test status
Simulation time 2845460534 ps
CPU time 69.62 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:59:44 PM PST 24
Peak memory 267204 kb
Host smart-f59fbc96-008a-4f31-a7a4-c52abe794ab8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468589710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2468589710
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3651686373
Short name T686
Test name
Test status
Simulation time 526027421 ps
CPU time 14.84 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:51 PM PST 24
Peak memory 222516 kb
Host smart-678c45ef-7440-4524-9cac-a16a7ff35ce2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651686373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3651686373
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1133696990
Short name T514
Test name
Test status
Simulation time 65926694 ps
CPU time 2.69 seconds
Started Feb 07 01:58:38 PM PST 24
Finished Feb 07 01:58:41 PM PST 24
Peak memory 217776 kb
Host smart-931134d8-c2cc-472b-acd8-dc20a75a4364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133696990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1133696990
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3853142961
Short name T924
Test name
Test status
Simulation time 218323878 ps
CPU time 7.89 seconds
Started Feb 07 01:58:29 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 213204 kb
Host smart-e878f8c9-9611-4319-af37-5ce87493aac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853142961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3853142961
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.4063726140
Short name T668
Test name
Test status
Simulation time 284388329 ps
CPU time 14.03 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:58:49 PM PST 24
Peak memory 218904 kb
Host smart-697cecf6-30b1-4889-89ec-f5ae402b248b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063726140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4063726140
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.793968478
Short name T427
Test name
Test status
Simulation time 2536927922 ps
CPU time 14.52 seconds
Started Feb 07 01:58:32 PM PST 24
Finished Feb 07 01:58:47 PM PST 24
Peak memory 217884 kb
Host smart-951e2584-dbd7-4cd5-9774-525a8a5875bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793968478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.793968478
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.717807218
Short name T460
Test name
Test status
Simulation time 307930347 ps
CPU time 8.03 seconds
Started Feb 07 01:58:31 PM PST 24
Finished Feb 07 01:58:40 PM PST 24
Peak memory 217816 kb
Host smart-3c8cdef8-683b-452a-9e15-818228fe7dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717807218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.717807218
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2974950424
Short name T782
Test name
Test status
Simulation time 908436466 ps
CPU time 13.28 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:58:48 PM PST 24
Peak memory 217864 kb
Host smart-9813f0ac-bf8f-49a6-b2ee-9d0ee7613590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974950424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2974950424
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.614225924
Short name T909
Test name
Test status
Simulation time 88334795 ps
CPU time 2.05 seconds
Started Feb 07 01:58:32 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 213396 kb
Host smart-9722e667-28a1-4d5a-98a6-f9acef6cd05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614225924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.614225924
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3571800826
Short name T786
Test name
Test status
Simulation time 160354602 ps
CPU time 21.14 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 250820 kb
Host smart-dce92384-cc18-4d01-8227-23799da2e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571800826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3571800826
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1007180447
Short name T552
Test name
Test status
Simulation time 83102323 ps
CPU time 6.6 seconds
Started Feb 07 01:58:24 PM PST 24
Finished Feb 07 01:58:31 PM PST 24
Peak memory 243884 kb
Host smart-70233bb2-1de1-4b3d-890c-a56a39f140c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007180447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1007180447
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3848148854
Short name T374
Test name
Test status
Simulation time 30383072375 ps
CPU time 229.5 seconds
Started Feb 07 01:58:32 PM PST 24
Finished Feb 07 02:02:23 PM PST 24
Peak memory 226016 kb
Host smart-6534f465-5d81-4719-a6d1-e14317a8d4f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848148854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3848148854
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.886520253
Short name T697
Test name
Test status
Simulation time 13904830 ps
CPU time 0.93 seconds
Started Feb 07 01:58:28 PM PST 24
Finished Feb 07 01:58:29 PM PST 24
Peak memory 211300 kb
Host smart-3ee6025f-caee-4e27-b3c2-2e90d2cf429c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886520253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.886520253
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3860534202
Short name T607
Test name
Test status
Simulation time 25060309 ps
CPU time 0.82 seconds
Started Feb 07 01:58:44 PM PST 24
Finished Feb 07 01:58:46 PM PST 24
Peak memory 209188 kb
Host smart-aac6544b-6e1c-4a0e-8abe-5b0408754add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860534202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3860534202
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3507073367
Short name T187
Test name
Test status
Simulation time 21626389 ps
CPU time 0.99 seconds
Started Feb 07 01:58:33 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 209268 kb
Host smart-6bb75744-8c6c-402d-ba94-3c559c3200af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507073367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3507073367
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4270815189
Short name T769
Test name
Test status
Simulation time 371869008 ps
CPU time 12.14 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:58:47 PM PST 24
Peak memory 217760 kb
Host smart-a96e4592-55aa-4227-bef6-835cb7049218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270815189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4270815189
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.504248758
Short name T630
Test name
Test status
Simulation time 326474898 ps
CPU time 5.16 seconds
Started Feb 07 01:58:35 PM PST 24
Finished Feb 07 01:58:41 PM PST 24
Peak memory 209480 kb
Host smart-040fade2-d2da-47aa-90ee-aeae7efce982
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504248758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_acc
ess.504248758
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2391699785
Short name T35
Test name
Test status
Simulation time 10119121388 ps
CPU time 26.73 seconds
Started Feb 07 01:58:32 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 218904 kb
Host smart-705507ca-c114-4c5d-affc-327ce3abfc9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391699785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2391699785
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1342756890
Short name T942
Test name
Test status
Simulation time 162183519 ps
CPU time 2.2 seconds
Started Feb 07 01:58:31 PM PST 24
Finished Feb 07 01:58:34 PM PST 24
Peak memory 209532 kb
Host smart-73a87d47-2326-476c-a42a-b04ab819ac00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342756890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.1342756890
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4205154451
Short name T839
Test name
Test status
Simulation time 1012623597 ps
CPU time 6.19 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:58:41 PM PST 24
Peak memory 217876 kb
Host smart-36638d86-0abc-4f7a-8a82-3c78c2a11985
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205154451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.4205154451
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1607588717
Short name T335
Test name
Test status
Simulation time 1898439489 ps
CPU time 13.83 seconds
Started Feb 07 01:58:33 PM PST 24
Finished Feb 07 01:58:47 PM PST 24
Peak memory 212844 kb
Host smart-e7976896-7d2a-45a6-8985-996562f837a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607588717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1607588717
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3368986257
Short name T473
Test name
Test status
Simulation time 1499003913 ps
CPU time 5.46 seconds
Started Feb 07 01:58:32 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 213112 kb
Host smart-3fcf9fa8-df8f-40f4-8b20-3b988a34ecda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368986257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3368986257
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.21846569
Short name T756
Test name
Test status
Simulation time 1069906428 ps
CPU time 37.73 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:59:13 PM PST 24
Peak memory 250892 kb
Host smart-b8519024-d863-4350-bb3d-87d50ce4772c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
state_failure.21846569
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3858638279
Short name T921
Test name
Test status
Simulation time 527055569 ps
CPU time 20.79 seconds
Started Feb 07 01:58:32 PM PST 24
Finished Feb 07 01:58:53 PM PST 24
Peak memory 250524 kb
Host smart-7e30e1cb-a150-4847-8fd9-802ba14249db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858638279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3858638279
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.433678592
Short name T375
Test name
Test status
Simulation time 245453296 ps
CPU time 2.69 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:58:44 PM PST 24
Peak memory 217796 kb
Host smart-0f106952-15fe-4131-8d6d-6c98dab4ea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433678592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.433678592
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2228616181
Short name T315
Test name
Test status
Simulation time 1653802552 ps
CPU time 8.66 seconds
Started Feb 07 01:58:33 PM PST 24
Finished Feb 07 01:58:42 PM PST 24
Peak memory 213368 kb
Host smart-b56ae07d-4a7a-4121-90a3-bad65fbe8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228616181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2228616181
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3294813962
Short name T348
Test name
Test status
Simulation time 518207371 ps
CPU time 13.02 seconds
Started Feb 07 01:58:30 PM PST 24
Finished Feb 07 01:58:43 PM PST 24
Peak memory 217752 kb
Host smart-f262209b-3e86-4565-b797-e198e4d13246
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294813962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3294813962
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1372860779
Short name T759
Test name
Test status
Simulation time 2542467402 ps
CPU time 15.78 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:58:54 PM PST 24
Peak memory 217928 kb
Host smart-5a0cd515-85c7-4fd8-abe7-f9c462de132e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372860779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1372860779
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3898330256
Short name T860
Test name
Test status
Simulation time 1314703169 ps
CPU time 11.95 seconds
Started Feb 07 01:58:32 PM PST 24
Finished Feb 07 01:58:44 PM PST 24
Peak memory 217856 kb
Host smart-2717b654-f4f0-43e8-bc4a-e75b9d2ef0fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898330256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
898330256
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1534857429
Short name T948
Test name
Test status
Simulation time 241928176 ps
CPU time 7.15 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:44 PM PST 24
Peak memory 217808 kb
Host smart-0864d5a3-fa16-4f8b-9c5f-49627507eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534857429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1534857429
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.351652792
Short name T629
Test name
Test status
Simulation time 32514103 ps
CPU time 1.08 seconds
Started Feb 07 01:58:33 PM PST 24
Finished Feb 07 01:58:35 PM PST 24
Peak memory 212796 kb
Host smart-0d6213ce-fdb8-437d-98ed-07bd8e352dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351652792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.351652792
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.331134801
Short name T675
Test name
Test status
Simulation time 433815229 ps
CPU time 27.2 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:59:02 PM PST 24
Peak memory 250780 kb
Host smart-e0dda564-b768-4660-91bf-adcef89a23c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331134801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.331134801
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2717777813
Short name T991
Test name
Test status
Simulation time 102149553 ps
CPU time 8.36 seconds
Started Feb 07 01:58:35 PM PST 24
Finished Feb 07 01:58:44 PM PST 24
Peak memory 250876 kb
Host smart-c6e66fad-77f3-459d-b6d7-274355fa126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717777813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2717777813
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2834494608
Short name T670
Test name
Test status
Simulation time 11894754876 ps
CPU time 258.04 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 02:02:55 PM PST 24
Peak memory 421844 kb
Host smart-c0d078c3-8d90-4259-944c-3f97862b73d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834494608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2834494608
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3714360072
Short name T111
Test name
Test status
Simulation time 72188049165 ps
CPU time 324.72 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 02:04:06 PM PST 24
Peak memory 445096 kb
Host smart-e0296322-aff4-45fd-b7a7-d1322277ff32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3714360072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3714360072
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1941477491
Short name T44
Test name
Test status
Simulation time 84167124 ps
CPU time 0.8 seconds
Started Feb 07 01:58:35 PM PST 24
Finished Feb 07 01:58:37 PM PST 24
Peak memory 208160 kb
Host smart-ce08dd53-9c49-4dcf-9415-ed6664b2b7bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941477491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1941477491
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3953971703
Short name T646
Test name
Test status
Simulation time 16288922 ps
CPU time 0.9 seconds
Started Feb 07 01:58:44 PM PST 24
Finished Feb 07 01:58:45 PM PST 24
Peak memory 209396 kb
Host smart-1dcbb7e4-d10a-4202-a483-61e1e1f92e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953971703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3953971703
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4043396125
Short name T75
Test name
Test status
Simulation time 19687137 ps
CPU time 0.92 seconds
Started Feb 07 01:58:38 PM PST 24
Finished Feb 07 01:58:40 PM PST 24
Peak memory 209388 kb
Host smart-afa04f3a-54b9-4977-ae0b-df8683a4769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043396125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4043396125
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.747568376
Short name T878
Test name
Test status
Simulation time 1511933820 ps
CPU time 17.07 seconds
Started Feb 07 01:58:44 PM PST 24
Finished Feb 07 01:59:02 PM PST 24
Peak memory 217816 kb
Host smart-e8d6404e-713f-43fd-8d73-da083fb42325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747568376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.747568376
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.437984963
Short name T10
Test name
Test status
Simulation time 563720142 ps
CPU time 4.08 seconds
Started Feb 07 01:58:38 PM PST 24
Finished Feb 07 01:58:43 PM PST 24
Peak memory 209412 kb
Host smart-2cf40cac-dc01-43fa-bc60-eef8bff575e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437984963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_acc
ess.437984963
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2990438825
Short name T690
Test name
Test status
Simulation time 11322859306 ps
CPU time 36.59 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:59:15 PM PST 24
Peak memory 218104 kb
Host smart-af6fde32-67d6-4c0a-8553-4c29573ce294
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990438825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2990438825
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2369316619
Short name T611
Test name
Test status
Simulation time 287445050 ps
CPU time 5.07 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:58:46 PM PST 24
Peak memory 217720 kb
Host smart-b3abe878-1ed1-4774-b441-e3aa3667d726
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369316619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2369316619
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2222901709
Short name T728
Test name
Test status
Simulation time 1096110840 ps
CPU time 25.98 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:59:03 PM PST 24
Peak memory 212696 kb
Host smart-9fadffbd-3180-4421-af76-d3164e12549a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222901709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2222901709
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4042551234
Short name T984
Test name
Test status
Simulation time 1120875438 ps
CPU time 4.13 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:41 PM PST 24
Peak memory 212948 kb
Host smart-26a09504-d0a0-433a-a9e7-39ddef53d619
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042551234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
4042551234
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2086215394
Short name T884
Test name
Test status
Simulation time 5022660200 ps
CPU time 35.8 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:59:14 PM PST 24
Peak memory 267184 kb
Host smart-ee9b8a30-295b-4ffa-b195-f99cf5b4522c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086215394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2086215394
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1388841624
Short name T771
Test name
Test status
Simulation time 1726146255 ps
CPU time 7.66 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:58:49 PM PST 24
Peak memory 217804 kb
Host smart-4b936fa6-31e6-4e5e-ad08-526103d5bbfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388841624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1388841624
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.534253671
Short name T842
Test name
Test status
Simulation time 205434472 ps
CPU time 4.17 seconds
Started Feb 07 01:58:33 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 217844 kb
Host smart-7354d025-c499-45ea-9746-80de47a3334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534253671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.534253671
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.410072217
Short name T681
Test name
Test status
Simulation time 410478374 ps
CPU time 9.43 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:58:50 PM PST 24
Peak memory 213660 kb
Host smart-bb1acb78-9bda-4d73-83c3-2d50daf17d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410072217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.410072217
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3784351244
Short name T541
Test name
Test status
Simulation time 288570089 ps
CPU time 13.74 seconds
Started Feb 07 01:58:44 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 217832 kb
Host smart-62746cf9-daa6-4e8c-a69a-8dd49777bb22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784351244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3784351244
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1795194441
Short name T194
Test name
Test status
Simulation time 1956523969 ps
CPU time 15.64 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:53 PM PST 24
Peak memory 217776 kb
Host smart-3a314a8b-c061-4c29-bede-4ff1bae597bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795194441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1795194441
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.376945582
Short name T833
Test name
Test status
Simulation time 829899954 ps
CPU time 6.4 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:58:45 PM PST 24
Peak memory 217788 kb
Host smart-48f85ce1-002b-4562-a47e-5de70ff87f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376945582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.376945582
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2200191942
Short name T437
Test name
Test status
Simulation time 566165443 ps
CPU time 10.88 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:48 PM PST 24
Peak memory 217804 kb
Host smart-b30692fd-a619-400c-a0e1-fe9cb1527955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200191942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2200191942
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3235435359
Short name T80
Test name
Test status
Simulation time 261564959 ps
CPU time 2.83 seconds
Started Feb 07 01:58:39 PM PST 24
Finished Feb 07 01:58:43 PM PST 24
Peak memory 214268 kb
Host smart-c47f4737-84b0-4ab3-82a5-1890f316b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235435359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3235435359
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1625732924
Short name T336
Test name
Test status
Simulation time 1304632457 ps
CPU time 30.2 seconds
Started Feb 07 01:58:44 PM PST 24
Finished Feb 07 01:59:15 PM PST 24
Peak memory 250832 kb
Host smart-d65c41a9-d9c4-47a3-95b4-c90b0750a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625732924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1625732924
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3849196815
Short name T317
Test name
Test status
Simulation time 726572986 ps
CPU time 8.51 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:45 PM PST 24
Peak memory 246308 kb
Host smart-b4017f85-9703-4b29-adae-f1f449cd8076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849196815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3849196815
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.596297337
Short name T433
Test name
Test status
Simulation time 19542070 ps
CPU time 0.9 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:37 PM PST 24
Peak memory 207924 kb
Host smart-1d347568-a8bd-4951-bdca-35b3f403f22e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596297337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.596297337
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1667007087
Short name T816
Test name
Test status
Simulation time 46094952 ps
CPU time 1.27 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:58:42 PM PST 24
Peak memory 209396 kb
Host smart-3f090807-1dc1-470d-b347-f16ed3f0d2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667007087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1667007087
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.663632721
Short name T642
Test name
Test status
Simulation time 1002023641 ps
CPU time 9.73 seconds
Started Feb 07 01:58:35 PM PST 24
Finished Feb 07 01:58:45 PM PST 24
Peak memory 217812 kb
Host smart-02bff116-f345-4bdc-8e29-634c89e2a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663632721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.663632721
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.279263409
Short name T700
Test name
Test status
Simulation time 1013468901 ps
CPU time 7.66 seconds
Started Feb 07 01:58:41 PM PST 24
Finished Feb 07 01:58:49 PM PST 24
Peak memory 209440 kb
Host smart-23d2f4e6-e95b-4163-9fcf-27b83712c477
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279263409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_acc
ess.279263409
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.4245842533
Short name T599
Test name
Test status
Simulation time 3292506037 ps
CPU time 44.74 seconds
Started Feb 07 01:58:39 PM PST 24
Finished Feb 07 01:59:25 PM PST 24
Peak memory 217952 kb
Host smart-37e7476f-4144-40a0-9b43-1d24f778c043
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245842533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.4245842533
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3219013221
Short name T452
Test name
Test status
Simulation time 617839047 ps
CPU time 15.89 seconds
Started Feb 07 01:58:41 PM PST 24
Finished Feb 07 01:58:58 PM PST 24
Peak memory 217692 kb
Host smart-e4b854f9-2b72-4e90-9676-7416d6c2dd29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219013221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.3219013221
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1733206044
Short name T517
Test name
Test status
Simulation time 2444264421 ps
CPU time 12.27 seconds
Started Feb 07 01:58:41 PM PST 24
Finished Feb 07 01:58:54 PM PST 24
Peak memory 217820 kb
Host smart-5489c76e-0e94-4abe-8280-5b981ae3f100
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733206044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1733206044
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3807681664
Short name T77
Test name
Test status
Simulation time 3235016651 ps
CPU time 13.63 seconds
Started Feb 07 01:58:41 PM PST 24
Finished Feb 07 01:58:56 PM PST 24
Peak memory 213252 kb
Host smart-503ef8d2-9abb-4428-b7d9-991f0323ae96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807681664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3807681664
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2203631389
Short name T467
Test name
Test status
Simulation time 372444527 ps
CPU time 4 seconds
Started Feb 07 01:58:41 PM PST 24
Finished Feb 07 01:58:46 PM PST 24
Peak memory 213012 kb
Host smart-3d6d384e-b5c1-44cd-8759-5cdbdf3e79fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203631389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2203631389
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2592498699
Short name T580
Test name
Test status
Simulation time 873040704 ps
CPU time 41.42 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:59:16 PM PST 24
Peak memory 250732 kb
Host smart-df171623-2a73-44be-aa5d-80276844cb0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592498699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2592498699
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1735992763
Short name T704
Test name
Test status
Simulation time 356578280 ps
CPU time 10 seconds
Started Feb 07 01:58:34 PM PST 24
Finished Feb 07 01:58:45 PM PST 24
Peak memory 245168 kb
Host smart-5585c846-715d-41c3-a24f-3d79504525ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735992763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1735992763
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2688018825
Short name T935
Test name
Test status
Simulation time 189814996 ps
CPU time 3.95 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:58:45 PM PST 24
Peak memory 217784 kb
Host smart-13a3498f-a84d-40a7-81c8-0f18ff6c1c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688018825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2688018825
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.286327128
Short name T591
Test name
Test status
Simulation time 376571370 ps
CPU time 15.12 seconds
Started Feb 07 01:58:38 PM PST 24
Finished Feb 07 01:58:54 PM PST 24
Peak memory 214060 kb
Host smart-1d3b5b48-9650-4949-b0e4-c6826478e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286327128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.286327128
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2475170727
Short name T876
Test name
Test status
Simulation time 1208498978 ps
CPU time 10.98 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:58:49 PM PST 24
Peak memory 217776 kb
Host smart-1705f58c-2507-4c10-a883-79b1406ade0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475170727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2475170727
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1299088766
Short name T623
Test name
Test status
Simulation time 793701501 ps
CPU time 17.69 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:58:56 PM PST 24
Peak memory 217884 kb
Host smart-668e639f-7557-43b3-8b92-5e96b3b9fefd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299088766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1299088766
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1590454888
Short name T326
Test name
Test status
Simulation time 576731586 ps
CPU time 12.09 seconds
Started Feb 07 01:58:41 PM PST 24
Finished Feb 07 01:58:54 PM PST 24
Peak memory 217812 kb
Host smart-b7b892ca-744c-4e53-b636-ea0835bd06f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590454888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
590454888
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3115831199
Short name T869
Test name
Test status
Simulation time 384023891 ps
CPU time 8.7 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:58:47 PM PST 24
Peak memory 217784 kb
Host smart-0d62e706-32cd-4f22-9278-955b5a5f62b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115831199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3115831199
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2471813083
Short name T328
Test name
Test status
Simulation time 120101854 ps
CPU time 1.78 seconds
Started Feb 07 01:58:36 PM PST 24
Finished Feb 07 01:58:39 PM PST 24
Peak memory 212996 kb
Host smart-250d432c-2077-4ecf-90bf-78bfc2b7890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471813083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2471813083
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1369153734
Short name T516
Test name
Test status
Simulation time 258054737 ps
CPU time 25.56 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:59:06 PM PST 24
Peak memory 250836 kb
Host smart-c652c52b-cb8f-49d0-b33c-541a6a6f301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369153734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1369153734
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3048777748
Short name T339
Test name
Test status
Simulation time 79186411 ps
CPU time 8.31 seconds
Started Feb 07 01:58:43 PM PST 24
Finished Feb 07 01:58:53 PM PST 24
Peak memory 250784 kb
Host smart-cc8b72a2-8bbe-4469-9811-2a702d4e6eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048777748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3048777748
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1525029129
Short name T355
Test name
Test status
Simulation time 4807666172 ps
CPU time 115.7 seconds
Started Feb 07 01:58:39 PM PST 24
Finished Feb 07 02:00:35 PM PST 24
Peak memory 277816 kb
Host smart-356b6f97-5181-4e65-a9dc-aed394a18436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525029129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1525029129
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3824617728
Short name T84
Test name
Test status
Simulation time 38941510 ps
CPU time 1.04 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:58:41 PM PST 24
Peak memory 212508 kb
Host smart-67f412bd-a458-47b5-bd38-a02ce47b8dfa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824617728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3824617728
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1780514307
Short name T321
Test name
Test status
Simulation time 18861038 ps
CPU time 0.88 seconds
Started Feb 07 01:58:52 PM PST 24
Finished Feb 07 01:58:54 PM PST 24
Peak memory 208096 kb
Host smart-1bb64107-d63a-46bd-9e28-371811681f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780514307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1780514307
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.955784464
Short name T653
Test name
Test status
Simulation time 1705340070 ps
CPU time 16.92 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:58:58 PM PST 24
Peak memory 217820 kb
Host smart-e10bf6d4-cf53-4dbd-a07f-8111efd34dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955784464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.955784464
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2778292077
Short name T31
Test name
Test status
Simulation time 1946475233 ps
CPU time 23.37 seconds
Started Feb 07 01:58:46 PM PST 24
Finished Feb 07 01:59:10 PM PST 24
Peak memory 217572 kb
Host smart-106bd23b-982e-4e26-9088-f39380de06ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778292077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.2778292077
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2693299740
Short name T331
Test name
Test status
Simulation time 2280531271 ps
CPU time 29.64 seconds
Started Feb 07 01:58:46 PM PST 24
Finished Feb 07 01:59:17 PM PST 24
Peak memory 217876 kb
Host smart-aec5abad-01d6-42df-879d-a83d95349c07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693299740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2693299740
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2558766488
Short name T687
Test name
Test status
Simulation time 980150219 ps
CPU time 7.75 seconds
Started Feb 07 01:58:47 PM PST 24
Finished Feb 07 01:58:55 PM PST 24
Peak memory 209504 kb
Host smart-1719bcd7-5c8c-48a2-a206-f45afdc4b5b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558766488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
priority.2558766488
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.228771507
Short name T589
Test name
Test status
Simulation time 1214483381 ps
CPU time 5.38 seconds
Started Feb 07 01:58:44 PM PST 24
Finished Feb 07 01:58:50 PM PST 24
Peak memory 217792 kb
Host smart-7de39e14-d2d0-4f7d-b268-b09c3110c768
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228771507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.228771507
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1800018089
Short name T579
Test name
Test status
Simulation time 5007316247 ps
CPU time 16.61 seconds
Started Feb 07 01:58:50 PM PST 24
Finished Feb 07 01:59:08 PM PST 24
Peak memory 213484 kb
Host smart-f1f2d942-04c8-4e98-b31b-3031c7c53d07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800018089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1800018089
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2662484722
Short name T69
Test name
Test status
Simulation time 1635911840 ps
CPU time 4.93 seconds
Started Feb 07 01:58:47 PM PST 24
Finished Feb 07 01:58:53 PM PST 24
Peak memory 212884 kb
Host smart-5ece8366-a42c-4daa-ba73-674739938e73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662484722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2662484722
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.4113207808
Short name T109
Test name
Test status
Simulation time 28190193260 ps
CPU time 51.48 seconds
Started Feb 07 01:58:46 PM PST 24
Finished Feb 07 01:59:38 PM PST 24
Peak memory 283616 kb
Host smart-06f0cf44-2bd0-4e5c-bc11-b3b8151da0c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113207808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.4113207808
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2008808429
Short name T191
Test name
Test status
Simulation time 1621176490 ps
CPU time 17.98 seconds
Started Feb 07 01:58:44 PM PST 24
Finished Feb 07 01:59:03 PM PST 24
Peak memory 250860 kb
Host smart-5f1e843e-417f-48e3-985c-d157b74be593
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008808429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2008808429
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.26494787
Short name T768
Test name
Test status
Simulation time 106123636 ps
CPU time 1.72 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:58:40 PM PST 24
Peak memory 217792 kb
Host smart-19d0cc9c-23bd-4688-a360-82074646c516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26494787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.26494787
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.326109104
Short name T960
Test name
Test status
Simulation time 3142149863 ps
CPU time 9.9 seconds
Started Feb 07 01:58:48 PM PST 24
Finished Feb 07 01:58:59 PM PST 24
Peak memory 214376 kb
Host smart-f34c4912-103c-448f-98d4-ed551b105028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326109104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.326109104
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.664604351
Short name T693
Test name
Test status
Simulation time 376253971 ps
CPU time 15.68 seconds
Started Feb 07 01:58:47 PM PST 24
Finished Feb 07 01:59:03 PM PST 24
Peak memory 218788 kb
Host smart-8d789eb7-2357-424a-babe-88561ea12f5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664604351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.664604351
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3054213440
Short name T715
Test name
Test status
Simulation time 569049635 ps
CPU time 16.26 seconds
Started Feb 07 01:58:46 PM PST 24
Finished Feb 07 01:59:04 PM PST 24
Peak memory 217852 kb
Host smart-e8d6958a-6d08-44f9-b18b-48defcf3d429
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054213440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3054213440
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3878528750
Short name T605
Test name
Test status
Simulation time 357293578 ps
CPU time 13.84 seconds
Started Feb 07 01:58:45 PM PST 24
Finished Feb 07 01:59:00 PM PST 24
Peak memory 217820 kb
Host smart-b69f3fb0-f21a-45db-9eca-8de5e9f40e2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878528750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
878528750
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1398109489
Short name T370
Test name
Test status
Simulation time 912768432 ps
CPU time 12.62 seconds
Started Feb 07 01:58:43 PM PST 24
Finished Feb 07 01:58:57 PM PST 24
Peak memory 217856 kb
Host smart-84267783-b167-4d2f-bdfe-7597f42628ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398109489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1398109489
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.494349177
Short name T740
Test name
Test status
Simulation time 103492540 ps
CPU time 2.95 seconds
Started Feb 07 01:58:39 PM PST 24
Finished Feb 07 01:58:43 PM PST 24
Peak memory 214012 kb
Host smart-5062870e-65d1-4f3a-b5ed-2ddf9aad6517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494349177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.494349177
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.308431822
Short name T388
Test name
Test status
Simulation time 250080152 ps
CPU time 26.57 seconds
Started Feb 07 01:58:40 PM PST 24
Finished Feb 07 01:59:08 PM PST 24
Peak memory 244580 kb
Host smart-4213ef90-70d4-47b8-912c-81d86a243979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308431822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.308431822
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3760792029
Short name T458
Test name
Test status
Simulation time 330122959 ps
CPU time 6.44 seconds
Started Feb 07 01:58:38 PM PST 24
Finished Feb 07 01:58:45 PM PST 24
Peak memory 250324 kb
Host smart-c3352590-5be4-4e5e-a96b-21d6c889e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760792029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3760792029
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4127142567
Short name T367
Test name
Test status
Simulation time 16277191566 ps
CPU time 87.69 seconds
Started Feb 07 01:58:44 PM PST 24
Finished Feb 07 02:00:12 PM PST 24
Peak memory 247280 kb
Host smart-f7cb497b-98bd-47f0-9a7c-5bbf71a0fa61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127142567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4127142567
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2447294448
Short name T1
Test name
Test status
Simulation time 11899043 ps
CPU time 0.83 seconds
Started Feb 07 01:58:37 PM PST 24
Finished Feb 07 01:58:39 PM PST 24
Peak memory 207808 kb
Host smart-def1415c-9f96-41f9-97b6-21332000cc56
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447294448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2447294448
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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