Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245882152

1

T1

14591

T2

1803

T3

2676

auto[1]

2972397

1

T1

98

T3

297

T4

19075

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245907726

1

T1

14591

T2

1803

T3

2775

auto[1]

2946823

1

T1

98

T3

198

T4

16904

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	15900927	1			T1	287		T2	71		T3	509
auto[IdleSt]	49191593	1			T1	10494		T2	1732		T3	1323
auto[ClkMuxSt]	77027	1			T1	2		T3	5		T4	527
auto[CntIncrSt]	76494	1			T1	2		T3	5		T4	527
auto[CntProgSt]	3699462	1			T1	27		T3	10		T4	913
auto[TransCheckSt]	59684	1			T4	398		T8	39		T9	17
auto[TokenHashSt]	107314476	1			T4	319854		T8	677		T9	1294
auto[FlashRmaSt]	61712	1			T4	494		T8	17		T9	40
auto[TokenCheck0St]	27618	1			T4	211		T8	8		T9	17
auto[TokenCheck1St]	20470	1			T4	160		T8	4		T9	17
auto[TransProgSt]	982829	1			T4	314		T8	240		T9	34
auto[PostTransSt]	29371632	1			T1	2237		T3	426		T4	554635
auto[ScrapSt]	326598	1			T4	5002		T20	637		T17	6
auto[EscalateSt]	15108976	1			T1	1640		T3	695		T4	120142
auto[InvalidSt]	26630802	1			T4	135924		T32	6107		T34	6730

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	4249	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	26630802	1			T4	135924		T32	6107		T34	6730
EscalateSt	15108976	1			T1	1640		T3	695		T4	120142
ScrapSt	326598	1			T4	5002		T20	637		T17	6
PostTransSt	29371632	1			T1	2237		T3	426		T4	554635
TransProgSt	982829	1			T4	314		T8	240		T9	34
TokenCheck1St	20470	1			T4	160		T8	4		T9	17
TokenCheck0St	27618	1			T4	211		T8	8		T9	17
FlashRmaSt	61712	1			T4	494		T8	17		T9	40
TokenHashSt	107314476	1			T4	319854		T8	677		T9	1294
TransCheckSt	59684	1			T4	398		T8	39		T9	17
CntProgSt	3699462	1			T1	27		T3	10		T4	913
CntIncrSt	76494	1			T1	2		T3	5		T4	527
ClkMuxSt	77027	1			T1	2		T3	5		T4	527
IdleSt	49191593	1			T1	10494		T2	1732		T3	1323
ResetSt	15900927	1			T1	287		T2	71		T3	509
arcs[ResetSt=>IdleSt]	117710	1			T1	3		T2	1		T3	6
arcs[IdleSt=>ScrapSt]	609	1			T4	8		T20	2		T17	2
arcs[IdleSt=>ClkMuxSt]	76613	1			T1	2		T3	5		T4	527
arcs[ClkMuxSt=>CntIncrSt]	76494	1			T1	2		T3	5		T4	527
arcs[CntIncrSt=>PostTransSt]	3972	1			T4	49		T8	11		T11	13
arcs[CntIncrSt=>CntProgSt]	72393	1			T1	2		T3	5		T4	478
arcs[CntProgSt=>PostTransSt]	10686	1			T1	2		T3	5		T4	80
arcs[CntProgSt=>TransCheckSt]	59684	1			T4	398		T8	39		T9	17
arcs[TransCheckSt=>PostTransSt]	8041	1			T4	43		T8	6		T11	10
arcs[TransCheckSt=>TokenHashSt]	51381	1			T4	355		T8	33		T9	17
arcs[TokenHashSt=>PostTransSt]	22160	1			T4	139		T8	25		T11	34
arcs[TokenHashSt=>FlashRmaSt]	27818	1			T4	211		T8	8		T9	17
arcs[FlashRmaSt=>TokenCheck0St]	27618	1			T4	211		T8	8		T9	17
arcs[TokenCheck0St=>PostTransSt]	7086	1			T4	51		T8	4		T11	12
arcs[TokenCheck0St=>TokenCheck1St]	20470	1			T4	160		T8	4		T9	17
arcs[TokenCheck1St=>PostTransSt]	1393	1			T4	2		T11	2		T19	8
arcs[TransProgSt=>PostTransSt]	17331	1			T4	158		T8	4		T9	17
arcs[IdleSt=>EscalateSt]	376	1			T48	7		T49	4		T50	4
arcs[ClkMuxSt=>EscalateSt]	119	1			T17	3		T45	2		T46	3
arcs[CntIncrSt=>EscalateSt]	129	1			T17	2		T45	2		T46	1
arcs[CntProgSt=>EscalateSt]	2012	1			T17	5		T45	11		T46	26
arcs[TransCheckSt=>EscalateSt]	262	1			T17	9		T45	7		T47	6
arcs[TokenHashSt=>EscalateSt]	1305	1			T4	3		T17	26		T45	30
arcs[FlashRmaSt=>EscalateSt]	200	1			T17	4		T46	1		T47	1
arcs[TokenCheck0St=>EscalateSt]	62	1			T17	1		T45	2		T48	2
arcs[TokenCheck1St=>EscalateSt]	295	1			T17	1		T45	1		T46	2
arcs[TransProgSt=>EscalateSt]	1451	1			T17	5		T45	9		T46	16
arcs[PostTransSt=>EscalateSt]	11201	1			T1	2		T3	5		T4	78
arcs[InvalidSt=>EscalateSt]	30703	1			T4	283		T32	83		T34	50

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	15900620	1			T1	287		T2	71		T3	509
auto[0]	auto[IdleSt]	49191350	1			T1	10494		T2	1732		T3	1323
auto[0]	auto[ClkMuxSt]	76947	1			T1	2		T3	5		T4	527
auto[0]	auto[CntIncrSt]	76410	1			T1	2		T3	5		T4	527
auto[0]	auto[CntProgSt]	3698114	1			T1	27		T3	10		T4	913
auto[0]	auto[TransCheckSt]	59499	1			T4	398		T8	39		T9	17
auto[0]	auto[TokenHashSt]	107313632	1			T4	319854		T8	677		T9	1294
auto[0]	auto[FlashRmaSt]	61579	1			T4	494		T8	17		T9	40
auto[0]	auto[TokenCheck0St]	27569	1			T4	211		T8	8		T9	17
auto[0]	auto[TokenCheck1St]	20280	1			T4	160		T8	4		T9	17
auto[0]	auto[TransProgSt]	981872	1			T4	314		T8	240		T9	34
auto[0]	auto[PostTransSt]	29365898	1			T1	2236		T3	423		T4	554595
auto[0]	auto[ScrapSt]	326508	1			T4	5002		T20	637		T17	4
auto[0]	auto[EscalateSt]	12162254	1			T1	1543		T3	401		T4	101260
auto[0]	auto[InvalidSt]	26615371	1			T4	135771		T32	6071		T34	6706
auto[1]	auto[ResetSt]	307	1			T17	5		T45	4		T46	1
auto[1]	auto[IdleSt]	243	1			T48	6		T49	3		T50	2
auto[1]	auto[ClkMuxSt]	80	1			T17	1		T45	2		T257	1
auto[1]	auto[CntIncrSt]	84	1			T17	2		T45	2		T46	1
auto[1]	auto[CntProgSt]	1348	1			T17	2		T45	8		T46	16
auto[1]	auto[TransCheckSt]	185	1			T17	3		T45	7		T47	5
auto[1]	auto[TokenHashSt]	844	1			T17	16		T45	17		T46	6
auto[1]	auto[FlashRmaSt]	133	1			T17	4		T46	1		T48	1
auto[1]	auto[TokenCheck0St]	49	1			T45	1		T48	2		T49	1
auto[1]	auto[TokenCheck1St]	190	1			T17	1		T46	1		T48	3
auto[1]	auto[TransProgSt]	957	1			T17	5		T45	6		T46	11
auto[1]	auto[PostTransSt]	5734	1			T1	1		T3	3		T4	40
auto[1]	auto[ScrapSt]	90	1			T17	2		T46	2		T48	2
auto[1]	auto[EscalateSt]	2946722	1			T1	97		T3	294		T4	18882
auto[1]	auto[InvalidSt]	15431	1			T4	153		T32	36		T34	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	15900617	1			T1	287		T2	71		T3	509
auto[0]	auto[IdleSt]	49191342	1			T1	10494		T2	1732		T3	1323
auto[0]	auto[ClkMuxSt]	76943	1			T1	2		T3	5		T4	527
auto[0]	auto[CntIncrSt]	76410	1			T1	2		T3	5		T4	527
auto[0]	auto[CntProgSt]	3698136	1			T1	27		T3	10		T4	913
auto[0]	auto[TransCheckSt]	59518	1			T4	398		T8	39		T9	17
auto[0]	auto[TokenHashSt]	107313605	1			T4	319854		T8	677		T9	1294
auto[0]	auto[FlashRmaSt]	61572	1			T4	494		T8	17		T9	40
auto[0]	auto[TokenCheck0St]	27582	1			T4	211		T8	8		T9	17
auto[0]	auto[TokenCheck1St]	20275	1			T4	160		T8	4		T9	17
auto[0]	auto[TransProgSt]	981848	1			T4	314		T8	240		T9	34
auto[0]	auto[PostTransSt]	29365992	1			T1	2236		T3	424		T4	554597
auto[0]	auto[ScrapSt]	326518	1			T4	5002		T20	637		T17	5
auto[0]	auto[EscalateSt]	12187589	1			T1	1543		T3	499		T4	103409
auto[0]	auto[InvalidSt]	26615530	1			T4	135794		T32	6060		T34	6704
auto[1]	auto[ResetSt]	310	1			T17	3		T45	5		T46	2
auto[1]	auto[IdleSt]	251	1			T48	3		T49	4		T50	2
auto[1]	auto[ClkMuxSt]	84	1			T17	2		T45	1		T46	3
auto[1]	auto[CntIncrSt]	84	1			T17	1		T48	1		T258	1
auto[1]	auto[CntProgSt]	1326	1			T17	5		T45	8		T46	17
auto[1]	auto[TransCheckSt]	166	1			T17	8		T45	4		T47	5
auto[1]	auto[TokenHashSt]	871	1			T4	3		T17	17		T45	19
auto[1]	auto[FlashRmaSt]	140	1			T17	2		T46	1		T47	1
auto[1]	auto[TokenCheck0St]	36	1			T17	1		T45	2		T257	1
auto[1]	auto[TokenCheck1St]	195	1			T17	1		T45	1		T46	2
auto[1]	auto[TransProgSt]	981	1			T17	3		T45	5		T46	11
auto[1]	auto[PostTransSt]	5640	1			T1	1		T3	2		T4	38
auto[1]	auto[ScrapSt]	80	1			T17	1		T45	1		T46	2
auto[1]	auto[EscalateSt]	2921387	1			T1	97		T3	196		T4	16733
auto[1]	auto[InvalidSt]	15272	1			T4	130		T32	47		T34	26