Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg
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Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
fsm_state_q 8 0 8 100.00 100 1 1 0


Summary for Variable fsm_state_q

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for fsm_state_q

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_states[ClkMuxSt] 917 1 T19 8 T55 13 T56 5
fsm_states[CntIncrSt] 882 1 T19 8 T55 8 T56 6
fsm_states[CntProgSt] 956 1 T19 11 T55 9 T56 13
fsm_states[TransCheckSt] 982 1 T19 19 T55 11 T56 13
fsm_states[FlashRmaSt] 925 1 T19 11 T55 9 T56 3
fsm_states[TokenHashSt] 989 1 T19 3 T55 12 T56 13
fsm_states[TokenCheck0St] 956 1 T19 5 T55 9 T56 7
fsm_states[TokenCheck1St] 949 1 T19 8 T55 17 T56 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%