SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
fsm_state_q | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_states[ClkMuxSt] | 917 | 1 | T19 | 8 | T55 | 13 | T56 | 5 | ||||
fsm_states[CntIncrSt] | 882 | 1 | T19 | 8 | T55 | 8 | T56 | 6 | ||||
fsm_states[CntProgSt] | 956 | 1 | T19 | 11 | T55 | 9 | T56 | 13 | ||||
fsm_states[TransCheckSt] | 982 | 1 | T19 | 19 | T55 | 11 | T56 | 13 | ||||
fsm_states[FlashRmaSt] | 925 | 1 | T19 | 11 | T55 | 9 | T56 | 3 | ||||
fsm_states[TokenHashSt] | 989 | 1 | T19 | 3 | T55 | 12 | T56 | 13 | ||||
fsm_states[TokenCheck0St] | 956 | 1 | T19 | 5 | T55 | 9 | T56 | 7 | ||||
fsm_states[TokenCheck1St] | 949 | 1 | T19 | 8 | T55 | 17 | T56 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |