Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99702 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3550 |
1 |
|
|
T4 |
82 |
|
T25 |
9 |
|
T6 |
37 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
101712 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
1540 |
1 |
|
|
T15 |
9 |
|
T69 |
13 |
|
T95 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99633 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3619 |
1 |
|
|
T9 |
1 |
|
T4 |
45 |
|
T14 |
10 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99747 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3505 |
1 |
|
|
T1 |
1 |
|
T9 |
2 |
|
T4 |
47 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99748 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3504 |
1 |
|
|
T1 |
1 |
|
T4 |
46 |
|
T14 |
15 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
94210 |
1 |
|
|
T1 |
7 |
|
T3 |
87 |
|
T9 |
8 |
no_err_inj |
9042 |
1 |
|
|
T1 |
3 |
|
T2 |
11 |
|
T9 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99786 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3466 |
1 |
|
|
T4 |
73 |
|
T25 |
2 |
|
T6 |
43 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
101703 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
1549 |
1 |
|
|
T15 |
7 |
|
T69 |
15 |
|
T95 |
19 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
74708 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
28544 |
1 |
|
|
T4 |
644 |
|
T6 |
354 |
|
T18 |
53 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99617 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3635 |
1 |
|
|
T1 |
1 |
|
T4 |
57 |
|
T14 |
9 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99745 |
1 |
|
|
T1 |
8 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3507 |
1 |
|
|
T1 |
2 |
|
T9 |
1 |
|
T4 |
46 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99741 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3511 |
1 |
|
|
T1 |
1 |
|
T9 |
1 |
|
T4 |
48 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99683 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3569 |
1 |
|
|
T4 |
86 |
|
T25 |
12 |
|
T6 |
39 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99294 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3958 |
1 |
|
|
T10 |
10 |
|
T4 |
43 |
|
T16 |
8 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
101672 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
1580 |
1 |
|
|
T15 |
12 |
|
T69 |
17 |
|
T95 |
21 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
101819 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
1433 |
1 |
|
|
T15 |
16 |
|
T69 |
15 |
|
T95 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
101687 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
1565 |
1 |
|
|
T15 |
9 |
|
T69 |
17 |
|
T95 |
14 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
98035 |
1 |
|
|
T2 |
11 |
|
T3 |
87 |
|
T10 |
10 |
auto[1] |
5217 |
1 |
|
|
T1 |
10 |
|
T9 |
13 |
|
T4 |
53 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
95673 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T9 |
13 |
auto[1] |
7579 |
1 |
|
|
T3 |
87 |
|
T17 |
71 |
|
T24 |
81 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99790 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3462 |
1 |
|
|
T1 |
1 |
|
T9 |
1 |
|
T4 |
41 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99751 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3501 |
1 |
|
|
T9 |
1 |
|
T4 |
46 |
|
T14 |
12 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99704 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3548 |
1 |
|
|
T9 |
1 |
|
T4 |
46 |
|
T14 |
8 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99694 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3558 |
1 |
|
|
T4 |
70 |
|
T25 |
9 |
|
T6 |
44 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
92447 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
10805 |
1 |
|
|
T4 |
57 |
|
T25 |
7 |
|
T6 |
39 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
95709 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
7543 |
1 |
|
|
T56 |
87 |
|
T262 |
78 |
|
T263 |
90 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
103252 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99664 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3588 |
1 |
|
|
T4 |
77 |
|
T25 |
19 |
|
T6 |
33 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99673 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3579 |
1 |
|
|
T4 |
72 |
|
T25 |
10 |
|
T6 |
36 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
99696 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[1] |
3556 |
1 |
|
|
T4 |
58 |
|
T25 |
10 |
|
T6 |
30 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
91571 |
1 |
|
|
T3 |
87 |
|
T10 |
10 |
|
T4 |
1009 |
auto[0] |
no_err_inj |
6464 |
1 |
|
|
T2 |
11 |
|
T4 |
129 |
|
T26 |
20 |
auto[1] |
err_inj |
2639 |
1 |
|
|
T1 |
7 |
|
T9 |
8 |
|
T4 |
31 |
auto[1] |
no_err_inj |
2578 |
1 |
|
|
T1 |
3 |
|
T9 |
5 |
|
T4 |
22 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
94822 |
1 |
|
|
T2 |
11 |
|
T3 |
87 |
|
T10 |
10 |
auto[0] |
auto[1] |
3213 |
1 |
|
|
T4 |
40 |
|
T14 |
12 |
|
T6 |
4 |
auto[1] |
auto[0] |
4929 |
1 |
|
|
T1 |
10 |
|
T9 |
12 |
|
T4 |
47 |
auto[1] |
auto[1] |
288 |
1 |
|
|
T9 |
1 |
|
T4 |
6 |
|
T6 |
4 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
94815 |
1 |
|
|
T2 |
11 |
|
T3 |
87 |
|
T10 |
10 |
auto[0] |
auto[1] |
3220 |
1 |
|
|
T4 |
44 |
|
T14 |
12 |
|
T6 |
5 |
auto[1] |
auto[0] |
4930 |
1 |
|
|
T1 |
8 |
|
T9 |
12 |
|
T4 |
51 |
auto[1] |
auto[1] |
287 |
1 |
|
|
T1 |
2 |
|
T9 |
1 |
|
T4 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
94751 |
1 |
|
|
T2 |
11 |
|
T3 |
87 |
|
T10 |
10 |
auto[0] |
auto[1] |
3284 |
1 |
|
|
T4 |
40 |
|
T14 |
8 |
|
T6 |
4 |
auto[1] |
auto[0] |
4953 |
1 |
|
|
T1 |
10 |
|
T9 |
12 |
|
T4 |
47 |
auto[1] |
auto[1] |
264 |
1 |
|
|
T9 |
1 |
|
T4 |
6 |
|
T19 |
9 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
94827 |
1 |
|
|
T2 |
11 |
|
T3 |
87 |
|
T10 |
10 |
auto[0] |
auto[1] |
3208 |
1 |
|
|
T4 |
47 |
|
T14 |
9 |
|
T6 |
6 |
auto[1] |
auto[0] |
4920 |
1 |
|
|
T1 |
9 |
|
T9 |
11 |
|
T4 |
53 |
auto[1] |
auto[1] |
297 |
1 |
|
|
T1 |
1 |
|
T9 |
2 |
|
T6 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
94829 |
1 |
|
|
T2 |
11 |
|
T3 |
87 |
|
T10 |
10 |
auto[0] |
auto[1] |
3206 |
1 |
|
|
T4 |
43 |
|
T14 |
15 |
|
T6 |
5 |
auto[1] |
auto[0] |
4919 |
1 |
|
|
T1 |
9 |
|
T9 |
13 |
|
T4 |
50 |
auto[1] |
auto[1] |
298 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T6 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
94733 |
1 |
|
|
T2 |
11 |
|
T3 |
87 |
|
T10 |
10 |
auto[0] |
auto[1] |
3302 |
1 |
|
|
T4 |
42 |
|
T14 |
10 |
|
T6 |
8 |
auto[1] |
auto[0] |
4900 |
1 |
|
|
T1 |
10 |
|
T9 |
12 |
|
T4 |
50 |
auto[1] |
auto[1] |
317 |
1 |
|
|
T9 |
1 |
|
T4 |
3 |
|
T19 |
8 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72521 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2187 |
1 |
|
|
T4 |
40 |
|
T25 |
9 |
|
T6 |
10 |
auto[1] |
auto[0] |
27181 |
1 |
|
|
T4 |
602 |
|
T6 |
327 |
|
T18 |
51 |
auto[1] |
auto[1] |
1363 |
1 |
|
|
T4 |
42 |
|
T6 |
27 |
|
T18 |
2 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72582 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2126 |
1 |
|
|
T4 |
40 |
|
T25 |
2 |
|
T6 |
7 |
auto[1] |
auto[0] |
27204 |
1 |
|
|
T4 |
611 |
|
T6 |
318 |
|
T18 |
48 |
auto[1] |
auto[1] |
1340 |
1 |
|
|
T4 |
33 |
|
T6 |
36 |
|
T18 |
5 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72289 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2419 |
1 |
|
|
T10 |
10 |
|
T16 |
8 |
|
T19 |
31 |
auto[1] |
auto[0] |
27005 |
1 |
|
|
T4 |
601 |
|
T6 |
310 |
|
T18 |
53 |
auto[1] |
auto[1] |
1539 |
1 |
|
|
T4 |
43 |
|
T6 |
44 |
|
T19 |
10 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72510 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2198 |
1 |
|
|
T4 |
50 |
|
T25 |
12 |
|
T6 |
9 |
auto[1] |
auto[0] |
27173 |
1 |
|
|
T4 |
608 |
|
T6 |
324 |
|
T18 |
47 |
auto[1] |
auto[1] |
1371 |
1 |
|
|
T4 |
36 |
|
T6 |
30 |
|
T18 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
65209 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
9499 |
1 |
|
|
T4 |
30 |
|
T25 |
7 |
|
T6 |
9 |
auto[1] |
auto[0] |
27238 |
1 |
|
|
T4 |
617 |
|
T6 |
324 |
|
T18 |
42 |
auto[1] |
auto[1] |
1306 |
1 |
|
|
T4 |
27 |
|
T6 |
30 |
|
T18 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72544 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2164 |
1 |
|
|
T9 |
1 |
|
T4 |
16 |
|
T14 |
12 |
auto[1] |
auto[0] |
27207 |
1 |
|
|
T4 |
614 |
|
T6 |
346 |
|
T18 |
53 |
auto[1] |
auto[1] |
1337 |
1 |
|
|
T4 |
30 |
|
T6 |
8 |
|
T19 |
5 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72538 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2170 |
1 |
|
|
T1 |
1 |
|
T9 |
1 |
|
T4 |
14 |
auto[1] |
auto[0] |
27252 |
1 |
|
|
T4 |
617 |
|
T6 |
347 |
|
T18 |
53 |
auto[1] |
auto[1] |
1292 |
1 |
|
|
T4 |
27 |
|
T6 |
7 |
|
T19 |
3 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72549 |
1 |
|
|
T1 |
8 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2159 |
1 |
|
|
T1 |
2 |
|
T9 |
1 |
|
T4 |
16 |
auto[1] |
auto[0] |
27196 |
1 |
|
|
T4 |
614 |
|
T6 |
349 |
|
T18 |
53 |
auto[1] |
auto[1] |
1348 |
1 |
|
|
T4 |
30 |
|
T6 |
5 |
|
T19 |
4 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72479 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2229 |
1 |
|
|
T1 |
1 |
|
T4 |
16 |
|
T14 |
9 |
auto[1] |
auto[0] |
27138 |
1 |
|
|
T4 |
603 |
|
T6 |
346 |
|
T18 |
53 |
auto[1] |
auto[1] |
1406 |
1 |
|
|
T4 |
41 |
|
T6 |
8 |
|
T19 |
5 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72582 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2126 |
1 |
|
|
T1 |
1 |
|
T9 |
2 |
|
T4 |
18 |
auto[1] |
auto[0] |
27165 |
1 |
|
|
T4 |
615 |
|
T6 |
347 |
|
T18 |
53 |
auto[1] |
auto[1] |
1379 |
1 |
|
|
T4 |
29 |
|
T6 |
7 |
|
T19 |
4 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72447 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2261 |
1 |
|
|
T9 |
1 |
|
T4 |
11 |
|
T14 |
10 |
auto[1] |
auto[0] |
27186 |
1 |
|
|
T4 |
610 |
|
T6 |
346 |
|
T18 |
53 |
auto[1] |
auto[1] |
1358 |
1 |
|
|
T4 |
34 |
|
T6 |
8 |
|
T19 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72544 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2164 |
1 |
|
|
T4 |
36 |
|
T25 |
10 |
|
T6 |
9 |
auto[1] |
auto[0] |
27152 |
1 |
|
|
T4 |
622 |
|
T6 |
333 |
|
T18 |
49 |
auto[1] |
auto[1] |
1392 |
1 |
|
|
T4 |
22 |
|
T6 |
21 |
|
T18 |
4 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
72536 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T3 |
87 |
auto[0] |
auto[1] |
2172 |
1 |
|
|
T4 |
43 |
|
T25 |
10 |
|
T6 |
11 |
auto[1] |
auto[0] |
27137 |
1 |
|
|
T4 |
615 |
|
T6 |
329 |
|
T18 |
42 |
auto[1] |
auto[1] |
1407 |
1 |
|
|
T4 |
29 |
|
T6 |
25 |
|
T18 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
71701 |
1 |
|
|
T2 |
11 |
|
T3 |
87 |
|
T10 |
10 |
auto[0] |
auto[1] |
3007 |
1 |
|
|
T1 |
10 |
|
T9 |
13 |
|
T4 |
43 |
auto[1] |
auto[0] |
26334 |
1 |
|
|
T4 |
634 |
|
T6 |
342 |
|
T18 |
53 |
auto[1] |
auto[1] |
2210 |
1 |
|
|
T4 |
10 |
|
T6 |
12 |
|
T19 |
89 |