Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187776626

1

T1

5396

T2

3437

T3

24932

auto[1]

2694221

1

T1

495

T3

12769

T9

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187747898

1

T1

5792

T2

3437

T3

24959

auto[1]

2722949

1

T1

99

T3

12742

T9

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	13731557	1			T1	1183		T2	1019		T3	8959
auto[IdleSt]	40947861	1			T1	1118		T2	951		T3	8216
auto[ClkMuxSt]	68660	1			T1	3		T2	10		T3	70
auto[CntIncrSt]	68213	1			T1	3		T2	10		T3	68
auto[CntProgSt]	3325220	1			T1	35		T2	20		T3	670
auto[TransCheckSt]	53622	1			T1	3		T2	10		T3	44
auto[TokenHashSt]	73799817	1			T1	290		T2	199		T3	694
auto[FlashRmaSt]	55599	1			T1	3		T2	10		T3	35
auto[TokenCheck0St]	24814	1			T1	3		T2	10		T3	28
auto[TokenCheck1St]	18363	1			T1	3		T2	10		T3	28
auto[TransProgSt]	861128	1			T1	126		T2	20		T3	69
auto[PostTransSt]	24033096	1			T1	731		T2	1146		T3	6
auto[ScrapSt]	247380	1			T2	22		T3	9		T4	8658
auto[EscalateSt]	12522532	1			T1	1581		T3	18805		T9	1340
auto[InvalidSt]	20709301	1			T1	807		T9	857		T4	386704

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	3684	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	20709301	1			T1	807		T9	857		T4	386704
EscalateSt	12522532	1			T1	1581		T3	18805		T9	1340
ScrapSt	247380	1			T2	22		T3	9		T4	8658
PostTransSt	24033096	1			T1	731		T2	1146		T3	6
TransProgSt	861128	1			T1	126		T2	20		T3	69
TokenCheck1St	18363	1			T1	3		T2	10		T3	28
TokenCheck0St	24814	1			T1	3		T2	10		T3	28
FlashRmaSt	55599	1			T1	3		T2	10		T3	35
TokenHashSt	73799817	1			T1	290		T2	199		T3	694
TransCheckSt	53622	1			T1	3		T2	10		T3	44
CntProgSt	3325220	1			T1	35		T2	20		T3	670
CntIncrSt	68213	1			T1	3		T2	10		T3	68
ClkMuxSt	68660	1			T1	3		T2	10		T3	70
IdleSt	40947861	1			T1	1118		T2	951		T3	8216
ResetSt	13731557	1			T1	1183		T2	1019		T3	8959
arcs[ResetSt=>IdleSt]	104029	1			T1	10		T2	11		T3	76
arcs[IdleSt=>ScrapSt]	596	1			T2	1		T3	3		T4	5
arcs[IdleSt=>ClkMuxSt]	68359	1			T1	3		T2	10		T3	70
arcs[ClkMuxSt=>CntIncrSt]	68213	1			T1	3		T2	10		T3	68
arcs[CntIncrSt=>PostTransSt]	3214	1			T4	62		T25	10		T6	32
arcs[CntIncrSt=>CntProgSt]	64849	1			T1	3		T2	10		T3	68
arcs[CntProgSt=>PostTransSt]	8954	1			T10	10		T4	125		T15	9
arcs[CntProgSt=>TransCheckSt]	53622	1			T1	3		T2	10		T3	44
arcs[TransCheckSt=>PostTransSt]	7350	1			T4	59		T25	10		T6	31
arcs[TransCheckSt=>TokenHashSt]	46076	1			T1	3		T2	10		T3	43
arcs[TokenHashSt=>PostTransSt]	19795	1			T4	204		T15	4		T25	35
arcs[TokenHashSt=>FlashRmaSt]	24998	1			T1	3		T2	10		T3	29
arcs[FlashRmaSt=>TokenCheck0St]	24814	1			T1	3		T2	10		T3	28
arcs[TokenCheck0St=>PostTransSt]	6387	1			T4	65		T15	7		T25	1
arcs[TokenCheck0St=>TokenCheck1St]	18363	1			T1	3		T2	10		T3	28
arcs[TokenCheck1St=>PostTransSt]	1322	1			T4	6		T25	1		T6	2
arcs[TransProgSt=>PostTransSt]	15185	1			T1	3		T2	10		T3	3
arcs[IdleSt=>EscalateSt]	435	1			T3	2		T36	6		T58	12
arcs[ClkMuxSt=>EscalateSt]	146	1			T3	2		T17	1		T24	2
arcs[CntIncrSt=>EscalateSt]	150	1			T17	4		T24	2		T36	1
arcs[CntProgSt=>EscalateSt]	2273	1			T3	24		T17	27		T24	42
arcs[TransCheckSt=>EscalateSt]	196	1			T3	1		T17	1		T24	1
arcs[TokenHashSt=>EscalateSt]	1283	1			T3	14		T17	11		T24	6
arcs[FlashRmaSt=>EscalateSt]	184	1			T3	1		T17	1		T24	4
arcs[TokenCheck0St=>EscalateSt]	64	1			T62	2		T63	2		T64	1
arcs[TokenCheck1St=>EscalateSt]	286	1			T3	6		T17	2		T24	6
arcs[TransProgSt=>EscalateSt]	1570	1			T3	19		T17	18		T24	17
arcs[PostTransSt=>EscalateSt]	9394	1			T3	3		T10	10		T4	125
arcs[InvalidSt=>EscalateSt]	26197	1			T1	6		T9	6		T4	331

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	13731221	1			T1	1183		T2	1019		T3	8952
auto[0]	auto[IdleSt]	40947558	1			T1	1118		T2	951		T3	8214
auto[0]	auto[ClkMuxSt]	68565	1			T1	3		T2	10		T3	68
auto[0]	auto[CntIncrSt]	68116	1			T1	3		T2	10		T3	68
auto[0]	auto[CntProgSt]	3323695	1			T1	35		T2	20		T3	650
auto[0]	auto[TransCheckSt]	53496	1			T1	3		T2	10		T3	43
auto[0]	auto[TokenHashSt]	73798999	1			T1	290		T2	199		T3	686
auto[0]	auto[FlashRmaSt]	55469	1			T1	3		T2	10		T3	34
auto[0]	auto[TokenCheck0St]	24772	1			T1	3		T2	10		T3	28
auto[0]	auto[TokenCheck1St]	18170	1			T1	3		T2	10		T3	25
auto[0]	auto[TransProgSt]	860071	1			T1	126		T2	20		T3	59
auto[0]	auto[PostTransSt]	24028333	1			T1	731		T2	1146		T3	3
auto[0]	auto[ScrapSt]	247280	1			T2	22		T3	7		T4	8658
auto[0]	auto[EscalateSt]	9850922	1			T1	1091		T3	6095		T9	1046
auto[0]	auto[InvalidSt]	20696275	1			T1	802		T9	854		T4	386545
auto[1]	auto[ResetSt]	336	1			T3	7		T17	1		T24	1
auto[1]	auto[IdleSt]	303	1			T3	2		T36	4		T58	7
auto[1]	auto[ClkMuxSt]	95	1			T3	2		T36	1		T58	1
auto[1]	auto[CntIncrSt]	97	1			T17	2		T24	1		T36	1
auto[1]	auto[CntProgSt]	1525	1			T3	20		T17	17		T24	29
auto[1]	auto[TransCheckSt]	126	1			T3	1		T17	1		T58	2
auto[1]	auto[TokenHashSt]	818	1			T3	8		T17	9		T24	3
auto[1]	auto[FlashRmaSt]	130	1			T3	1		T17	1		T24	2
auto[1]	auto[TokenCheck0St]	42	1			T63	2		T64	1		T259	1
auto[1]	auto[TokenCheck1St]	193	1			T3	3		T24	4		T36	2
auto[1]	auto[TransProgSt]	1057	1			T3	10		T17	10		T24	10
auto[1]	auto[PostTransSt]	4763	1			T3	3		T10	4		T4	53
auto[1]	auto[ScrapSt]	100	1			T3	2		T17	1		T65	1
auto[1]	auto[EscalateSt]	2671610	1			T1	490		T3	12710		T9	294
auto[1]	auto[InvalidSt]	13026	1			T1	5		T9	3		T4	159

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	13731230	1			T1	1183		T2	1019		T3	8950
auto[0]	auto[IdleSt]	40947585	1			T1	1118		T2	951		T3	8215
auto[0]	auto[ClkMuxSt]	68556	1			T1	3		T2	10		T3	68
auto[0]	auto[CntIncrSt]	68110	1			T1	3		T2	10		T3	68
auto[0]	auto[CntProgSt]	3323679	1			T1	35		T2	20		T3	655
auto[0]	auto[TransCheckSt]	53487	1			T1	3		T2	10		T3	43
auto[0]	auto[TokenHashSt]	73798928	1			T1	290		T2	199		T3	685
auto[0]	auto[FlashRmaSt]	55476	1			T1	3		T2	10		T3	35
auto[0]	auto[TokenCheck0St]	24775	1			T1	3		T2	10		T3	28
auto[0]	auto[TokenCheck1St]	18178	1			T1	3		T2	10		T3	24
auto[0]	auto[TransProgSt]	860068	1			T1	126		T2	20		T3	55
auto[0]	auto[PostTransSt]	24028341	1			T1	731		T2	1146		T3	5
auto[0]	auto[ScrapSt]	247271	1			T2	22		T3	7		T4	8658
auto[0]	auto[EscalateSt]	9822400	1			T1	1483		T3	6121		T9	1046
auto[0]	auto[InvalidSt]	20696130	1			T1	806		T9	854		T4	386532
auto[1]	auto[ResetSt]	327	1			T3	9		T17	3		T36	2
auto[1]	auto[IdleSt]	276	1			T3	1		T36	4		T58	10
auto[1]	auto[ClkMuxSt]	104	1			T3	2		T17	1		T24	2
auto[1]	auto[CntIncrSt]	103	1			T17	3		T24	2		T62	3
auto[1]	auto[CntProgSt]	1541	1			T3	15		T17	18		T24	31
auto[1]	auto[TransCheckSt]	135	1			T3	1		T24	1		T36	1
auto[1]	auto[TokenHashSt]	889	1			T3	9		T17	8		T24	5
auto[1]	auto[FlashRmaSt]	123	1			T24	3		T65	2		T62	3
auto[1]	auto[TokenCheck0St]	39	1			T62	2		T64	1		T260	1
auto[1]	auto[TokenCheck1St]	185	1			T3	4		T17	2		T24	5
auto[1]	auto[TransProgSt]	1060	1			T3	14		T17	13		T24	12
auto[1]	auto[PostTransSt]	4755	1			T3	1		T10	6		T4	72
auto[1]	auto[ScrapSt]	109	1			T3	2		T58	1		T261	1
auto[1]	auto[EscalateSt]	2700132	1			T1	98		T3	12684		T9	294
auto[1]	auto[InvalidSt]	13171	1			T1	1		T9	3		T4	172